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-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity topModule is Port (
CLK : in std_logic;
GPIO0: out std_logic;
GPIO1: out std_logic;
RX: in std_logic;
TX: out std_logic);
end topModule;
architecture Behavioral of topModule is
component uart_tx port(
clk : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_ready : out std_logic;
tx : out std_logic);
end component;
component uart_rx port (
clk : in std_logic;
rx :in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_ready : out std_logic);
end component;
signal counter : std_logic_vector(7 downto 0):= (others=>'0');
signal tx_en : std_logic := '0';
signal tx_ready : std_logic;
signal tx_out : std_logic;
signal tx_data : std_logic_vector(7 downto 0):= (others=>'0');
signal rx_ready : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
begin
TX <= tx_out;
GPIO0 <= RX;
GPIO1 <= tx_out;
uart1_tx : uart_tx port map(
clk => CLK,
tx_data => tx_data,
tx_en => tx_en,
tx_ready => tx_ready,
tx => tx_out
);
uart1_rx: uart_rx port map(
clk => CLK,
rx => RX,
rx_data => rx_data,
rx_ready => rx_ready
);
retransmit : process(clk) begin
if rising_edge(clk) then
if (rx_ready and tx_ready) = '1' then
tx_data <= rx_data + 1;
tx_en <= '1';
else
tx_en <= '0';
end if;
end if;
end process;
end Behavioral; |
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--64-bit Kogge-Stone adder is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------
-------------------------------------------------------
-- Project : Computer arithmetic, fast adders (3rd year mini project)
-- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi
-- Date : 10-05-2014
-- File : carry_op.vhd
-- Design : 64-bit Kogge-Stone adder
------------------------------------------------------
-- Description : a carry operator unit
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY carry_op IS
PORT(
g1 : IN std_logic;
p1 : IN std_logic;
g2 : IN std_logic;
p2 : IN std_logic;
go : OUT std_logic;
po : OUT std_logic
);
END carry_op;
ARCHITECTURE arch OF carry_op IS
BEGIN
go <= g2 OR (g1 AND p2);
po <= P2 AND p1;
END arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_adEe_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_AddSubnS_0 is
component convolve_kernel_adEe_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (22-1 downto 0);
fab : IN STD_LOGIC_VECTOR (22-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (22-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component convolve_kernel_adEe_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (20-1 downto 0);
fab : IN STD_LOGIC_VECTOR (20-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (20-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(21 downto 0);
signal b0_cb : std_logic_vector(21 downto 0);
signal a1_cb : std_logic_vector(43 downto 22);
signal b1_cb : std_logic_vector(43 downto 22);
signal a2_cb : std_logic_vector(63 downto 44);
signal b2_cb : std_logic_vector(63 downto 44);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(19 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo1 is array (1 downto 0) of std_logic_vector(21 downto 0);
signal s0_ca_rego0 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal s1_ca_rego1 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= std_logic_vector(resize(unsigned(a), 64));
b_reg <= std_logic_vector(resize(unsigned(b), 64));
-- small adder input assigments
a0_cb <= a_reg(21 downto 0);
b0_cb <= b_reg(21 downto 0);
a1_cb <= a_reg(43 downto 22);
b1_cb <= b_reg(43 downto 22);
a2_cb <= a_reg(63 downto 44);
b2_cb <= b_reg(63 downto 44);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
end if;
end if;
end process;
-- small adder generation
u0 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(21 downto 0),
facout => faccout0_co0);
u1 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(43 downto 22),
facout => faccout1_co1);
u2 : convolve_kernel_adEe_AddSubnS_0_fadder_f
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(63 downto 44),
facout => faccout2_co2);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(21 downto 0);
s1_ca_rego1 (0) <= fas(43 downto 22);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(21 downto 0) <= s0_ca_rego0(1);
s_tmp(43 downto 22) <= s1_ca_rego1(0);
s_tmp(63 downto 44) <= fas(63 downto 44);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder is
generic(N : natural :=22);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder_f is
generic(N : natural :=20);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_AddSubnS_0_U : component convolve_kernel_adEe_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_adEe_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_AddSubnS_0 is
component convolve_kernel_adEe_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (22-1 downto 0);
fab : IN STD_LOGIC_VECTOR (22-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (22-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component convolve_kernel_adEe_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (20-1 downto 0);
fab : IN STD_LOGIC_VECTOR (20-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (20-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(21 downto 0);
signal b0_cb : std_logic_vector(21 downto 0);
signal a1_cb : std_logic_vector(43 downto 22);
signal b1_cb : std_logic_vector(43 downto 22);
signal a2_cb : std_logic_vector(63 downto 44);
signal b2_cb : std_logic_vector(63 downto 44);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(19 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo1 is array (1 downto 0) of std_logic_vector(21 downto 0);
signal s0_ca_rego0 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal s1_ca_rego1 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= std_logic_vector(resize(unsigned(a), 64));
b_reg <= std_logic_vector(resize(unsigned(b), 64));
-- small adder input assigments
a0_cb <= a_reg(21 downto 0);
b0_cb <= b_reg(21 downto 0);
a1_cb <= a_reg(43 downto 22);
b1_cb <= b_reg(43 downto 22);
a2_cb <= a_reg(63 downto 44);
b2_cb <= b_reg(63 downto 44);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
end if;
end if;
end process;
-- small adder generation
u0 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(21 downto 0),
facout => faccout0_co0);
u1 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(43 downto 22),
facout => faccout1_co1);
u2 : convolve_kernel_adEe_AddSubnS_0_fadder_f
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(63 downto 44),
facout => faccout2_co2);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(21 downto 0);
s1_ca_rego1 (0) <= fas(43 downto 22);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(21 downto 0) <= s0_ca_rego0(1);
s_tmp(43 downto 22) <= s1_ca_rego1(0);
s_tmp(63 downto 44) <= fas(63 downto 44);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder is
generic(N : natural :=22);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder_f is
generic(N : natural :=20);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_AddSubnS_0_U : component convolve_kernel_adEe_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_adEe_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_AddSubnS_0 is
component convolve_kernel_adEe_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (22-1 downto 0);
fab : IN STD_LOGIC_VECTOR (22-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (22-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component convolve_kernel_adEe_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (20-1 downto 0);
fab : IN STD_LOGIC_VECTOR (20-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (20-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(21 downto 0);
signal b0_cb : std_logic_vector(21 downto 0);
signal a1_cb : std_logic_vector(43 downto 22);
signal b1_cb : std_logic_vector(43 downto 22);
signal a2_cb : std_logic_vector(63 downto 44);
signal b2_cb : std_logic_vector(63 downto 44);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(19 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo1 is array (1 downto 0) of std_logic_vector(21 downto 0);
signal s0_ca_rego0 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal s1_ca_rego1 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= std_logic_vector(resize(unsigned(a), 64));
b_reg <= std_logic_vector(resize(unsigned(b), 64));
-- small adder input assigments
a0_cb <= a_reg(21 downto 0);
b0_cb <= b_reg(21 downto 0);
a1_cb <= a_reg(43 downto 22);
b1_cb <= b_reg(43 downto 22);
a2_cb <= a_reg(63 downto 44);
b2_cb <= b_reg(63 downto 44);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
end if;
end if;
end process;
-- small adder generation
u0 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(21 downto 0),
facout => faccout0_co0);
u1 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(43 downto 22),
facout => faccout1_co1);
u2 : convolve_kernel_adEe_AddSubnS_0_fadder_f
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(63 downto 44),
facout => faccout2_co2);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(21 downto 0);
s1_ca_rego1 (0) <= fas(43 downto 22);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(21 downto 0) <= s0_ca_rego0(1);
s_tmp(43 downto 22) <= s1_ca_rego1(0);
s_tmp(63 downto 44) <= fas(63 downto 44);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder is
generic(N : natural :=22);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder_f is
generic(N : natural :=20);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_AddSubnS_0_U : component convolve_kernel_adEe_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_out_8b_sync_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_out_8b_sync_0 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
wait_req : out std_logic; -- .waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
st_ready : in std_logic := '0'; -- .ready
st_valid : out std_logic; -- .valid
irq : out std_logic -- conduit_end.export
);
end entity fifo_out_8b_sync_0;
architecture rtl of fifo_out_8b_sync_0 is
component fifo_out_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
wait_req : out std_logic; -- waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : out std_logic_vector(7 downto 0); -- data
st_ready : in std_logic := 'X'; -- ready
st_valid : out std_logic; -- valid
irq : out std_logic -- export
);
end component fifo_out_8b_sync;
begin
fifo_out_8b_sync_0 : component fifo_out_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
addr => addr, -- avalon_slave_0.address
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
wait_req => wait_req, -- .waitrequest
byte_en => byte_en, -- .byteenable
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_source.data
st_ready => st_ready, -- .ready
st_valid => st_valid, -- .valid
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_out_8b_sync_0
|
entity SAMPLE is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE is
begin
process begin
wait for delay;
assert (FALSE) report NAME & ":OK" severity NOTE;
wait;
end process;
end MODEL;
entity SAMPLE_NG is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE_NG is
component SAMPLE generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U: SAMPLE generic map (NAME => NAME & "(" & ")", delay => delay);
end MODEL;
entity issue433 is
generic (NAME: string := "TEST_NG");
end entity;
architecture MODEL of issue433 is
component SAMPLE_NG generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U1: SAMPLE_NG generic map(NAME => NAME & string'(":U1"), delay => 1 ns);
U2: SAMPLE_NG generic map(NAME => NAME & string'(":U2"), delay => 2 ns);
end MODEL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
use work.automotive_valve_defs.all;
entity brake_system is
end entity brake_system;
-- end not in book
architecture structure of brake_system is
use work.automotive_valve_defs.all;
-- ... -- declarations of other components, terminals, etc
-- not in book
terminal master_reservoir, brake_line : valve_fluidic;
terminal brake_pedal : valve_translational;
-- end not in book
begin
pedal_valve : component automotive_valve
port map ( p1 => master_reservoir,
p2 => brake_line,
control => brake_pedal );
-- ... -- other component instances
end architecture structure;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
use work.automotive_valve_defs.all;
entity brake_system is
end entity brake_system;
-- end not in book
architecture structure of brake_system is
use work.automotive_valve_defs.all;
-- ... -- declarations of other components, terminals, etc
-- not in book
terminal master_reservoir, brake_line : valve_fluidic;
terminal brake_pedal : valve_translational;
-- end not in book
begin
pedal_valve : component automotive_valve
port map ( p1 => master_reservoir,
p2 => brake_line,
control => brake_pedal );
-- ... -- other component instances
end architecture structure;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
use work.automotive_valve_defs.all;
entity brake_system is
end entity brake_system;
-- end not in book
architecture structure of brake_system is
use work.automotive_valve_defs.all;
-- ... -- declarations of other components, terminals, etc
-- not in book
terminal master_reservoir, brake_line : valve_fluidic;
terminal brake_pedal : valve_translational;
-- end not in book
begin
pedal_valve : component automotive_valve
port map ( p1 => master_reservoir,
p2 => brake_line,
control => brake_pedal );
-- ... -- other component instances
end architecture structure;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas_net
-- File: cpu_disas_net.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') and (disas = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity fpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') and (disas /= '0') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
-- pragma translate_on
end;
|
-- NEED RESULT: ARCH00031.P1: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P2: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P3: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P4: Target of a variable assignment may be a aggregate of simple names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00031
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00031)
-- ENT00031_Test_Bench(ARCH00031_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00031 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P1" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00031.P2" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P3" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_boolean_2 : inout boolean
; v_bit_2 : inout bit
; v_severity_level_2 : inout severity_level
; v_character_2 : inout character
; v_st_enum1_2 : inout st_enum1
; v_integer_2 : inout integer
; v_st_int1_2 : inout st_int1
; v_time_2 : inout time
; v_st_phys1_2 : inout st_phys1
; v_real_2 : inout real
; v_st_real1_2 : inout st_real1
; v_st_rec1_2 : inout st_rec1
; v_st_rec2_2 : inout st_rec2
; v_st_rec3_2 : inout st_rec3
; v_st_arr1_2 : inout st_arr1
; v_st_arr2_2 : inout st_arr2
; v_st_arr3_2 : inout st_arr3
)
is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 (
v_boolean_2
, v_bit_2
, v_severity_level_2
, v_character_2
, v_st_enum1_2
, v_integer_2
, v_st_int1_2
, v_time_2
, v_st_phys1_2
, v_real_2
, v_st_real1_2
, v_st_rec1_2
, v_st_rec2_2
, v_st_rec3_2
, v_st_arr1_2
, v_st_arr2_2
, v_st_arr3_2
) ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P4" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P4 ;
--
end ARCH00031 ;
--
entity ENT00031_Test_Bench is
end ENT00031_Test_Bench ;
--
architecture ARCH00031_Test_Bench of ENT00031_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00031 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00031_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
entity clock_divider_tb is
end clock_divider_tb;
architecture behavior of clock_divider_tb is
use work.utils_pkg.all;
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
uut : clock_divider
generic map (DIV => 5)
port map(
clk => clk,
clk_out_p => output);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity clock_divider_tb is
end clock_divider_tb;
architecture behavior of clock_divider_tb is
use work.utils_pkg.all;
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
uut : clock_divider
generic map (DIV => 5)
port map(
clk => clk,
clk_out_p => output);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dot_product - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dot_product is
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
result : out coord_type_ext;
rdy : out std_logic
);
end dot_product;
architecture Behavioral of dot_product is
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(D))));
type mul_res_array_type is array(0 to D-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1-1 downto 0);
--type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to D/2-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
signal tmp_mul_res : mul_res_array_type;
signal tmp_tree_adder_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
--signal tmp_tree_adder_res : tree_adder_res_array_type;
signal tmp_tree_adder_res : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal const_0 : std_logic_vector(MUL_BITWIDTH-1 downto 0);
signal tmp_mul_rdy : std_logic;
signal delay_line_tree_adder : std_logic_vector(0 to 2*LAYERS_TREE_ADDER-1);
signal tmp_final_res : coord_type_ext;
begin
const_0 <= (others => '0');
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
madd_inst : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => tmp_mul_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
madd_inst : madd
generic map(
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
G2 : for I in 0 to D-1 generate
tmp_tree_adder_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_res(I);
end generate G2;
adder_tree_inst : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_mul_rdy,
sub => '0',
input_string => tmp_tree_adder_input_string,
rdy => rdy,
output => tmp_tree_adder_res
);
G3: if COORD_BITWIDTH_EXT <= 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(COORD_BITWIDTH_EXT-1 downto 0);
tmp_final_res <= tmp_tree_adder_res(COORD_BITWIDTH_EXT-1 downto 0);
end generate G3;
G4: if COORD_BITWIDTH_EXT > 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
--tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
end generate G4;
--rdy <= delay_line_tree_adder(2*LAYERS_TREE_ADDER-1);
result <= tmp_final_res;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11344)
`protect data_block
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Ie4iMETjiXT5079kOatwiQSZTK3IRpQ1Z3UxiW11j4w7mKQeSIktIvZGpSKj5cScnAyWnL4jRTJV
twjNLt+IL+5gI5Hva0ed6jTgD6zanz+pkhYcUinoSbPbVBMMt3T9p3ikI6reSD2VibiVoVi+3rpP
lkxvhpwWphzKkPvZJVnf3rIJvybDACdSMbfrUiW0irpuG3au8h6f27deCKBi8qdq4b4g+KY+d84i
Lshk4bNl4uxqpwOD4TltJjUxgc9sWhDnMU3m+aO92wTh7dowFp5GcFhi6AevSwvVry5a2f7h8iP6
RrkVrTr1KWonzK4La59ogr0wBDzUXFI6xprBNTA/iO+mUp1iKxPfzp7kuK/kMcfb27MSWXtPbrcR
geuIJmkViTbsBtnK0EBMPcEis7xfgbPLWfwEliOEsOJaQ2kRo9ZRk2agi0ITBIAMaP+zkMC18I6/
cEL8M3cs0/UqiGIQhKPkQE0vHVrA71Z+BopTIpsjKfA/8M08x1bifuyuieybN7oP6C/dOe8xIit3
4g==
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity nfa_get_initials is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0);
ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0);
ap_ST_pp0_stg2_fsm_2: vl_logic_vector(0 to 1) := (Hi0, Hi1);
ap_ST_pp0_stg3_fsm_3: vl_logic_vector(0 to 1) := (Hi1, Hi1);
ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv32_0 : integer := 0;
ap_const_lv32_1 : integer := 1;
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
ap_ce : in vl_logic;
nfa_initials_buckets_req_din: out vl_logic;
nfa_initials_buckets_req_full_n: in vl_logic;
nfa_initials_buckets_req_write: out vl_logic;
nfa_initials_buckets_rsp_empty_n: in vl_logic;
nfa_initials_buckets_rsp_read: out vl_logic;
nfa_initials_buckets_address: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_initials_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_size: out vl_logic_vector(31 downto 0);
ap_return_0 : out vl_logic_vector(31 downto 0);
ap_return_1 : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg1_fsm_1 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg2_fsm_2 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg3_fsm_3 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end nfa_get_initials;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2002.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:40:54 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:27:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:35:51 1996 --
-- **************************** --
use std.textio.all;
ENTITY c07s02b02x00p07n01i02002ent IS
END c07s02b02x00p07n01i02002ent;
ARCHITECTURE c07s02b02x00p07n01i02002arch OF c07s02b02x00p07n01i02002ent IS
BEGIN
TESTING: PROCESS
file f1 : text open write_mode is "aout";
file f2 : text open write_mode is "aout";
BEGIN
if f1 = f2 then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i02002 - Equality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i02002arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2002.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:40:54 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:27:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:35:51 1996 --
-- **************************** --
use std.textio.all;
ENTITY c07s02b02x00p07n01i02002ent IS
END c07s02b02x00p07n01i02002ent;
ARCHITECTURE c07s02b02x00p07n01i02002arch OF c07s02b02x00p07n01i02002ent IS
BEGIN
TESTING: PROCESS
file f1 : text open write_mode is "aout";
file f2 : text open write_mode is "aout";
BEGIN
if f1 = f2 then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i02002 - Equality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i02002arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2002.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:40:54 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:27:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:35:51 1996 --
-- **************************** --
use std.textio.all;
ENTITY c07s02b02x00p07n01i02002ent IS
END c07s02b02x00p07n01i02002ent;
ARCHITECTURE c07s02b02x00p07n01i02002arch OF c07s02b02x00p07n01i02002ent IS
BEGIN
TESTING: PROCESS
file f1 : text open write_mode is "aout";
file f2 : text open write_mode is "aout";
BEGIN
if f1 = f2 then
null;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p07n01i02002 - Equality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i02002arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- fault injector signals
shift: in std_logic;
fault_clk: in std_logic;
data_in_serial: in std_logic;
data_out_serial: out std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end component;
signal FI_add_sta: std_logic_vector(?? downto 0);
begin
FI: fault_injector generic map(DATA_WIDTH => ??)
port map (data_in=> ?? , address=> FI_add_sta(?? downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=>??
);
SR: shift_register_serial_in generic map(REG_WIDTH => )
port map( clk=> fault_clk, reset=>reset, shift=> shift,data_in_serial=> data_in_serial,
data_out_parallel=> FI_add_sta, data_out_serial=> data_out_serial
);
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
-- Direct Memory Access for UART
-- 8 bit words - Configurable number of address bytes
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_dma is
generic(
RAM_READ_TICKS: integer := 1; -- Number of clocks ticks to wait to get data from memory
ADDR_BYTES: integer := 1 -- Total adress bytes: 7 + ADDR_BYTES, so 15 bits by default
);
port(
clk, reset: in std_logic;
-- UART
rx_done_tick: in std_logic;
tx_done_tick: in std_logic;
data_rx: in std_logic_vector(7 downto 0); -- UART Received byte
data_tx: out std_logic_vector(7 downto 0); -- UART byte to transmit
tx_start_tick: out std_logic; -- Tick to start UART transmission
-- Synchronous RAM
data_ram_rd: in std_logic_vector(7 downto 0); -- RAM read byte
data_ram_wr: out std_logic_vector(7 downto 0); -- RAM byte to write
addr: out std_logic_vector(ADDR_BYTES*8 + 6 downto 0); -- RAM address (15 bits)
wr: out std_logic -- RAM read/write switch
);
-- Number of bits necessary to represent integer value
function int_width(value: integer) return integer is
begin
return integer(floor(log2(real(value))));
end function;
end uart_dma;
architecture uart_dma_arch of uart_dma is
type state_type is (idle, addr_recv, send_start, send, recv, write_mem, read_mem);
signal state_reg, state_next: state_type; -- State register
signal cmd_reg, cmd_next: std_logic; -- Command register (0 - read, 1 - write)
constant ADDR_OTHER_MSB: integer := (ADDR_BYTES * 8) - 1; -- MSB for "other" address bits
constant ADDR_MSB: integer := (ADDR_OTHER_MSB + 7); -- MSB for total address bits
signal addr_reg, addr_next: std_logic_vector(ADDR_MSB downto 0); -- Memory address register
signal addr_msb_reg, addr_msb_next:
unsigned(int_width(ADDR_OTHER_MSB) downto 0); -- Most significant bit position in addr_reg for next received byte
signal data_reg, data_next: std_logic_vector(7 downto 0); -- Received data
signal ticks_reg, ticks_next:
unsigned(int_width(RAM_READ_TICKS) downto 0); -- Clock cycles counter for memory accesses
begin
-- State and data regisuter
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
cmd_reg <= '0';
addr_msb_reg <= (others => '0');
addr_reg <= (others => '0');
data_reg <= (others => '0');
ticks_reg <= (others => '0');
elsif rising_edge(clk) then
state_reg <= state_next;
cmd_reg <= cmd_next;
addr_msb_reg <= addr_msb_next;
addr_reg <= addr_next;
data_reg <= data_next;
ticks_reg <= ticks_next;
end if;
end process;
-- Next state logic and data path
process(clk, state_reg, rx_done_tick, tx_done_tick,
state_reg, cmd_reg, addr_msb_reg, addr_reg, data_reg, ticks_reg,
data_rx, data_ram_rd)
begin
-- Default values
state_next <= state_reg;
cmd_next <= cmd_reg;
addr_msb_next <= addr_msb_reg;
addr_next <= addr_reg;
data_next <= data_reg;
ticks_next <= ticks_reg;
tx_start_tick <= '0';
wr <= '0';
case state_reg is
-- Idle, waiting for a command
-- When byte received:
-- data_rx[7] (MSB): 1 -> write to memory, 0 -> read from memory (Command)
-- data_rx[6..0]: 7 address most significant bits
when idle =>
if rx_done_tick = '1' then -- We got a byte from UART
state_next <= addr_recv;
cmd_next <= data_rx(7);
addr_msb_next <= to_unsigned(ADDR_OTHER_MSB, addr_msb_reg'length);
addr_next(ADDR_MSB downto ADDR_MSB-6) <= data_rx(6 downto 0);
end if;
-- Receive others address byte
when addr_recv =>
if rx_done_tick = '1' then
addr_next(to_integer(addr_msb_reg) downto to_integer(addr_msb_reg - 7)) <= data_rx;
if addr_msb_reg = to_unsigned(7, addr_msb_reg'length) then -- Last address byte ?
if cmd_reg = '0' then -- Move to send_start state
state_next <= read_mem;
ticks_next <= (others => '0');
else
state_next <= recv;
end if;
else
addr_msb_next <= addr_msb_reg - 8;
end if;
end if;
-- Read byte (to register)
when read_mem =>
if ticks_reg = RAM_READ_TICKS then
data_next <= data_ram_rd;
state_next <= send_start;
else
ticks_next <= ticks_reg + 1;
end if;
-- Send read byte
when send_start =>
tx_start_tick <= '1';
state_next <= send;
when send =>
if tx_done_tick = '1' then
state_next <= idle;
end if;
-- Receive byte (to register)
when recv =>
if rx_done_tick = '1' then
data_next <= data_rx;
state_next <= write_mem;
end if;
-- Write received byte (register to memory)
when write_mem =>
wr <= '1';
state_next <= idle;
end case;
end process;
-- Output logic
-- UART
data_tx <= data_reg;
-- Memory
addr <= addr_reg;
data_ram_wr <= data_reg;
end uart_dma_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff02 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rstn : std_logic);
end dff02;
architecture behav of dff02 is
begin
process (clk, rstn) is
begin
if rstn = '0' then
q <= '0';
elsif rising_edge (clk) then
q <= d;
end if;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 08/25/2013
-- Design Name:
-- Module Name: pulsegen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY pulsegen IS
GENERIC (
COUNTER_WIDTH : positive := 32
);
PORT (
CLK : IN std_logic;
PERIOD : IN std_logic_vector(COUNTER_WIDTH-1 DOWNTO 0);
I : IN std_logic;
O : OUT std_logic
);
END pulsegen;
ARCHITECTURE Behavioral OF pulsegen IS
SIGNAL counter : unsigned(COUNTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (CLK) IS
VARIABLE zeros : unsigned(COUNTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
O <= '0';
IF I = '1' THEN
O <= I;
ELSIF rising_edge(CLK) THEN
IF unsigned(PERIOD) = zeros THEN
O <= I;
ELSE
counter <= counter + 1;
O <= '0';
IF counter = unsigned(PERIOD)-1 THEN
O <= '1';
ELSIF counter >= unsigned(PERIOD) THEN
O <= '0';
counter <= (OTHERS => '0');
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;
|
-- NEED RESULT: ARCH00552: Signal declarations - scalar static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00552
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (6)
-- 4.3.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00552)
-- ENT00552_Test_Bench(ARCH00552_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00552 of E00000 is
signal si_boolean_1 : boolean
:= c_boolean_1 ;
signal si_bit_1 : bit
:= c_bit_1 ;
signal si_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal si_character_1 : character
:= c_character_1 ;
signal si_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
signal si_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal si_integer_1 : integer
:= c_integer_1 ;
signal si_t_int1_1 : t_int1
:= c_t_int1_1 ;
signal si_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal si_time_1 : time
:= c_time_1 ;
signal si_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
signal si_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal si_real_1 : real
:= c_real_1 ;
signal si_t_real1_1 : t_real1
:= c_t_real1_1 ;
signal si_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal synch : boolean := false ;
signal s_correct : boolean := true ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and si_boolean_1 = c_boolean_1 ;
correct := correct and si_bit_1 = c_bit_1 ;
correct := correct and si_severity_level_1 = c_severity_level_1 ;
correct := correct and si_character_1 = c_character_1 ;
correct := correct and si_t_enum1_1 = c_t_enum1_1 ;
correct := correct and si_st_enum1_1 = c_st_enum1_1 ;
correct := correct and si_integer_1 = c_integer_1 ;
correct := correct and si_t_int1_1 = c_t_int1_1 ;
correct := correct and si_st_int1_1 = c_st_int1_1 ;
correct := correct and si_time_1 = c_time_1 ;
correct := correct and si_t_phys1_1 = c_t_phys1_1 ;
correct := correct and si_st_phys1_1 = c_st_phys1_1 ;
correct := correct and si_real_1 = c_real_1 ;
correct := correct and si_t_real1_1 = c_t_real1_1 ;
correct := correct and si_st_real1_1 = c_st_real1_1 ;
si_boolean_1 <= c_boolean_2 ;
si_bit_1 <= c_bit_2 ;
si_severity_level_1 <= c_severity_level_2 ;
si_character_1 <= c_character_2 ;
si_t_enum1_1 <= c_t_enum1_2 ;
si_st_enum1_1 <= c_st_enum1_2 ;
si_integer_1 <= c_integer_2 ;
si_t_int1_1 <= c_t_int1_2 ;
si_st_int1_1 <= c_st_int1_2 ;
si_time_1 <= c_time_2 ;
si_t_phys1_1 <= c_t_phys1_2 ;
si_st_phys1_1 <= c_st_phys1_2 ;
si_real_1 <= c_real_2 ;
si_t_real1_1 <= c_t_real1_2 ;
si_st_real1_1 <= c_st_real1_2 ;
synch <= true ;
s_correct <= s_correct and correct ;
wait ;
end process ;
process (synch)
variable correct : boolean ;
begin
correct := s_correct ;
if synch = true then
correct := correct and si_boolean_1 = c_boolean_2 ;
correct := correct and si_bit_1 = c_bit_2 ;
correct := correct and si_severity_level_1 = c_severity_level_2 ;
correct := correct and si_character_1 = c_character_2 ;
correct := correct and si_t_enum1_1 = c_t_enum1_2 ;
correct := correct and si_st_enum1_1 = c_st_enum1_2 ;
correct := correct and si_integer_1 = c_integer_2 ;
correct := correct and si_t_int1_1 = c_t_int1_2 ;
correct := correct and si_st_int1_1 = c_st_int1_2 ;
correct := correct and si_time_1 = c_time_2 ;
correct := correct and si_t_phys1_1 = c_t_phys1_2 ;
correct := correct and si_st_phys1_1 = c_st_phys1_2 ;
correct := correct and si_real_1 = c_real_2 ;
correct := correct and si_t_real1_1 = c_t_real1_2 ;
correct := correct and si_st_real1_1 = c_st_real1_2 ;
test_report ( "ARCH00552" ,
"Signal declarations - scalar static subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00552 ;
--
entity ENT00552_Test_Bench is
end ENT00552_Test_Bench ;
--
architecture ARCH00552_Test_Bench of ENT00552_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00552 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00552_Test_Bench ;
|
package access2 is
type bv_ptr is access bit_vector;
function get_fresh(b : bit_vector) return bv_ptr;
end package;
package body access2 is
function get_fresh(b : bit_vector) return bv_ptr is
begin
return new bit_vector(b'range);
end function;
end package body;
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1669.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01669ent IS
END c09s01b00x00p05n01i01669ent;
ARCHITECTURE c09s01b00x00p05n01i01669arch OF c09s01b00x00p05n01i01669ent IS
BEGIN
B:block
begin
L: loop -- illegal location for loop statement
end loop L;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01669 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01669arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1669.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01669ent IS
END c09s01b00x00p05n01i01669ent;
ARCHITECTURE c09s01b00x00p05n01i01669arch OF c09s01b00x00p05n01i01669ent IS
BEGIN
B:block
begin
L: loop -- illegal location for loop statement
end loop L;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01669 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01669arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1669.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01669ent IS
END c09s01b00x00p05n01i01669ent;
ARCHITECTURE c09s01b00x00p05n01i01669arch OF c09s01b00x00p05n01i01669ent IS
BEGIN
B:block
begin
L: loop -- illegal location for loop statement
end loop L;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01669 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01669arch;
|
-------------------------------------------------------------------------------
-- $Id: xbic_be_reset_gen.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_be_reset_gen - entity / architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_be_reset_gen.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: GAB
--
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from plbv46_slave_burst_V1_00_a library
-- ^^^^^^
--
-- DET 3/6/2007 Reduced latency revision
-- ~~~~~~
-- - Added missing 64-bit case for when C_SMALLEST = 32 and C_NATIVE_DWIDTH=128.
-- this cause bus2ip_be to be driven incorrectly for address offets 0x4,
-- 0x5, 0x6,and 0x7.
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Changed the design to output active low BE reset mask.
-- - Modifed output Mask width to be the full width of the BE bus.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity xbic_be_reset_gen is
generic (
C_NATIVE_DWIDTH : integer := 32;
C_SMALLEST : integer := 32
);
port(
Addr : in std_logic_vector(0 to 1);
MSize : in std_logic_vector(0 to 1);
BE_Sngl_Mask : out std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1)
);
end entity xbic_be_reset_gen;
architecture implementation of xbic_be_reset_gen is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal reset_be_extended : std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1);
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
BE_Sngl_Mask <= not(reset_be_extended);
GEN_FOR_SAME : if C_NATIVE_DWIDTH <= C_SMALLEST generate
reset_be_extended <= (others => '0');
end generate GEN_FOR_SAME;
---------------------
-- 64 Bit Support --
---------------------
GEN_BE_64_32: if C_NATIVE_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(1); --a29
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "00001111";
when others => null;
end case;
when '1' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "11110000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_BE_128_32: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr; -- 24 25 26 27 | 28 29 30 31
reset_be_extended <= (others => '0');
case addr_bits is
when "00" => --0
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "0000111111111111";
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "01" => --4
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111000011111111";
when "01" => -- 64-Bit Master -- GAB 12/22/06
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "10" => --8
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111111100001111";
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when "11" => --C
case MSize is
when "00" => --32-Bit Master
reset_be_extended <= "1111111111110000";
when "01" => --64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_32;
GEN_BE_128_64: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(0);
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when '1' => --8
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_64;
end implementation; -- (architecture)
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top is
port (
Reset : in std_logic; -- Low_level-active asynchronous reset
Clk : in std_logic; -- System clock (20MHz), rising edge used
Data_in : in std_logic_vector(7 downto 0); -- Data to be sent
Valid_D : in std_logic; -- Handshake signal
-- from guest system, low when data is valid
Ack_in : out std_logic; -- ACK for data received, low once data
-- has been stored
TX_RDY : out std_logic; -- System ready to transmit
TD : out std_logic; -- RS232 Transmission line
RD : in std_logic; -- RS232 Reception line
Data_out : out std_logic_vector(7 downto 0); -- Received data
Data_read : in std_logic; -- Data read for guest system
Full : out std_logic; -- Full internal memory
Empty : out std_logic; -- Empty internal memory
FF_Count : out std_logic_vector(5 downto 0)); -- Number of bytes in fifo
end RS232top;
architecture RTL of RS232top is
------------------------------------------------------------------------
-- Components for Transmitter Block
------------------------------------------------------------------------
component RS232_TX
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end component;
------------------------------------------------------------------------
-- Components for Receiver Block
------------------------------------------------------------------------
component ShiftRegister
port (
Reset : in std_logic;
Clk : in std_logic;
Enable : in std_logic;
D : in std_logic;
Q : out std_logic_vector(7 downto 0));
end component;
component RS232_RX
port (
Clk : in std_logic;
Reset : in std_logic;
LineRD_in : in std_logic;
Valid_out : out std_logic;
Code_out : out std_logic;
Store_out : out std_logic);
end component;
component fifo
port (
clk : IN std_logic;
rst : IN std_logic;
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
data_count : OUT std_logic_VECTOR(5 downto 0));
end component;
------------------------------------------------------------------------
-- Internal Signals
------------------------------------------------------------------------
signal Data_FF : std_logic_vector(7 downto 0);
signal StartTX : std_logic; -- start signal for transmitter
signal LineRD_in : std_logic; -- internal RX line
signal Valid_out : std_logic; -- valid bit @ receiver
signal Code_out : std_logic; -- bit @ receiver output
signal sinit : std_logic; -- fifo reset
signal Fifo_in : std_logic_vector(7 downto 0);
signal Fifo_write : std_logic;
signal TX_RDY_i : std_logic;
begin -- RTL
Transmitter: RS232_TX
port map (
Clk => Clk,
Reset => Reset,
Start => StartTX,
Data => Data_FF,
EOT => TX_RDY_i,
TX => TD);
Receiver: RS232_RX
port map (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Fifo_write);
Shift: ShiftRegister
port map (
Reset => Reset,
Clk => Clk,
Enable => Valid_Out,
D => Code_Out,
Q => Fifo_in);
sinit <= not reset;
Internal_memory: fifo
port map (
clk => clk,
rst => sinit,
din => Fifo_in,
wr_en => Fifo_write,
rd_en => Data_read,
dout => Data_out,
full => Full,
empty => Empty,
data_count => FF_Count);
-- purpose: Clocking process for input protocol
Clocking : process (Clk, Reset)
begin
if Reset = '0' then -- asynchronous reset (active low)
Data_FF <= (others => '0');
LineRD_in <= '1';
Ack_in <= '1';
elsif Clk'event and Clk = '1' then -- rising edge clock
LineRD_in <= RD;
if Valid_D = '0' and TX_RDY_i = '1' then
Data_FF <= Data_in;
Ack_in <= '0';
StartTX <= '1';
else
Ack_in <= '1';
StartTX <= '0';
end if;
end if;
end process Clocking;
TX_RDY <= TX_RDY_i;
end RTL;
|
library verilog;
use verilog.vl_types.all;
entity datapath is
port(
clk : in vl_logic;
reset : in vl_logic;
soda_Value : in vl_logic_vector(7 downto 0);
cost : in vl_logic_vector(7 downto 0);
enable_Change : in vl_logic;
enable_Total : in vl_logic;
comp_Greater : out vl_logic;
comp_Smaller : out vl_logic;
comp_Equal : out vl_logic;
final_Total : out vl_logic_vector(7 downto 0);
final_Change : out vl_logic_vector(7 downto 0)
);
end datapath;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2899.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p06n02i02899ent IS
END c02s01b01x00p06n02i02899ent;
ARCHITECTURE c02s01b01x00p06n02i02899arch OF c02s01b01x00p06n02i02899ent IS
signal p: integer := 3;
BEGIN
TESTING: PROCESS
procedure check (variable x:in integer; y:in boolean := true) is
begin
end;
BEGIN
check (p);
assert FALSE
report "***FAILED TEST: c02s01b01x00p06n02i02899 - Class mismatch in procudure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p06n02i02899arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2899.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p06n02i02899ent IS
END c02s01b01x00p06n02i02899ent;
ARCHITECTURE c02s01b01x00p06n02i02899arch OF c02s01b01x00p06n02i02899ent IS
signal p: integer := 3;
BEGIN
TESTING: PROCESS
procedure check (variable x:in integer; y:in boolean := true) is
begin
end;
BEGIN
check (p);
assert FALSE
report "***FAILED TEST: c02s01b01x00p06n02i02899 - Class mismatch in procudure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p06n02i02899arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2899.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p06n02i02899ent IS
END c02s01b01x00p06n02i02899ent;
ARCHITECTURE c02s01b01x00p06n02i02899arch OF c02s01b01x00p06n02i02899ent IS
signal p: integer := 3;
BEGIN
TESTING: PROCESS
procedure check (variable x:in integer; y:in boolean := true) is
begin
end;
BEGIN
check (p);
assert FALSE
report "***FAILED TEST: c02s01b01x00p06n02i02899 - Class mismatch in procudure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p06n02i02899arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_XOR is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_XOR;
----------------------------------------------------------------------------------
architecture Behavioral of Gate_XOR is
begin
Z <= A xor B;
end Behavioral;
|
entity top is
end top;
use std.textio.all;
architecture ARCH of TOP is
type int_vector is array (integer range<>) of integer;
function driver_counter( values : int_vector ) return integer is
variable result : integer := 1;
variable l: line;
begin
for index in values'range loop
if values(index) /= 0 then
result := result + values (index);
write (l, integer'image(values(index)) & ",");
end if;
end loop;
report l.all & " count resolved => " & integer'image(result);
return result;
end function;
signal S1: driver_counter integer := 6;
begin
s1 <= 1 after 1 ns;
check: process
begin
assert s1 = 7 report "resolution function not called at init"
severity failure;
wait for 1 ns;
assert s1 = 2 report "resolution function not called at 1 ns"
severity failure;
wait;
end process;
end architecture;
|
entity top is
end top;
use std.textio.all;
architecture ARCH of TOP is
type int_vector is array (integer range<>) of integer;
function driver_counter( values : int_vector ) return integer is
variable result : integer := 1;
variable l: line;
begin
for index in values'range loop
if values(index) /= 0 then
result := result + values (index);
write (l, integer'image(values(index)) & ",");
end if;
end loop;
report l.all & " count resolved => " & integer'image(result);
return result;
end function;
signal S1: driver_counter integer := 6;
begin
s1 <= 1 after 1 ns;
check: process
begin
assert s1 = 7 report "resolution function not called at init"
severity failure;
wait for 1 ns;
assert s1 = 2 report "resolution function not called at 1 ns"
severity failure;
wait;
end process;
end architecture;
|
entity top is
end top;
use std.textio.all;
architecture ARCH of TOP is
type int_vector is array (integer range<>) of integer;
function driver_counter( values : int_vector ) return integer is
variable result : integer := 1;
variable l: line;
begin
for index in values'range loop
if values(index) /= 0 then
result := result + values (index);
write (l, integer'image(values(index)) & ",");
end if;
end loop;
report l.all & " count resolved => " & integer'image(result);
return result;
end function;
signal S1: driver_counter integer := 6;
begin
s1 <= 1 after 1 ns;
check: process
begin
assert s1 = 7 report "resolution function not called at init"
severity failure;
wait for 1 ns;
assert s1 = 2 report "resolution function not called at 1 ns"
severity failure;
wait;
end process;
end architecture;
|
-- VHDL model of UNNAMED
-- generated by RTeasy
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
-- generic components
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
-- CONTROL UNIT
-- combinatorial circuit for state transition function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_statetrans_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
CONSTANT endstate : std_logic_vector(1 DOWNTO 0) := "11";
END UNNAMED_cu_statetrans_net;
ARCHITECTURE behavioural OF UNNAMED_cu_statetrans_net IS
BEGIN
statetrans: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
NEXTSTATE <= "01";
WHEN "01" =>
NEXTSTATE <= "10";
WHEN "10" => -- LOOP:
IF I(0)='1' THEN -- if FAKTOR <> 0 then goto LOOP fi
NEXTSTATE <= "10";
ELSE
NEXTSTATE <= endstate;
END IF;
WHEN OTHERS =>
NEXTSTATE <= endstate;
END CASE;
END PROCESS;
END behavioural;
-- combinatorial circuit for output function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_output_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END UNNAMED_cu_output_net;
ARCHITECTURE behavioural OF UNNAMED_cu_output_net IS
BEGIN
output: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
C(0) <= '1';
C(1) <= '1';
C(2) <= '0';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "01" =>
C(0) <= '0';
C(1) <= '0';
C(2) <= '1';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "10" => -- LOOP:
C(0) <= '0';
C(1) <= '0';
C(2) <= '0';
-- if FAKTOR <> 0 then ERG <- ERG + A fi
C(3) <= I(0);
-- if FAKTOR <> 0 then FAKTOR <- FAKTOR - 1 fi
C(4) <= I(0);
-- if not FAKTOR <> 0 then OUTBUS <- ERG fi
C(5) <= NOT (I(0));
WHEN OTHERS =>
C <= (OTHERS => '0');
END CASE;
END PROCESS;
END behavioural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO 5);
I : IN std_logic_vector(0 TO 0)
);
END UNNAMED_cu;
ARCHITECTURE struct OF UNNAMED_cu IS
SIGNAL I_BUFFERED : std_logic_vector(0 TO 0);
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL STATE, NEXTSTATE : std_logic_vector(1 DOWNTO 0);
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
COMPONENT UNNAMED_cu_statetrans_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_statetrans_net USE ENTITY
WORK.UNNAMED_cu_statetrans_net(behavioural);
COMPONENT UNNAMED_cu_output_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_output_net USE ENTITY
WORK.UNNAMED_cu_output_net(behavioural);
BEGIN
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => 1, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => 2, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: UNNAMED_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: UNNAMED_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
END struct;
-- OPERATION UNIT
-- circuits realizing register-transfer operations
-- realization of RT operation A <- INBUS
-- triggered by control signal C(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C0_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C0_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C0_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- 0
-- triggered by control signal C(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C1_circuit IS
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C1_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C1_circuit IS
BEGIN
-- 0
OUTPUT <= "00000000";
END primitive;
-- realization of RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C2_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C2_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C2_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- ERG + A
-- triggered by control signal C(3)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C3_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C3_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C3_circuit IS
BEGIN
-- ERG + A
OUTPUT <= ("0" & reg_ERG_out_0_7(0 TO 7)) + ("0" & reg_A_out_0_7(0 TO 7));
END primitive;
-- realization of RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C4_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C4_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C4_circuit IS
BEGIN
-- FAKTOR - 1
OUTPUT <= ("0" & reg_FAKTOR_out_0_7(0 TO 7)) + ((not ("000000001")) + "000000001");
END primitive;
-- realization of RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C5_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C5_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C5_circuit IS
BEGIN
-- ERG
OUTPUT <= reg_ERG_out_0_7(0 TO 7);
END primitive;
-- circuits realizing conditions
-- realization of condition FAKTOR <> 0
-- driving condition signal I(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_cond_I0_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END UNNAMED_cond_I0_circuit;
ARCHITECTURE primitive OF UNNAMED_cond_I0_circuit IS
BEGIN
-- FAKTOR <> 0
OUTPUT <= signed_ne(("0" & reg_FAKTOR_out_0_7(0 TO 7)), ("000000000"), 8);
END primitive;
-- register logic circuits
-- register logic for A
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_A_logic_circuit IS
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_A_logic_circuit;
ARCHITECTURE primitive OF reg_A_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C0_out_7_0(7) WHEN C0 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C0_out_7_0(6) WHEN C0 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C0_out_7_0(5) WHEN C0 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C0_out_7_0(4) WHEN C0 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C0_out_7_0(3) WHEN C0 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C0_out_7_0(2) WHEN C0 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C0_out_7_0(1) WHEN C0 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C0_out_7_0(0) WHEN C0 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for ERG
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_ERG_logic_circuit IS
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_ERG_logic_circuit;
ARCHITECTURE primitive OF reg_ERG_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C1_out_7_0(7) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(7) WHEN C3 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C1_out_7_0(6) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(6) WHEN C3 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C1_out_7_0(5) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(5) WHEN C3 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C1_out_7_0(4) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(4) WHEN C3 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C1_out_7_0(3) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(3) WHEN C3 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C1_out_7_0(2) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(2) WHEN C3 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C1_out_7_0(1) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(1) WHEN C3 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C1_out_7_0(0) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(0) WHEN C3 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for FAKTOR
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_FAKTOR_logic_circuit IS
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_FAKTOR_logic_circuit;
ARCHITECTURE primitive OF reg_FAKTOR_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C2_out_7_0(7) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(7) WHEN C4 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C2_out_7_0(6) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(6) WHEN C4 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C2_out_7_0(5) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(5) WHEN C4 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C2_out_7_0(4) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(4) WHEN C4 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C2_out_7_0(3) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(3) WHEN C4 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C2_out_7_0(2) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(2) WHEN C4 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C2_out_7_0(1) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(1) WHEN C4 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C2_out_7_0(0) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(0) WHEN C4 = '1'
ELSE FROM_reg(7);
END primitive;
-- bus zero driver logic circuits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for OUTBUS
ENTITY bus_OUTBUS_zero_driver_logic_circuit IS
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_OUTBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_OUTBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(1) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(2) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(3) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(4) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(5) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(6) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(7) <= '0' WHEN NOT C5='1' ELSE 'Z';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for INBUS
ENTITY bus_INBUS_zero_driver_logic_circuit IS
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_INBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_INBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0';
TO_bus(1) <= '0';
TO_bus(2) <= '0';
TO_bus(3) <= '0';
TO_bus(4) <= '0';
TO_bus(5) <= '0';
TO_bus(6) <= '0';
TO_bus(7) <= '0';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_ou IS
PORT(
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 TO 5);
I : OUT std_logic_vector(0 TO 0)
);
END UNNAMED_ou;
ARCHITECTURE struct OF UNNAMED_ou IS
-- signal declarations
SIGNAL CLK_SIG, RESET_SIG : std_logic;
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL I0 : std_logic_vector(0 DOWNTO 0);
SIGNAL bus_OUTBUS : std_logic_vector (0 TO 7);
SIGNAL bus_INBUS : std_logic_vector (0 TO 7);
SIGNAL reg_A_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_A_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_ERG_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_ERG_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_FAKTOR_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_FAKTOR_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
-- D-flipflop register component declaration
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
-- register logic component declarations
COMPONENT reg_A_logic_circuit
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_A_logic_circuit USE ENTITY WORK.reg_A_logic_circuit(primitive);
COMPONENT reg_ERG_logic_circuit
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_ERG_logic_circuit USE ENTITY WORK.reg_ERG_logic_circuit(primitive);
COMPONENT reg_FAKTOR_logic_circuit
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_FAKTOR_logic_circuit USE ENTITY WORK.reg_FAKTOR_logic_circuit(primitive);
-- bus zero driver logic component declarations
COMPONENT bus_OUTBUS_zero_driver_logic_circuit
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_OUTBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_OUTBUS_zero_driver_logic_circuit(primitive);
COMPONENT bus_INBUS_zero_driver_logic_circuit
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_INBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_INBUS_zero_driver_logic_circuit(primitive);
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
-- function for input forcing (to 0 and 1)
FUNCTION forceSL (b : std_logic) RETURN std_logic IS
BEGIN
CASE b IS
WHEN '1'|'H' => RETURN '1';
WHEN OTHERS => RETURN '0';
END CASE;
END forceSL;
-- declarations for register-transfer circuits and signals
-- RT operation A <- INBUS
-- triggered by control signal C(0)
SIGNAL rtop_C0_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C0_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C0_circuit USE ENTITY WORK.UNNAMED_rtop_C0_circuit(primitive);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
SIGNAL rtop_C1_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C1_circuit
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C1_circuit USE ENTITY WORK.UNNAMED_rtop_C1_circuit(primitive);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
SIGNAL rtop_C2_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C2_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C2_circuit USE ENTITY WORK.UNNAMED_rtop_C2_circuit(primitive);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
SIGNAL rtop_C3_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C3_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C3_circuit USE ENTITY WORK.UNNAMED_rtop_C3_circuit(primitive);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
SIGNAL rtop_C4_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C4_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C4_circuit USE ENTITY WORK.UNNAMED_rtop_C4_circuit(primitive);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
SIGNAL rtop_C5_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C5_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C5_circuit USE ENTITY WORK.UNNAMED_rtop_C5_circuit(primitive);
-- COMPONENT declarations for condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
COMPONENT UNNAMED_cond_I0_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cond_I0_circuit USE ENTITY WORK.UNNAMED_cond_I0_circuit(primitive);
BEGIN
CLK_SIG <= CLK; RESET_SIG <= RESET; C_SIG <= C;
-- register logic instantiations
-- register A
-- component instantiation for register A
reg_A: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_A_in,
OUTPUT => reg_A_out);
reg_A_logic: reg_A_logic_circuit
PORT MAP(
C0 => C_SIG(0),
rtop_C0_out_7_0 => rtop_C0_out(7 DOWNTO 0),
FROM_reg => reg_A_out,
TO_reg => reg_A_in);
-- register ERG
-- component instantiation for register ERG
reg_ERG: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_ERG_in,
OUTPUT => reg_ERG_out);
reg_ERG_logic: reg_ERG_logic_circuit
PORT MAP(
C1 => C_SIG(1),
C3 => C_SIG(3),
rtop_C1_out_7_0 => rtop_C1_out(7 DOWNTO 0),
rtop_C3_out_7_0 => rtop_C3_out(7 DOWNTO 0),
FROM_reg => reg_ERG_out,
TO_reg => reg_ERG_in);
-- register FAKTOR
-- component instantiation for register FAKTOR
reg_FAKTOR: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_FAKTOR_in,
OUTPUT => reg_FAKTOR_out);
reg_FAKTOR_logic: reg_FAKTOR_logic_circuit
PORT MAP(
C2 => C_SIG(2),
C4 => C_SIG(4),
rtop_C2_out_7_0 => rtop_C2_out(7 DOWNTO 0),
rtop_C4_out_7_0 => rtop_C4_out(7 DOWNTO 0),
FROM_reg => reg_FAKTOR_out,
TO_reg => reg_FAKTOR_in);
-- bus zero driver logic logic instantiations
bus_OUTBUS_zero_driver_logic: bus_OUTBUS_zero_driver_logic_circuit
PORT MAP(
C5 => C_SIG(5),
TO_bus => bus_OUTBUS);
bus_INBUS_zero_driver_logic: bus_INBUS_zero_driver_logic_circuit
PORT MAP(
TO_bus => bus_INBUS);
-- instantiations for register-transfer circuits
-- RT operation A <- INBUS
-- triggered by control signal C(0)
rtop_C0: UNNAMED_rtop_C0_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C0_out);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
rtop_C1: UNNAMED_rtop_C1_circuit
PORT MAP(
OUTPUT => rtop_C1_out);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
rtop_C2: UNNAMED_rtop_C2_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C2_out);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
rtop_C3: UNNAMED_rtop_C3_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
reg_A_out_0_7 => reg_A_out(0 TO 7),
OUTPUT => rtop_C3_out);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
rtop_C4: UNNAMED_rtop_C4_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_out(0 TO 7),
OUTPUT => rtop_C4_out);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
rtop_C5: UNNAMED_rtop_C5_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
OUTPUT => rtop_C5_out);
tristate_OUTBUS_0_7_C5: tristate
GENERIC MAP(width => 8)
PORT MAP(
ENABLE => C(5),
INPUT => rtop_C5_out(7 DOWNTO 0),
OUTPUT => bus_OUTBUS(0 TO 7));
-- instantiations of condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
I(0) <= I0(0);
cond_I0: UNNAMED_cond_I0_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_in(0 TO 7),
OUTPUT => I0);
END struct;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED IS
PORT(
CLK, RESET : IN std_logic
);
END UNNAMED;
ARCHITECTURE struct OF UNNAMED IS
SIGNAL CLK_SIGNAL, RESET_SIGNAL : std_logic;
SIGNAL C : std_logic_vector(0 to 5);
SIGNAL I : std_logic_vector(0 to 0);
COMPONENT UNNAMED_cu
PORT (
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 to 5);
I : IN std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu USE ENTITY WORK.UNNAMED_cu(struct);
COMPONENT UNNAMED_ou
PORT (
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 to 5);
I : OUT std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_ou USE ENTITY WORK.UNNAMED_ou(struct);
BEGIN
CLK_SIGNAL <= CLK;
RESET_SIGNAL <= RESET;
Control_Unit: UNNAMED_cu
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
Operation_Unit: UNNAMED_ou
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
END struct;
|
-- VHDL model of UNNAMED
-- generated by RTeasy
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
-- generic components
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
-- CONTROL UNIT
-- combinatorial circuit for state transition function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_statetrans_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
CONSTANT endstate : std_logic_vector(1 DOWNTO 0) := "11";
END UNNAMED_cu_statetrans_net;
ARCHITECTURE behavioural OF UNNAMED_cu_statetrans_net IS
BEGIN
statetrans: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
NEXTSTATE <= "01";
WHEN "01" =>
NEXTSTATE <= "10";
WHEN "10" => -- LOOP:
IF I(0)='1' THEN -- if FAKTOR <> 0 then goto LOOP fi
NEXTSTATE <= "10";
ELSE
NEXTSTATE <= endstate;
END IF;
WHEN OTHERS =>
NEXTSTATE <= endstate;
END CASE;
END PROCESS;
END behavioural;
-- combinatorial circuit for output function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_output_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END UNNAMED_cu_output_net;
ARCHITECTURE behavioural OF UNNAMED_cu_output_net IS
BEGIN
output: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
C(0) <= '1';
C(1) <= '1';
C(2) <= '0';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "01" =>
C(0) <= '0';
C(1) <= '0';
C(2) <= '1';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "10" => -- LOOP:
C(0) <= '0';
C(1) <= '0';
C(2) <= '0';
-- if FAKTOR <> 0 then ERG <- ERG + A fi
C(3) <= I(0);
-- if FAKTOR <> 0 then FAKTOR <- FAKTOR - 1 fi
C(4) <= I(0);
-- if not FAKTOR <> 0 then OUTBUS <- ERG fi
C(5) <= NOT (I(0));
WHEN OTHERS =>
C <= (OTHERS => '0');
END CASE;
END PROCESS;
END behavioural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO 5);
I : IN std_logic_vector(0 TO 0)
);
END UNNAMED_cu;
ARCHITECTURE struct OF UNNAMED_cu IS
SIGNAL I_BUFFERED : std_logic_vector(0 TO 0);
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL STATE, NEXTSTATE : std_logic_vector(1 DOWNTO 0);
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
COMPONENT UNNAMED_cu_statetrans_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_statetrans_net USE ENTITY
WORK.UNNAMED_cu_statetrans_net(behavioural);
COMPONENT UNNAMED_cu_output_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_output_net USE ENTITY
WORK.UNNAMED_cu_output_net(behavioural);
BEGIN
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => 1, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => 2, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: UNNAMED_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: UNNAMED_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
END struct;
-- OPERATION UNIT
-- circuits realizing register-transfer operations
-- realization of RT operation A <- INBUS
-- triggered by control signal C(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C0_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C0_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C0_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- 0
-- triggered by control signal C(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C1_circuit IS
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C1_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C1_circuit IS
BEGIN
-- 0
OUTPUT <= "00000000";
END primitive;
-- realization of RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C2_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C2_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C2_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- ERG + A
-- triggered by control signal C(3)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C3_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C3_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C3_circuit IS
BEGIN
-- ERG + A
OUTPUT <= ("0" & reg_ERG_out_0_7(0 TO 7)) + ("0" & reg_A_out_0_7(0 TO 7));
END primitive;
-- realization of RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C4_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C4_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C4_circuit IS
BEGIN
-- FAKTOR - 1
OUTPUT <= ("0" & reg_FAKTOR_out_0_7(0 TO 7)) + ((not ("000000001")) + "000000001");
END primitive;
-- realization of RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C5_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C5_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C5_circuit IS
BEGIN
-- ERG
OUTPUT <= reg_ERG_out_0_7(0 TO 7);
END primitive;
-- circuits realizing conditions
-- realization of condition FAKTOR <> 0
-- driving condition signal I(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_cond_I0_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END UNNAMED_cond_I0_circuit;
ARCHITECTURE primitive OF UNNAMED_cond_I0_circuit IS
BEGIN
-- FAKTOR <> 0
OUTPUT <= signed_ne(("0" & reg_FAKTOR_out_0_7(0 TO 7)), ("000000000"), 8);
END primitive;
-- register logic circuits
-- register logic for A
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_A_logic_circuit IS
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_A_logic_circuit;
ARCHITECTURE primitive OF reg_A_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C0_out_7_0(7) WHEN C0 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C0_out_7_0(6) WHEN C0 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C0_out_7_0(5) WHEN C0 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C0_out_7_0(4) WHEN C0 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C0_out_7_0(3) WHEN C0 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C0_out_7_0(2) WHEN C0 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C0_out_7_0(1) WHEN C0 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C0_out_7_0(0) WHEN C0 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for ERG
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_ERG_logic_circuit IS
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_ERG_logic_circuit;
ARCHITECTURE primitive OF reg_ERG_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C1_out_7_0(7) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(7) WHEN C3 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C1_out_7_0(6) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(6) WHEN C3 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C1_out_7_0(5) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(5) WHEN C3 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C1_out_7_0(4) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(4) WHEN C3 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C1_out_7_0(3) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(3) WHEN C3 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C1_out_7_0(2) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(2) WHEN C3 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C1_out_7_0(1) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(1) WHEN C3 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C1_out_7_0(0) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(0) WHEN C3 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for FAKTOR
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_FAKTOR_logic_circuit IS
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_FAKTOR_logic_circuit;
ARCHITECTURE primitive OF reg_FAKTOR_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C2_out_7_0(7) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(7) WHEN C4 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C2_out_7_0(6) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(6) WHEN C4 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C2_out_7_0(5) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(5) WHEN C4 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C2_out_7_0(4) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(4) WHEN C4 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C2_out_7_0(3) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(3) WHEN C4 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C2_out_7_0(2) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(2) WHEN C4 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C2_out_7_0(1) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(1) WHEN C4 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C2_out_7_0(0) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(0) WHEN C4 = '1'
ELSE FROM_reg(7);
END primitive;
-- bus zero driver logic circuits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for OUTBUS
ENTITY bus_OUTBUS_zero_driver_logic_circuit IS
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_OUTBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_OUTBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(1) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(2) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(3) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(4) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(5) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(6) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(7) <= '0' WHEN NOT C5='1' ELSE 'Z';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for INBUS
ENTITY bus_INBUS_zero_driver_logic_circuit IS
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_INBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_INBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0';
TO_bus(1) <= '0';
TO_bus(2) <= '0';
TO_bus(3) <= '0';
TO_bus(4) <= '0';
TO_bus(5) <= '0';
TO_bus(6) <= '0';
TO_bus(7) <= '0';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_ou IS
PORT(
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 TO 5);
I : OUT std_logic_vector(0 TO 0)
);
END UNNAMED_ou;
ARCHITECTURE struct OF UNNAMED_ou IS
-- signal declarations
SIGNAL CLK_SIG, RESET_SIG : std_logic;
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL I0 : std_logic_vector(0 DOWNTO 0);
SIGNAL bus_OUTBUS : std_logic_vector (0 TO 7);
SIGNAL bus_INBUS : std_logic_vector (0 TO 7);
SIGNAL reg_A_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_A_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_ERG_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_ERG_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_FAKTOR_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_FAKTOR_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
-- D-flipflop register component declaration
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
-- register logic component declarations
COMPONENT reg_A_logic_circuit
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_A_logic_circuit USE ENTITY WORK.reg_A_logic_circuit(primitive);
COMPONENT reg_ERG_logic_circuit
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_ERG_logic_circuit USE ENTITY WORK.reg_ERG_logic_circuit(primitive);
COMPONENT reg_FAKTOR_logic_circuit
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_FAKTOR_logic_circuit USE ENTITY WORK.reg_FAKTOR_logic_circuit(primitive);
-- bus zero driver logic component declarations
COMPONENT bus_OUTBUS_zero_driver_logic_circuit
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_OUTBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_OUTBUS_zero_driver_logic_circuit(primitive);
COMPONENT bus_INBUS_zero_driver_logic_circuit
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_INBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_INBUS_zero_driver_logic_circuit(primitive);
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
-- function for input forcing (to 0 and 1)
FUNCTION forceSL (b : std_logic) RETURN std_logic IS
BEGIN
CASE b IS
WHEN '1'|'H' => RETURN '1';
WHEN OTHERS => RETURN '0';
END CASE;
END forceSL;
-- declarations for register-transfer circuits and signals
-- RT operation A <- INBUS
-- triggered by control signal C(0)
SIGNAL rtop_C0_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C0_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C0_circuit USE ENTITY WORK.UNNAMED_rtop_C0_circuit(primitive);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
SIGNAL rtop_C1_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C1_circuit
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C1_circuit USE ENTITY WORK.UNNAMED_rtop_C1_circuit(primitive);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
SIGNAL rtop_C2_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C2_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C2_circuit USE ENTITY WORK.UNNAMED_rtop_C2_circuit(primitive);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
SIGNAL rtop_C3_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C3_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C3_circuit USE ENTITY WORK.UNNAMED_rtop_C3_circuit(primitive);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
SIGNAL rtop_C4_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C4_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C4_circuit USE ENTITY WORK.UNNAMED_rtop_C4_circuit(primitive);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
SIGNAL rtop_C5_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C5_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C5_circuit USE ENTITY WORK.UNNAMED_rtop_C5_circuit(primitive);
-- COMPONENT declarations for condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
COMPONENT UNNAMED_cond_I0_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cond_I0_circuit USE ENTITY WORK.UNNAMED_cond_I0_circuit(primitive);
BEGIN
CLK_SIG <= CLK; RESET_SIG <= RESET; C_SIG <= C;
-- register logic instantiations
-- register A
-- component instantiation for register A
reg_A: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_A_in,
OUTPUT => reg_A_out);
reg_A_logic: reg_A_logic_circuit
PORT MAP(
C0 => C_SIG(0),
rtop_C0_out_7_0 => rtop_C0_out(7 DOWNTO 0),
FROM_reg => reg_A_out,
TO_reg => reg_A_in);
-- register ERG
-- component instantiation for register ERG
reg_ERG: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_ERG_in,
OUTPUT => reg_ERG_out);
reg_ERG_logic: reg_ERG_logic_circuit
PORT MAP(
C1 => C_SIG(1),
C3 => C_SIG(3),
rtop_C1_out_7_0 => rtop_C1_out(7 DOWNTO 0),
rtop_C3_out_7_0 => rtop_C3_out(7 DOWNTO 0),
FROM_reg => reg_ERG_out,
TO_reg => reg_ERG_in);
-- register FAKTOR
-- component instantiation for register FAKTOR
reg_FAKTOR: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_FAKTOR_in,
OUTPUT => reg_FAKTOR_out);
reg_FAKTOR_logic: reg_FAKTOR_logic_circuit
PORT MAP(
C2 => C_SIG(2),
C4 => C_SIG(4),
rtop_C2_out_7_0 => rtop_C2_out(7 DOWNTO 0),
rtop_C4_out_7_0 => rtop_C4_out(7 DOWNTO 0),
FROM_reg => reg_FAKTOR_out,
TO_reg => reg_FAKTOR_in);
-- bus zero driver logic logic instantiations
bus_OUTBUS_zero_driver_logic: bus_OUTBUS_zero_driver_logic_circuit
PORT MAP(
C5 => C_SIG(5),
TO_bus => bus_OUTBUS);
bus_INBUS_zero_driver_logic: bus_INBUS_zero_driver_logic_circuit
PORT MAP(
TO_bus => bus_INBUS);
-- instantiations for register-transfer circuits
-- RT operation A <- INBUS
-- triggered by control signal C(0)
rtop_C0: UNNAMED_rtop_C0_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C0_out);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
rtop_C1: UNNAMED_rtop_C1_circuit
PORT MAP(
OUTPUT => rtop_C1_out);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
rtop_C2: UNNAMED_rtop_C2_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C2_out);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
rtop_C3: UNNAMED_rtop_C3_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
reg_A_out_0_7 => reg_A_out(0 TO 7),
OUTPUT => rtop_C3_out);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
rtop_C4: UNNAMED_rtop_C4_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_out(0 TO 7),
OUTPUT => rtop_C4_out);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
rtop_C5: UNNAMED_rtop_C5_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
OUTPUT => rtop_C5_out);
tristate_OUTBUS_0_7_C5: tristate
GENERIC MAP(width => 8)
PORT MAP(
ENABLE => C(5),
INPUT => rtop_C5_out(7 DOWNTO 0),
OUTPUT => bus_OUTBUS(0 TO 7));
-- instantiations of condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
I(0) <= I0(0);
cond_I0: UNNAMED_cond_I0_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_in(0 TO 7),
OUTPUT => I0);
END struct;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED IS
PORT(
CLK, RESET : IN std_logic
);
END UNNAMED;
ARCHITECTURE struct OF UNNAMED IS
SIGNAL CLK_SIGNAL, RESET_SIGNAL : std_logic;
SIGNAL C : std_logic_vector(0 to 5);
SIGNAL I : std_logic_vector(0 to 0);
COMPONENT UNNAMED_cu
PORT (
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 to 5);
I : IN std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu USE ENTITY WORK.UNNAMED_cu(struct);
COMPONENT UNNAMED_ou
PORT (
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 to 5);
I : OUT std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_ou USE ENTITY WORK.UNNAMED_ou(struct);
BEGIN
CLK_SIGNAL <= CLK;
RESET_SIGNAL <= RESET;
Control_Unit: UNNAMED_cu
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
Operation_Unit: UNNAMED_ou
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
END struct;
|
-- VHDL model of UNNAMED
-- generated by RTeasy
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
-- generic components
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
-- CONTROL UNIT
-- combinatorial circuit for state transition function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_statetrans_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
CONSTANT endstate : std_logic_vector(1 DOWNTO 0) := "11";
END UNNAMED_cu_statetrans_net;
ARCHITECTURE behavioural OF UNNAMED_cu_statetrans_net IS
BEGIN
statetrans: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
NEXTSTATE <= "01";
WHEN "01" =>
NEXTSTATE <= "10";
WHEN "10" => -- LOOP:
IF I(0)='1' THEN -- if FAKTOR <> 0 then goto LOOP fi
NEXTSTATE <= "10";
ELSE
NEXTSTATE <= endstate;
END IF;
WHEN OTHERS =>
NEXTSTATE <= endstate;
END CASE;
END PROCESS;
END behavioural;
-- combinatorial circuit for output function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_output_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END UNNAMED_cu_output_net;
ARCHITECTURE behavioural OF UNNAMED_cu_output_net IS
BEGIN
output: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
C(0) <= '1';
C(1) <= '1';
C(2) <= '0';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "01" =>
C(0) <= '0';
C(1) <= '0';
C(2) <= '1';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "10" => -- LOOP:
C(0) <= '0';
C(1) <= '0';
C(2) <= '0';
-- if FAKTOR <> 0 then ERG <- ERG + A fi
C(3) <= I(0);
-- if FAKTOR <> 0 then FAKTOR <- FAKTOR - 1 fi
C(4) <= I(0);
-- if not FAKTOR <> 0 then OUTBUS <- ERG fi
C(5) <= NOT (I(0));
WHEN OTHERS =>
C <= (OTHERS => '0');
END CASE;
END PROCESS;
END behavioural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO 5);
I : IN std_logic_vector(0 TO 0)
);
END UNNAMED_cu;
ARCHITECTURE struct OF UNNAMED_cu IS
SIGNAL I_BUFFERED : std_logic_vector(0 TO 0);
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL STATE, NEXTSTATE : std_logic_vector(1 DOWNTO 0);
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
COMPONENT UNNAMED_cu_statetrans_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_statetrans_net USE ENTITY
WORK.UNNAMED_cu_statetrans_net(behavioural);
COMPONENT UNNAMED_cu_output_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_output_net USE ENTITY
WORK.UNNAMED_cu_output_net(behavioural);
BEGIN
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => 1, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => 2, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: UNNAMED_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: UNNAMED_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
END struct;
-- OPERATION UNIT
-- circuits realizing register-transfer operations
-- realization of RT operation A <- INBUS
-- triggered by control signal C(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C0_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C0_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C0_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- 0
-- triggered by control signal C(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C1_circuit IS
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C1_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C1_circuit IS
BEGIN
-- 0
OUTPUT <= "00000000";
END primitive;
-- realization of RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C2_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C2_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C2_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- ERG + A
-- triggered by control signal C(3)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C3_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C3_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C3_circuit IS
BEGIN
-- ERG + A
OUTPUT <= ("0" & reg_ERG_out_0_7(0 TO 7)) + ("0" & reg_A_out_0_7(0 TO 7));
END primitive;
-- realization of RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C4_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C4_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C4_circuit IS
BEGIN
-- FAKTOR - 1
OUTPUT <= ("0" & reg_FAKTOR_out_0_7(0 TO 7)) + ((not ("000000001")) + "000000001");
END primitive;
-- realization of RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C5_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C5_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C5_circuit IS
BEGIN
-- ERG
OUTPUT <= reg_ERG_out_0_7(0 TO 7);
END primitive;
-- circuits realizing conditions
-- realization of condition FAKTOR <> 0
-- driving condition signal I(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_cond_I0_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END UNNAMED_cond_I0_circuit;
ARCHITECTURE primitive OF UNNAMED_cond_I0_circuit IS
BEGIN
-- FAKTOR <> 0
OUTPUT <= signed_ne(("0" & reg_FAKTOR_out_0_7(0 TO 7)), ("000000000"), 8);
END primitive;
-- register logic circuits
-- register logic for A
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_A_logic_circuit IS
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_A_logic_circuit;
ARCHITECTURE primitive OF reg_A_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C0_out_7_0(7) WHEN C0 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C0_out_7_0(6) WHEN C0 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C0_out_7_0(5) WHEN C0 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C0_out_7_0(4) WHEN C0 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C0_out_7_0(3) WHEN C0 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C0_out_7_0(2) WHEN C0 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C0_out_7_0(1) WHEN C0 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C0_out_7_0(0) WHEN C0 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for ERG
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_ERG_logic_circuit IS
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_ERG_logic_circuit;
ARCHITECTURE primitive OF reg_ERG_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C1_out_7_0(7) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(7) WHEN C3 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C1_out_7_0(6) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(6) WHEN C3 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C1_out_7_0(5) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(5) WHEN C3 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C1_out_7_0(4) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(4) WHEN C3 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C1_out_7_0(3) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(3) WHEN C3 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C1_out_7_0(2) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(2) WHEN C3 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C1_out_7_0(1) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(1) WHEN C3 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C1_out_7_0(0) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(0) WHEN C3 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for FAKTOR
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_FAKTOR_logic_circuit IS
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_FAKTOR_logic_circuit;
ARCHITECTURE primitive OF reg_FAKTOR_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C2_out_7_0(7) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(7) WHEN C4 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C2_out_7_0(6) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(6) WHEN C4 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C2_out_7_0(5) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(5) WHEN C4 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C2_out_7_0(4) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(4) WHEN C4 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C2_out_7_0(3) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(3) WHEN C4 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C2_out_7_0(2) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(2) WHEN C4 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C2_out_7_0(1) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(1) WHEN C4 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C2_out_7_0(0) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(0) WHEN C4 = '1'
ELSE FROM_reg(7);
END primitive;
-- bus zero driver logic circuits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for OUTBUS
ENTITY bus_OUTBUS_zero_driver_logic_circuit IS
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_OUTBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_OUTBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(1) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(2) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(3) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(4) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(5) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(6) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(7) <= '0' WHEN NOT C5='1' ELSE 'Z';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for INBUS
ENTITY bus_INBUS_zero_driver_logic_circuit IS
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_INBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_INBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0';
TO_bus(1) <= '0';
TO_bus(2) <= '0';
TO_bus(3) <= '0';
TO_bus(4) <= '0';
TO_bus(5) <= '0';
TO_bus(6) <= '0';
TO_bus(7) <= '0';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_ou IS
PORT(
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 TO 5);
I : OUT std_logic_vector(0 TO 0)
);
END UNNAMED_ou;
ARCHITECTURE struct OF UNNAMED_ou IS
-- signal declarations
SIGNAL CLK_SIG, RESET_SIG : std_logic;
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL I0 : std_logic_vector(0 DOWNTO 0);
SIGNAL bus_OUTBUS : std_logic_vector (0 TO 7);
SIGNAL bus_INBUS : std_logic_vector (0 TO 7);
SIGNAL reg_A_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_A_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_ERG_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_ERG_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_FAKTOR_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_FAKTOR_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
-- D-flipflop register component declaration
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
-- register logic component declarations
COMPONENT reg_A_logic_circuit
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_A_logic_circuit USE ENTITY WORK.reg_A_logic_circuit(primitive);
COMPONENT reg_ERG_logic_circuit
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_ERG_logic_circuit USE ENTITY WORK.reg_ERG_logic_circuit(primitive);
COMPONENT reg_FAKTOR_logic_circuit
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_FAKTOR_logic_circuit USE ENTITY WORK.reg_FAKTOR_logic_circuit(primitive);
-- bus zero driver logic component declarations
COMPONENT bus_OUTBUS_zero_driver_logic_circuit
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_OUTBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_OUTBUS_zero_driver_logic_circuit(primitive);
COMPONENT bus_INBUS_zero_driver_logic_circuit
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_INBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_INBUS_zero_driver_logic_circuit(primitive);
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
-- function for input forcing (to 0 and 1)
FUNCTION forceSL (b : std_logic) RETURN std_logic IS
BEGIN
CASE b IS
WHEN '1'|'H' => RETURN '1';
WHEN OTHERS => RETURN '0';
END CASE;
END forceSL;
-- declarations for register-transfer circuits and signals
-- RT operation A <- INBUS
-- triggered by control signal C(0)
SIGNAL rtop_C0_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C0_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C0_circuit USE ENTITY WORK.UNNAMED_rtop_C0_circuit(primitive);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
SIGNAL rtop_C1_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C1_circuit
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C1_circuit USE ENTITY WORK.UNNAMED_rtop_C1_circuit(primitive);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
SIGNAL rtop_C2_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C2_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C2_circuit USE ENTITY WORK.UNNAMED_rtop_C2_circuit(primitive);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
SIGNAL rtop_C3_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C3_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C3_circuit USE ENTITY WORK.UNNAMED_rtop_C3_circuit(primitive);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
SIGNAL rtop_C4_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C4_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C4_circuit USE ENTITY WORK.UNNAMED_rtop_C4_circuit(primitive);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
SIGNAL rtop_C5_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C5_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C5_circuit USE ENTITY WORK.UNNAMED_rtop_C5_circuit(primitive);
-- COMPONENT declarations for condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
COMPONENT UNNAMED_cond_I0_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cond_I0_circuit USE ENTITY WORK.UNNAMED_cond_I0_circuit(primitive);
BEGIN
CLK_SIG <= CLK; RESET_SIG <= RESET; C_SIG <= C;
-- register logic instantiations
-- register A
-- component instantiation for register A
reg_A: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_A_in,
OUTPUT => reg_A_out);
reg_A_logic: reg_A_logic_circuit
PORT MAP(
C0 => C_SIG(0),
rtop_C0_out_7_0 => rtop_C0_out(7 DOWNTO 0),
FROM_reg => reg_A_out,
TO_reg => reg_A_in);
-- register ERG
-- component instantiation for register ERG
reg_ERG: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_ERG_in,
OUTPUT => reg_ERG_out);
reg_ERG_logic: reg_ERG_logic_circuit
PORT MAP(
C1 => C_SIG(1),
C3 => C_SIG(3),
rtop_C1_out_7_0 => rtop_C1_out(7 DOWNTO 0),
rtop_C3_out_7_0 => rtop_C3_out(7 DOWNTO 0),
FROM_reg => reg_ERG_out,
TO_reg => reg_ERG_in);
-- register FAKTOR
-- component instantiation for register FAKTOR
reg_FAKTOR: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_FAKTOR_in,
OUTPUT => reg_FAKTOR_out);
reg_FAKTOR_logic: reg_FAKTOR_logic_circuit
PORT MAP(
C2 => C_SIG(2),
C4 => C_SIG(4),
rtop_C2_out_7_0 => rtop_C2_out(7 DOWNTO 0),
rtop_C4_out_7_0 => rtop_C4_out(7 DOWNTO 0),
FROM_reg => reg_FAKTOR_out,
TO_reg => reg_FAKTOR_in);
-- bus zero driver logic logic instantiations
bus_OUTBUS_zero_driver_logic: bus_OUTBUS_zero_driver_logic_circuit
PORT MAP(
C5 => C_SIG(5),
TO_bus => bus_OUTBUS);
bus_INBUS_zero_driver_logic: bus_INBUS_zero_driver_logic_circuit
PORT MAP(
TO_bus => bus_INBUS);
-- instantiations for register-transfer circuits
-- RT operation A <- INBUS
-- triggered by control signal C(0)
rtop_C0: UNNAMED_rtop_C0_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C0_out);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
rtop_C1: UNNAMED_rtop_C1_circuit
PORT MAP(
OUTPUT => rtop_C1_out);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
rtop_C2: UNNAMED_rtop_C2_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C2_out);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
rtop_C3: UNNAMED_rtop_C3_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
reg_A_out_0_7 => reg_A_out(0 TO 7),
OUTPUT => rtop_C3_out);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
rtop_C4: UNNAMED_rtop_C4_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_out(0 TO 7),
OUTPUT => rtop_C4_out);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
rtop_C5: UNNAMED_rtop_C5_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
OUTPUT => rtop_C5_out);
tristate_OUTBUS_0_7_C5: tristate
GENERIC MAP(width => 8)
PORT MAP(
ENABLE => C(5),
INPUT => rtop_C5_out(7 DOWNTO 0),
OUTPUT => bus_OUTBUS(0 TO 7));
-- instantiations of condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
I(0) <= I0(0);
cond_I0: UNNAMED_cond_I0_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_in(0 TO 7),
OUTPUT => I0);
END struct;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED IS
PORT(
CLK, RESET : IN std_logic
);
END UNNAMED;
ARCHITECTURE struct OF UNNAMED IS
SIGNAL CLK_SIGNAL, RESET_SIGNAL : std_logic;
SIGNAL C : std_logic_vector(0 to 5);
SIGNAL I : std_logic_vector(0 to 0);
COMPONENT UNNAMED_cu
PORT (
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 to 5);
I : IN std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu USE ENTITY WORK.UNNAMED_cu(struct);
COMPONENT UNNAMED_ou
PORT (
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 to 5);
I : OUT std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_ou USE ENTITY WORK.UNNAMED_ou(struct);
BEGIN
CLK_SIGNAL <= CLK;
RESET_SIGNAL <= RESET;
Control_Unit: UNNAMED_cu
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
Operation_Unit: UNNAMED_ou
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
END struct;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.02 zelenkaj changed header
-- 2012-01-03 V0.03 zelenkaj added initialization file (mif)
-- 2012-02-21 V0.05 zelenkaj replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.02 zelenkaj changed header
-- 2012-01-03 V0.03 zelenkaj added initialization file (mif)
-- 2012-02-21 V0.05 zelenkaj replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
|
-- File: dyplo_user_logic_adder_2_to_1.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic�s maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
entity dyplo_user_logic_adder_2_to_1 is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 DOWNTO 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end dyplo_user_logic_adder_2_to_1;
architecture rtl of dyplo_user_logic_adder_2_to_1 is
type sm_calc_type is (RECEIVE, SEND);
signal sm_calc : sm_calc_type;
begin
process(dab_clk)
begin
if(rising_edge(dab_clk)) then
if(dab_rst = '1') then
cout_tdata <= (others => (others => '0'));
cout_tvalid <= (others => '0');
cin_tready <= (others => '0');
sm_calc <= RECEIVE;
else
case(sm_calc) is
when RECEIVE =>
if(cin_tvalid(0) = '1' and cin_tvalid(1) = '1') then
cin_tready(1 downto 0) <= "11";
cout_tdata(0) <= cin_tdata(0) + cin_tdata(1);
cout_tvalid(0) <= '1';
sm_calc <= SEND;
end if;
when SEND =>
cin_tready(1 downto 0) <= "00";
if(cout_tready(0) = '1') then
cout_tvalid(0) <= '0';
sm_calc <= RECEIVE;
end if;
end case;
end if;
end if;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2835.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SELECT is
end SELECT;
ENTITY c13s09b00x00p99n01i02835ent IS
END c13s09b00x00p99n01i02835ent;
ARCHITECTURE c13s09b00x00p99n01i02835arch OF c13s09b00x00p99n01i02835ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02835 - Reserved word SELECT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02835arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2835.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SELECT is
end SELECT;
ENTITY c13s09b00x00p99n01i02835ent IS
END c13s09b00x00p99n01i02835ent;
ARCHITECTURE c13s09b00x00p99n01i02835arch OF c13s09b00x00p99n01i02835ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02835 - Reserved word SELECT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02835arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2835.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SELECT is
end SELECT;
ENTITY c13s09b00x00p99n01i02835ent IS
END c13s09b00x00p99n01i02835ent;
ARCHITECTURE c13s09b00x00p99n01i02835arch OF c13s09b00x00p99n01i02835ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02835 - Reserved word SELECT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02835arch;
|
-- $Id: rlink_tba.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_tba - syn
-- Description: rlink test bench adapter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic [synthesizable, but only used in tb's]
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 4.0 now full rlink v4 iface
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add state r_txal;
-- 2011-11-22 432 3.0.2 now numeric_std clean
-- 2011-11-19 427 3.0.1 fix crc8_update usage;
-- 2010-12-24 347 3.0 rename rritba->rlink_tba, CP_*->RL_*; rbus v3 port;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-05-05 289 1.0.3 drop dead snooper code and unneeded unsigned casts
-- 2008-03-02 121 1.0.2 remove snoopers
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
entity rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end entity rlink_tba;
architecture syn of rlink_tba is
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_data is integer range 7 downto 0; -- d9: data field
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
type txstate_type is (
s_txidle, -- s_txidle: wait for ENA
s_txsop, -- s_txsop: send sop
s_txeop, -- s_txeop: send eop
s_txcmd, -- s_txcmd: send cmd
s_txal, -- s_txal: send addr lsb
s_txah, -- s_txah: send addr msb
s_txcl, -- s_txcl: send blk count lsb
s_txch, -- s_txcl: send blk count msb
s_txdl, -- s_txdl: send data lsb
s_txdh, -- s_txdh: send data msb
s_txcrcl1, -- s_txcrcl1: send cmd crc lsb in wblk
s_txcrch1, -- s_txcrch1: send cmd crc msb in wblk
s_txwbld, -- s_txwbld: wblk data load
s_txwbdl, -- s_txwbdl: wblk send data lsb
s_txwbdh, -- s_txwbdh: wblk send data msb
s_txcrcl2, -- s_txcrcl2: send final crc lsb
s_txcrch2 -- s_txcrch2: send final crc msb
);
type txregs_type is record
state : txstate_type; -- state
ccmd : slv3; -- current command
snum : slv5; -- command sequence number
crc : slv16; -- crc (cmd and data)
braddr : slv16; -- block read address
bdata : slv16; -- block data
bloop : slbit; -- block loop flag
tcnt : slv16; -- tcnt (down count for wblk)
sopdone : slbit; -- sop send
eoppend : slbit; -- eop pending
end record txregs_type;
constant txregs_init : txregs_type := (
s_txidle, -- state
"000", -- ccmd
"00000", -- snum
(others=>'0'), -- crc
(others=>'0'), -- braddr
(others=>'0'), -- bdata
'0', -- bloop
(others=>'0'), -- tcnt
'0','0' -- sopdone, eoppend
);
type rxstate_type is (
s_rxidle, -- s_rxidle: wait for ENA
s_rxcmd, -- s_rxcmd: wait cmd
s_rxcl, -- s_rxcl: wait cnt lsb
s_rxch, -- s_rxcl: wait cnt msb
s_rxbabo, -- s_rxbabo: wait babo
s_rxdcl, -- s_rxdcl: wait dcnt lsb
s_rxdch, -- s_rxdch: wait dcnt msb
s_rxdl, -- s_rxdl: wait data lsb
s_rxdh, -- s_rxdh: wait data msb
s_rxstat, -- s_rxstat: wait status
s_rxcrcl, -- s_rxcrcl: wait crc lsb
s_rxcrch, -- s_rxcrch: wait crc msb
s_rxapl, -- s_rxapl: wait attn pat lsb
s_rxaph, -- s_rxaph: wait attn pat msb
s_rxacl, -- s_rxapl: wait attn crc lsb
s_rxach -- s_rxaph: wait attn crc msb
);
type rxregs_type is record
state : rxstate_type; -- state
ccmd : slv3; -- current command
crc : slv16; -- crc
bwaddr : slv16; -- block write address
data : slv16; -- received data
dcnt : slv16; -- done count
tcnt : slv16; -- tcnt (down count for rblk)
ack : slbit; -- ack flag
err : slbit; -- crc error flag
stat : slv8; -- stat
apend : slbit; -- attn pending
ano : slbit; -- attn notify seen
apat : slv16; -- attn pat
end record rxregs_type;
constant rxregs_init : rxregs_type := (
s_rxidle, -- state
"000", -- ccmd
(others=>'0'), -- crc
(others=>'0'), -- bwaddr
(others=>'0'), -- data
(others=>'0'), -- dcnt
(others=>'0'), -- tcnt
'0','0', -- ack, err
(others=>'0'), -- stat
'0','0', -- apend, ano
(others=>'0') -- attn pat
);
signal R_TXREGS : txregs_type := txregs_init; -- TX state registers
signal N_TXREGS : txregs_type := txregs_init; -- TX next value state regs
signal R_RXREGS : rxregs_type := rxregs_init; -- RX state registers
signal N_RXREGS : rxregs_type := rxregs_init; -- RX next value state regs
signal TXBUSY : slbit := '0';
signal RXBUSY : slbit := '0';
signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_TXREGS <= txregs_init;
R_RXREGS <= rxregs_init;
else
R_TXREGS <= N_TXREGS;
R_RXREGS <= N_RXREGS;
end if;
end if;
end process proc_regs;
-- tx FSM ==================================================================
proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)
variable r : txregs_type := txregs_init;
variable n : txregs_type := txregs_init;
variable itxbusy : slbit := '0';
variable icpdi : slv9 := (others=>'0');
variable iena : slbit := '0';
variable ibre : slbit := '0';
variable do_crc : slbit := '0';
begin
r := R_TXREGS;
n := R_TXREGS;
itxbusy := '1';
icpdi := (others=>'0');
iena := '0';
ibre := '0';
do_crc := '0';
if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy
n.eoppend := '1'; -- queue it
end if;
case r.state is
when s_txidle => -- s_txidle: wait for ENA ------------
itxbusy := '0';
if CNTL.ena = '1' then -- cmd requested
n.ccmd := CNTL.cmd;
if CNTL.eop = '1' then -- if eop requested with ENA
n.eoppend := '1'; -- queue it, eop after this cmd
end if;
if r.sopdone = '0' then -- if not in active packet
n.snum := (others=>'0'); -- set snum=0
n.state := s_txsop; -- send sop
else
n.state := s_txcmd;
end if;
else -- no cmd requested
if CNTL.eop='1' and r.sopdone='1' then -- if eop req and in packet
n.state := s_txeop; -- send eop
end if;
end if;
when s_txsop => -- s_txsop: send sop -----------------
n.sopdone := '1';
icpdi := c_rlink_dat_sop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txcmd;
end if;
when s_txeop => -- s_txeop: send eop -----------------
n.sopdone := '0';
n.eoppend := '0';
icpdi := c_rlink_dat_eop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txidle;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
n.tcnt := CNTL.cnt;
n.braddr := (others=>'0');
icpdi(c_rlink_cmd_rbf_seq) := r.snum;
icpdi(c_rlink_cmd_rbf_code) := r.ccmd;
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum
case r.ccmd is
when c_rlink_cmd_labo => n.state := s_txcrcl2;
when c_rlink_cmd_attn => n.state := s_txcrcl2;
when others => n.state := s_txal;
end case;
end if;
when s_txal => -- s_txal: send addr lsb -------------
icpdi := '0' & CNTL.addr(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txah;
end if;
when s_txah => -- s_txah: send addr msb -------------
icpdi := '0' & CNTL.addr(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
case r.ccmd is
when c_rlink_cmd_rreg => n.state := s_txcrcl2;
when c_rlink_cmd_rblk => n.state := s_txcl;
when c_rlink_cmd_wblk => n.state := s_txcl;
when others => n.state := s_txdl;
end case;
end if;
when s_txcl => -- s_txcl: send blk count lsb -------
icpdi := '0' & CNTL.cnt(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txch;
end if;
when s_txch => -- s_txch: send blk count msb -------
icpdi := '0' & CNTL.cnt(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.ccmd = c_rlink_cmd_wblk then
n.state := s_txcrcl1;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txdl => -- s_txdl: send data lsb -------------
icpdi := '0' & DI(d_f_data);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txdh;
end if;
when s_txdh => -- s_txdh: send data msb -------------
icpdi := '0' & DI(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txcrcl2;
end if;
when s_txcrcl1 => -- s_txcrcl1: send cmd crc lsb in wblk
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch1;
end if;
when s_txcrch1 => -- s_txcrch1: send cmd crc msb in wblk
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txwbld;
end if;
when s_txwbld => -- s_txwbld: wblk data load ----------
-- this state runs when s_wreg is
-- executed in rlink, thus doesn't cost
-- an extra cycle in 2nd+ iteration.
ibre := '1';
n.bdata := DI;
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.braddr := slv(unsigned(r.braddr) + 1);
if unsigned(r.tcnt) = 1 then
n.bloop := '0';
else
n.bloop := '1';
end if;
n.state := s_txwbdl;
when s_txwbdl => -- s_txwbdl: wblk send data lsb ------
icpdi := '0' & r.bdata(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txwbdh;
end if;
when s_txwbdh => -- s_txwbdh: wblk send data msb ------
icpdi := '0' & r.bdata(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.bloop = '1' then
n.state := s_txwbld;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txcrcl2 => -- s_txcrcl2: send final crc lsb -----
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch2;
end if;
when s_txcrch2 => -- s_txcrch2: send final crc msb -----
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
if r.eoppend = '1' or unsigned(r.snum)=31 then
n.state := s_txeop;
else
n.state := s_txidle;
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, icpdi(d_f_data));
end if;
N_TXREGS <= n;
TXBUSY <= itxbusy;
STAT_L.braddr <= r.braddr;
STAT_L.bre <= ibre;
RL_DI <= icpdi;
RL_ENA <= iena;
end process proc_txnext;
-- rx FSM ==================================================================
proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)
variable r : rxregs_type := rxregs_init;
variable n : rxregs_type := rxregs_init;
variable irxbusy : slbit := '0';
variable ibwe : slbit := '0';
variable do_crc : slbit := '0';
variable ido : slv16 := (others=>'0');
begin
r := R_RXREGS;
n := R_RXREGS;
n.ack := '0';
n.ano := '0';
irxbusy := '1';
ibwe := '0';
do_crc := '0';
ido := r.data;
case r.state is
when s_rxidle => -- s_rxidle: wait --------------------
n.crc := (others=>'0');
n.err := '0';
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_attn then -- attn seen ?
n.state := s_rxapl;
elsif RL_DO = c_rlink_dat_sop then
n.state := s_rxcmd;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcmd => -- s_rxcmd: wait cmd ----------------
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_eop then
n.state := s_rxidle;
else
n.bwaddr := (others=>'0');
do_crc := '1';
n.ccmd := RL_DO(n.ccmd'range);
case RL_DO(n.ccmd'range) is
when c_rlink_cmd_rreg => n.state := s_rxdl;
when c_rlink_cmd_rblk => n.state := s_rxcl;
when c_rlink_cmd_wreg => n.state := s_rxstat;
when c_rlink_cmd_wblk => n.state := s_rxdcl;
when c_rlink_cmd_labo => n.state := s_rxbabo;
when c_rlink_cmd_attn => n.state := s_rxdl;
when c_rlink_cmd_init => n.state := s_rxstat;
when others => null;
end case;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcl => -- s_rxcl: wait cnt lsb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxch;
end if;
when s_rxch => -- s_rxch: wait cnt msb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxdl;
end if;
when s_rxbabo => -- s_rxbabo: wait babo ---------------
if RL_VAL = '1' then
do_crc := '1';
n.data(15 downto 0) := (others=>'0');
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxdl => -- s_rxdl: wait data lsb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdh;
end if;
when s_rxdh => -- s_rxdh: wait data msb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte1) := RL_DO(d_f_data);
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.bwaddr := slv(unsigned(r.bwaddr) + 1);
if r.ccmd = c_rlink_cmd_rblk then
ido(f_byte1) := RL_DO(d_f_data);
ibwe := '1';
end if;
if r.ccmd /= c_rlink_cmd_rblk then
n.state := s_rxstat;
elsif unsigned(r.tcnt) = 1 then
n.state := s_rxdcl;
else
n.state := s_rxdl;
end if;
end if;
when s_rxdcl => -- s_rxdcl: wait dcnt lsb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdch;
end if;
when s_rxdch => -- s_rxdch: wait dcnt msb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxstat => -- s_rxstat: wait status -------------
if RL_VAL = '1' then
do_crc := '1';
n.stat := RL_DO(d_f_data);
n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status
n.state := s_rxcrcl;
end if;
when s_rxcrcl => -- s_rxcrcl: wait crc lsb ------------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxcrch;
end if;
when s_rxcrch => -- s_rxcrch: wait crc msb ------------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ack := '1';
n.state := s_rxcmd;
end if;
when s_rxapl => -- s_rxapl: wait attn pat lsb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte0) := RL_DO(d_f_data);
n.state := s_rxaph;
end if;
when s_rxaph => -- s_rxaph: wait attn pat msb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte1) := RL_DO(d_f_data);
n.state := s_rxacl;
end if;
when s_rxacl => -- s_rxacl: wait attn crc lsb --------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxach;
end if;
when s_rxach => -- s_rxach: wait attn crc msb --------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ano := '1';
n.state := s_rxidle;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, RL_DO(d_f_data));
end if;
N_RXREGS <= n;
RXBUSY <= irxbusy;
DO <= ido;
STAT_L.stat <= r.stat;
STAT_L.ack <= r.ack;
STAT_L.err <= r.err;
STAT_L.bwaddr <= r.bwaddr;
STAT_L.bwe <= ibwe;
STAT_L.dcnt <= r.dcnt;
STAT_L.apend <= r.apend;
STAT_L.ano <= r.ano;
STAT_L.apat <= r.apat;
RL_HOLD <= '0';
end process proc_rxnext;
STAT_L.busy <= RXBUSY or TXBUSY;
STAT <= STAT_L;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal GPIO_0 : std_logic_vector(DW-1 downto 0);
signal GPIO_1 : std_logic_vector(DW-1 downto 0);
signal GPIO_2 : std_logic_vector(DW-1 downto 0);
signal GPIO_3 : std_logic_vector(DW-1 downto 0);
signal LCD : std_logic_vector(LCD_PW-1 downto 0);
begin
-- instantiate MUT
MUT : entity work.mcu
port map(
rst => rst,
clk => clk,
GPIO_0 => GPIO_0,
GPIO_1 => GPIO_1,
GPIO_2 => GPIO_2,
GPIO_3 => GPIO_3,
LCD => LCD
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / CF/2;
clk <= not clk;
end process;
end TB;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal GPIO_0 : std_logic_vector(DW-1 downto 0);
signal GPIO_1 : std_logic_vector(DW-1 downto 0);
signal GPIO_2 : std_logic_vector(DW-1 downto 0);
signal GPIO_3 : std_logic_vector(DW-1 downto 0);
signal LCD : std_logic_vector(LCD_PW-1 downto 0);
begin
-- instantiate MUT
MUT : entity work.mcu
port map(
rst => rst,
clk => clk,
GPIO_0 => GPIO_0,
GPIO_1 => GPIO_1,
GPIO_2 => GPIO_2,
GPIO_3 => GPIO_3,
LCD => LCD
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / CF/2;
clk <= not clk;
end process;
end TB;
|
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_Req_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_IDLE_grant_N <= '0';
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_Req_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_North_grant_N <= '0';
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_Req_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
end if;
end process;
process (state, req_X_E, X_E)
begin
err_East_grant_E <= '0';
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_Req_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
end if;
end process;
process (state, req_X_W, X_W)
begin
err_West_grant_W <= '0';
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_Req_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
end if;
end process;
process (state, req_X_S, X_S)
begin
err_South_grant_S <= '0';
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_Req_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
end if;
end process;
process (state, req_X_L, X_L)
begin
err_Local_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_Req_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_IDLE_grant_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
err_North_Req_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_North_grant_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
err_East_Req_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
err_East_grant_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
err_West_Req_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
err_West_grant_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_Req_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
err_South_grant_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_Req_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
err_Local_grant_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_Req_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_IDLE_grant_W <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_Req_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_North_grant_W <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_Req_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
err_East_grant_S <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_Req_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
err_West_grant_L <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_Req_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
err_South_grant_N <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_Req_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
err_Local_grant_E <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_Req_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_IDLE_grant_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_Req_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_North_grant_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_Req_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_East_grant_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_Req_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_West_grant_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_Req_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_South_grant_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_Req_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_Local_grant_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_Req_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_IDLE_grant_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_Req_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_North_grant_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_Req_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_East_grant_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_Req_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_West_grant_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_Req_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_South_grant_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_Req_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_Local_grant_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
end if;
end process;
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process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_request_no_grants <= '0';
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
end if;
end process;
process (req_X_N, X_N)
begin
err_no_Req_N_grant_N <= '0';
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
end if;
end process;
process (req_X_E, X_E)
begin
err_no_Req_E_grant_E <= '0';
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
end if;
end process;
process (req_X_W, X_W)
begin
err_no_Req_W_grant_W <= '0';
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
end if;
end process;
process (req_X_S, X_S)
begin
err_no_Req_S_grant_S <= '0';
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
end if;
end process;
process (req_X_L, X_L)
begin
err_no_Req_L_grant_L <= '0';
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_Req_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_IDLE_grant_N <= '0';
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_Req_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_North_grant_N <= '0';
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_Req_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
end if;
end process;
process (state, req_X_E, X_E)
begin
err_East_grant_E <= '0';
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_Req_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
end if;
end process;
process (state, req_X_W, X_W)
begin
err_West_grant_W <= '0';
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_Req_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
end if;
end process;
process (state, req_X_S, X_S)
begin
err_South_grant_S <= '0';
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_Req_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
end if;
end process;
process (state, req_X_L, X_L)
begin
err_Local_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_Req_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_IDLE_grant_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
err_North_Req_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_North_grant_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
err_East_Req_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
err_East_grant_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
err_West_Req_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
err_West_grant_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_Req_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
err_South_grant_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_Req_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
err_Local_grant_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_Req_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_IDLE_grant_W <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_Req_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_North_grant_W <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_Req_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
err_East_grant_S <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_Req_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
err_West_grant_L <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_Req_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
err_South_grant_N <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_Req_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
err_Local_grant_E <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_Req_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_IDLE_grant_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_Req_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_North_grant_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_Req_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_East_grant_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_Req_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_West_grant_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_Req_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_South_grant_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_Req_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_Local_grant_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_Req_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_IDLE_grant_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_Req_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_North_grant_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_Req_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_East_grant_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_Req_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_West_grant_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_Req_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_South_grant_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_Req_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_Local_grant_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
end if;
end process;
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process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_request_no_grants <= '0';
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
end if;
end process;
process (req_X_N, X_N)
begin
err_no_Req_N_grant_N <= '0';
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
end if;
end process;
process (req_X_E, X_E)
begin
err_no_Req_E_grant_E <= '0';
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
end if;
end process;
process (req_X_W, X_W)
begin
err_no_Req_W_grant_W <= '0';
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
end if;
end process;
process (req_X_S, X_S)
begin
err_no_Req_S_grant_S <= '0';
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
end if;
end process;
process (req_X_L, X_L)
begin
err_no_Req_L_grant_L <= '0';
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
use work.component_pack.all;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N,
err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
err_IDLE_Req_N <= '0';
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_IDLE_grant_N <= '0';
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
end if;
end process;
process (state, req_X_N, state_in)
begin
err_North_Req_N <= '0';
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
end if;
end process;
process (state, req_X_N, X_N)
begin
err_North_grant_N <= '0';
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
end if;
end process;
process (state, req_X_E, state_in)
begin
err_East_Req_E <= '0';
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
end if;
end process;
process (state, req_X_E, X_E)
begin
err_East_grant_E <= '0';
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
end if;
end process;
process (state, req_X_W, state_in)
begin
err_West_Req_W <= '0';
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
end if;
end process;
process (state, req_X_W, X_W)
begin
err_West_grant_W <= '0';
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
end if;
end process;
process (state, req_X_S, state_in)
begin
err_South_Req_S <= '0';
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
end if;
end process;
process (state, req_X_S, X_S)
begin
err_South_grant_S <= '0';
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
err_Local_Req_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
end if;
end process;
process (state, req_X_L, X_L)
begin
err_Local_grant_L <= '0';
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
err_IDLE_Req_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_IDLE_grant_E <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
err_North_Req_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
err_North_grant_E <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
err_East_Req_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
err_East_grant_W <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
err_West_Req_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
err_West_grant_S <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
err_South_Req_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
err_South_grant_L <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
err_Local_Req_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
err_Local_grant_N <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_IDLE_Req_W <= '0';
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_IDLE_grant_W <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
err_North_Req_W <= '0';
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
err_North_grant_W <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
err_East_Req_S <= '0';
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
err_East_grant_S <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
err_West_Req_L <= '0';
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
err_West_grant_L <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
err_South_Req_N <= '0';
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
err_South_grant_N <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
err_Local_Req_E <= '0';
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
err_Local_grant_E <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_IDLE_Req_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_IDLE_grant_S <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_North_Req_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_North_grant_S <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_East_Req_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_East_grant_L <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_West_Req_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_West_grant_N <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_South_Req_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_South_grant_E <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_Local_Req_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_Local_grant_W <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_IDLE_Req_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_IDLE_grant_L <= '0';
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
err_North_Req_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
err_North_grant_L <= '0';
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
err_East_Req_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
err_East_grant_N <= '0';
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
err_West_Req_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
err_West_grant_E <= '0';
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
err_South_Req_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
err_South_grant_W <= '0';
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
err_Local_Req_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
err_Local_grant_S <= '0';
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
err_state_in_onehot <= '0';
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_no_request_grants <= '0';
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
end if;
end process;
process (Requests, Grants)
begin
err_request_no_grants <= '0';
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
end if;
end process;
process (req_X_N, X_N)
begin
err_no_Req_N_grant_N <= '0';
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
end if;
end process;
process (req_X_E, X_E)
begin
err_no_Req_E_grant_E <= '0';
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
end if;
end process;
process (req_X_W, X_W)
begin
err_no_Req_W_grant_W <= '0';
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
end if;
end process;
process (req_X_S, X_S)
begin
err_no_Req_S_grant_S <= '0';
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
end if;
end process;
process (req_X_L, X_L)
begin
err_no_Req_L_grant_L <= '0';
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
end if;
end process;
end behavior; |
-- NEED RESULT: ARCH00043.P1: Target of a variable assignment may be a selected name prefixed by an indexed name passed
-- NEED RESULT: ARCH00043.P2: Target of a variable assignment may be a selected name prefixed by an indexed name passed
-- NEED RESULT: ARCH00043.P3: Target of a variable assignment may be a selected name prefixed by an indexed name passed
-- NEED RESULT: ARCH00043.P4: Target of a variable assignment may be a selected name prefixed by an indexed name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00043
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00043)
-- ENT00043_Test_Bench(ARCH00043_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00043 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_st_rec1_vector : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
--
variable correct : boolean := true ;
begin
v_st_rec1_vector(lowb).f2 := c_st_rec1_vector_2(lowb).f2 ;
v_st_rec2_vector(lowb).f2 := c_st_rec2_vector_2(lowb).f2 ;
v_st_rec3_vector(lowb).f2 := c_st_rec3_vector_2(lowb).f2 ;
--
correct := correct and
v_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 ;
correct := correct and
v_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 ;
correct := correct and
v_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(lowb).f2 ;
--
test_report ( "ARCH00043.P1" ,
"Target of a variable assignment may be a " &
"selected name prefixed by an indexed name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_st_rec1_vector : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
--
begin
v_st_rec1_vector(lowb).f2 := c_st_rec1_vector_2(lowb).f2 ;
v_st_rec2_vector(lowb).f2 := c_st_rec2_vector_2(lowb).f2 ;
v_st_rec3_vector(lowb).f2 := c_st_rec3_vector_2(lowb).f2 ;
--
correct := correct and
v_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 ;
correct := correct and
v_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 ;
correct := correct and
v_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(lowb).f2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00043.P2" ,
"Target of a variable assignment may be a " &
"selected name prefixed by an indexed name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_st_rec1_vector : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_st_rec1_vector(lowb).f2 := c_st_rec1_vector_2(lowb).f2 ;
v_st_rec2_vector(lowb).f2 := c_st_rec2_vector_2(lowb).f2 ;
v_st_rec3_vector(lowb).f2 := c_st_rec3_vector_2(lowb).f2 ;
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 ;
correct := correct and
v_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 ;
correct := correct and
v_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(lowb).f2 ;
--
test_report ( "ARCH00043.P3" ,
"Target of a variable assignment may be a " &
"selected name prefixed by an indexed name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_st_rec1_vector : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec1_vector : inout st_rec1_vector
; v_st_rec2_vector : inout st_rec2_vector
; v_st_rec3_vector : inout st_rec3_vector
)
is
begin
v_st_rec1_vector(lowb).f2 := c_st_rec1_vector_2(lowb).f2 ;
v_st_rec2_vector(lowb).f2 := c_st_rec2_vector_2(lowb).f2 ;
v_st_rec3_vector(lowb).f2 := c_st_rec3_vector_2(lowb).f2 ;
--
end Proc1 ;
begin
Proc1 (
v_st_rec1_vector
, v_st_rec2_vector
, v_st_rec3_vector
) ;
correct := correct and
v_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 ;
correct := correct and
v_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 ;
correct := correct and
v_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(lowb).f2 ;
--
test_report ( "ARCH00043.P4" ,
"Target of a variable assignment may be a " &
"selected name prefixed by an indexed name" ,
correct) ;
end process P4 ;
--
end ARCH00043 ;
--
entity ENT00043_Test_Bench is
end ENT00043_Test_Bench ;
--
architecture ARCH00043_Test_Bench of ENT00043_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00043 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00043_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02463ent IS
END c07s03b02x02p03n02i02463ent;
ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := ('1', others => '0');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02463"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02463ent IS
END c07s03b02x02p03n02i02463ent;
ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := ('1', others => '0');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02463"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02463ent IS
END c07s03b02x02p03n02i02463ent;
ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := ('1', others => '0');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02463"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02463arch;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- fLink definitions --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fLink_definitions IS
-- Global
CONSTANT c_fLink_avs_data_width : INTEGER := 32;
CONSTANT c_fLink_avs_data_width_in_byte : INTEGER := c_fLink_avs_data_width/8;
-- Header registers
CONSTANT c_fLink_number_of_std_registers : INTEGER := 8;
CONSTANT c_fLink_typdef_address : INTEGER := 0;
CONSTANT c_fLink_mem_size_address : INTEGER := 1;
CONSTANT c_fLink_number_of_channels_address : INTEGER := 2;
CONSTANT c_fLink_unique_id_address : INTEGER := 3;
CONSTANT c_fLink_status_address : INTEGER := 4;
CONSTANT c_fLink_configuration_address : INTEGER := 5;
CONSTANT c_fLink_id_length : INTEGER := 16;
CONSTANT c_fLink_subtype_length : INTEGER := 8;
CONSTANT c_fLink_interface_version_length : INTEGER := 8;
CONSTANT c_fLink_reset_bit_num : INTEGER := 0;
-- Interface IDs:
CONSTANT c_fLink_info_id : INTEGER := 0;
CONSTANT c_fLink_analog_input_id : INTEGER := 1;
CONSTANT c_fLink_analog_output_id : INTEGER := 2;
CONSTANT c_fLink_digital_io_id : INTEGER := 5;
CONSTANT c_fLink_counter_id : INTEGER := 6;
CONSTANT c_fLink_timer_id : INTEGER := 7;
CONSTANT c_fLink_memory_id : INTEGER := 8;
CONSTANT c_fLink_pwm_out_id : INTEGER := 12;
CONSTANT c_fLink_ppwa_id : INTEGER := 13;
CONSTANT c_fLink_watchdog_id : INTEGER := 16;
CONSTANT c_fLink_sensor_id : INTEGER := 17;
END PACKAGE fLink_definitions;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p05n01i01637pkg is
-- type declarations
type ENUM is ( E1, E2, E3 );
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type ANARRAY is ARRAY( 0 to 1 ) of REAL;
type ARECORD is
RECORD
Field1 : INTEGER;
Field2 : BOOLEAN;
end record;
-- constant declarations
CONSTANT CONSTI : INTEGER := 47;
CONSTANT CONSTR : REAL := 47.0;
CONSTANT CONSTE : ENUM := E1;
CONSTANT CONSTD : DISTANCE := 1 A;
CONSTANT CONSTT : TIME := 1 hr;
CONSTANT CONSTB : BIT := '1';
CONSTANT CONSTS : SEVERITY_LEVEL := WARNING;
CONSTANT CONSTBO : BOOLEAN := FALSE;
CONSTANT CONSTA : ANARRAY := ( 3.1415926, 4.0 );
CONSTANT CONSTRE : ARECORD := ( Field1 => 2, Field2 => TRUE );
-- function declarations.
function funcI return INTEGER;
function funcR return REAL;
function funcE return ENUM;
function funcD return DISTANCE;
function funcT return TIME;
function funcB return BIT;
function funcS return SEVERITY_LEVEL;
function funcBO return BOOLEAN;
function funcA return ANARRAY;
function funcRE return ARECORD;
end c08s12b00x00p05n01i01637pkg;
package body c08s12b00x00p05n01i01637pkg is
function funcI return INTEGER is
begin
return( CONSTI );
end;
function funcR return REAL is
begin
return( CONSTR );
end;
function funcE return ENUM is
begin
return( CONSTE );
end;
function funcD return DISTANCE is
begin
return( CONSTD );
end;
function funcT return TIME is
begin
return( CONSTT );
end;
function funcB return BIT is
begin
return( CONSTB );
end;
function funcS return SEVERITY_LEVEL is
begin
return( CONSTS );
end;
function funcBO return BOOLEAN is
begin
return( CONSTBO );
end;
function funcA return ANARRAY is
begin
return( CONSTA );
end;
function funcRE return ARECORD is
begin
return( CONSTRE );
end;
end c08s12b00x00p05n01i01637pkg;
use work.c08s12b00x00p05n01i01637pkg.all;
ENTITY c08s12b00x00p05n01i01637ent IS
END c08s12b00x00p05n01i01637ent;
ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
BEGIN
TESTING: PROCESS
-- variable declarations.
VARIABLE VARI : INTEGER;
VARIABLE VARR : REAL;
VARIABLE VARE : ENUM;
VARIABLE VARD : DISTANCE;
VARIABLE VART : TIME;
VARIABLE VARB : BIT;
VARIABLE VARS : SEVERITY_LEVEL;
VARIABLE VARBO : BOOLEAN;
VARIABLE VARA : ANARRAY;
VARIABLE VARRE : ARECORD;
BEGIN
-- Call each function, verify that it returns the proper value.
assert (funcI = CONSTI);
assert (funcR = CONSTR);
assert (funcE = CONSTE);
assert (funcD = CONSTD);
assert (funcT = CONSTT);
assert (funcB = CONSTB);
assert (funcS = CONSTS);
assert (funcBO = CONSTBO);
assert (funcA = CONSTA);
assert (funcRE = CONSTRE);
-- Assign function values to variables, make sure they're OK.
VARI := funcI;
VARR := funcR;
VARE := funcE;
VARD := funcD;
VART := funcT;
VARB := funcB;
VARS := funcS;
VARBO := funcBO;
VARA := funcA;
VARRE := funcRE;
assert (VARI = CONSTI);
assert (VARR = CONSTR);
assert (VARE = CONSTE);
assert (VARD = CONSTD);
assert (VART = CONSTT);
assert (VARB = CONSTB);
assert (VARS = CONSTS);
assert (VARBO = CONSTBO);
assert (VARA = CONSTA);
assert (VARRE = CONSTRE);
assert NOT((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***PASSED TEST: c08s12b00x00p05n01i01637"
severity NOTE;
assert ((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01637arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p05n01i01637pkg is
-- type declarations
type ENUM is ( E1, E2, E3 );
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type ANARRAY is ARRAY( 0 to 1 ) of REAL;
type ARECORD is
RECORD
Field1 : INTEGER;
Field2 : BOOLEAN;
end record;
-- constant declarations
CONSTANT CONSTI : INTEGER := 47;
CONSTANT CONSTR : REAL := 47.0;
CONSTANT CONSTE : ENUM := E1;
CONSTANT CONSTD : DISTANCE := 1 A;
CONSTANT CONSTT : TIME := 1 hr;
CONSTANT CONSTB : BIT := '1';
CONSTANT CONSTS : SEVERITY_LEVEL := WARNING;
CONSTANT CONSTBO : BOOLEAN := FALSE;
CONSTANT CONSTA : ANARRAY := ( 3.1415926, 4.0 );
CONSTANT CONSTRE : ARECORD := ( Field1 => 2, Field2 => TRUE );
-- function declarations.
function funcI return INTEGER;
function funcR return REAL;
function funcE return ENUM;
function funcD return DISTANCE;
function funcT return TIME;
function funcB return BIT;
function funcS return SEVERITY_LEVEL;
function funcBO return BOOLEAN;
function funcA return ANARRAY;
function funcRE return ARECORD;
end c08s12b00x00p05n01i01637pkg;
package body c08s12b00x00p05n01i01637pkg is
function funcI return INTEGER is
begin
return( CONSTI );
end;
function funcR return REAL is
begin
return( CONSTR );
end;
function funcE return ENUM is
begin
return( CONSTE );
end;
function funcD return DISTANCE is
begin
return( CONSTD );
end;
function funcT return TIME is
begin
return( CONSTT );
end;
function funcB return BIT is
begin
return( CONSTB );
end;
function funcS return SEVERITY_LEVEL is
begin
return( CONSTS );
end;
function funcBO return BOOLEAN is
begin
return( CONSTBO );
end;
function funcA return ANARRAY is
begin
return( CONSTA );
end;
function funcRE return ARECORD is
begin
return( CONSTRE );
end;
end c08s12b00x00p05n01i01637pkg;
use work.c08s12b00x00p05n01i01637pkg.all;
ENTITY c08s12b00x00p05n01i01637ent IS
END c08s12b00x00p05n01i01637ent;
ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
BEGIN
TESTING: PROCESS
-- variable declarations.
VARIABLE VARI : INTEGER;
VARIABLE VARR : REAL;
VARIABLE VARE : ENUM;
VARIABLE VARD : DISTANCE;
VARIABLE VART : TIME;
VARIABLE VARB : BIT;
VARIABLE VARS : SEVERITY_LEVEL;
VARIABLE VARBO : BOOLEAN;
VARIABLE VARA : ANARRAY;
VARIABLE VARRE : ARECORD;
BEGIN
-- Call each function, verify that it returns the proper value.
assert (funcI = CONSTI);
assert (funcR = CONSTR);
assert (funcE = CONSTE);
assert (funcD = CONSTD);
assert (funcT = CONSTT);
assert (funcB = CONSTB);
assert (funcS = CONSTS);
assert (funcBO = CONSTBO);
assert (funcA = CONSTA);
assert (funcRE = CONSTRE);
-- Assign function values to variables, make sure they're OK.
VARI := funcI;
VARR := funcR;
VARE := funcE;
VARD := funcD;
VART := funcT;
VARB := funcB;
VARS := funcS;
VARBO := funcBO;
VARA := funcA;
VARRE := funcRE;
assert (VARI = CONSTI);
assert (VARR = CONSTR);
assert (VARE = CONSTE);
assert (VARD = CONSTD);
assert (VART = CONSTT);
assert (VARB = CONSTB);
assert (VARS = CONSTS);
assert (VARBO = CONSTBO);
assert (VARA = CONSTA);
assert (VARRE = CONSTRE);
assert NOT((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***PASSED TEST: c08s12b00x00p05n01i01637"
severity NOTE;
assert ((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01637arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p05n01i01637pkg is
-- type declarations
type ENUM is ( E1, E2, E3 );
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type ANARRAY is ARRAY( 0 to 1 ) of REAL;
type ARECORD is
RECORD
Field1 : INTEGER;
Field2 : BOOLEAN;
end record;
-- constant declarations
CONSTANT CONSTI : INTEGER := 47;
CONSTANT CONSTR : REAL := 47.0;
CONSTANT CONSTE : ENUM := E1;
CONSTANT CONSTD : DISTANCE := 1 A;
CONSTANT CONSTT : TIME := 1 hr;
CONSTANT CONSTB : BIT := '1';
CONSTANT CONSTS : SEVERITY_LEVEL := WARNING;
CONSTANT CONSTBO : BOOLEAN := FALSE;
CONSTANT CONSTA : ANARRAY := ( 3.1415926, 4.0 );
CONSTANT CONSTRE : ARECORD := ( Field1 => 2, Field2 => TRUE );
-- function declarations.
function funcI return INTEGER;
function funcR return REAL;
function funcE return ENUM;
function funcD return DISTANCE;
function funcT return TIME;
function funcB return BIT;
function funcS return SEVERITY_LEVEL;
function funcBO return BOOLEAN;
function funcA return ANARRAY;
function funcRE return ARECORD;
end c08s12b00x00p05n01i01637pkg;
package body c08s12b00x00p05n01i01637pkg is
function funcI return INTEGER is
begin
return( CONSTI );
end;
function funcR return REAL is
begin
return( CONSTR );
end;
function funcE return ENUM is
begin
return( CONSTE );
end;
function funcD return DISTANCE is
begin
return( CONSTD );
end;
function funcT return TIME is
begin
return( CONSTT );
end;
function funcB return BIT is
begin
return( CONSTB );
end;
function funcS return SEVERITY_LEVEL is
begin
return( CONSTS );
end;
function funcBO return BOOLEAN is
begin
return( CONSTBO );
end;
function funcA return ANARRAY is
begin
return( CONSTA );
end;
function funcRE return ARECORD is
begin
return( CONSTRE );
end;
end c08s12b00x00p05n01i01637pkg;
use work.c08s12b00x00p05n01i01637pkg.all;
ENTITY c08s12b00x00p05n01i01637ent IS
END c08s12b00x00p05n01i01637ent;
ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
BEGIN
TESTING: PROCESS
-- variable declarations.
VARIABLE VARI : INTEGER;
VARIABLE VARR : REAL;
VARIABLE VARE : ENUM;
VARIABLE VARD : DISTANCE;
VARIABLE VART : TIME;
VARIABLE VARB : BIT;
VARIABLE VARS : SEVERITY_LEVEL;
VARIABLE VARBO : BOOLEAN;
VARIABLE VARA : ANARRAY;
VARIABLE VARRE : ARECORD;
BEGIN
-- Call each function, verify that it returns the proper value.
assert (funcI = CONSTI);
assert (funcR = CONSTR);
assert (funcE = CONSTE);
assert (funcD = CONSTD);
assert (funcT = CONSTT);
assert (funcB = CONSTB);
assert (funcS = CONSTS);
assert (funcBO = CONSTBO);
assert (funcA = CONSTA);
assert (funcRE = CONSTRE);
-- Assign function values to variables, make sure they're OK.
VARI := funcI;
VARR := funcR;
VARE := funcE;
VARD := funcD;
VART := funcT;
VARB := funcB;
VARS := funcS;
VARBO := funcBO;
VARA := funcA;
VARRE := funcRE;
assert (VARI = CONSTI);
assert (VARR = CONSTR);
assert (VARE = CONSTE);
assert (VARD = CONSTD);
assert (VART = CONSTT);
assert (VARB = CONSTB);
assert (VARS = CONSTS);
assert (VARBO = CONSTBO);
assert (VARA = CONSTA);
assert (VARRE = CONSTRE);
assert NOT((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***PASSED TEST: c08s12b00x00p05n01i01637"
severity NOTE;
assert ((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01637arch;
|
-- File: ConcatDemo_TB_V_VHDL.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:28:04 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_010.all;
entity ConcatDemo_TB_V_VHDL is
end entity ConcatDemo_TB_V_VHDL;
architecture MyHDL of ConcatDemo_TB_V_VHDL is
signal Res: unsigned(6 downto 0) := 7X"00";
signal ResS: signed (6 downto 0) := 7X"00";
signal ConcatDemo0_0_RefVal: unsigned(5 downto 0);
begin
ConcatDemo0_0_RefVal <= to_unsigned(25, 6);
CONCATDEMO_TB_V_VHDL_PRINT_DATA: process (ResS, Res) is
variable L: line;
begin
write(L, to_hstring(Res));
write(L, string'(" "));
write(L, to_hstring(unsigned(ResS)));
writeline(output, L);
end process CONCATDEMO_TB_V_VHDL_PRINT_DATA;
Res <= unsigned'('1' & ConcatDemo0_0_RefVal);
ResS <= signed(unsigned'('1' & ConcatDemo0_0_RefVal));
CONCATDEMO_TB_V_VHDL_STIMULES: process is
begin
for i in 0 to 2-1 loop
wait for 1 * 1 ns;
end loop;
assert False report "End of Simulation" severity Failure;
wait;
end process CONCATDEMO_TB_V_VHDL_STIMULES;
end architecture MyHDL;
|
-- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library user_logic;
use user_logic.all;
entity dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
attribute secure_config : string;
attribute secure_config of dyplo_hdl_node : entity is "PROTECT";
attribute secure_netlist : string;
attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT";
attribute secure_net_editing : string;
attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT";
attribute secure_net_probing : string;
attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT";
end dyplo_hdl_node;
architecture rtl of dyplo_hdl_node is
component dyplo_user_logic_adder_2_to_1 is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component dyplo_user_logic_adder_2_to_1;
signal dab_sel_ul : std_logic;
signal dab_wvalid_ul : std_logic;
signal dab_rvalid_ul : std_logic;
signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal cin_tdata_i : cin_tdata_ul_type;
signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tlevel_i : cin_tlevel_ul_type;
signal cout_tdata_i : cout_tdata_ul_type;
signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0);
signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE --
-----------------------------------------------------------------------------
-- The available memory range for the CPU fifo control is limited to --
-- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the --
-- AXI bus is 256 words. The actual FIFO data memory range is also limited --
-- to 64Kbytes or 16Kwords. Also, the space is divided between reading and --
-- writing. This leaves 8Kwords per direction and with a burst length of --
-- 256 words, maximum 32 input streams and 32 output streams can be --
-- supported. --
-----------------------------------------------------------------------------
-- Each fifo has the following metrics: --
-- - FIFO full and FIFO empty flag --
-- - FIFO fill level compare register and compare flag --
-- - Actual FIFO fill level indicator --
-- - Under/overflow detection flag when operating FIFO out of range --
-- --
-- Per input FIFO (from FPGA fabric to the CPU) it is required to specify --
-- the stream source. Also, a maskable interrupt should be issued per --
-- input FIFO to signal the need to empty the FIFO by the CPU. --
-----------------------------------------------------------------------------
dyplo_hdl_node_logic_i : dyplo_hdl_node_logic
generic map (
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Miscellaneous
node_id => node_id,
-- DAB interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr,
dab_sel => dab_sel,
dab_wvalid => dab_wvalid,
dab_rvalid => dab_rvalid,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata,
b2f_tstream_id => b2f_tstream_id,
b2f_tvalid => b2f_tvalid,
b2f_tready => b2f_tready,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata,
f2b_tstream_id => f2b_tstream_id,
f2b_tvalid => f2b_tvalid,
f2b_tready => f2b_tready,
-- Serial fifo status info
fifo_status_sync => fifo_status_sync,
fifo_status_flag => fifo_status_flag,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0),
-- DAB interface to user logic
dab_sel_ul => dab_sel_ul,
dab_wvalid_ul => dab_wvalid_ul,
dab_rvalid_ul => dab_rvalid_ul,
dab_rdata_ul => dab_rdata_ul,
-- In streams to user logic
cin_tdata_ul => cin_tdata_i,
cin_tvalid_ul => cin_tvalid_i,
cin_tready_ul => cin_tready_i,
cin_tlevel_ul => cin_tlevel_i,
-- Out streams from user logic
cout_tdata_ul => cout_tdata_i,
cout_tvalid_ul => cout_tvalid_i,
cout_tready_ul => cout_tready_i
);
dyplo_user_logic_i : dyplo_user_logic_adder_2_to_1
generic map(
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Processor bus interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr(15 downto 0),
dab_sel => dab_sel_ul,
dab_wvalid => dab_wvalid_ul,
dab_rvalid => dab_rvalid_ul,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata_ul,
-- Streaming input interfaces
cin_tdata => cin_tdata_i,
cin_tvalid => cin_tvalid_i,
cin_tready => cin_tready_i,
cin_tlevel => cin_tlevel_i,
-- Streaming output interfaces
cout_tdata => cout_tdata_i,
cout_tvalid => cout_tvalid_i,
cout_tready => cout_tready_i,
-- Clock signals
user_clocks => user_clocks
);
end rtl;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis VIP AXISTREAM Library : axistream_bfm_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s).
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package axistream_bfm_pkg is
--========================================================================================================================
-- Types and constants for AXISTREAM_BFM
--========================================================================================================================
constant C_SCOPE : string := "AXISTREAM_BFM";
--========================================================================================================================
-- C_MAX_*_BITS : Maximum number of bits per data word supported by the BFM.
-- These constant can be increased as needed.
constant C_MAX_TUSER_BITS : positive := 8;
constant C_MAX_TSTRB_BITS : positive := 32; -- Must be large enough for number of data bytes per transfer, C_MAX_TSTRB_BITS >= tdata/8
constant C_MAX_TID_BITS : positive := 8; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_MAX_TDEST_BITS : positive := 4; -- Recommended maximum in protocol specification (ARM IHI0051A)
type t_user_array is array(natural range <>) of std_logic_vector(C_MAX_TUSER_BITS-1 downto 0);
type t_strb_array is array(natural range <>) of std_logic_vector(C_MAX_TSTRB_BITS-1 downto 0);
type t_id_array is array(natural range <>) of std_logic_vector(C_MAX_TID_BITS-1 downto 0);
type t_dest_array is array(natural range <>) of std_logic_vector(C_MAX_TDEST_BITS-1 downto 0);
--========================================================================================================================
-- Interface record for BFM signals
type t_axistream_if is record
tdata : std_logic_vector; -- Data. Width is constrained when the procedure is called
tkeep : std_logic_vector; -- One valid-bit per data byte
tuser : std_logic_vector; -- User sideband data
tvalid : std_logic; -- Data valid
tlast : std_logic; -- Active high during last data word in packet.
tready : std_logic; -- Backpressure
tstrb : std_logic_vector; -- Treated as sideband data by BFM: tstrb does not affect tdata
tid : std_logic_vector; -- Treated as sideband data by BFM
tdest : std_logic_vector; -- Treated as sideband data by BFM
end record;
-- Configuration record to be assigned in the test harness.
type t_axistream_bfm_config is
record
-- Common
max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready or valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
-- config for axistream_receive()
check_packet_length : boolean; -- When true, receive() will check that last is set at data_array'high
protocol_error_severity : t_alert_level; -- severity if protocol errors are detected by axistream_receive()
ready_low_at_word_num : integer; -- When the Sink BFM shall deassert ready
ready_low_duration : integer; -- Number of clock cycles to deassert ready
ready_default_value : std_logic; -- Which value the BFM shall set ready to between accesses.
-- Common
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the BFM
end record;
-- Define the default value for the BFM config
constant C_AXISTREAM_BFM_CONFIG_DEFAULT : t_axistream_bfm_config := (
max_wait_cycles => 100,
max_wait_cycles_severity => ERROR,
clock_period => 0 ns, -- Make sure we notice if we forget to set clock period.
check_packet_length => false,
protocol_error_severity => ERROR,
ready_low_at_word_num => 0,
ready_low_duration => 0,
ready_default_value => '0',
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--========================================================================================================================
-- BFM procedures
--========================================================================================================================
-- - This function returns an AXI Stream interface with initialized signals.
-- - All input signals are initialized to 0
-- - All output signals are initialized to Z
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural
) return t_axistream_if;
--
-- Source: BFM
-- Sink: DUT
--
procedure axistream_transmit (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
procedure axistream_transmit (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
procedure axistream_transmit (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
procedure axistream_transmit (
constant data_array : in t_byte_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
--
-- Source: DUT
-- Sink: BFM
--
procedure axistream_receive (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
-- Overloaded version without records
procedure axistream_receive (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
);
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
procedure axistream_expect (
constant exp_data_array : in t_byte_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
procedure axistream_expect (
constant exp_data_array : in t_byte_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
end package axistream_bfm_pkg;
--========================================================================================================================
--========================================================================================================================
package body axistream_bfm_pkg is
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural
) return t_axistream_if is
variable init_if : t_axistream_if(tdata(data_width-1 downto 0),
tkeep(data_width/8-1 downto 0),
tuser(user_width-1 downto 0),
tstrb(data_width/8-1 downto 0),
tid (id_width-1 downto 0),
tdest(dest_width-1 downto 0)
);
begin
if is_master then
-- from slave to master
init_if.tready := 'Z';
-- from master to slave
init_if.tvalid := '0';
init_if.tdata := (init_if.tdata'range => '0');
init_if.tkeep := (init_if.tkeep'range => '0');
init_if.tuser := (init_if.tuser'range => '0');
init_if.tstrb := (init_if.tstrb'range => '0');
init_if.tid := (init_if.tid'range => '0');
init_if.tdest := (init_if.tdest'range => '0');
init_if.tlast := '0';
else
-- from slave to master
init_if.tready := '0';
-- from master to slave
init_if.tvalid := 'Z';
init_if.tdata := (init_if.tdata'range => 'Z');
init_if.tkeep := (init_if.tkeep'range => 'Z');
init_if.tuser := (init_if.tuser'range => 'Z');
init_if.tstrb := (init_if.tstrb'range => 'Z');
init_if.tid := (init_if.tid'range => 'Z');
init_if.tdest := (init_if.tdest'range => 'Z');
init_if.tlast := 'Z';
end if;
return init_if;
end function;
-- Send a packet on the AXI interface.
-- Packet length and data is defined by data_array
-- tuser is set based on user_array,
-- tstrb is set based on strb_array, etc
procedure axistream_transmit (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_transmit";
constant proc_call : string := "axistream_transmit(" & to_string(data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current byte within the data word
variable v_byte_cnt : natural := 0;
variable v_clk_cycles_waited : natural := 0;
variable v_wait_for_next_transfer_cycle : boolean; -- When set, the BFM shall wait for at least one clock cycle, until tready='1' before continuing
-- Sampled tready for the current clock cycle
variable v_tready : std_logic;
begin
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.clock_period /= 0 ns, TB_ERROR, "Sanity check: Check that bfm_config.clock_period is set", scope, ID_NEVER, msg_id_panel, proc_call);
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length);
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
log(ID_PACKET_INITIATE, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
for byte in 0 to data_array'high loop
log(ID_PACKET_DATA, proc_call & "=> Tx " & to_string(data_array(byte), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
", byte# " & to_string(byte) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
axistream_if.tvalid <= '1';
-- Byte locations within the data word is described in chapter 2.3 in "ARM IHI0051A"
axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word) <= data_array(byte);
-- Set sideband data for this transfer (i.e. this word)
if v_byte_in_word = 0 then
axistream_if.tuser(c_num_user_bits_per_word-1 downto 0) <= user_array(byte/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0);
axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0) <= strb_array(byte/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0);
axistream_if.tid(c_num_id_bits_per_word-1 downto 0) <= id_array(byte/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0);
axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0) <= dest_array(byte/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0);
end if;
-- TKEEP[x] is associated with TDATA[(7+8*v_byte_in_word) : 8*v_byte_in_word].
axistream_if.tkeep(v_byte_in_word) <= '1';
-- Default: Go to next 'byte' iteration in zero time (when tdata is not completely fillled with bytes).
v_wait_for_next_transfer_cycle := false;
if byte = data_array'high then
-- Packet done.
axistream_if.tlast <= '1';
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
axistream_if.tlast <= '0';
end if;
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Next byte is in the next clk cycle
v_byte_in_word := 0;
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
-- Next byte is in the same clk cycle
v_byte_in_word := v_byte_in_word + 1;
end if;
--
-- If no more bytes to fill in tdata, wait until the transfer takes place (tvalid=1 and tready=1)
--
if v_wait_for_next_transfer_cycle then
wait until rising_edge(clk);
v_tready := axistream_if.tready; -- Will this cycle be a transfer? (tvalid=1 and tready=1)
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
while v_tready = '0' loop
wait until rising_edge(clk);
v_tready := axistream_if.tready; -- Will this cycle be a transfer? (tvalid=1 and tready=1)
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for tready " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
-- Default values for the next clk cycle
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length
);
end if;
end loop;
-- Done.
axistream_if.tvalid <= '0';
log(ID_PACKET_COMPLETE, proc_call & "=> Tx DONE" &
". " & add_msg_delimiter(msg),
scope, msg_id_panel);
end procedure axistream_transmit;
-- Overload that doesn't use records for the AXI interface:
-- (In turn calls the record version)
procedure axistream_transmit (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for strb_array, id_array, dest_array
procedure axistream_transmit (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for user_array, strb_array, id_array, dest_array
procedure axistream_transmit (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Receive a packet, store it in data_array
-- data_array'length can be longer than the actual packet, so that you can call receive() without knowing the length to be expected.
procedure axistream_receive (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
constant local_proc_name : string := "axistream_receive"; -- Internal proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()"; -- Internal proc_call; used if called from sequncer or VVC
-- Helper variables
variable v_proc_call : line; -- Current proc_call, external or local
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current Byte within the data word
variable v_byte_cnt : integer := 0; -- # bytes received
variable v_timeout : boolean := false;
variable v_done : boolean := false;
variable v_invalid_count : integer := 0; -- # cycles without valid being asserted
variable v_waited_this_iteration : boolean := false;
variable v_ready_low_done : boolean := false;
variable v_byte_idx : integer;
variable v_word_idx : integer;
begin
-- If called from sequencer/VVC, show 'axistream_receive()...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure like axistream_expect, log 'axistream_expect() while executing axistream_receive()...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(config.clock_period /= 0 ns, TB_ERROR, "Sanity check: Check that bfm_config.clock_period is set", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for knowing which byte is sent first", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- Avoid driving inputs
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length );
check_value(config.clock_period /= 0 ns, TB_ERROR, "Check that bfm_config.clock_period is set" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- wait until 1/4 clk period before rising edge
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
log(ID_PACKET_INITIATE, v_proc_call.all & "=> Receive packet. " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Sample byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
while not v_done loop
v_waited_this_iteration := false;
--
-- Set tready low before given word
--
if (v_byte_in_word = 0) and
(config.ready_low_at_word_num = v_byte_cnt/c_num_bytes_per_word) and
(not v_ready_low_done) then
axistream_if.tready <= '0';
-- If we deassert ready before byte 0, keep it deasserted until valid goes high so that it matters
if config.ready_low_at_word_num = 0 and axistream_if.tvalid = '0' then
wait until axistream_if.tvalid = '1';
-- wait until 1/4 clk period after rising edge
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
end if;
wait for config.ready_low_duration * config.clock_period;
v_ready_low_done := true;
end if;
axistream_if.tready <= '1'; -- In case it was '0'
wait for 0 ns; -- Wait for signal to change value
-- Wait until data is transferred: valid and ready
if axistream_if.tvalid = '1' and axistream_if.tready = '1' then
v_invalid_count := 0;
-- Sample data.
data_array(v_byte_cnt) := axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word);
-- Sample tuser for this transfer (this word): There is one user_array entry per word
if v_byte_in_word = 0 then
v_word_idx := v_byte_cnt/c_num_bytes_per_word;
if (v_word_idx <= user_array'high) then -- Include this 'if' to allow a shorter user_array if the caller doesn't care what tuser is
user_array(v_byte_cnt/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0) := axistream_if.tuser(c_num_user_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= strb_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tstrb is
strb_array(v_byte_cnt/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0) := axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= id_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tid is
id_array(v_byte_cnt/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0) := axistream_if.tid(c_num_id_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= dest_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tdest is
dest_array(v_byte_cnt/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0) := axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0);
end if;
end if;
log(ID_PACKET_DATA, v_proc_call.all & "=> Rx " & to_string(data_array(v_byte_cnt), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
" (byte# " & to_string(v_byte_cnt) & "). " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Check tlast='1' at expected last byte
if v_byte_cnt = data_array'high then
check_value(axistream_if.tlast, '1', config.protocol_error_severity, "Check tlast at expected last byte = " & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope);
v_done := true; -- Stop sampling data when we have filled the data_array
end if;
-- Allow that tlast arrives sooner than indicated by data_array'high
-- if receive() is called without knowing the length to be expected.
if axistream_if.tlast = '1' then
if axistream_if.tkeep(v_byte_in_word) = '1' then
if v_byte_in_word = c_num_bytes_per_word-1 then
-- it's the last byte in word and tlast='1', thus the last in packet.
v_done := true;
else
if axistream_if.tkeep(v_byte_in_word+1) = '0' then
-- Next byte in word is invalid, so this is the last byte
v_done := true;
-- Check that tkeep for the remaining bytes in the last word are also '0'. (Only continous stream supported)
v_byte_idx := v_byte_in_word+1;
l_check_remaining_TKEEP: loop
check_value(axistream_if.tkeep(v_byte_idx), '0', ERROR, "Check that tkeep doesn't go from '1' to '0' to '1' again within this last word. (The BFM supports only continuous stream)", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if v_byte_idx < (axistream_if.tkeep'length-1) then
v_byte_idx := v_byte_idx + 1;
else
exit l_check_remaining_TKEEP;
end if;
end loop;
end if;
end if;
end if;
else
-- tlast = 0
if (v_byte_cnt = data_array'high) then
alert(config.protocol_error_severity, v_proc_call.all & "=> Failed. tlast not received, expected at or before byte#" & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope);
end if;
-- Check that all tkeep bits are '1'. (Only continous stream supported)
check_value(axistream_if.tkeep(v_byte_in_word), '1', ERROR, "When tlast='0', check that all tkeep bits are '1'. (The BFM supports only continuous stream)" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Next byte is in the next clk cycle
wait for config.clock_period;
v_waited_this_iteration := true;
v_byte_in_word := 0;
else
-- Next byte is in the same clk cycle
v_byte_in_word := v_byte_in_word + 1;
end if;
-- Next byte
v_byte_cnt := v_byte_cnt + 1;
else
-- (tvalid and tready) = '0'
-- Check for timeout (also when max_wait_cycles_severity = NO_ALERT,
-- or else the VVC will wait forever, until the UVVM cmd times out)
if (v_invalid_count >= config.max_wait_cycles) then
v_timeout := true;
v_done := true;
else
v_invalid_count := v_invalid_count + 1;
end if;
wait for config.clock_period;
v_waited_this_iteration := true;
end if;
end loop; -- while not v_done
data_length := v_byte_cnt;
-- did we time out?
if v_timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " & add_msg_delimiter(msg), scope);
else
log(ID_PACKET_COMPLETE, v_proc_call.all & "=> Rx DONE (" & to_string(v_byte_cnt) & "B)" &
". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
if not v_waited_this_iteration then
-- Avoid sampling the same word again if the BFM is called again immediately
wait for config.clock_period;
end if;
-- Done
axistream_if.tready <= config.ready_default_value;
end procedure axistream_receive;
-- Overloaded version without records
procedure axistream_receive (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axistream_expect
) is
begin
-- Simply call the record version
axistream_receive(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure;
-- Receive data, then compare the received data against exp_data_array
-- - If the received data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_expect";
constant proc_call : string := "axistream_expect(" & to_string(exp_data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_config : t_axistream_bfm_config := config;
variable v_rx_data_array : t_byte_array(exp_data_array'range); -- received data
variable v_rx_user_array : t_user_array(exp_user_array'range); -- received tuser
variable v_rx_strb_array : t_strb_array(exp_strb_array'range);
variable v_rx_id_array : t_id_array(exp_id_array'range);
variable v_rx_dest_array : t_dest_array(exp_dest_array'range);
variable v_rx_data_length : natural;
variable v_data_error_cnt : natural := 0;
variable v_user_error_cnt : natural := 0;
variable v_strb_error_cnt : natural := 0;
variable v_id_error_cnt : natural := 0;
variable v_dest_error_cnt : natural := 0;
variable v_first_errored_byte : natural;
begin
-- Make the receive() procedure check tlast position is as expected
v_config.check_packet_length := true;
-- Receive and store data
axistream_receive(data_array => v_rx_data_array,
data_length => v_rx_data_length,
user_array => v_rx_user_array,
strb_array => v_rx_strb_array,
id_array => v_rx_id_array,
dest_array => v_rx_dest_array,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => v_config,
ext_proc_call => proc_call);
-- Check if each received bit matches the expected
-- Find and report the first errored byte
for byte in v_rx_data_array'high downto 0 loop
for i in v_rx_data_array(byte)'range loop
if (exp_data_array(byte)(i) = '-') or -- Expected set to don't care, or
(v_rx_data_array(byte)(i) = exp_data_array(byte)(i)) then -- received value matches expected
-- Check is OK
else
-- Received byte does not match the expected byte
--log(config.id_for_bfm, proc_call & "=> NOK, checked " & to_string(v_rx_data_array(byte), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_data_array(byte), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
v_data_error_cnt := v_data_error_cnt + 1;
v_first_errored_byte := byte;
end if;
end loop;
end loop;
-- Check tuser matches exp_user_array
-- Check all bits the exp_user_array. If the caller (Test Sequencer or VVC) don't care, the length of exp_user_array input shall be only one
for word in exp_user_array'high downto 0 loop
for i in c_num_user_bits_per_word-1 downto 0 loop -- i = bit
if (exp_user_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_user_array(word)(i) = exp_user_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tuser word does not match the expected word
v_user_error_cnt := v_user_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_strb_array matches received tstrb
for word in exp_strb_array'high downto 0 loop
for i in c_num_strb_bits_per_word-1 downto 0 loop -- i = bit
if (exp_strb_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_strb_array(word)(i) = exp_strb_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tstrb word does not match the expected word
v_strb_error_cnt := v_strb_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_id_array matches received tid
for word in exp_id_array'high downto 0 loop
for i in c_num_id_bits_per_word-1 downto 0 loop -- i = bit
if (exp_id_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_id_array(word)(i) = exp_id_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tid word does not match the expected word
v_id_error_cnt := v_id_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_dest_array matches received tdest
for word in exp_dest_array'high downto 0 loop
for i in c_num_dest_bits_per_word-1 downto 0 loop -- i = bit
if (exp_dest_array(word)(i) = '-') or -- Expected set to don't care, or
(v_rx_dest_array(word)(i) = exp_dest_array(word)(i)) then -- received value matches expected
-- Check is OK
-- log(ID_PACKET_COMPLETE, proc_call & "=> OK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tdest word does not match the expected word
v_dest_error_cnt := v_dest_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- No more than one alert per packet
if v_data_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_data_array(v_first_errored_byte), HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_data_array(v_first_errored_byte), HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_user_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_user_error_cnt) & " tuser bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_strb_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_strb_error_cnt) & " tstrb bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_id_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_id_error_cnt) & " tid bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_dest_error_cnt /= 0 then
alert(alert_level, proc_call & "=> Failed in "& to_string(v_dest_error_cnt) & " tdest bits. First mismatch in word# " & to_string(v_first_errored_byte) & ". Was " & to_string(v_rx_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & "B. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_expect;
-- Overloaded version without records
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-- Overload without exp_strb_array, exp_id_array, exp_dest_array arguments' argument
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-- Overload without arguments exp_user_array, exp_strb_array, exp_id_array, exp_dest_array arguments
procedure axistream_expect (
constant exp_data_array : in t_byte_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
end package body axistream_bfm_pkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
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