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-- -- pciradio.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A -- Author: Stephen A. Rodgers -- -- Copyright (c) 2004,2005 Stephen A. Rodgers -- -- Steve Rodgers <[email protected]> -- -- This program is free software, and the design, schematics, layout, -- and artwork for the hardware on which it runs is free, and all are -- distributed under the terms of the GNU General Public License. -- -- -- I/O Map -- -- Addr Read Write -- 0 MX_828_status_ch0 MX_828_address -- 1 MX_828_status_ch1 MX_828_first_byte/Xilinx programming -- 2 MX_828_status_ch2 MX_828 second byte -- 3 MX_828_status_ch3 MX_828_command -- 4 Uart Receive Data Uart Transmit Data -- 5 - - -- 6 - - -- 7 - - -- 8 UIO_AB UIO_AB -- 9 COR LED control -- A TEST/PTT TEST/PTT -- B RBS_Bytes_Queued RBS_Cmd -- C General_Status RBS_Data -- D IRQ_mask IRQ_mask -- E Control1 Control1 -- F Control2 Control2 -- -- * Control1 * -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- UIOBD3 UIOBD2 UIOBD1 UIOBD0 UIOAD3 UIOAD2 UIOAD1 UIOAD0 -- -- This register controls the direction of the UIOA and UIOB ports. -- Writing a 0 sets the port bit as an output, writing a 1 sets the -- port bit as an input. -- -- This register is cleared at power up. -- -- * Control2 * -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- SERSEL1 SERSEL0 SERC1 SERC0 TESTD3 TESTD2 TESTD1 TESTD0 -- -- This register controls the direction of the TEST port, and assigns the -- remote base serializer to a specific channel. -- -- SERSEL[1:0] -- -- Select which serializer to use: -- -- 00 - None -- 01 - RBI -- 10 - UART -- 11 - Reserved for future use -- -- -- SERC[1:0] -- Select the channel to assign the remote base serializer to using -- the following truth table: -- -- 00 - Channel 0 -- 01 - Channel 1 -- 10 - Channel 2 -- 11 - Channel 3 -- -- To use the remote base serializer on a given channel, that channel must -- have both its UIOA and UIOB direction bits set as output (0), and preferably -- have 0's programmed into the output register to prevent false clocking, if -- the serializer is dynamically shared between channels. -- -- -- TESTD[3:0] -- -- Writing a 0 sets the port bit as an output, writing a 1 sets the -- port bit as an input. This register is cleared at power up. -- -- This register is cleared at power up. -- -- * USTAT/COR * -- -- 7 6 5 4 3 2 1 0 -- UTXBUSY UOVRRUN UDIRTY UDAV COR3 COR2 COR1 COR0 -- -- -- These bits reflect the state of the UART and of the cor lines. -- -- -- * General Status * -- -- Read only -- -- 7 6 5 4 3 2 1 0 -- INT IMX828 RBSDN PLSDN - TXWTRIP RBSBSY PLSBSY -- -- -- -- INT - State of the interrupt line prior to reading this register -- IMX828 - Reflects the state of the MX828 wire-or interrupt -- PLSDN - Set to 1 when a command to the PL serializer completes -- RBSDN - Set to 1 when a command to the remote base serializer completes -- TXWTRIP - Set when the PTT's get inhibited by the TX watchdog -- RBSBSY - Set to 1 when the remote serializer is busy -- PLSBSY - Set to 1 when the PL serializer is busy -- -- To clear RBSDN and PLSDN, see the IRQ mask register. -- -- -- -- * IRQ mask * -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- MASTERM - - - - MMX828 MRBS MPLS -- -- MASTERM - Master mask. Masks the IRQ line when set to 1. -- MPLS - Masks the MX828 serializer completion interrupt -- MRBS - Masks the RBS serializer completion interrupt -- MMX828 - Masks the wire-or MX828 chip interrupt pins -- -- Mask = 1, Unmask = 0 -- This register will be set to 10000111 on power up -- -- Interrupts will be generated for the following events: -- -- High-to-low transition of the PLSBSY status bit (edge) -- High-to-low transition of the RBSBSY status bit (edge) -- When the IMX828 status bit is set (level). -- -- When the PLSDN or or RBSDN bits are set in the status -- register and you wish to clear them, you must mask then -- unmask them to clear them. -- -- -- -- * LED control * -- -- Write only -- -- 7 6 5 4 3 2 1 0 -- LED31 LED30 LED21 LED20 LED11 LED10 LED01 LED00 -- Where LEDx1 and LEDx0 are a truth table of: -- -- 00 - LED off -- 01 - LED green -- 10 - LED red -- 11 - LED yellow -- -- This register will be cleared on power up -- -- * MX828 address * -- -- Write only -- 7 6 5 4 3 2 1 0 -- - - - - - FREEZE MXA1 MXA0 -- This is the address used to select a particular MX828 device -- to issue a command to. This address doubles as the address used -- to program the Xilinx at initialization. -- The freeze bit is used to freeze the status update to the 4 MX828 status -- registers. Once the status has been read, the freeze bit should be cleared. -- -- Important: the freeze bit must be set and unset periodically to reset the -- TX watchdog. the TX watchdog will time out in 100 milliseconds if there is no -- freeze/unfreeze activity present. -- -- * MX828_command * -- -- Write only -- -- Command code to send to MX828 -- Refer to the MX828 data sheet -- -- Writing to this address starts the MX828 command serializer. -- -- * MX828_first_byte * -- -- Write only -- -- First data byte sent to MX828, also doubles as Xilinx programming write location. -- Refer to the MX828 data sheet. -- -- -- * MX828_status_ch0 * -- * MX828_status_ch1 * -- * MX828_status_ch2 * -- * MX828_status_ch3 * -- -- Read only -- -- Byte of data returned when MX828 read commands ar executed -- Refer to the MX828 data sheet -- -- * MX828_second_byte * -- -- Write only -- -- Second data byte sent to MX828. -- Refer to the MX828 data sheet -- -- -- * TEST/PTT * -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- -- TEST3 TEST2 TEST1 TEST0 PTT3 PTT2 PTT1 PTT0 -- -- Write a 1 to set PTT, 0 to clear PTT. -- Write 1 1 to set a test bit, and a 0 to clear a test bit -- This register will be cleared on power up. -- -- * RBS_Bytes_Queued * -- -- Read only -- -- 7 6 5 4 3 2 1 0 -- -- - - - - - BQ2 BQ1 BQ0 -- Indicates number of remote base serializer bytes queued in fifo (up to 6) -- This register will be cleared on power up. -- -- * RBS_Cmd * -- -- Write only -- -- 0x00 - Clear Queue -- 0x01 - Send bytes -- -- * RBS_Data * -- -- Write only -- -- Writing a byte to this register places it into the serializer FIFO. -- The FIFO can hold up to 6 bytes -- -- -- * UIO_AB * -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- UIOB3 UIOB2 UIOB1 UIOB0 UIOA3 UIOA2 UIOA1 UIOA0 -- -- This register will be cleared on power up. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pciradio is port ( arn : in std_logic; -- global reset clko_tj : in std_logic; -- clock from TJ oscillator cell from_mx828 : in std_logic; -- serial data from MX828 chips irqn_mx828 : in std_logic; -- IRQ from MX828 rdn : in std_logic; -- read strobe in from tigerjet wrn : in std_logic; -- write strobe in from tigerjet cor : in std_logic_vector(3 downto 0); -- cor status bits in ha : in std_logic_vector(3 downto 0); -- tigerjet GPIO address bus in hd : inout std_logic_vector(7 downto 0); -- tigerjet GPIO data bus testhdr : inout std_logic_vector(3 downto 0); -- test header pins uioa : inout std_logic_vector(3 downto 0); -- uio port a uiob : inout std_logic_vector(3 downto 0); -- uio port b clk2048 : out std_logic; -- 2048 KHz clock out tjfsc : out std_logic; -- tigerjet frame sync out clk_mx828 : out std_logic; -- serial clock to MX828's to_mx828 : out std_logic; -- serial data to MX828's tjirq : out std_logic; -- IRQ to tigerjet fsync : out std_logic_vector(3 downto 0); -- frame syncs to codecs csbn_mx828 : out std_logic_vector(3 downto 0); -- low-true chip selects to MX828's pttn : out std_logic_vector(3 downto 0); -- low-true PTT outputs led0 : out std_logic_vector(1 downto 0); -- LED for channel 0 led1 : out std_logic_vector(1 downto 0); -- LED for channel 1 led2 : out std_logic_vector(1 downto 0); -- LED for channel 2 led3 : out std_logic_vector(1 downto 0) -- LED for channel 3 ); end pciradio; architecture rtl of pciradio is signal busy_mx828 : std_logic; signal rd : std_logic; signal clk : std_logic; signal cmdsel_mx828 : std_logic; signal fbsel_mx828 : std_logic; signal sbsel_mx828 : std_logic; signal adsel_mx828 : std_logic; signal sel_uio : std_logic; signal sel_testptt : std_logic; signal sel_ctrl1 : std_logic; signal sel_ctrl2 : std_logic; signal sel_leds : std_logic; signal sel_irqmask : std_logic; signal sel_uarttx : std_logic; signal ledpwm : std_logic; signal rbs_regsel : std_logic; signal rbs_cmdsel : std_logic; signal rbsclk : std_logic; signal rbsdata : std_logic; signal rbs_busy : std_logic; signal irq_mx828 : std_logic; signal mxaccess : std_logic; signal tjirqint : std_logic; signal rbs_bq : std_logic_vector(2 downto 0); signal csb_mx828 : std_logic_vector(3 downto 0); signal stat_mx8280 : std_logic_vector(7 downto 0); signal stat_mx8281 : std_logic_vector(7 downto 0); signal stat_mx8282 : std_logic_vector(7 downto 0); signal stat_mx8283 : std_logic_vector(7 downto 0); signal uart_rxdata : std_logic_vector(7 downto 0); signal uioin : std_logic_vector(7 downto 0); signal uioout : std_logic_vector(7 downto 0); signal testpttin : std_logic_vector(7 downto 0); signal testpttout : std_logic_vector(7 downto 0); signal wdb : std_logic_vector(7 downto 0); signal rdb : std_logic_vector(7 downto 0); signal statusreg : std_logic_vector(7 downto 0); signal ctrlout1 : std_logic_vector(7 downto 0); signal ctrlout2 : std_logic_vector(7 downto 0); signal corbits : std_logic_vector(7 downto 0); signal irqmaskbits : std_logic_vector(7 downto 0); component mx_seq port ( signal arn : in std_logic; signal clk : in std_logic; signal from_mx828 : in std_logic; signal wrn : in std_logic; signal cmdsel : in std_logic; signal fbsel : in std_logic; signal sbsel : in std_logic; signal adsel : in std_logic; signal wdb : in std_logic_vector(7 downto 0); signal busy : out std_logic; signal to_mx828 : out std_logic; signal clk_mx828 : out std_logic; signal mxaccess : out std_logic; signal csb_mx828 : out std_logic_vector(3 downto 0); signal stat_mx8280 : out std_logic_vector(7 downto 0); signal stat_mx8281 : out std_logic_vector(7 downto 0); signal stat_mx8282 : out std_logic_vector(7 downto 0); signal stat_mx8283 : out std_logic_vector(7 downto 0) ); end component; component io port ( arn : in std_logic; clk : in std_logic; wrn : in std_logic; rd : in std_logic; sel_uio : in std_logic; sel_testptt : in std_logic; sel_ctrl1 : in std_logic; sel_ctrl2 : in std_logic; sel_leds : in std_logic; sel_irqmask : in std_logic; sel_uarttx : in std_logic; rbsclk : in std_logic; rbsdata : in std_logic; irq_mx828 : in std_logic; ledpwm : in std_logic; rbs_busy : in std_logic; busy_mx828 : in std_logic; mxaccess : in std_logic; uioinlsb : in std_logic_vector(3 downto 0); cor : in std_logic_vector(3 downto 0); wdb : in std_logic_vector(7 downto 0); tjirq : out std_logic; led0 : out std_logic_vector(1 downto 0); led1 : out std_logic_vector(1 downto 0); led2 : out std_logic_vector(1 downto 0); led3 : out std_logic_vector(1 downto 0); uioout : out std_logic_vector(7 downto 0); testpttout : out std_logic_vector(7 downto 0); ctrlout1 : out std_logic_vector(7 downto 0); ctrlout2 : out std_logic_vector(7 downto 0); statusreg : out std_logic_vector(7 downto 0); corbits : out std_logic_vector(7 downto 0); irqmaskbits : out std_logic_vector(7 downto 0); uart_rxdata : out std_logic_vector(7 downto 0) ); end component; component frame port ( arn : in std_logic; clk : in std_logic; clk2048 : out std_logic; tjfsc : out std_logic; ledpwm : out std_logic; fsync : out std_logic_vector(3 downto 0) ); end component; component rbs port ( arn : in std_logic; clk : in std_logic; wrn : in std_logic; regsel : in std_logic; cmdsel : in std_logic; wdb : in std_logic_vector(7 downto 0); rbsclk : out std_logic; rbsdata : out std_logic; busy : out std_logic; bq : out std_logic_vector(2 downto 0) ); end component; begin mxseq_i : mx_seq port map ( arn => arn, clk => clk, from_mx828 => from_mx828, wrn => wrn, cmdsel => cmdsel_mx828, fbsel => fbsel_mx828, sbsel => sbsel_mx828, adsel => adsel_mx828, wdb => wdb, busy => busy_mx828, to_mx828 => to_mx828, clk_mx828 => clk_mx828, csb_mx828 => csb_mx828, mxaccess => mxaccess, stat_mx8280 => stat_mx8280, stat_mx8281 => stat_mx8281, stat_mx8282 => stat_mx8282, stat_mx8283 => stat_mx8283 ); io_i : io port map ( arn => arn, clk => clk, wrn => wrn, rd => rd, sel_uio => sel_uio, sel_testptt => sel_testptt, sel_ctrl1 => sel_ctrl1, sel_ctrl2 => sel_ctrl2, sel_leds => sel_leds, sel_irqmask => sel_irqmask, sel_uarttx => sel_uarttx, rbsclk => rbsclk, rbsdata => rbsdata, irq_mx828 => irq_mx828, ledpwm => ledpwm, rbs_busy => rbs_busy, busy_mx828 => busy_mx828, mxaccess => mxaccess, uioinlsb => uioin(3 downto 0), cor => cor, wdb => wdb, tjirq => tjirqint, led0 => led0, led1 => led1, led2 => led2, led3 => led3, uioout => uioout, testpttout => testpttout, ctrlout1 => ctrlout1, ctrlout2 => ctrlout2, statusreg => statusreg, corbits => corbits, irqmaskbits => irqmaskbits, uart_rxdata => uart_rxdata ); frame_i : frame port map ( arn => arn, clk => clk, clk2048 => clk2048, tjfsc => tjfsc, ledpwm => ledpwm, fsync => fsync ); rbs_i : rbs port map ( arn => arn, clk => clk, wrn => wrn, regsel => rbs_regsel, cmdsel => rbs_cmdsel, wdb => wdb, rbsclk => rbsclk, rbsdata => rbsdata, busy => rbs_busy, bq => rbs_bq ); -- multiplex all read ports rd_mux : process( ha, stat_mx8280, stat_mx8281, stat_mx8282, stat_mx8283, testpttin, uioin, ctrlout1, ctrlout2, rbs_bq, statusreg, corbits, irqmaskbits, uart_rxdata) begin case ha is when "0000" => rdb <= stat_mx8280; when "0001" => rdb <= stat_mx8281; when "0010" => rdb <= stat_mx8282; when "0011" => rdb <= stat_mx8283; when "0100" => rdb <= uart_rxdata; when "1000" => rdb <= uioin; when "1001" => rdb <= corbits; when "1010" => rdb <= testpttin; when "1011" => rdb <= "00000" & rbs_bq; when "1100" => rdb <= statusreg; when "1101" => rdb <= irqmaskbits; when "1110" => rdb <= ctrlout1; when "1111" => rdb <= ctrlout2; when others => rdb <= "00000000"; end case; end process rd_mux; -- decode individual selects sel_dec : process(ha) begin cmdsel_mx828 <= '0'; fbsel_mx828 <= '0'; sbsel_mx828 <= '0'; adsel_mx828 <= '0'; sel_uio <= '0'; sel_testptt <= '0'; sel_ctrl1 <= '0'; sel_ctrl2 <= '0'; sel_irqmask <= '0'; sel_uarttx <= '0'; sel_leds <= '0'; rbs_regsel <= '0'; rbs_cmdsel <= '0'; case ha is when "0000" => adsel_mx828 <= '1'; when "0001" => fbsel_mx828 <= '1'; when "0010" => sbsel_mx828 <= '1'; when "0011" => cmdsel_mx828 <= '1'; when "0100" => sel_uarttx <= '1'; when "1000" => sel_uio <= '1'; when "1001" => sel_leds <= '1'; when "1010" => sel_testptt <= '1'; when "1011" => rbs_cmdsel <= '1'; when "1100" => rbs_regsel <= '1'; when "1101" => sel_irqmask <= '1'; when "1110" => sel_ctrl1 <= '1'; when "1111" => sel_ctrl2 <= '1'; when others => null; end case; end process sel_dec; -- -- concurrent statements -- clk <= clko_tj; rd <= not rdn; irq_mx828 <= not irqn_mx828; -- data bus bidirect hd <= rdb when rd = '1' and wrn = '1' else "ZZZZZZZZ"; -- drive data bus on rd active; don't drive the bus during a reset wdb <= hd; -- interrupt tristate driver tjirq <= 'Z'; -- implement tristate control for bidirects GEN_testhdr : for I in 0 to 3 generate testhdr(I) <= testpttout(I+4) when ctrlout2(I) = '0' else 'Z'; end generate GEN_testhdr; GEN_uioa : for I in 0 to 3 generate uioa(I) <= uioout(I) when ctrlout1(I) = '0' else 'Z'; end generate GEN_uioa; GEN_uiob : for I in 0 to 3 generate uiob(I) <= uioout(I+4) when ctrlout1(I+4) = '0' else 'Z'; end generate GEN_uiob; uioin <= uiob(3 downto 0) & uioa(3 downto 0); testpttin <= testhdr(3 downto 0) & testpttout(3 downto 0); -- invert outputs which need to be csbn_mx828 <= not csb_mx828; pttn <= not testpttout(3 downto 0); end rtl;
use std.env.all; entity wave7 is end entity; architecture test of wave7 is signal x : integer; begin x <= 1 after 1 ns, 2 after 2 ns, 3 after 4 ns; process is begin wait for 3 ns; stop; end process; end architecture;
--------------------------------------------------------------------------- -- (c) 2013 mark watson -- I am happy for anyone to use this for non-commercial use. -- If my vhdl files are used commercially or otherwise sold, -- please contact me for explicit permission at scrameta (gmail). -- This applies for source and binary form and derived works. --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; -- KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code -- KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed -- SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held -- CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held -- BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers) ENTITY ps2_keyboard IS PORT ( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; PS2_CLK : IN STD_LOGIC; PS2_DAT : IN STD_LOGIC; KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code KEY_EXTENDED : OUT STD_LOGIC; -- valid on event, if scan code extended KEY_UP : OUT STD_LOGIC -- value on event, if key released ); END ps2_keyboard; ARCHITECTURE vhdl OF ps2_keyboard IS component enable_divider IS generic(COUNT : natural := 1); PORT ( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; ENABLE_IN : IN STD_LOGIC; ENABLE_OUT : OUT STD_LOGIC ); END component; function To_Std_Logic(L: BOOLEAN) return std_ulogic is begin if L then return('1'); else return('0'); end if; end function To_Std_Logic; -- PS2 keyboard sends on its own clock high->low transition -- start, 8 data bits, parity, stop -- Codes are either 1 bytes or 2 bytes (extended) on press -- XX -- EX YY -- Codes are eighter 2 bytes or 3 bytes (extended) on release -- F0 XX -- EX F0 YY -- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77 -- LSB first -- Start bit 0 -- Stop bit 1 -- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7)) -- e.g. -- '0 1100 0010 0 1' -- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0 -- Receive raw data from ps2 serial interface signal ps2_shiftreg_next : std_logic_vector(10 downto 0); signal ps2_shiftreg_reg : std_logic_vector(10 downto 0); signal idle_next : std_logic_vector(3 downto 0); signal idle_reg : std_logic_vector(3 downto 0); signal bitcount_next : std_logic_vector(3 downto 0); signal bitcount_reg : std_logic_vector(3 downto 0); signal enable_ps2 : std_logic; signal last_ps2_clk_next : std_logic; signal last_ps2_clk_reg : std_logic; signal ps2_clk_reg : std_logic; signal ps2_dat_reg : std_logic; signal parity : std_logic; -- Once we have whole parity checked bytes signal byte_next : std_logic_vector(7 downto 0); signal byte_reg : std_logic_vector(7 downto 0); signal byte_received_next : std_logic; signal byte_received_reg : std_logic; -- Decode if they are press(or repeat)/release or extended signal pending_extended_next : std_logic; signal pending_extended_reg : std_logic; signal pending_keyup_next : std_logic; signal pending_keyup_reg : std_logic; -- To eventually get the code itself signal key_event_next : std_logic; signal key_event_reg : std_logic; signal key_value_next : std_logic_vector(9 downto 0); signal key_value_reg : std_logic_vector(9 downto 0); -- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard signal key_value_last_next : std_logic_vector(9 downto 0); signal key_value_last_reg : std_logic_vector(9 downto 0); BEGIN -- register process(clk,reset_n) begin if (reset_n = '0') then ps2_clk_reg <= '0'; ps2_dat_reg <= '0'; -- Convert to bytes/verify last_ps2_clk_reg <= '0'; ps2_shiftreg_reg<= (others=>'0'); idle_reg <= (others=>'0'); bitcount_reg <= (others=>'0'); byte_received_reg <= '0'; byte_reg <= (others=>'0'); -- Handle simple byte strings (extended,byte extended,release,byte byte release,byte) pending_extended_reg <= '0'; pending_keyup_reg <= '0'; -- Output registers key_event_reg <= '0'; key_value_reg <= (others=>'0'); key_value_last_reg <= (others=>'0'); elsif (clk'event and clk='1') then -- Raw interface -- async - do we need some form of synchronizer? ps2_clk_reg <= ps2_clk; ps2_dat_reg <= ps2_dat; -- Convert to bytes/verify last_ps2_clk_reg <= last_ps2_clk_next; ps2_shiftreg_reg<= ps2_shiftreg_next; idle_reg <= idle_next; bitcount_reg <= bitcount_next; byte_received_reg <= byte_received_next; byte_reg <= byte_next; -- Handle simple byte strings (extended,byte extended,release,byte byte release,byte) pending_extended_reg <= pending_extended_next; pending_keyup_reg <= pending_keyup_next; -- Output registers key_event_reg <= key_event_next; key_value_reg <= key_value_next; key_value_last_reg <= key_value_last_next; end if; end process; -- Divide clock by 256 to get approx 4*ps2 clock enable_div : enable_divider generic map (COUNT=>256) port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2); -- capture bytes from ps2 parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1)); process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity) begin ps2_shiftreg_next <= ps2_shiftreg_reg; last_ps2_clk_next <= last_ps2_clk_reg; bitcount_next <= bitcount_reg; idle_next <= idle_reg; byte_received_next <= '0'; byte_next <= (others=>'0'); if (enable_ps2 = '1') then last_ps2_clk_next <= ps2_clk_reg; -- sample on falling edge if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1); bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1); end if; -- output to next stage when done if (bitcount_reg = X"B") then byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10); byte_next <= ps2_shiftreg_reg(8 downto 1); bitcount_next <= (others=>'0'); end if; -- reset if both high for a time period idle_next <= std_logic_vector(unsigned(idle_reg) +1); if (idle_reg = X"F") then ps2_shiftreg_next <= (others=>'0'); bitcount_next <= (others=>'0'); end if; if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then idle_next <= X"0"; end if; end if; end process; -- process bytes process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg) begin pending_extended_next <= pending_extended_reg; pending_keyup_next <= pending_keyup_reg; key_event_next <= '0'; key_value_next <= (others =>'0'); key_value_last_next <= key_value_last_reg; if (byte_received_reg = '1') then case byte_reg is when X"E0" => pending_extended_next <= '1'; when X"E1" => pending_extended_next <= '1'; when X"F0" => pending_keyup_next <= '1'; when others => pending_extended_next <= '0'; pending_keyup_next <= '0'; if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then key_event_next <= '1'; key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0); key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0); end if; end case; end if; end process; -- Output key_event <= key_event_reg; key_value <= key_value_reg(7 downto 0); key_extended <= key_value_reg(8); key_up <= key_value_reg(9); END vhdl;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pgfafIGGp1tHNQPDXi+OQpZbcu2upcV93o63NRGqNNXWpUk0deitz7Tr2tFq2IAmDb9e5cDGzosN wc2HwV4SZrznPMxa5rnP4UZLSClctZgURi4Som//iIktCWSStO+jq5SZyuVvMYghufzLjPqnSq9U 1bj9vnfPyo8Q2hlqXWg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block heJdJqnqzjVrY/S+XNH4QV3QihEwi8x4Ix2h9aqH6V7ViDMghYArPkAxVO6Vx9Htmx+sZ2yLq4Cz x8ynQe3IaPqHbBNdi9n+KbU2uCHWUpGKFGmU/LYOmNMRLKMEyqEUfJLzc8NpaFHn85hzZraBmUO4 aGpuvZoUNP+bwT2kd44TT7MOnaC7QDOjmY0xtsBie6UH37DZd62dHCPksfoaABt20PcFMr2srBib bLhzlGOJLjsebEcXRnzCco4XEuikFgWWWB2pd+Mj8elgDokgaXws6I5912Ez8ZdNcrsdgzgJk1m6 EDRohn4BMUWNyQVs+GvfHBB2PAQOdskUT25CmA== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ED3v4CpU6j53PGNeXye1tx8ABSsZBn1OT/PYmlGlCDLQWHFrax6zuosDPcbkRx4O0w8xZyqIx8qV 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architecture RTL of SPIShifter is signal EnableShiftReg : STD_LOGIC; signal ShiftRegister : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal NextShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal LoadShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataInRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataOut : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataOutRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal SampleRegister : STD_LOGIC; begin -- calculate DataInRev DataInputReversion: process (Data_i) begin for BitNumber in DataWidth-1 downto 0 loop DataInRev(BitNumber) <= Data_i((DataWidth-1) - BitNumber); end loop; end process DataInputReversion; -- combinational inputs EnableShiftReg <= LdShifter_i or EnShift_i; LoadShiftReg <= Data_i when LSBFE_i = '0' else DataInRev; NextShiftReg <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister when LdShifter_i = '0' else LoadShiftReg; -- sequential statements SPIShiftRegister: process (Reset_n, Clk) begin if Reset_n = '0' then ShiftRegister <= (others => '0'); elsif Clk'event and Clk = '1' then if EnableShiftReg = '1' then ShiftRegister <= NextShiftReg; end if; end if; end process SPIShiftRegister; SPISampleRegister: process (Reset_n, Clk) begin if Reset_n = '0' then SampleRegister <= '0'; elsif Clk'event and Clk = '1' then if EnSample_i = '1' then SampleRegister <= To_X01(MISO_i); end if; end if; end process SPISampleRegister; -- calculate DataOut DataOut <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister; -- calculate DataOutRev DataOutputReversion: process (DataOut) begin for BitNumber in DataWidth-1 downto 0 loop DataOutRev(BitNumber) <= DataOut((DataWidth-1) - BitNumber); end loop; end process DataOutputReversion; -- combinational outputs MOSI_o <= ShiftRegister(DataWidth-1); Data_o <= DataOut when LSBFE_i = '0' else DataOutRev; end RTL;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity aestest_sboxes_rom is generic( dwidth : integer := 8; awidth : integer := 8; mem_size : integer := 256 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); addr2 : in std_logic_vector(awidth-1 downto 0); ce2 : in std_logic; q2 : out std_logic_vector(dwidth-1 downto 0); addr3 : in std_logic_vector(awidth-1 downto 0); ce3 : in std_logic; q3 : out std_logic_vector(dwidth-1 downto 0); addr4 : in std_logic_vector(awidth-1 downto 0); ce4 : in std_logic; q4 : out std_logic_vector(dwidth-1 downto 0); addr5 : in std_logic_vector(awidth-1 downto 0); ce5 : in std_logic; q5 : out std_logic_vector(dwidth-1 downto 0); addr6 : in std_logic_vector(awidth-1 downto 0); ce6 : in std_logic; q6 : out std_logic_vector(dwidth-1 downto 0); addr7 : in std_logic_vector(awidth-1 downto 0); ce7 : in std_logic; q7 : out std_logic_vector(dwidth-1 downto 0); addr8 : in std_logic_vector(awidth-1 downto 0); ce8 : in std_logic; q8 : out std_logic_vector(dwidth-1 downto 0); addr9 : in std_logic_vector(awidth-1 downto 0); ce9 : in std_logic; q9 : out std_logic_vector(dwidth-1 downto 0); addr10 : in std_logic_vector(awidth-1 downto 0); ce10 : in std_logic; q10 : out std_logic_vector(dwidth-1 downto 0); addr11 : in std_logic_vector(awidth-1 downto 0); ce11 : in std_logic; q11 : out std_logic_vector(dwidth-1 downto 0); addr12 : in std_logic_vector(awidth-1 downto 0); ce12 : in std_logic; q12 : out std_logic_vector(dwidth-1 downto 0); addr13 : in std_logic_vector(awidth-1 downto 0); ce13 : in std_logic; q13 : out std_logic_vector(dwidth-1 downto 0); addr14 : in std_logic_vector(awidth-1 downto 0); ce14 : in std_logic; q14 : out std_logic_vector(dwidth-1 downto 0); addr15 : in std_logic_vector(awidth-1 downto 0); ce15 : in std_logic; q15 : out std_logic_vector(dwidth-1 downto 0); addr16 : in std_logic_vector(awidth-1 downto 0); ce16 : in std_logic; q16 : out std_logic_vector(dwidth-1 downto 0); addr17 : in std_logic_vector(awidth-1 downto 0); ce17 : in std_logic; q17 : out std_logic_vector(dwidth-1 downto 0); addr18 : in std_logic_vector(awidth-1 downto 0); ce18 : in std_logic; q18 : out std_logic_vector(dwidth-1 downto 0); addr19 : in std_logic_vector(awidth-1 downto 0); ce19 : in std_logic; q19 : out std_logic_vector(dwidth-1 downto 0); addr20 : in std_logic_vector(awidth-1 downto 0); ce20 : in std_logic; q20 : out std_logic_vector(dwidth-1 downto 0); addr21 : in std_logic_vector(awidth-1 downto 0); ce21 : in std_logic; q21 : out std_logic_vector(dwidth-1 downto 0); addr22 : in std_logic_vector(awidth-1 downto 0); ce22 : in std_logic; q22 : out std_logic_vector(dwidth-1 downto 0); addr23 : in std_logic_vector(awidth-1 downto 0); ce23 : in std_logic; q23 : out std_logic_vector(dwidth-1 downto 0); addr24 : in std_logic_vector(awidth-1 downto 0); ce24 : in std_logic; q24 : out std_logic_vector(dwidth-1 downto 0); addr25 : in std_logic_vector(awidth-1 downto 0); ce25 : in std_logic; q25 : out std_logic_vector(dwidth-1 downto 0); addr26 : in std_logic_vector(awidth-1 downto 0); ce26 : in std_logic; q26 : out std_logic_vector(dwidth-1 downto 0); addr27 : in std_logic_vector(awidth-1 downto 0); ce27 : in std_logic; q27 : out std_logic_vector(dwidth-1 downto 0); addr28 : in std_logic_vector(awidth-1 downto 0); ce28 : in std_logic; q28 : out std_logic_vector(dwidth-1 downto 0); addr29 : in std_logic_vector(awidth-1 downto 0); ce29 : in std_logic; q29 : out std_logic_vector(dwidth-1 downto 0); addr30 : in std_logic_vector(awidth-1 downto 0); ce30 : in std_logic; q30 : out std_logic_vector(dwidth-1 downto 0); addr31 : in std_logic_vector(awidth-1 downto 0); ce31 : in std_logic; q31 : out std_logic_vector(dwidth-1 downto 0); addr32 : in std_logic_vector(awidth-1 downto 0); ce32 : in std_logic; q32 : out std_logic_vector(dwidth-1 downto 0); addr33 : in std_logic_vector(awidth-1 downto 0); ce33 : in std_logic; q33 : out std_logic_vector(dwidth-1 downto 0); addr34 : in std_logic_vector(awidth-1 downto 0); ce34 : in std_logic; q34 : out std_logic_vector(dwidth-1 downto 0); addr35 : in std_logic_vector(awidth-1 downto 0); ce35 : in std_logic; q35 : out std_logic_vector(dwidth-1 downto 0); addr36 : in std_logic_vector(awidth-1 downto 0); ce36 : in std_logic; q36 : out std_logic_vector(dwidth-1 downto 0); addr37 : in std_logic_vector(awidth-1 downto 0); ce37 : in std_logic; q37 : out std_logic_vector(dwidth-1 downto 0); addr38 : in std_logic_vector(awidth-1 downto 0); ce38 : in std_logic; q38 : out std_logic_vector(dwidth-1 downto 0); addr39 : in std_logic_vector(awidth-1 downto 0); ce39 : in std_logic; q39 : out std_logic_vector(dwidth-1 downto 0); addr40 : in std_logic_vector(awidth-1 downto 0); ce40 : in std_logic; q40 : out std_logic_vector(dwidth-1 downto 0); addr41 : in std_logic_vector(awidth-1 downto 0); ce41 : in std_logic; q41 : out std_logic_vector(dwidth-1 downto 0); addr42 : in std_logic_vector(awidth-1 downto 0); ce42 : in std_logic; q42 : out std_logic_vector(dwidth-1 downto 0); addr43 : in std_logic_vector(awidth-1 downto 0); ce43 : in std_logic; q43 : out std_logic_vector(dwidth-1 downto 0); addr44 : in std_logic_vector(awidth-1 downto 0); ce44 : in std_logic; q44 : out std_logic_vector(dwidth-1 downto 0); addr45 : in std_logic_vector(awidth-1 downto 0); ce45 : in std_logic; q45 : out std_logic_vector(dwidth-1 downto 0); addr46 : in std_logic_vector(awidth-1 downto 0); ce46 : in std_logic; q46 : out std_logic_vector(dwidth-1 downto 0); addr47 : in std_logic_vector(awidth-1 downto 0); ce47 : in std_logic; q47 : out std_logic_vector(dwidth-1 downto 0); addr48 : in std_logic_vector(awidth-1 downto 0); ce48 : in std_logic; q48 : out std_logic_vector(dwidth-1 downto 0); addr49 : in std_logic_vector(awidth-1 downto 0); ce49 : in std_logic; q49 : out std_logic_vector(dwidth-1 downto 0); addr50 : in std_logic_vector(awidth-1 downto 0); ce50 : in std_logic; q50 : out std_logic_vector(dwidth-1 downto 0); addr51 : in std_logic_vector(awidth-1 downto 0); ce51 : in std_logic; q51 : out std_logic_vector(dwidth-1 downto 0); addr52 : in std_logic_vector(awidth-1 downto 0); ce52 : in std_logic; q52 : out std_logic_vector(dwidth-1 downto 0); addr53 : in std_logic_vector(awidth-1 downto 0); ce53 : in std_logic; q53 : out std_logic_vector(dwidth-1 downto 0); addr54 : in std_logic_vector(awidth-1 downto 0); ce54 : in std_logic; q54 : out std_logic_vector(dwidth-1 downto 0); addr55 : in std_logic_vector(awidth-1 downto 0); ce55 : in std_logic; q55 : out std_logic_vector(dwidth-1 downto 0); addr56 : in std_logic_vector(awidth-1 downto 0); ce56 : in std_logic; q56 : out std_logic_vector(dwidth-1 downto 0); addr57 : in std_logic_vector(awidth-1 downto 0); ce57 : in std_logic; q57 : out std_logic_vector(dwidth-1 downto 0); addr58 : in std_logic_vector(awidth-1 downto 0); ce58 : in std_logic; q58 : out std_logic_vector(dwidth-1 downto 0); addr59 : in std_logic_vector(awidth-1 downto 0); ce59 : in std_logic; q59 : out std_logic_vector(dwidth-1 downto 0); addr60 : in std_logic_vector(awidth-1 downto 0); ce60 : in std_logic; q60 : out std_logic_vector(dwidth-1 downto 0); addr61 : in std_logic_vector(awidth-1 downto 0); ce61 : in std_logic; q61 : out std_logic_vector(dwidth-1 downto 0); addr62 : in std_logic_vector(awidth-1 downto 0); ce62 : in std_logic; q62 : out std_logic_vector(dwidth-1 downto 0); addr63 : in std_logic_vector(awidth-1 downto 0); ce63 : in std_logic; q63 : out std_logic_vector(dwidth-1 downto 0); addr64 : in std_logic_vector(awidth-1 downto 0); ce64 : in std_logic; q64 : out std_logic_vector(dwidth-1 downto 0); addr65 : in std_logic_vector(awidth-1 downto 0); ce65 : in std_logic; q65 : out std_logic_vector(dwidth-1 downto 0); addr66 : in std_logic_vector(awidth-1 downto 0); ce66 : in std_logic; q66 : out std_logic_vector(dwidth-1 downto 0); addr67 : in std_logic_vector(awidth-1 downto 0); ce67 : in std_logic; q67 : out std_logic_vector(dwidth-1 downto 0); addr68 : in std_logic_vector(awidth-1 downto 0); ce68 : in std_logic; q68 : out std_logic_vector(dwidth-1 downto 0); addr69 : in std_logic_vector(awidth-1 downto 0); ce69 : in std_logic; q69 : out std_logic_vector(dwidth-1 downto 0); addr70 : in std_logic_vector(awidth-1 downto 0); ce70 : in std_logic; q70 : out std_logic_vector(dwidth-1 downto 0); addr71 : in std_logic_vector(awidth-1 downto 0); ce71 : in std_logic; q71 : out std_logic_vector(dwidth-1 downto 0); addr72 : in std_logic_vector(awidth-1 downto 0); ce72 : in std_logic; q72 : out std_logic_vector(dwidth-1 downto 0); addr73 : in std_logic_vector(awidth-1 downto 0); ce73 : in std_logic; q73 : out std_logic_vector(dwidth-1 downto 0); addr74 : in std_logic_vector(awidth-1 downto 0); ce74 : in std_logic; q74 : out std_logic_vector(dwidth-1 downto 0); addr75 : in std_logic_vector(awidth-1 downto 0); ce75 : in std_logic; q75 : out std_logic_vector(dwidth-1 downto 0); addr76 : in std_logic_vector(awidth-1 downto 0); ce76 : in std_logic; q76 : out std_logic_vector(dwidth-1 downto 0); addr77 : in std_logic_vector(awidth-1 downto 0); ce77 : in std_logic; q77 : out std_logic_vector(dwidth-1 downto 0); addr78 : in std_logic_vector(awidth-1 downto 0); ce78 : in std_logic; q78 : out std_logic_vector(dwidth-1 downto 0); addr79 : in std_logic_vector(awidth-1 downto 0); ce79 : in std_logic; q79 : out std_logic_vector(dwidth-1 downto 0); addr80 : in std_logic_vector(awidth-1 downto 0); ce80 : in std_logic; q80 : out std_logic_vector(dwidth-1 downto 0); addr81 : in std_logic_vector(awidth-1 downto 0); ce81 : in std_logic; q81 : out std_logic_vector(dwidth-1 downto 0); addr82 : in std_logic_vector(awidth-1 downto 0); ce82 : in std_logic; q82 : out std_logic_vector(dwidth-1 downto 0); addr83 : in std_logic_vector(awidth-1 downto 0); ce83 : in std_logic; q83 : out std_logic_vector(dwidth-1 downto 0); addr84 : in std_logic_vector(awidth-1 downto 0); ce84 : in std_logic; q84 : out std_logic_vector(dwidth-1 downto 0); addr85 : in std_logic_vector(awidth-1 downto 0); ce85 : in std_logic; q85 : out std_logic_vector(dwidth-1 downto 0); addr86 : in std_logic_vector(awidth-1 downto 0); ce86 : in std_logic; q86 : out std_logic_vector(dwidth-1 downto 0); addr87 : in std_logic_vector(awidth-1 downto 0); ce87 : in std_logic; q87 : out std_logic_vector(dwidth-1 downto 0); addr88 : in std_logic_vector(awidth-1 downto 0); ce88 : in std_logic; q88 : out std_logic_vector(dwidth-1 downto 0); addr89 : in std_logic_vector(awidth-1 downto 0); ce89 : in std_logic; q89 : out std_logic_vector(dwidth-1 downto 0); addr90 : in std_logic_vector(awidth-1 downto 0); ce90 : in std_logic; q90 : out std_logic_vector(dwidth-1 downto 0); addr91 : in std_logic_vector(awidth-1 downto 0); ce91 : in std_logic; q91 : out std_logic_vector(dwidth-1 downto 0); addr92 : in std_logic_vector(awidth-1 downto 0); ce92 : in std_logic; q92 : out std_logic_vector(dwidth-1 downto 0); addr93 : in std_logic_vector(awidth-1 downto 0); ce93 : in std_logic; q93 : out std_logic_vector(dwidth-1 downto 0); addr94 : in std_logic_vector(awidth-1 downto 0); ce94 : in std_logic; q94 : out std_logic_vector(dwidth-1 downto 0); addr95 : in std_logic_vector(awidth-1 downto 0); ce95 : in std_logic; q95 : out std_logic_vector(dwidth-1 downto 0); addr96 : in std_logic_vector(awidth-1 downto 0); ce96 : in std_logic; q96 : out std_logic_vector(dwidth-1 downto 0); addr97 : in std_logic_vector(awidth-1 downto 0); ce97 : in std_logic; q97 : out std_logic_vector(dwidth-1 downto 0); addr98 : in std_logic_vector(awidth-1 downto 0); ce98 : in std_logic; q98 : out std_logic_vector(dwidth-1 downto 0); addr99 : in std_logic_vector(awidth-1 downto 0); ce99 : in std_logic; q99 : out std_logic_vector(dwidth-1 downto 0); addr100 : in std_logic_vector(awidth-1 downto 0); ce100 : in std_logic; q100 : out std_logic_vector(dwidth-1 downto 0); addr101 : in std_logic_vector(awidth-1 downto 0); ce101 : in std_logic; q101 : out std_logic_vector(dwidth-1 downto 0); addr102 : in std_logic_vector(awidth-1 downto 0); ce102 : in std_logic; q102 : out std_logic_vector(dwidth-1 downto 0); addr103 : in std_logic_vector(awidth-1 downto 0); ce103 : in std_logic; q103 : out std_logic_vector(dwidth-1 downto 0); addr104 : in std_logic_vector(awidth-1 downto 0); ce104 : in std_logic; q104 : out std_logic_vector(dwidth-1 downto 0); addr105 : in std_logic_vector(awidth-1 downto 0); ce105 : in std_logic; q105 : out std_logic_vector(dwidth-1 downto 0); addr106 : in std_logic_vector(awidth-1 downto 0); ce106 : in std_logic; q106 : out std_logic_vector(dwidth-1 downto 0); addr107 : in std_logic_vector(awidth-1 downto 0); ce107 : in std_logic; q107 : out std_logic_vector(dwidth-1 downto 0); addr108 : in std_logic_vector(awidth-1 downto 0); ce108 : in std_logic; q108 : out std_logic_vector(dwidth-1 downto 0); addr109 : in std_logic_vector(awidth-1 downto 0); ce109 : in std_logic; q109 : out std_logic_vector(dwidth-1 downto 0); addr110 : in std_logic_vector(awidth-1 downto 0); ce110 : in std_logic; q110 : out std_logic_vector(dwidth-1 downto 0); addr111 : in std_logic_vector(awidth-1 downto 0); ce111 : in std_logic; q111 : out std_logic_vector(dwidth-1 downto 0); addr112 : in std_logic_vector(awidth-1 downto 0); ce112 : in std_logic; q112 : out std_logic_vector(dwidth-1 downto 0); addr113 : in std_logic_vector(awidth-1 downto 0); ce113 : in std_logic; q113 : out std_logic_vector(dwidth-1 downto 0); addr114 : in std_logic_vector(awidth-1 downto 0); ce114 : in std_logic; q114 : out std_logic_vector(dwidth-1 downto 0); addr115 : in std_logic_vector(awidth-1 downto 0); ce115 : in std_logic; q115 : out std_logic_vector(dwidth-1 downto 0); addr116 : in std_logic_vector(awidth-1 downto 0); ce116 : in std_logic; q116 : out std_logic_vector(dwidth-1 downto 0); addr117 : in std_logic_vector(awidth-1 downto 0); ce117 : in std_logic; q117 : out std_logic_vector(dwidth-1 downto 0); addr118 : in std_logic_vector(awidth-1 downto 0); ce118 : in std_logic; q118 : out std_logic_vector(dwidth-1 downto 0); addr119 : in std_logic_vector(awidth-1 downto 0); ce119 : in std_logic; q119 : out std_logic_vector(dwidth-1 downto 0); addr120 : in std_logic_vector(awidth-1 downto 0); ce120 : in std_logic; q120 : out std_logic_vector(dwidth-1 downto 0); addr121 : in std_logic_vector(awidth-1 downto 0); ce121 : in std_logic; q121 : out std_logic_vector(dwidth-1 downto 0); addr122 : in std_logic_vector(awidth-1 downto 0); ce122 : in std_logic; q122 : out std_logic_vector(dwidth-1 downto 0); addr123 : in std_logic_vector(awidth-1 downto 0); ce123 : in std_logic; q123 : out std_logic_vector(dwidth-1 downto 0); addr124 : in std_logic_vector(awidth-1 downto 0); ce124 : in std_logic; q124 : out std_logic_vector(dwidth-1 downto 0); addr125 : in std_logic_vector(awidth-1 downto 0); ce125 : in std_logic; q125 : out std_logic_vector(dwidth-1 downto 0); addr126 : in std_logic_vector(awidth-1 downto 0); ce126 : in std_logic; q126 : out std_logic_vector(dwidth-1 downto 0); addr127 : in std_logic_vector(awidth-1 downto 0); ce127 : in std_logic; q127 : out std_logic_vector(dwidth-1 downto 0); addr128 : in std_logic_vector(awidth-1 downto 0); ce128 : in std_logic; q128 : out std_logic_vector(dwidth-1 downto 0); addr129 : in std_logic_vector(awidth-1 downto 0); ce129 : in std_logic; q129 : out std_logic_vector(dwidth-1 downto 0); addr130 : in std_logic_vector(awidth-1 downto 0); ce130 : in std_logic; q130 : out std_logic_vector(dwidth-1 downto 0); addr131 : in std_logic_vector(awidth-1 downto 0); ce131 : in std_logic; q131 : out std_logic_vector(dwidth-1 downto 0); addr132 : in std_logic_vector(awidth-1 downto 0); ce132 : in std_logic; q132 : out std_logic_vector(dwidth-1 downto 0); addr133 : in std_logic_vector(awidth-1 downto 0); ce133 : in std_logic; q133 : out std_logic_vector(dwidth-1 downto 0); addr134 : in std_logic_vector(awidth-1 downto 0); ce134 : in std_logic; q134 : out std_logic_vector(dwidth-1 downto 0); addr135 : in std_logic_vector(awidth-1 downto 0); ce135 : in std_logic; q135 : out std_logic_vector(dwidth-1 downto 0); addr136 : in std_logic_vector(awidth-1 downto 0); ce136 : in std_logic; q136 : out std_logic_vector(dwidth-1 downto 0); addr137 : in std_logic_vector(awidth-1 downto 0); ce137 : in std_logic; q137 : out std_logic_vector(dwidth-1 downto 0); addr138 : in std_logic_vector(awidth-1 downto 0); ce138 : in std_logic; q138 : out std_logic_vector(dwidth-1 downto 0); addr139 : in std_logic_vector(awidth-1 downto 0); ce139 : in std_logic; q139 : out std_logic_vector(dwidth-1 downto 0); addr140 : in std_logic_vector(awidth-1 downto 0); ce140 : in std_logic; q140 : out std_logic_vector(dwidth-1 downto 0); addr141 : in std_logic_vector(awidth-1 downto 0); ce141 : in std_logic; q141 : out std_logic_vector(dwidth-1 downto 0); addr142 : in std_logic_vector(awidth-1 downto 0); ce142 : in std_logic; q142 : out std_logic_vector(dwidth-1 downto 0); addr143 : in std_logic_vector(awidth-1 downto 0); ce143 : in std_logic; q143 : out std_logic_vector(dwidth-1 downto 0); addr144 : in std_logic_vector(awidth-1 downto 0); ce144 : in std_logic; q144 : out std_logic_vector(dwidth-1 downto 0); addr145 : in std_logic_vector(awidth-1 downto 0); ce145 : in std_logic; q145 : out std_logic_vector(dwidth-1 downto 0); addr146 : in std_logic_vector(awidth-1 downto 0); ce146 : in std_logic; q146 : out std_logic_vector(dwidth-1 downto 0); addr147 : in std_logic_vector(awidth-1 downto 0); ce147 : in std_logic; q147 : out std_logic_vector(dwidth-1 downto 0); addr148 : in std_logic_vector(awidth-1 downto 0); ce148 : in std_logic; q148 : out std_logic_vector(dwidth-1 downto 0); addr149 : in std_logic_vector(awidth-1 downto 0); ce149 : in std_logic; q149 : out std_logic_vector(dwidth-1 downto 0); addr150 : in std_logic_vector(awidth-1 downto 0); ce150 : in std_logic; q150 : out std_logic_vector(dwidth-1 downto 0); addr151 : in std_logic_vector(awidth-1 downto 0); ce151 : in std_logic; q151 : out std_logic_vector(dwidth-1 downto 0); addr152 : in std_logic_vector(awidth-1 downto 0); ce152 : in std_logic; q152 : out std_logic_vector(dwidth-1 downto 0); addr153 : in std_logic_vector(awidth-1 downto 0); ce153 : in std_logic; q153 : out std_logic_vector(dwidth-1 downto 0); addr154 : in std_logic_vector(awidth-1 downto 0); ce154 : in std_logic; q154 : out std_logic_vector(dwidth-1 downto 0); addr155 : in std_logic_vector(awidth-1 downto 0); ce155 : in std_logic; q155 : out std_logic_vector(dwidth-1 downto 0); addr156 : in std_logic_vector(awidth-1 downto 0); ce156 : in std_logic; q156 : out std_logic_vector(dwidth-1 downto 0); addr157 : in std_logic_vector(awidth-1 downto 0); ce157 : in std_logic; q157 : out std_logic_vector(dwidth-1 downto 0); addr158 : in std_logic_vector(awidth-1 downto 0); ce158 : in std_logic; q158 : out std_logic_vector(dwidth-1 downto 0); addr159 : in std_logic_vector(awidth-1 downto 0); ce159 : in std_logic; q159 : out std_logic_vector(dwidth-1 downto 0); addr160 : in std_logic_vector(awidth-1 downto 0); ce160 : in std_logic; q160 : out std_logic_vector(dwidth-1 downto 0); addr161 : in std_logic_vector(awidth-1 downto 0); ce161 : in std_logic; q161 : out std_logic_vector(dwidth-1 downto 0); addr162 : in std_logic_vector(awidth-1 downto 0); ce162 : in std_logic; q162 : out std_logic_vector(dwidth-1 downto 0); addr163 : in std_logic_vector(awidth-1 downto 0); ce163 : in std_logic; q163 : out std_logic_vector(dwidth-1 downto 0); addr164 : in std_logic_vector(awidth-1 downto 0); ce164 : in std_logic; q164 : out std_logic_vector(dwidth-1 downto 0); addr165 : in std_logic_vector(awidth-1 downto 0); ce165 : in std_logic; q165 : out std_logic_vector(dwidth-1 downto 0); addr166 : in std_logic_vector(awidth-1 downto 0); ce166 : in std_logic; q166 : out std_logic_vector(dwidth-1 downto 0); addr167 : in std_logic_vector(awidth-1 downto 0); ce167 : in std_logic; q167 : out std_logic_vector(dwidth-1 downto 0); addr168 : in std_logic_vector(awidth-1 downto 0); ce168 : in std_logic; q168 : out std_logic_vector(dwidth-1 downto 0); addr169 : in std_logic_vector(awidth-1 downto 0); ce169 : in std_logic; q169 : out std_logic_vector(dwidth-1 downto 0); addr170 : in std_logic_vector(awidth-1 downto 0); ce170 : in std_logic; q170 : out std_logic_vector(dwidth-1 downto 0); addr171 : in std_logic_vector(awidth-1 downto 0); ce171 : in std_logic; q171 : out std_logic_vector(dwidth-1 downto 0); addr172 : in std_logic_vector(awidth-1 downto 0); ce172 : in std_logic; q172 : out std_logic_vector(dwidth-1 downto 0); addr173 : in std_logic_vector(awidth-1 downto 0); ce173 : in std_logic; q173 : out std_logic_vector(dwidth-1 downto 0); addr174 : in std_logic_vector(awidth-1 downto 0); ce174 : in std_logic; q174 : out std_logic_vector(dwidth-1 downto 0); addr175 : in std_logic_vector(awidth-1 downto 0); ce175 : in std_logic; q175 : out std_logic_vector(dwidth-1 downto 0); addr176 : in std_logic_vector(awidth-1 downto 0); ce176 : in std_logic; q176 : out std_logic_vector(dwidth-1 downto 0); addr177 : in std_logic_vector(awidth-1 downto 0); ce177 : in std_logic; q177 : out std_logic_vector(dwidth-1 downto 0); addr178 : in std_logic_vector(awidth-1 downto 0); ce178 : in std_logic; q178 : out std_logic_vector(dwidth-1 downto 0); addr179 : in std_logic_vector(awidth-1 downto 0); ce179 : in std_logic; q179 : out std_logic_vector(dwidth-1 downto 0); addr180 : in std_logic_vector(awidth-1 downto 0); ce180 : in std_logic; q180 : out std_logic_vector(dwidth-1 downto 0); addr181 : in std_logic_vector(awidth-1 downto 0); ce181 : in std_logic; q181 : out std_logic_vector(dwidth-1 downto 0); addr182 : in std_logic_vector(awidth-1 downto 0); ce182 : in std_logic; q182 : out std_logic_vector(dwidth-1 downto 0); addr183 : in std_logic_vector(awidth-1 downto 0); ce183 : in std_logic; q183 : out std_logic_vector(dwidth-1 downto 0); addr184 : in std_logic_vector(awidth-1 downto 0); ce184 : in std_logic; q184 : out std_logic_vector(dwidth-1 downto 0); addr185 : in std_logic_vector(awidth-1 downto 0); ce185 : in std_logic; q185 : out std_logic_vector(dwidth-1 downto 0); addr186 : in std_logic_vector(awidth-1 downto 0); ce186 : in std_logic; q186 : out std_logic_vector(dwidth-1 downto 0); addr187 : in std_logic_vector(awidth-1 downto 0); ce187 : in std_logic; q187 : out std_logic_vector(dwidth-1 downto 0); addr188 : in std_logic_vector(awidth-1 downto 0); ce188 : in std_logic; q188 : out std_logic_vector(dwidth-1 downto 0); addr189 : in std_logic_vector(awidth-1 downto 0); ce189 : in std_logic; q189 : out std_logic_vector(dwidth-1 downto 0); addr190 : in std_logic_vector(awidth-1 downto 0); ce190 : in std_logic; q190 : out std_logic_vector(dwidth-1 downto 0); addr191 : in std_logic_vector(awidth-1 downto 0); ce191 : in std_logic; q191 : out std_logic_vector(dwidth-1 downto 0); addr192 : in std_logic_vector(awidth-1 downto 0); ce192 : in std_logic; q192 : out std_logic_vector(dwidth-1 downto 0); addr193 : in std_logic_vector(awidth-1 downto 0); ce193 : in std_logic; q193 : out std_logic_vector(dwidth-1 downto 0); addr194 : in std_logic_vector(awidth-1 downto 0); ce194 : in std_logic; q194 : out std_logic_vector(dwidth-1 downto 0); addr195 : in std_logic_vector(awidth-1 downto 0); ce195 : in std_logic; q195 : out std_logic_vector(dwidth-1 downto 0); addr196 : in std_logic_vector(awidth-1 downto 0); ce196 : in std_logic; q196 : out std_logic_vector(dwidth-1 downto 0); addr197 : in std_logic_vector(awidth-1 downto 0); ce197 : in std_logic; q197 : out std_logic_vector(dwidth-1 downto 0); addr198 : in std_logic_vector(awidth-1 downto 0); ce198 : in std_logic; q198 : out std_logic_vector(dwidth-1 downto 0); addr199 : in std_logic_vector(awidth-1 downto 0); ce199 : in std_logic; q199 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of aestest_sboxes_rom is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); signal addr2_tmp : std_logic_vector(awidth-1 downto 0); signal addr3_tmp : std_logic_vector(awidth-1 downto 0); signal addr4_tmp : std_logic_vector(awidth-1 downto 0); signal addr5_tmp : std_logic_vector(awidth-1 downto 0); signal addr6_tmp : std_logic_vector(awidth-1 downto 0); signal addr7_tmp : std_logic_vector(awidth-1 downto 0); signal addr8_tmp : std_logic_vector(awidth-1 downto 0); signal addr9_tmp : std_logic_vector(awidth-1 downto 0); signal addr10_tmp : std_logic_vector(awidth-1 downto 0); signal addr11_tmp : std_logic_vector(awidth-1 downto 0); signal addr12_tmp : std_logic_vector(awidth-1 downto 0); signal addr13_tmp : std_logic_vector(awidth-1 downto 0); signal addr14_tmp : std_logic_vector(awidth-1 downto 0); signal addr15_tmp : std_logic_vector(awidth-1 downto 0); signal addr16_tmp : std_logic_vector(awidth-1 downto 0); signal addr17_tmp : std_logic_vector(awidth-1 downto 0); signal addr18_tmp : std_logic_vector(awidth-1 downto 0); signal addr19_tmp : std_logic_vector(awidth-1 downto 0); signal addr20_tmp : std_logic_vector(awidth-1 downto 0); signal addr21_tmp : std_logic_vector(awidth-1 downto 0); signal addr22_tmp : std_logic_vector(awidth-1 downto 0); signal addr23_tmp : std_logic_vector(awidth-1 downto 0); signal addr24_tmp : std_logic_vector(awidth-1 downto 0); signal addr25_tmp : std_logic_vector(awidth-1 downto 0); signal addr26_tmp : std_logic_vector(awidth-1 downto 0); signal addr27_tmp : std_logic_vector(awidth-1 downto 0); signal addr28_tmp : std_logic_vector(awidth-1 downto 0); signal addr29_tmp : std_logic_vector(awidth-1 downto 0); signal addr30_tmp : std_logic_vector(awidth-1 downto 0); signal addr31_tmp : std_logic_vector(awidth-1 downto 0); signal addr32_tmp : std_logic_vector(awidth-1 downto 0); signal addr33_tmp : std_logic_vector(awidth-1 downto 0); signal addr34_tmp : std_logic_vector(awidth-1 downto 0); signal addr35_tmp : std_logic_vector(awidth-1 downto 0); signal addr36_tmp : std_logic_vector(awidth-1 downto 0); signal addr37_tmp : std_logic_vector(awidth-1 downto 0); signal addr38_tmp : std_logic_vector(awidth-1 downto 0); signal addr39_tmp : std_logic_vector(awidth-1 downto 0); signal addr40_tmp : std_logic_vector(awidth-1 downto 0); signal addr41_tmp : std_logic_vector(awidth-1 downto 0); signal addr42_tmp : std_logic_vector(awidth-1 downto 0); signal addr43_tmp : std_logic_vector(awidth-1 downto 0); signal addr44_tmp : std_logic_vector(awidth-1 downto 0); signal addr45_tmp : std_logic_vector(awidth-1 downto 0); signal addr46_tmp : std_logic_vector(awidth-1 downto 0); signal addr47_tmp : std_logic_vector(awidth-1 downto 0); signal addr48_tmp : std_logic_vector(awidth-1 downto 0); signal addr49_tmp : std_logic_vector(awidth-1 downto 0); signal addr50_tmp : std_logic_vector(awidth-1 downto 0); signal addr51_tmp : std_logic_vector(awidth-1 downto 0); signal addr52_tmp : std_logic_vector(awidth-1 downto 0); signal addr53_tmp : std_logic_vector(awidth-1 downto 0); signal addr54_tmp : std_logic_vector(awidth-1 downto 0); signal addr55_tmp : std_logic_vector(awidth-1 downto 0); signal addr56_tmp : std_logic_vector(awidth-1 downto 0); signal addr57_tmp : std_logic_vector(awidth-1 downto 0); signal addr58_tmp : std_logic_vector(awidth-1 downto 0); signal addr59_tmp : std_logic_vector(awidth-1 downto 0); signal addr60_tmp : std_logic_vector(awidth-1 downto 0); signal addr61_tmp : std_logic_vector(awidth-1 downto 0); signal addr62_tmp : std_logic_vector(awidth-1 downto 0); signal addr63_tmp : std_logic_vector(awidth-1 downto 0); signal addr64_tmp : std_logic_vector(awidth-1 downto 0); signal addr65_tmp : std_logic_vector(awidth-1 downto 0); signal addr66_tmp : std_logic_vector(awidth-1 downto 0); signal addr67_tmp : std_logic_vector(awidth-1 downto 0); signal addr68_tmp : std_logic_vector(awidth-1 downto 0); signal addr69_tmp : std_logic_vector(awidth-1 downto 0); signal addr70_tmp : std_logic_vector(awidth-1 downto 0); signal addr71_tmp : std_logic_vector(awidth-1 downto 0); signal addr72_tmp : std_logic_vector(awidth-1 downto 0); signal addr73_tmp : std_logic_vector(awidth-1 downto 0); signal addr74_tmp : std_logic_vector(awidth-1 downto 0); signal addr75_tmp : std_logic_vector(awidth-1 downto 0); signal addr76_tmp : std_logic_vector(awidth-1 downto 0); signal addr77_tmp : std_logic_vector(awidth-1 downto 0); signal addr78_tmp : std_logic_vector(awidth-1 downto 0); signal addr79_tmp : std_logic_vector(awidth-1 downto 0); signal addr80_tmp : std_logic_vector(awidth-1 downto 0); signal addr81_tmp : std_logic_vector(awidth-1 downto 0); signal addr82_tmp : std_logic_vector(awidth-1 downto 0); signal addr83_tmp : std_logic_vector(awidth-1 downto 0); signal addr84_tmp : std_logic_vector(awidth-1 downto 0); signal addr85_tmp : std_logic_vector(awidth-1 downto 0); signal addr86_tmp : std_logic_vector(awidth-1 downto 0); signal addr87_tmp : std_logic_vector(awidth-1 downto 0); signal addr88_tmp : std_logic_vector(awidth-1 downto 0); signal addr89_tmp : std_logic_vector(awidth-1 downto 0); signal addr90_tmp : std_logic_vector(awidth-1 downto 0); signal addr91_tmp : std_logic_vector(awidth-1 downto 0); signal addr92_tmp : std_logic_vector(awidth-1 downto 0); signal addr93_tmp : std_logic_vector(awidth-1 downto 0); signal addr94_tmp : std_logic_vector(awidth-1 downto 0); signal addr95_tmp : std_logic_vector(awidth-1 downto 0); signal addr96_tmp : std_logic_vector(awidth-1 downto 0); signal addr97_tmp : std_logic_vector(awidth-1 downto 0); signal addr98_tmp : std_logic_vector(awidth-1 downto 0); signal addr99_tmp : std_logic_vector(awidth-1 downto 0); signal addr100_tmp : std_logic_vector(awidth-1 downto 0); signal addr101_tmp : std_logic_vector(awidth-1 downto 0); signal addr102_tmp : std_logic_vector(awidth-1 downto 0); signal addr103_tmp : std_logic_vector(awidth-1 downto 0); signal addr104_tmp : std_logic_vector(awidth-1 downto 0); signal addr105_tmp : std_logic_vector(awidth-1 downto 0); signal addr106_tmp : std_logic_vector(awidth-1 downto 0); signal addr107_tmp : std_logic_vector(awidth-1 downto 0); signal addr108_tmp : std_logic_vector(awidth-1 downto 0); signal addr109_tmp : std_logic_vector(awidth-1 downto 0); signal addr110_tmp : std_logic_vector(awidth-1 downto 0); signal addr111_tmp : std_logic_vector(awidth-1 downto 0); signal addr112_tmp : std_logic_vector(awidth-1 downto 0); signal addr113_tmp : std_logic_vector(awidth-1 downto 0); signal addr114_tmp : std_logic_vector(awidth-1 downto 0); signal addr115_tmp : std_logic_vector(awidth-1 downto 0); signal addr116_tmp : std_logic_vector(awidth-1 downto 0); signal addr117_tmp : std_logic_vector(awidth-1 downto 0); signal addr118_tmp : std_logic_vector(awidth-1 downto 0); signal addr119_tmp : std_logic_vector(awidth-1 downto 0); signal addr120_tmp : std_logic_vector(awidth-1 downto 0); signal addr121_tmp : std_logic_vector(awidth-1 downto 0); signal addr122_tmp : std_logic_vector(awidth-1 downto 0); signal addr123_tmp : std_logic_vector(awidth-1 downto 0); signal addr124_tmp : std_logic_vector(awidth-1 downto 0); signal addr125_tmp : std_logic_vector(awidth-1 downto 0); signal addr126_tmp : std_logic_vector(awidth-1 downto 0); signal addr127_tmp : std_logic_vector(awidth-1 downto 0); signal addr128_tmp : std_logic_vector(awidth-1 downto 0); signal addr129_tmp : std_logic_vector(awidth-1 downto 0); signal addr130_tmp : std_logic_vector(awidth-1 downto 0); signal addr131_tmp : std_logic_vector(awidth-1 downto 0); signal addr132_tmp : std_logic_vector(awidth-1 downto 0); signal addr133_tmp : std_logic_vector(awidth-1 downto 0); signal addr134_tmp : std_logic_vector(awidth-1 downto 0); signal addr135_tmp : std_logic_vector(awidth-1 downto 0); signal addr136_tmp : std_logic_vector(awidth-1 downto 0); signal addr137_tmp : std_logic_vector(awidth-1 downto 0); signal addr138_tmp : std_logic_vector(awidth-1 downto 0); signal addr139_tmp : std_logic_vector(awidth-1 downto 0); signal addr140_tmp : std_logic_vector(awidth-1 downto 0); signal addr141_tmp : std_logic_vector(awidth-1 downto 0); signal addr142_tmp : std_logic_vector(awidth-1 downto 0); signal addr143_tmp : std_logic_vector(awidth-1 downto 0); signal addr144_tmp : std_logic_vector(awidth-1 downto 0); signal addr145_tmp : std_logic_vector(awidth-1 downto 0); signal addr146_tmp : std_logic_vector(awidth-1 downto 0); signal addr147_tmp : std_logic_vector(awidth-1 downto 0); signal addr148_tmp : std_logic_vector(awidth-1 downto 0); signal addr149_tmp : std_logic_vector(awidth-1 downto 0); signal addr150_tmp : std_logic_vector(awidth-1 downto 0); signal addr151_tmp : std_logic_vector(awidth-1 downto 0); signal addr152_tmp : std_logic_vector(awidth-1 downto 0); signal addr153_tmp : std_logic_vector(awidth-1 downto 0); signal addr154_tmp : std_logic_vector(awidth-1 downto 0); signal addr155_tmp : std_logic_vector(awidth-1 downto 0); signal addr156_tmp : std_logic_vector(awidth-1 downto 0); signal addr157_tmp : std_logic_vector(awidth-1 downto 0); signal addr158_tmp : std_logic_vector(awidth-1 downto 0); signal addr159_tmp : std_logic_vector(awidth-1 downto 0); signal addr160_tmp : std_logic_vector(awidth-1 downto 0); signal addr161_tmp : std_logic_vector(awidth-1 downto 0); signal addr162_tmp : std_logic_vector(awidth-1 downto 0); signal addr163_tmp : std_logic_vector(awidth-1 downto 0); signal addr164_tmp : std_logic_vector(awidth-1 downto 0); signal addr165_tmp : std_logic_vector(awidth-1 downto 0); signal addr166_tmp : std_logic_vector(awidth-1 downto 0); signal addr167_tmp : std_logic_vector(awidth-1 downto 0); signal addr168_tmp : std_logic_vector(awidth-1 downto 0); signal addr169_tmp : std_logic_vector(awidth-1 downto 0); signal addr170_tmp : std_logic_vector(awidth-1 downto 0); signal addr171_tmp : std_logic_vector(awidth-1 downto 0); signal addr172_tmp : std_logic_vector(awidth-1 downto 0); signal addr173_tmp : std_logic_vector(awidth-1 downto 0); signal addr174_tmp : std_logic_vector(awidth-1 downto 0); signal addr175_tmp : std_logic_vector(awidth-1 downto 0); signal addr176_tmp : std_logic_vector(awidth-1 downto 0); signal addr177_tmp : std_logic_vector(awidth-1 downto 0); signal addr178_tmp : std_logic_vector(awidth-1 downto 0); signal addr179_tmp : std_logic_vector(awidth-1 downto 0); signal addr180_tmp : std_logic_vector(awidth-1 downto 0); signal addr181_tmp : std_logic_vector(awidth-1 downto 0); signal addr182_tmp : std_logic_vector(awidth-1 downto 0); signal addr183_tmp : std_logic_vector(awidth-1 downto 0); signal addr184_tmp : std_logic_vector(awidth-1 downto 0); signal addr185_tmp : std_logic_vector(awidth-1 downto 0); signal addr186_tmp : std_logic_vector(awidth-1 downto 0); signal addr187_tmp : std_logic_vector(awidth-1 downto 0); signal addr188_tmp : std_logic_vector(awidth-1 downto 0); signal addr189_tmp : std_logic_vector(awidth-1 downto 0); signal addr190_tmp : std_logic_vector(awidth-1 downto 0); signal addr191_tmp : std_logic_vector(awidth-1 downto 0); signal addr192_tmp : std_logic_vector(awidth-1 downto 0); signal addr193_tmp : std_logic_vector(awidth-1 downto 0); signal addr194_tmp : std_logic_vector(awidth-1 downto 0); signal addr195_tmp : std_logic_vector(awidth-1 downto 0); signal addr196_tmp : std_logic_vector(awidth-1 downto 0); signal addr197_tmp : std_logic_vector(awidth-1 downto 0); signal addr198_tmp : std_logic_vector(awidth-1 downto 0); signal addr199_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); signal mem0 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem1 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem2 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem3 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem4 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem5 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem6 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem7 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem8 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem9 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem10 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem11 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem12 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem13 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem14 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem15 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem16 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem17 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem18 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem19 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem20 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem21 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem22 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem23 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem24 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem25 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem26 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem27 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem28 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem29 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem30 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem31 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem32 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem33 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem34 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem35 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem36 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem37 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem38 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem39 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem40 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem41 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem42 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem43 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem44 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem45 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem46 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem47 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem48 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem49 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem50 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem51 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem52 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem53 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem54 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem55 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem56 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem57 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem58 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem59 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem60 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem61 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem62 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem63 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem64 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem65 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem66 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem67 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem68 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem69 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem70 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem71 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem72 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem73 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem74 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem75 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem76 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem77 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem78 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem79 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem80 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem81 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem82 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem83 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem84 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem85 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem86 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem87 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem88 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem89 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem90 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem91 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem92 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem93 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem94 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem95 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem96 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem97 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem98 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem99 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); attribute syn_rom_style : string; attribute syn_rom_style of mem0 : signal is "block_rom"; attribute syn_rom_style of mem1 : signal is "block_rom"; attribute syn_rom_style of mem2 : signal is "block_rom"; attribute syn_rom_style of mem3 : signal is "block_rom"; attribute syn_rom_style of mem4 : signal is "block_rom"; attribute syn_rom_style of mem5 : signal is "block_rom"; attribute syn_rom_style of mem6 : signal is "block_rom"; attribute syn_rom_style of mem7 : signal is "block_rom"; attribute syn_rom_style of mem8 : signal is "block_rom"; attribute syn_rom_style of mem9 : signal is "block_rom"; attribute syn_rom_style of mem10 : signal is "block_rom"; attribute syn_rom_style of mem11 : signal is "block_rom"; attribute syn_rom_style of mem12 : signal is "block_rom"; attribute syn_rom_style of mem13 : signal is "block_rom"; attribute syn_rom_style of mem14 : signal is "block_rom"; attribute syn_rom_style of mem15 : signal is "block_rom"; attribute syn_rom_style of mem16 : signal is "block_rom"; attribute syn_rom_style of mem17 : signal is "block_rom"; attribute syn_rom_style of mem18 : signal is "block_rom"; attribute syn_rom_style of mem19 : signal is "block_rom"; attribute syn_rom_style of mem20 : signal is "block_rom"; attribute syn_rom_style of mem21 : signal is "block_rom"; attribute syn_rom_style of mem22 : signal is "block_rom"; attribute syn_rom_style of mem23 : signal is "block_rom"; attribute syn_rom_style of mem24 : signal is "block_rom"; attribute syn_rom_style of mem25 : signal is "block_rom"; attribute syn_rom_style of mem26 : signal is "block_rom"; attribute syn_rom_style of mem27 : signal is "block_rom"; attribute syn_rom_style of mem28 : signal is "block_rom"; attribute syn_rom_style of mem29 : signal is "block_rom"; attribute syn_rom_style of mem30 : signal is "block_rom"; attribute syn_rom_style of mem31 : signal is "block_rom"; attribute syn_rom_style of mem32 : signal is "block_rom"; attribute syn_rom_style of mem33 : signal is "block_rom"; attribute syn_rom_style of mem34 : signal is "block_rom"; attribute syn_rom_style of mem35 : signal is "block_rom"; attribute syn_rom_style of mem36 : signal is "block_rom"; attribute syn_rom_style of mem37 : signal is "block_rom"; attribute syn_rom_style of mem38 : signal is "block_rom"; attribute syn_rom_style of mem39 : signal is "block_rom"; attribute syn_rom_style of mem40 : signal is "block_rom"; attribute syn_rom_style of mem41 : signal is "block_rom"; attribute syn_rom_style of mem42 : signal is "block_rom"; attribute syn_rom_style of mem43 : signal is "block_rom"; attribute syn_rom_style of mem44 : signal is "block_rom"; attribute syn_rom_style of mem45 : signal is "block_rom"; attribute syn_rom_style of mem46 : signal is "block_rom"; attribute syn_rom_style of mem47 : signal is "block_rom"; attribute syn_rom_style of mem48 : signal is "block_rom"; attribute syn_rom_style of mem49 : signal is "block_rom"; attribute syn_rom_style of mem50 : signal is "block_rom"; attribute syn_rom_style of mem51 : signal is "block_rom"; attribute syn_rom_style of mem52 : signal is "block_rom"; attribute syn_rom_style of mem53 : signal is "block_rom"; attribute syn_rom_style of mem54 : signal is "block_rom"; attribute syn_rom_style of mem55 : signal is "block_rom"; attribute syn_rom_style of mem56 : signal is "block_rom"; attribute syn_rom_style of mem57 : signal is "block_rom"; attribute syn_rom_style of mem58 : signal is "block_rom"; attribute syn_rom_style of mem59 : signal is "block_rom"; attribute syn_rom_style of mem60 : signal is "block_rom"; attribute syn_rom_style of mem61 : signal is "block_rom"; attribute syn_rom_style of mem62 : signal is "block_rom"; attribute syn_rom_style of mem63 : signal is "block_rom"; attribute syn_rom_style of mem64 : signal is "block_rom"; attribute syn_rom_style of mem65 : signal is "block_rom"; attribute syn_rom_style of mem66 : signal is "block_rom"; attribute syn_rom_style of mem67 : signal is "block_rom"; attribute syn_rom_style of mem68 : signal is "block_rom"; attribute syn_rom_style of mem69 : signal is "block_rom"; attribute syn_rom_style of mem70 : signal is "block_rom"; attribute syn_rom_style of mem71 : signal is "block_rom"; attribute syn_rom_style of mem72 : signal is "block_rom"; attribute syn_rom_style of mem73 : signal is "block_rom"; attribute syn_rom_style of mem74 : signal is "block_rom"; attribute syn_rom_style of mem75 : signal is "block_rom"; attribute syn_rom_style of mem76 : signal is "block_rom"; attribute syn_rom_style of mem77 : signal is "block_rom"; attribute syn_rom_style of mem78 : signal is "block_rom"; attribute syn_rom_style of mem79 : signal is "block_rom"; attribute syn_rom_style of mem80 : signal is "block_rom"; attribute syn_rom_style of mem81 : signal is "block_rom"; attribute syn_rom_style of mem82 : signal is "block_rom"; attribute syn_rom_style of mem83 : signal is "block_rom"; attribute syn_rom_style of mem84 : signal is "block_rom"; attribute syn_rom_style of mem85 : signal is "block_rom"; attribute syn_rom_style of mem86 : signal is "block_rom"; attribute syn_rom_style of mem87 : signal is "block_rom"; attribute syn_rom_style of mem88 : signal is "block_rom"; attribute syn_rom_style of mem89 : signal is "block_rom"; attribute syn_rom_style of mem90 : signal is "block_rom"; attribute syn_rom_style of mem91 : signal is "block_rom"; attribute syn_rom_style of mem92 : signal is "block_rom"; attribute syn_rom_style of mem93 : signal is "block_rom"; attribute syn_rom_style of mem94 : signal is "block_rom"; attribute syn_rom_style of mem95 : signal is "block_rom"; attribute syn_rom_style of mem96 : signal is "block_rom"; attribute syn_rom_style of mem97 : signal is "block_rom"; attribute syn_rom_style of mem98 : signal is "block_rom"; attribute syn_rom_style of mem99 : signal is "block_rom"; attribute ROM_STYLE : string; attribute ROM_STYLE of mem0 : signal is "block"; attribute ROM_STYLE of mem1 : signal is "block"; attribute ROM_STYLE of mem2 : signal is "block"; attribute ROM_STYLE of mem3 : signal is "block"; attribute ROM_STYLE of mem4 : signal is "block"; attribute ROM_STYLE of mem5 : signal is "block"; attribute ROM_STYLE of mem6 : signal is "block"; attribute ROM_STYLE of mem7 : signal is "block"; attribute ROM_STYLE of mem8 : signal is "block"; attribute ROM_STYLE of mem9 : signal is "block"; attribute ROM_STYLE of mem10 : signal is "block"; attribute ROM_STYLE of mem11 : signal is "block"; attribute ROM_STYLE of mem12 : signal is "block"; attribute ROM_STYLE of mem13 : signal is "block"; attribute ROM_STYLE of mem14 : signal is "block"; attribute ROM_STYLE of mem15 : signal is "block"; attribute ROM_STYLE of mem16 : signal is "block"; attribute ROM_STYLE of mem17 : signal is "block"; attribute ROM_STYLE of mem18 : signal is "block"; attribute ROM_STYLE of mem19 : signal is "block"; attribute ROM_STYLE of mem20 : signal is "block"; attribute ROM_STYLE of mem21 : signal is "block"; attribute ROM_STYLE of mem22 : signal is "block"; attribute ROM_STYLE of mem23 : signal is "block"; attribute ROM_STYLE of mem24 : signal is "block"; attribute ROM_STYLE of mem25 : signal is "block"; attribute ROM_STYLE of mem26 : signal is "block"; attribute ROM_STYLE of mem27 : signal is "block"; attribute ROM_STYLE of mem28 : signal is "block"; attribute ROM_STYLE of mem29 : signal is "block"; attribute ROM_STYLE of mem30 : signal is "block"; attribute ROM_STYLE of mem31 : signal is "block"; attribute ROM_STYLE of mem32 : signal is "block"; attribute ROM_STYLE of mem33 : signal is "block"; attribute ROM_STYLE of mem34 : signal is "block"; attribute ROM_STYLE of mem35 : signal is "block"; attribute ROM_STYLE of mem36 : signal is "block"; attribute ROM_STYLE of mem37 : signal is "block"; attribute ROM_STYLE of mem38 : signal is "block"; attribute ROM_STYLE of mem39 : signal is "block"; attribute ROM_STYLE of mem40 : signal is "block"; attribute ROM_STYLE of mem41 : signal is "block"; attribute ROM_STYLE of mem42 : signal is "block"; attribute ROM_STYLE of mem43 : signal is "block"; attribute ROM_STYLE of mem44 : signal is "block"; attribute ROM_STYLE of mem45 : signal is "block"; attribute ROM_STYLE of mem46 : signal is "block"; attribute ROM_STYLE of mem47 : signal is "block"; attribute ROM_STYLE of mem48 : signal is "block"; attribute ROM_STYLE of mem49 : signal is "block"; attribute ROM_STYLE of mem50 : signal is "block"; attribute ROM_STYLE of mem51 : signal is "block"; attribute ROM_STYLE of mem52 : signal is "block"; attribute ROM_STYLE of mem53 : signal is "block"; attribute ROM_STYLE of mem54 : signal is "block"; attribute ROM_STYLE of mem55 : signal is "block"; attribute ROM_STYLE of mem56 : signal is "block"; attribute ROM_STYLE of mem57 : signal is "block"; attribute ROM_STYLE of mem58 : signal is "block"; attribute ROM_STYLE of mem59 : signal is "block"; attribute ROM_STYLE of mem60 : signal is "block"; attribute ROM_STYLE of mem61 : signal is "block"; attribute ROM_STYLE of mem62 : signal is "block"; attribute ROM_STYLE of mem63 : signal is "block"; attribute ROM_STYLE of mem64 : signal is "block"; attribute ROM_STYLE of mem65 : signal is "block"; attribute ROM_STYLE of mem66 : signal is "block"; attribute ROM_STYLE of mem67 : signal is "block"; attribute ROM_STYLE of mem68 : signal is "block"; attribute ROM_STYLE of mem69 : signal is "block"; attribute ROM_STYLE of mem70 : signal is "block"; attribute ROM_STYLE of mem71 : signal is "block"; attribute ROM_STYLE of mem72 : signal is "block"; attribute ROM_STYLE of mem73 : signal is "block"; attribute ROM_STYLE of mem74 : signal is "block"; attribute ROM_STYLE of mem75 : signal is "block"; attribute ROM_STYLE of mem76 : signal is "block"; attribute ROM_STYLE of mem77 : signal is "block"; attribute ROM_STYLE of mem78 : signal is "block"; attribute ROM_STYLE of mem79 : signal is "block"; attribute ROM_STYLE of mem80 : signal is "block"; attribute ROM_STYLE of mem81 : signal is "block"; attribute ROM_STYLE of mem82 : signal is "block"; attribute ROM_STYLE of mem83 : signal is "block"; attribute ROM_STYLE of mem84 : signal is "block"; attribute ROM_STYLE of mem85 : signal is "block"; attribute ROM_STYLE of mem86 : signal is "block"; attribute ROM_STYLE of mem87 : signal is "block"; attribute ROM_STYLE of mem88 : signal is "block"; attribute ROM_STYLE of mem89 : signal is "block"; attribute ROM_STYLE of mem90 : signal is "block"; attribute ROM_STYLE of mem91 : signal is "block"; attribute ROM_STYLE of mem92 : signal is "block"; attribute ROM_STYLE of mem93 : signal is "block"; attribute ROM_STYLE of mem94 : signal is "block"; attribute ROM_STYLE of mem95 : signal is "block"; attribute ROM_STYLE of mem96 : signal is "block"; attribute ROM_STYLE of mem97 : signal is "block"; attribute ROM_STYLE of mem98 : signal is "block"; attribute ROM_STYLE of mem99 : signal is "block"; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; memory_access_guard_2: process (addr2) begin addr2_tmp <= addr2; --synthesis translate_off if (CONV_INTEGER(addr2) > mem_size-1) then addr2_tmp <= (others => '0'); else addr2_tmp <= addr2; end if; --synthesis translate_on end process; memory_access_guard_3: process (addr3) begin addr3_tmp <= addr3; --synthesis translate_off if (CONV_INTEGER(addr3) > mem_size-1) then addr3_tmp <= (others => '0'); else addr3_tmp <= addr3; end if; --synthesis translate_on end process; memory_access_guard_4: process (addr4) begin addr4_tmp <= addr4; --synthesis translate_off if (CONV_INTEGER(addr4) > mem_size-1) then addr4_tmp <= (others => '0'); else addr4_tmp <= addr4; end if; --synthesis translate_on end process; memory_access_guard_5: process (addr5) begin addr5_tmp <= addr5; --synthesis translate_off if (CONV_INTEGER(addr5) > mem_size-1) then addr5_tmp <= (others => '0'); else addr5_tmp <= addr5; end if; --synthesis translate_on end process; memory_access_guard_6: process (addr6) begin addr6_tmp <= addr6; --synthesis translate_off if (CONV_INTEGER(addr6) > mem_size-1) then addr6_tmp <= (others => '0'); else addr6_tmp <= addr6; end if; --synthesis translate_on end process; memory_access_guard_7: process (addr7) begin addr7_tmp <= addr7; --synthesis translate_off if (CONV_INTEGER(addr7) > mem_size-1) then addr7_tmp <= (others => '0'); else addr7_tmp <= addr7; end if; --synthesis translate_on end process; memory_access_guard_8: process (addr8) begin addr8_tmp <= addr8; --synthesis translate_off if (CONV_INTEGER(addr8) > mem_size-1) then addr8_tmp <= (others => '0'); else addr8_tmp <= addr8; end if; --synthesis translate_on end process; memory_access_guard_9: process (addr9) begin addr9_tmp <= addr9; --synthesis translate_off if (CONV_INTEGER(addr9) > mem_size-1) then addr9_tmp <= (others => '0'); else addr9_tmp <= addr9; end if; --synthesis translate_on end process; memory_access_guard_10: process (addr10) begin addr10_tmp <= addr10; --synthesis translate_off if (CONV_INTEGER(addr10) > mem_size-1) then addr10_tmp <= (others => '0'); else addr10_tmp <= addr10; end if; --synthesis translate_on end process; memory_access_guard_11: process (addr11) begin addr11_tmp <= addr11; --synthesis translate_off if (CONV_INTEGER(addr11) > mem_size-1) then addr11_tmp <= (others => '0'); else addr11_tmp <= addr11; end if; --synthesis translate_on end process; memory_access_guard_12: process (addr12) begin addr12_tmp <= addr12; --synthesis translate_off if (CONV_INTEGER(addr12) > mem_size-1) then addr12_tmp <= (others => '0'); else addr12_tmp <= addr12; end if; --synthesis translate_on end process; memory_access_guard_13: process (addr13) begin addr13_tmp <= addr13; --synthesis translate_off if (CONV_INTEGER(addr13) > mem_size-1) then addr13_tmp <= (others => '0'); else addr13_tmp <= addr13; end if; --synthesis translate_on end process; memory_access_guard_14: process (addr14) begin addr14_tmp <= addr14; --synthesis translate_off if (CONV_INTEGER(addr14) > mem_size-1) then addr14_tmp <= (others => '0'); else addr14_tmp <= addr14; end if; --synthesis translate_on end process; memory_access_guard_15: process (addr15) begin addr15_tmp <= addr15; --synthesis translate_off if (CONV_INTEGER(addr15) > mem_size-1) then addr15_tmp <= (others => '0'); else addr15_tmp <= addr15; end if; --synthesis translate_on end process; memory_access_guard_16: process (addr16) begin addr16_tmp <= addr16; --synthesis translate_off if (CONV_INTEGER(addr16) > mem_size-1) then addr16_tmp <= (others => '0'); else addr16_tmp <= addr16; end if; --synthesis translate_on end process; memory_access_guard_17: process (addr17) begin addr17_tmp <= addr17; --synthesis translate_off if (CONV_INTEGER(addr17) > mem_size-1) then addr17_tmp <= (others => '0'); else addr17_tmp <= addr17; end if; --synthesis translate_on end process; memory_access_guard_18: process (addr18) begin addr18_tmp <= addr18; --synthesis translate_off if (CONV_INTEGER(addr18) > mem_size-1) then addr18_tmp <= (others => '0'); else addr18_tmp <= addr18; end if; --synthesis translate_on end process; memory_access_guard_19: process (addr19) begin addr19_tmp <= addr19; --synthesis translate_off if (CONV_INTEGER(addr19) > mem_size-1) then addr19_tmp <= (others => '0'); else addr19_tmp <= addr19; end if; --synthesis translate_on end process; memory_access_guard_20: process (addr20) begin addr20_tmp <= addr20; --synthesis translate_off if (CONV_INTEGER(addr20) > mem_size-1) then addr20_tmp <= (others => '0'); else addr20_tmp <= addr20; end if; --synthesis translate_on end process; memory_access_guard_21: process (addr21) begin addr21_tmp <= addr21; --synthesis translate_off if (CONV_INTEGER(addr21) > mem_size-1) then addr21_tmp <= (others => '0'); else addr21_tmp <= addr21; end if; --synthesis translate_on end process; memory_access_guard_22: process (addr22) begin addr22_tmp <= addr22; --synthesis translate_off if (CONV_INTEGER(addr22) > mem_size-1) then addr22_tmp <= (others => '0'); else addr22_tmp <= addr22; end if; --synthesis translate_on end process; memory_access_guard_23: process (addr23) begin addr23_tmp <= addr23; --synthesis translate_off if (CONV_INTEGER(addr23) > mem_size-1) then addr23_tmp <= (others => '0'); else addr23_tmp <= addr23; end if; --synthesis translate_on end process; memory_access_guard_24: process (addr24) begin addr24_tmp <= addr24; --synthesis translate_off if (CONV_INTEGER(addr24) > mem_size-1) then addr24_tmp <= (others => '0'); else addr24_tmp <= addr24; end if; --synthesis translate_on end process; memory_access_guard_25: process (addr25) begin addr25_tmp <= addr25; --synthesis translate_off if (CONV_INTEGER(addr25) > mem_size-1) then addr25_tmp <= (others => '0'); else addr25_tmp <= addr25; end if; --synthesis translate_on end process; memory_access_guard_26: process (addr26) begin addr26_tmp <= addr26; --synthesis translate_off if (CONV_INTEGER(addr26) > mem_size-1) then addr26_tmp <= (others => '0'); else addr26_tmp <= addr26; end if; --synthesis translate_on end process; memory_access_guard_27: process (addr27) begin addr27_tmp <= addr27; --synthesis translate_off if (CONV_INTEGER(addr27) > mem_size-1) then addr27_tmp <= (others => '0'); else addr27_tmp <= addr27; end if; --synthesis translate_on end process; memory_access_guard_28: process (addr28) begin addr28_tmp <= addr28; --synthesis translate_off if (CONV_INTEGER(addr28) > mem_size-1) then addr28_tmp <= (others => '0'); else addr28_tmp <= addr28; end if; --synthesis translate_on end process; memory_access_guard_29: process (addr29) begin addr29_tmp <= addr29; --synthesis translate_off if (CONV_INTEGER(addr29) > mem_size-1) then addr29_tmp <= (others => '0'); else addr29_tmp <= addr29; end if; --synthesis translate_on end process; memory_access_guard_30: process (addr30) begin addr30_tmp <= addr30; --synthesis translate_off if (CONV_INTEGER(addr30) > mem_size-1) then addr30_tmp <= (others => '0'); else addr30_tmp <= addr30; end if; --synthesis translate_on end process; memory_access_guard_31: process (addr31) begin addr31_tmp <= addr31; --synthesis translate_off if (CONV_INTEGER(addr31) > mem_size-1) then addr31_tmp <= (others => '0'); else addr31_tmp <= addr31; end if; --synthesis translate_on end process; memory_access_guard_32: process (addr32) begin addr32_tmp <= addr32; --synthesis translate_off if (CONV_INTEGER(addr32) > mem_size-1) then addr32_tmp <= (others => '0'); else addr32_tmp <= addr32; end if; --synthesis translate_on end process; memory_access_guard_33: process (addr33) begin addr33_tmp <= addr33; --synthesis translate_off if (CONV_INTEGER(addr33) > mem_size-1) then addr33_tmp <= (others => '0'); else addr33_tmp <= addr33; end if; --synthesis translate_on end process; memory_access_guard_34: process (addr34) begin addr34_tmp <= addr34; --synthesis translate_off if (CONV_INTEGER(addr34) > mem_size-1) then addr34_tmp <= (others => '0'); else addr34_tmp <= addr34; end if; --synthesis translate_on end process; memory_access_guard_35: process (addr35) begin addr35_tmp <= addr35; --synthesis translate_off if (CONV_INTEGER(addr35) > mem_size-1) then addr35_tmp <= (others => '0'); else addr35_tmp <= addr35; end if; --synthesis translate_on end process; memory_access_guard_36: process (addr36) begin addr36_tmp <= addr36; --synthesis translate_off if (CONV_INTEGER(addr36) > mem_size-1) then addr36_tmp <= (others => '0'); else addr36_tmp <= addr36; end if; --synthesis translate_on end process; memory_access_guard_37: process (addr37) begin addr37_tmp <= addr37; --synthesis translate_off if (CONV_INTEGER(addr37) > mem_size-1) then addr37_tmp <= (others => '0'); else addr37_tmp <= addr37; end if; --synthesis translate_on end process; memory_access_guard_38: process (addr38) begin addr38_tmp <= addr38; --synthesis translate_off if (CONV_INTEGER(addr38) > mem_size-1) then addr38_tmp <= (others => '0'); else addr38_tmp <= addr38; end if; --synthesis translate_on end process; memory_access_guard_39: process (addr39) begin addr39_tmp <= addr39; --synthesis translate_off if (CONV_INTEGER(addr39) > mem_size-1) then addr39_tmp <= (others => '0'); else addr39_tmp <= addr39; end if; --synthesis translate_on end process; memory_access_guard_40: process (addr40) begin addr40_tmp <= addr40; --synthesis translate_off if (CONV_INTEGER(addr40) > mem_size-1) then addr40_tmp <= (others => '0'); else addr40_tmp <= addr40; end if; --synthesis translate_on end process; memory_access_guard_41: process (addr41) begin addr41_tmp <= addr41; --synthesis translate_off if (CONV_INTEGER(addr41) > mem_size-1) then addr41_tmp <= (others => '0'); else addr41_tmp <= addr41; end if; --synthesis translate_on end process; memory_access_guard_42: process (addr42) begin addr42_tmp <= addr42; --synthesis translate_off if (CONV_INTEGER(addr42) > mem_size-1) then addr42_tmp <= (others => '0'); else addr42_tmp <= addr42; end if; --synthesis translate_on end process; memory_access_guard_43: process (addr43) begin addr43_tmp <= addr43; --synthesis translate_off if (CONV_INTEGER(addr43) > mem_size-1) then addr43_tmp <= (others => '0'); else addr43_tmp <= addr43; end if; --synthesis translate_on end process; memory_access_guard_44: process (addr44) begin addr44_tmp <= addr44; --synthesis translate_off if (CONV_INTEGER(addr44) > mem_size-1) then addr44_tmp <= (others => '0'); else addr44_tmp <= addr44; end if; --synthesis translate_on end process; memory_access_guard_45: process (addr45) begin addr45_tmp <= addr45; --synthesis translate_off if (CONV_INTEGER(addr45) > mem_size-1) then addr45_tmp <= (others => '0'); else addr45_tmp <= addr45; end if; --synthesis translate_on end process; memory_access_guard_46: process (addr46) begin addr46_tmp <= addr46; --synthesis translate_off if (CONV_INTEGER(addr46) > mem_size-1) then addr46_tmp <= (others => '0'); else addr46_tmp <= addr46; end if; --synthesis translate_on end process; memory_access_guard_47: process (addr47) begin addr47_tmp <= addr47; --synthesis translate_off if (CONV_INTEGER(addr47) > mem_size-1) then addr47_tmp <= (others => '0'); else addr47_tmp <= addr47; end if; --synthesis translate_on end process; memory_access_guard_48: process (addr48) begin addr48_tmp <= addr48; --synthesis translate_off if (CONV_INTEGER(addr48) > mem_size-1) then addr48_tmp <= (others => '0'); else addr48_tmp <= addr48; end if; --synthesis translate_on end process; memory_access_guard_49: process (addr49) begin addr49_tmp <= addr49; --synthesis translate_off if (CONV_INTEGER(addr49) > mem_size-1) then addr49_tmp <= (others => '0'); else addr49_tmp <= addr49; end if; --synthesis translate_on end process; memory_access_guard_50: process (addr50) begin addr50_tmp <= addr50; --synthesis translate_off if (CONV_INTEGER(addr50) > mem_size-1) then addr50_tmp <= (others => '0'); else addr50_tmp <= addr50; end if; --synthesis translate_on end process; memory_access_guard_51: process (addr51) begin addr51_tmp <= addr51; --synthesis translate_off if (CONV_INTEGER(addr51) > mem_size-1) then addr51_tmp <= (others => '0'); else addr51_tmp <= addr51; end if; --synthesis translate_on end process; memory_access_guard_52: process (addr52) begin addr52_tmp <= addr52; --synthesis translate_off if (CONV_INTEGER(addr52) > mem_size-1) then addr52_tmp <= (others => '0'); else addr52_tmp <= addr52; end if; --synthesis translate_on end process; memory_access_guard_53: process (addr53) begin addr53_tmp <= addr53; --synthesis translate_off if (CONV_INTEGER(addr53) > mem_size-1) then addr53_tmp <= (others => '0'); else addr53_tmp <= addr53; end if; --synthesis translate_on end process; memory_access_guard_54: process (addr54) begin addr54_tmp <= addr54; --synthesis translate_off if (CONV_INTEGER(addr54) > mem_size-1) then addr54_tmp <= (others => '0'); else addr54_tmp <= addr54; end if; --synthesis translate_on end process; memory_access_guard_55: process (addr55) begin addr55_tmp <= addr55; --synthesis translate_off if (CONV_INTEGER(addr55) > mem_size-1) then addr55_tmp <= (others => '0'); else addr55_tmp <= addr55; end if; --synthesis translate_on end process; memory_access_guard_56: process (addr56) begin addr56_tmp <= addr56; --synthesis translate_off if (CONV_INTEGER(addr56) > mem_size-1) then addr56_tmp <= (others => '0'); else addr56_tmp <= addr56; end if; --synthesis translate_on end process; memory_access_guard_57: process (addr57) begin addr57_tmp <= addr57; --synthesis translate_off if (CONV_INTEGER(addr57) > mem_size-1) then addr57_tmp <= (others => '0'); else addr57_tmp <= addr57; end if; --synthesis translate_on end process; memory_access_guard_58: process (addr58) begin addr58_tmp <= addr58; --synthesis translate_off if (CONV_INTEGER(addr58) > mem_size-1) then addr58_tmp <= (others => '0'); else addr58_tmp <= addr58; end if; --synthesis translate_on end process; memory_access_guard_59: process (addr59) begin addr59_tmp <= addr59; --synthesis translate_off if (CONV_INTEGER(addr59) > mem_size-1) then addr59_tmp <= (others => '0'); else addr59_tmp <= addr59; end if; --synthesis translate_on end process; memory_access_guard_60: process (addr60) begin addr60_tmp <= addr60; --synthesis translate_off if (CONV_INTEGER(addr60) > mem_size-1) then addr60_tmp <= (others => '0'); else addr60_tmp <= addr60; end if; --synthesis translate_on end process; memory_access_guard_61: process (addr61) begin addr61_tmp <= addr61; --synthesis translate_off if (CONV_INTEGER(addr61) > mem_size-1) then addr61_tmp <= (others => '0'); else addr61_tmp <= addr61; end if; --synthesis translate_on end process; memory_access_guard_62: process (addr62) begin addr62_tmp <= addr62; --synthesis translate_off if (CONV_INTEGER(addr62) > mem_size-1) then addr62_tmp <= (others => '0'); else addr62_tmp <= addr62; end if; --synthesis translate_on end process; memory_access_guard_63: process (addr63) begin addr63_tmp <= addr63; --synthesis translate_off if (CONV_INTEGER(addr63) > mem_size-1) then addr63_tmp <= (others => '0'); else addr63_tmp <= addr63; end if; --synthesis translate_on end process; memory_access_guard_64: process (addr64) begin addr64_tmp <= addr64; --synthesis translate_off if (CONV_INTEGER(addr64) > mem_size-1) then addr64_tmp <= (others => '0'); else addr64_tmp <= addr64; end if; --synthesis translate_on end process; memory_access_guard_65: process (addr65) begin addr65_tmp <= addr65; --synthesis translate_off if (CONV_INTEGER(addr65) > mem_size-1) then addr65_tmp <= (others => '0'); else addr65_tmp <= addr65; end if; --synthesis translate_on end process; memory_access_guard_66: process (addr66) begin addr66_tmp <= addr66; --synthesis translate_off if (CONV_INTEGER(addr66) > mem_size-1) then addr66_tmp <= (others => '0'); else addr66_tmp <= addr66; end if; --synthesis translate_on end process; memory_access_guard_67: process (addr67) begin addr67_tmp <= addr67; --synthesis translate_off if (CONV_INTEGER(addr67) > mem_size-1) then addr67_tmp <= (others => '0'); else addr67_tmp <= addr67; end if; --synthesis translate_on end process; memory_access_guard_68: process (addr68) begin addr68_tmp <= addr68; --synthesis translate_off if (CONV_INTEGER(addr68) > mem_size-1) then addr68_tmp <= (others => '0'); else addr68_tmp <= addr68; end if; --synthesis translate_on end process; memory_access_guard_69: process (addr69) begin addr69_tmp <= addr69; --synthesis translate_off if (CONV_INTEGER(addr69) > mem_size-1) then addr69_tmp <= (others => '0'); else addr69_tmp <= addr69; end if; --synthesis translate_on end process; memory_access_guard_70: process (addr70) begin addr70_tmp <= addr70; --synthesis translate_off if (CONV_INTEGER(addr70) > mem_size-1) then addr70_tmp <= (others => '0'); else addr70_tmp <= addr70; end if; --synthesis translate_on end process; memory_access_guard_71: process (addr71) begin addr71_tmp <= addr71; --synthesis translate_off if (CONV_INTEGER(addr71) > mem_size-1) then addr71_tmp <= (others => '0'); else addr71_tmp <= addr71; end if; --synthesis translate_on end process; memory_access_guard_72: process (addr72) begin addr72_tmp <= addr72; --synthesis translate_off if (CONV_INTEGER(addr72) > mem_size-1) then addr72_tmp <= (others => '0'); else addr72_tmp <= addr72; end if; --synthesis translate_on end process; memory_access_guard_73: process (addr73) begin addr73_tmp <= addr73; --synthesis translate_off if (CONV_INTEGER(addr73) > mem_size-1) then addr73_tmp <= (others => '0'); else addr73_tmp <= addr73; end if; --synthesis translate_on end process; memory_access_guard_74: process (addr74) begin addr74_tmp <= addr74; --synthesis translate_off if (CONV_INTEGER(addr74) > mem_size-1) then addr74_tmp <= (others => '0'); else addr74_tmp <= addr74; end if; --synthesis translate_on end process; memory_access_guard_75: process (addr75) begin addr75_tmp <= addr75; --synthesis translate_off if (CONV_INTEGER(addr75) > mem_size-1) then addr75_tmp <= (others => '0'); else addr75_tmp <= addr75; end if; --synthesis translate_on end process; memory_access_guard_76: process (addr76) begin addr76_tmp <= addr76; --synthesis translate_off if (CONV_INTEGER(addr76) > mem_size-1) then addr76_tmp <= (others => '0'); else addr76_tmp <= addr76; end if; --synthesis translate_on end process; memory_access_guard_77: process (addr77) begin addr77_tmp <= addr77; --synthesis translate_off if (CONV_INTEGER(addr77) > mem_size-1) then addr77_tmp <= (others => '0'); else addr77_tmp <= addr77; end if; --synthesis translate_on end process; memory_access_guard_78: process (addr78) begin addr78_tmp <= addr78; --synthesis translate_off if (CONV_INTEGER(addr78) > mem_size-1) then addr78_tmp <= (others => '0'); else addr78_tmp <= addr78; end if; --synthesis translate_on end process; memory_access_guard_79: process (addr79) begin addr79_tmp <= addr79; --synthesis translate_off if (CONV_INTEGER(addr79) > mem_size-1) then addr79_tmp <= (others => '0'); else addr79_tmp <= addr79; end if; --synthesis translate_on end process; memory_access_guard_80: process (addr80) begin addr80_tmp <= addr80; --synthesis translate_off if (CONV_INTEGER(addr80) > mem_size-1) then addr80_tmp <= (others => '0'); else addr80_tmp <= addr80; end if; --synthesis translate_on end process; memory_access_guard_81: process (addr81) begin addr81_tmp <= addr81; --synthesis translate_off if (CONV_INTEGER(addr81) > mem_size-1) then addr81_tmp <= (others => '0'); else addr81_tmp <= addr81; end if; --synthesis translate_on end process; memory_access_guard_82: process (addr82) begin addr82_tmp <= addr82; --synthesis translate_off if (CONV_INTEGER(addr82) > mem_size-1) then addr82_tmp <= (others => '0'); else addr82_tmp <= addr82; end if; --synthesis translate_on end process; memory_access_guard_83: process (addr83) begin addr83_tmp <= addr83; --synthesis translate_off if (CONV_INTEGER(addr83) > mem_size-1) then addr83_tmp <= (others => '0'); else addr83_tmp <= addr83; end if; --synthesis translate_on end process; memory_access_guard_84: process (addr84) begin addr84_tmp <= addr84; --synthesis translate_off if (CONV_INTEGER(addr84) > mem_size-1) then addr84_tmp <= (others => '0'); else addr84_tmp <= addr84; end if; --synthesis translate_on end process; memory_access_guard_85: process (addr85) begin addr85_tmp <= addr85; --synthesis translate_off if (CONV_INTEGER(addr85) > mem_size-1) then addr85_tmp <= (others => '0'); else addr85_tmp <= addr85; end if; --synthesis translate_on end process; memory_access_guard_86: process (addr86) begin addr86_tmp <= addr86; --synthesis translate_off if (CONV_INTEGER(addr86) > mem_size-1) then addr86_tmp <= (others => '0'); else addr86_tmp <= addr86; end if; --synthesis translate_on end process; memory_access_guard_87: process (addr87) begin addr87_tmp <= addr87; --synthesis translate_off if (CONV_INTEGER(addr87) > mem_size-1) then addr87_tmp <= (others => '0'); else addr87_tmp <= addr87; end if; --synthesis translate_on end process; memory_access_guard_88: process (addr88) begin addr88_tmp <= addr88; --synthesis translate_off if (CONV_INTEGER(addr88) > mem_size-1) then addr88_tmp <= (others => '0'); else addr88_tmp <= addr88; end if; --synthesis translate_on end process; memory_access_guard_89: process (addr89) begin addr89_tmp <= addr89; --synthesis translate_off if (CONV_INTEGER(addr89) > mem_size-1) then addr89_tmp <= (others => '0'); else addr89_tmp <= addr89; end if; --synthesis translate_on end process; memory_access_guard_90: process (addr90) begin addr90_tmp <= addr90; --synthesis translate_off if (CONV_INTEGER(addr90) > mem_size-1) then addr90_tmp <= (others => '0'); else addr90_tmp <= addr90; end if; --synthesis translate_on end process; memory_access_guard_91: process (addr91) begin addr91_tmp <= addr91; --synthesis translate_off if (CONV_INTEGER(addr91) > mem_size-1) then addr91_tmp <= (others => '0'); else addr91_tmp <= addr91; end if; --synthesis translate_on end process; memory_access_guard_92: process (addr92) begin addr92_tmp <= addr92; --synthesis translate_off if (CONV_INTEGER(addr92) > mem_size-1) then addr92_tmp <= (others => '0'); else addr92_tmp <= addr92; end if; --synthesis translate_on end process; memory_access_guard_93: process (addr93) begin addr93_tmp <= addr93; --synthesis translate_off if (CONV_INTEGER(addr93) > mem_size-1) then addr93_tmp <= (others => '0'); else addr93_tmp <= addr93; end if; --synthesis translate_on end process; memory_access_guard_94: process (addr94) begin addr94_tmp <= addr94; --synthesis translate_off if (CONV_INTEGER(addr94) > mem_size-1) then addr94_tmp <= (others => '0'); else addr94_tmp <= addr94; end if; --synthesis translate_on end process; memory_access_guard_95: process (addr95) begin addr95_tmp <= addr95; --synthesis translate_off if (CONV_INTEGER(addr95) > mem_size-1) then addr95_tmp <= (others => '0'); else addr95_tmp <= addr95; end if; --synthesis translate_on end process; memory_access_guard_96: process (addr96) begin addr96_tmp <= addr96; --synthesis translate_off if (CONV_INTEGER(addr96) > mem_size-1) then addr96_tmp <= (others => '0'); else addr96_tmp <= addr96; end if; --synthesis translate_on end process; memory_access_guard_97: process (addr97) begin addr97_tmp <= addr97; --synthesis translate_off if (CONV_INTEGER(addr97) > mem_size-1) then addr97_tmp <= (others => '0'); else addr97_tmp <= addr97; end if; --synthesis translate_on end process; memory_access_guard_98: process (addr98) begin addr98_tmp <= addr98; --synthesis translate_off if (CONV_INTEGER(addr98) > mem_size-1) then addr98_tmp <= (others => '0'); else addr98_tmp <= addr98; end if; --synthesis translate_on end process; memory_access_guard_99: process (addr99) begin addr99_tmp <= addr99; --synthesis translate_off if (CONV_INTEGER(addr99) > mem_size-1) then addr99_tmp <= (others => '0'); else addr99_tmp <= addr99; end if; --synthesis translate_on end process; memory_access_guard_100: process (addr100) begin addr100_tmp <= addr100; --synthesis translate_off if (CONV_INTEGER(addr100) > mem_size-1) then addr100_tmp <= (others => '0'); else addr100_tmp <= addr100; end if; --synthesis translate_on end process; memory_access_guard_101: process (addr101) begin addr101_tmp <= addr101; --synthesis translate_off if (CONV_INTEGER(addr101) > mem_size-1) then addr101_tmp <= (others => '0'); else addr101_tmp <= addr101; end if; --synthesis translate_on end process; memory_access_guard_102: process (addr102) begin addr102_tmp <= addr102; --synthesis translate_off if (CONV_INTEGER(addr102) > mem_size-1) then addr102_tmp <= (others => '0'); else addr102_tmp <= addr102; end if; --synthesis translate_on end process; memory_access_guard_103: process (addr103) begin addr103_tmp <= addr103; --synthesis translate_off if (CONV_INTEGER(addr103) > mem_size-1) then addr103_tmp <= (others => '0'); else addr103_tmp <= addr103; end if; --synthesis translate_on end process; memory_access_guard_104: process (addr104) begin addr104_tmp <= addr104; --synthesis translate_off if (CONV_INTEGER(addr104) > mem_size-1) then addr104_tmp <= (others => '0'); else addr104_tmp <= addr104; end if; --synthesis translate_on end process; memory_access_guard_105: process (addr105) begin addr105_tmp <= addr105; --synthesis translate_off if (CONV_INTEGER(addr105) > mem_size-1) then addr105_tmp <= (others => '0'); else addr105_tmp <= addr105; end if; --synthesis translate_on end process; memory_access_guard_106: process (addr106) begin addr106_tmp <= addr106; --synthesis translate_off if (CONV_INTEGER(addr106) > mem_size-1) then addr106_tmp <= (others => '0'); else addr106_tmp <= addr106; end if; --synthesis translate_on end process; memory_access_guard_107: process (addr107) begin addr107_tmp <= addr107; --synthesis translate_off if (CONV_INTEGER(addr107) > mem_size-1) then addr107_tmp <= (others => '0'); else addr107_tmp <= addr107; end if; --synthesis translate_on end process; memory_access_guard_108: process (addr108) begin addr108_tmp <= addr108; --synthesis translate_off if (CONV_INTEGER(addr108) > mem_size-1) then addr108_tmp <= (others => '0'); else addr108_tmp <= addr108; end if; --synthesis translate_on end process; memory_access_guard_109: process (addr109) begin addr109_tmp <= addr109; --synthesis translate_off if (CONV_INTEGER(addr109) > mem_size-1) then addr109_tmp <= (others => '0'); else addr109_tmp <= addr109; end if; --synthesis translate_on end process; memory_access_guard_110: process (addr110) begin addr110_tmp <= addr110; --synthesis translate_off if (CONV_INTEGER(addr110) > mem_size-1) then addr110_tmp <= (others => '0'); else addr110_tmp <= addr110; end if; --synthesis translate_on end process; memory_access_guard_111: process (addr111) begin addr111_tmp <= addr111; --synthesis translate_off if (CONV_INTEGER(addr111) > mem_size-1) then addr111_tmp <= (others => '0'); else addr111_tmp <= addr111; end if; --synthesis translate_on end process; memory_access_guard_112: process (addr112) begin addr112_tmp <= addr112; --synthesis translate_off if (CONV_INTEGER(addr112) > mem_size-1) then addr112_tmp <= (others => '0'); else addr112_tmp <= addr112; end if; --synthesis translate_on end process; memory_access_guard_113: process (addr113) begin addr113_tmp <= addr113; --synthesis translate_off if (CONV_INTEGER(addr113) > mem_size-1) then addr113_tmp <= (others => '0'); else addr113_tmp <= addr113; end if; --synthesis translate_on end process; memory_access_guard_114: process (addr114) begin addr114_tmp <= addr114; --synthesis translate_off if (CONV_INTEGER(addr114) > mem_size-1) then addr114_tmp <= (others => '0'); else addr114_tmp <= addr114; end if; --synthesis translate_on end process; memory_access_guard_115: process (addr115) begin addr115_tmp <= addr115; --synthesis translate_off if (CONV_INTEGER(addr115) > mem_size-1) then addr115_tmp <= (others => '0'); else addr115_tmp <= addr115; end if; --synthesis translate_on end process; memory_access_guard_116: process (addr116) begin addr116_tmp <= addr116; --synthesis translate_off if (CONV_INTEGER(addr116) > mem_size-1) then addr116_tmp <= (others => '0'); else addr116_tmp <= addr116; end if; --synthesis translate_on end process; memory_access_guard_117: process (addr117) begin addr117_tmp <= addr117; --synthesis translate_off if (CONV_INTEGER(addr117) > mem_size-1) then addr117_tmp <= (others => '0'); else addr117_tmp <= addr117; end if; --synthesis translate_on end process; memory_access_guard_118: process (addr118) begin addr118_tmp <= addr118; --synthesis translate_off if (CONV_INTEGER(addr118) > mem_size-1) then addr118_tmp <= (others => '0'); else addr118_tmp <= addr118; end if; --synthesis translate_on end process; memory_access_guard_119: process (addr119) begin addr119_tmp <= addr119; --synthesis translate_off if (CONV_INTEGER(addr119) > mem_size-1) then addr119_tmp <= (others => '0'); else addr119_tmp <= addr119; end if; --synthesis translate_on end process; memory_access_guard_120: process (addr120) begin addr120_tmp <= addr120; --synthesis translate_off if (CONV_INTEGER(addr120) > mem_size-1) then addr120_tmp <= (others => '0'); else addr120_tmp <= addr120; end if; --synthesis translate_on end process; memory_access_guard_121: process (addr121) begin addr121_tmp <= addr121; --synthesis translate_off if (CONV_INTEGER(addr121) > mem_size-1) then addr121_tmp <= (others => '0'); else addr121_tmp <= addr121; end if; --synthesis translate_on end process; memory_access_guard_122: process (addr122) begin addr122_tmp <= addr122; --synthesis translate_off if (CONV_INTEGER(addr122) > mem_size-1) then addr122_tmp <= (others => '0'); else addr122_tmp <= addr122; end if; --synthesis translate_on end process; memory_access_guard_123: process (addr123) begin addr123_tmp <= addr123; --synthesis translate_off if (CONV_INTEGER(addr123) > mem_size-1) then addr123_tmp <= (others => '0'); else addr123_tmp <= addr123; end if; --synthesis translate_on end process; memory_access_guard_124: process (addr124) begin addr124_tmp <= addr124; --synthesis translate_off if (CONV_INTEGER(addr124) > mem_size-1) then addr124_tmp <= (others => '0'); else addr124_tmp <= addr124; end if; --synthesis translate_on end process; memory_access_guard_125: process (addr125) begin addr125_tmp <= addr125; --synthesis translate_off if (CONV_INTEGER(addr125) > mem_size-1) then addr125_tmp <= (others => '0'); else addr125_tmp <= addr125; end if; --synthesis translate_on end process; memory_access_guard_126: process (addr126) begin addr126_tmp <= addr126; --synthesis translate_off if (CONV_INTEGER(addr126) > mem_size-1) then addr126_tmp <= (others => '0'); else addr126_tmp <= addr126; end if; --synthesis translate_on end process; memory_access_guard_127: process (addr127) begin addr127_tmp <= addr127; --synthesis translate_off if (CONV_INTEGER(addr127) > mem_size-1) then addr127_tmp <= (others => '0'); else addr127_tmp <= addr127; end if; --synthesis translate_on end process; memory_access_guard_128: process (addr128) begin addr128_tmp <= addr128; --synthesis translate_off if (CONV_INTEGER(addr128) > mem_size-1) then addr128_tmp <= (others => '0'); else addr128_tmp <= addr128; end if; --synthesis translate_on end process; memory_access_guard_129: process (addr129) begin addr129_tmp <= addr129; --synthesis translate_off if (CONV_INTEGER(addr129) > mem_size-1) then addr129_tmp <= (others => '0'); else addr129_tmp <= addr129; end if; --synthesis translate_on end process; memory_access_guard_130: process (addr130) begin addr130_tmp <= addr130; --synthesis translate_off if (CONV_INTEGER(addr130) > mem_size-1) then addr130_tmp <= (others => '0'); else addr130_tmp <= addr130; end if; --synthesis translate_on end process; memory_access_guard_131: process (addr131) begin addr131_tmp <= addr131; --synthesis translate_off if (CONV_INTEGER(addr131) > mem_size-1) then addr131_tmp <= (others => '0'); else addr131_tmp <= addr131; end if; --synthesis translate_on end process; memory_access_guard_132: process (addr132) begin addr132_tmp <= addr132; --synthesis translate_off if (CONV_INTEGER(addr132) > mem_size-1) then addr132_tmp <= (others => '0'); else addr132_tmp <= addr132; end if; --synthesis translate_on end process; memory_access_guard_133: process (addr133) begin addr133_tmp <= addr133; --synthesis translate_off if (CONV_INTEGER(addr133) > mem_size-1) then addr133_tmp <= (others => '0'); else addr133_tmp <= addr133; end if; --synthesis translate_on end process; memory_access_guard_134: process (addr134) begin addr134_tmp <= addr134; --synthesis translate_off if (CONV_INTEGER(addr134) > mem_size-1) then addr134_tmp <= (others => '0'); else addr134_tmp <= addr134; end if; --synthesis translate_on end process; memory_access_guard_135: process (addr135) begin addr135_tmp <= addr135; --synthesis translate_off if (CONV_INTEGER(addr135) > mem_size-1) then addr135_tmp <= (others => '0'); else addr135_tmp <= addr135; end if; --synthesis translate_on end process; memory_access_guard_136: process (addr136) begin addr136_tmp <= addr136; --synthesis translate_off if (CONV_INTEGER(addr136) > mem_size-1) then addr136_tmp <= (others => '0'); else addr136_tmp <= addr136; end if; --synthesis translate_on end process; memory_access_guard_137: process (addr137) begin addr137_tmp <= addr137; --synthesis translate_off if (CONV_INTEGER(addr137) > mem_size-1) then addr137_tmp <= (others => '0'); else addr137_tmp <= addr137; end if; --synthesis translate_on end process; memory_access_guard_138: process (addr138) begin addr138_tmp <= addr138; --synthesis translate_off if (CONV_INTEGER(addr138) > mem_size-1) then addr138_tmp <= (others => '0'); else addr138_tmp <= addr138; end if; --synthesis translate_on end process; memory_access_guard_139: process (addr139) begin addr139_tmp <= addr139; --synthesis translate_off if (CONV_INTEGER(addr139) > mem_size-1) then addr139_tmp <= (others => '0'); else addr139_tmp <= addr139; end if; --synthesis translate_on end process; memory_access_guard_140: process (addr140) begin addr140_tmp <= addr140; --synthesis translate_off if (CONV_INTEGER(addr140) > mem_size-1) then addr140_tmp <= (others => '0'); else addr140_tmp <= addr140; end if; --synthesis translate_on end process; memory_access_guard_141: process (addr141) begin addr141_tmp <= addr141; --synthesis translate_off if (CONV_INTEGER(addr141) > mem_size-1) then addr141_tmp <= (others => '0'); else addr141_tmp <= addr141; end if; --synthesis translate_on end process; memory_access_guard_142: process (addr142) begin addr142_tmp <= addr142; --synthesis translate_off if (CONV_INTEGER(addr142) > mem_size-1) then addr142_tmp <= (others => '0'); else addr142_tmp <= addr142; end if; --synthesis translate_on end process; memory_access_guard_143: process (addr143) begin addr143_tmp <= addr143; --synthesis translate_off if (CONV_INTEGER(addr143) > mem_size-1) then addr143_tmp <= (others => '0'); else addr143_tmp <= addr143; end if; --synthesis translate_on end process; memory_access_guard_144: process (addr144) begin addr144_tmp <= addr144; --synthesis translate_off if (CONV_INTEGER(addr144) > mem_size-1) then addr144_tmp <= (others => '0'); else addr144_tmp <= addr144; end if; --synthesis translate_on end process; memory_access_guard_145: process (addr145) begin addr145_tmp <= addr145; --synthesis translate_off if (CONV_INTEGER(addr145) > mem_size-1) then addr145_tmp <= (others => '0'); else addr145_tmp <= addr145; end if; --synthesis translate_on end process; memory_access_guard_146: process (addr146) begin addr146_tmp <= addr146; --synthesis translate_off if (CONV_INTEGER(addr146) > mem_size-1) then addr146_tmp <= (others => '0'); else addr146_tmp <= addr146; end if; --synthesis translate_on end process; memory_access_guard_147: process (addr147) begin addr147_tmp <= addr147; --synthesis translate_off if (CONV_INTEGER(addr147) > mem_size-1) then addr147_tmp <= (others => '0'); else addr147_tmp <= addr147; end if; --synthesis translate_on end process; memory_access_guard_148: process (addr148) begin addr148_tmp <= addr148; --synthesis translate_off if (CONV_INTEGER(addr148) > mem_size-1) then addr148_tmp <= (others => '0'); else addr148_tmp <= addr148; end if; --synthesis translate_on end process; memory_access_guard_149: process (addr149) begin addr149_tmp <= addr149; --synthesis translate_off if (CONV_INTEGER(addr149) > mem_size-1) then addr149_tmp <= (others => '0'); else addr149_tmp <= addr149; end if; --synthesis translate_on end process; memory_access_guard_150: process (addr150) begin addr150_tmp <= addr150; --synthesis translate_off if (CONV_INTEGER(addr150) > mem_size-1) then addr150_tmp <= (others => '0'); else addr150_tmp <= addr150; end if; --synthesis translate_on end process; memory_access_guard_151: process (addr151) begin addr151_tmp <= addr151; --synthesis translate_off if (CONV_INTEGER(addr151) > mem_size-1) then addr151_tmp <= (others => '0'); else addr151_tmp <= addr151; end if; --synthesis translate_on end process; memory_access_guard_152: process (addr152) begin addr152_tmp <= addr152; --synthesis translate_off if (CONV_INTEGER(addr152) > mem_size-1) then addr152_tmp <= (others => '0'); else addr152_tmp <= addr152; end if; --synthesis translate_on end process; memory_access_guard_153: process (addr153) begin addr153_tmp <= addr153; --synthesis translate_off if (CONV_INTEGER(addr153) > mem_size-1) then addr153_tmp <= (others => '0'); else addr153_tmp <= addr153; end if; --synthesis translate_on end process; memory_access_guard_154: process (addr154) begin addr154_tmp <= addr154; --synthesis translate_off if (CONV_INTEGER(addr154) > mem_size-1) then addr154_tmp <= (others => '0'); else addr154_tmp <= addr154; end if; --synthesis translate_on end process; memory_access_guard_155: process (addr155) begin addr155_tmp <= addr155; --synthesis translate_off if (CONV_INTEGER(addr155) > mem_size-1) then addr155_tmp <= (others => '0'); else addr155_tmp <= addr155; end if; --synthesis translate_on end process; memory_access_guard_156: process (addr156) begin addr156_tmp <= addr156; --synthesis translate_off if (CONV_INTEGER(addr156) > mem_size-1) then addr156_tmp <= (others => '0'); else addr156_tmp <= addr156; end if; --synthesis translate_on end process; memory_access_guard_157: process (addr157) begin addr157_tmp <= addr157; --synthesis translate_off if (CONV_INTEGER(addr157) > mem_size-1) then addr157_tmp <= (others => '0'); else addr157_tmp <= addr157; end if; --synthesis translate_on end process; memory_access_guard_158: process (addr158) begin addr158_tmp <= addr158; --synthesis translate_off if (CONV_INTEGER(addr158) > mem_size-1) then addr158_tmp <= (others => '0'); else addr158_tmp <= addr158; end if; --synthesis translate_on end process; memory_access_guard_159: process (addr159) begin addr159_tmp <= addr159; --synthesis translate_off if (CONV_INTEGER(addr159) > mem_size-1) then addr159_tmp <= (others => '0'); else addr159_tmp <= addr159; end if; --synthesis translate_on end process; memory_access_guard_160: process (addr160) begin addr160_tmp <= addr160; --synthesis translate_off if (CONV_INTEGER(addr160) > mem_size-1) then addr160_tmp <= (others => '0'); else addr160_tmp <= addr160; end if; --synthesis translate_on end process; memory_access_guard_161: process (addr161) begin addr161_tmp <= addr161; --synthesis translate_off if (CONV_INTEGER(addr161) > mem_size-1) then addr161_tmp <= (others => '0'); else addr161_tmp <= addr161; end if; --synthesis translate_on end process; memory_access_guard_162: process (addr162) begin addr162_tmp <= addr162; --synthesis translate_off if (CONV_INTEGER(addr162) > mem_size-1) then addr162_tmp <= (others => '0'); else addr162_tmp <= addr162; end if; --synthesis translate_on end process; memory_access_guard_163: process (addr163) begin addr163_tmp <= addr163; --synthesis translate_off if (CONV_INTEGER(addr163) > mem_size-1) then addr163_tmp <= (others => '0'); else addr163_tmp <= addr163; end if; --synthesis translate_on end process; memory_access_guard_164: process (addr164) begin addr164_tmp <= addr164; --synthesis translate_off if (CONV_INTEGER(addr164) > mem_size-1) then addr164_tmp <= (others => '0'); else addr164_tmp <= addr164; end if; --synthesis translate_on end process; memory_access_guard_165: process (addr165) begin addr165_tmp <= addr165; --synthesis translate_off if (CONV_INTEGER(addr165) > mem_size-1) then addr165_tmp <= (others => '0'); else addr165_tmp <= addr165; end if; --synthesis translate_on end process; memory_access_guard_166: process (addr166) begin addr166_tmp <= addr166; --synthesis translate_off if (CONV_INTEGER(addr166) > mem_size-1) then addr166_tmp <= (others => '0'); else addr166_tmp <= addr166; end if; --synthesis translate_on end process; memory_access_guard_167: process (addr167) begin addr167_tmp <= addr167; --synthesis translate_off if (CONV_INTEGER(addr167) > mem_size-1) then addr167_tmp <= (others => '0'); else addr167_tmp <= addr167; end if; --synthesis translate_on end process; memory_access_guard_168: process (addr168) begin addr168_tmp <= addr168; --synthesis translate_off if (CONV_INTEGER(addr168) > mem_size-1) then addr168_tmp <= (others => '0'); else addr168_tmp <= addr168; end if; --synthesis translate_on end process; memory_access_guard_169: process (addr169) begin addr169_tmp <= addr169; --synthesis translate_off if (CONV_INTEGER(addr169) > mem_size-1) then addr169_tmp <= (others => '0'); else addr169_tmp <= addr169; end if; --synthesis translate_on end process; memory_access_guard_170: process (addr170) begin addr170_tmp <= addr170; --synthesis translate_off if (CONV_INTEGER(addr170) > mem_size-1) then addr170_tmp <= (others => '0'); else addr170_tmp <= addr170; end if; --synthesis translate_on end process; memory_access_guard_171: process (addr171) begin addr171_tmp <= addr171; --synthesis translate_off if (CONV_INTEGER(addr171) > mem_size-1) then addr171_tmp <= (others => '0'); else addr171_tmp <= addr171; end if; --synthesis translate_on end process; memory_access_guard_172: process (addr172) begin addr172_tmp <= addr172; --synthesis translate_off if (CONV_INTEGER(addr172) > mem_size-1) then addr172_tmp <= (others => '0'); else addr172_tmp <= addr172; end if; --synthesis translate_on end process; memory_access_guard_173: process (addr173) begin addr173_tmp <= addr173; --synthesis translate_off if (CONV_INTEGER(addr173) > mem_size-1) then addr173_tmp <= (others => '0'); else addr173_tmp <= addr173; end if; --synthesis translate_on end process; memory_access_guard_174: process (addr174) begin addr174_tmp <= addr174; --synthesis translate_off if (CONV_INTEGER(addr174) > mem_size-1) then addr174_tmp <= (others => '0'); else addr174_tmp <= addr174; end if; --synthesis translate_on end process; memory_access_guard_175: process (addr175) begin addr175_tmp <= addr175; --synthesis translate_off if (CONV_INTEGER(addr175) > mem_size-1) then addr175_tmp <= (others => '0'); else addr175_tmp <= addr175; end if; --synthesis translate_on end process; memory_access_guard_176: process (addr176) begin addr176_tmp <= addr176; --synthesis translate_off if (CONV_INTEGER(addr176) > mem_size-1) then addr176_tmp <= (others => '0'); else addr176_tmp <= addr176; end if; --synthesis translate_on end process; memory_access_guard_177: process (addr177) begin addr177_tmp <= addr177; --synthesis translate_off if (CONV_INTEGER(addr177) > mem_size-1) then addr177_tmp <= (others => '0'); else addr177_tmp <= addr177; end if; --synthesis translate_on end process; memory_access_guard_178: process (addr178) begin addr178_tmp <= addr178; --synthesis translate_off if (CONV_INTEGER(addr178) > mem_size-1) then addr178_tmp <= (others => '0'); else addr178_tmp <= addr178; end if; --synthesis translate_on end process; memory_access_guard_179: process (addr179) begin addr179_tmp <= addr179; --synthesis translate_off if (CONV_INTEGER(addr179) > mem_size-1) then addr179_tmp <= (others => '0'); else addr179_tmp <= addr179; end if; --synthesis translate_on end process; memory_access_guard_180: process (addr180) begin addr180_tmp <= addr180; --synthesis translate_off if (CONV_INTEGER(addr180) > mem_size-1) then addr180_tmp <= (others => '0'); else addr180_tmp <= addr180; end if; --synthesis translate_on end process; memory_access_guard_181: process (addr181) begin addr181_tmp <= addr181; --synthesis translate_off if (CONV_INTEGER(addr181) > mem_size-1) then addr181_tmp <= (others => '0'); else addr181_tmp <= addr181; end if; --synthesis translate_on end process; memory_access_guard_182: process (addr182) begin addr182_tmp <= addr182; --synthesis translate_off if (CONV_INTEGER(addr182) > mem_size-1) then addr182_tmp <= (others => '0'); else addr182_tmp <= addr182; end if; --synthesis translate_on end process; memory_access_guard_183: process (addr183) begin addr183_tmp <= addr183; --synthesis translate_off if (CONV_INTEGER(addr183) > mem_size-1) then addr183_tmp <= (others => '0'); else addr183_tmp <= addr183; end if; --synthesis translate_on end process; memory_access_guard_184: process (addr184) begin addr184_tmp <= addr184; --synthesis translate_off if (CONV_INTEGER(addr184) > mem_size-1) then addr184_tmp <= (others => '0'); else addr184_tmp <= addr184; end if; --synthesis translate_on end process; memory_access_guard_185: process (addr185) begin addr185_tmp <= addr185; --synthesis translate_off if (CONV_INTEGER(addr185) > mem_size-1) then addr185_tmp <= (others => '0'); else addr185_tmp <= addr185; end if; --synthesis translate_on end process; memory_access_guard_186: process (addr186) begin addr186_tmp <= addr186; --synthesis translate_off if (CONV_INTEGER(addr186) > mem_size-1) then addr186_tmp <= (others => '0'); else addr186_tmp <= addr186; end if; --synthesis translate_on end process; memory_access_guard_187: process (addr187) begin addr187_tmp <= addr187; --synthesis translate_off if (CONV_INTEGER(addr187) > mem_size-1) then addr187_tmp <= (others => '0'); else addr187_tmp <= addr187; end if; --synthesis translate_on end process; memory_access_guard_188: process (addr188) begin addr188_tmp <= addr188; --synthesis translate_off if (CONV_INTEGER(addr188) > mem_size-1) then addr188_tmp <= (others => '0'); else addr188_tmp <= addr188; end if; --synthesis translate_on end process; memory_access_guard_189: process (addr189) begin addr189_tmp <= addr189; --synthesis translate_off if (CONV_INTEGER(addr189) > mem_size-1) then addr189_tmp <= (others => '0'); else addr189_tmp <= addr189; end if; --synthesis translate_on end process; memory_access_guard_190: process (addr190) begin addr190_tmp <= addr190; --synthesis translate_off if (CONV_INTEGER(addr190) > mem_size-1) then addr190_tmp <= (others => '0'); else addr190_tmp <= addr190; end if; --synthesis translate_on end process; memory_access_guard_191: process (addr191) begin addr191_tmp <= addr191; --synthesis translate_off if (CONV_INTEGER(addr191) > mem_size-1) then addr191_tmp <= (others => '0'); else addr191_tmp <= addr191; end if; --synthesis translate_on end process; memory_access_guard_192: process (addr192) begin addr192_tmp <= addr192; --synthesis translate_off if (CONV_INTEGER(addr192) > mem_size-1) then addr192_tmp <= (others => '0'); else addr192_tmp <= addr192; end if; --synthesis translate_on end process; memory_access_guard_193: process (addr193) begin addr193_tmp <= addr193; --synthesis translate_off if (CONV_INTEGER(addr193) > mem_size-1) then addr193_tmp <= (others => '0'); else addr193_tmp <= addr193; end if; --synthesis translate_on end process; memory_access_guard_194: process (addr194) begin addr194_tmp <= addr194; --synthesis translate_off if (CONV_INTEGER(addr194) > mem_size-1) then addr194_tmp <= (others => '0'); else addr194_tmp <= addr194; end if; --synthesis translate_on end process; memory_access_guard_195: process (addr195) begin addr195_tmp <= addr195; --synthesis translate_off if (CONV_INTEGER(addr195) > mem_size-1) then addr195_tmp <= (others => '0'); else addr195_tmp <= addr195; end if; --synthesis translate_on end process; memory_access_guard_196: process (addr196) begin addr196_tmp <= addr196; --synthesis translate_off if (CONV_INTEGER(addr196) > mem_size-1) then addr196_tmp <= (others => '0'); else addr196_tmp <= addr196; end if; --synthesis translate_on end process; memory_access_guard_197: process (addr197) begin addr197_tmp <= addr197; --synthesis translate_off if (CONV_INTEGER(addr197) > mem_size-1) then addr197_tmp <= (others => '0'); else addr197_tmp <= addr197; end if; --synthesis translate_on end process; memory_access_guard_198: process (addr198) begin addr198_tmp <= addr198; --synthesis translate_off if (CONV_INTEGER(addr198) > mem_size-1) then addr198_tmp <= (others => '0'); else addr198_tmp <= addr198; end if; --synthesis translate_on end process; memory_access_guard_199: process (addr199) begin addr199_tmp <= addr199; --synthesis translate_off if (CONV_INTEGER(addr199) > mem_size-1) then addr199_tmp <= (others => '0'); else addr199_tmp <= addr199; end if; --synthesis translate_on end process; p_rom_access: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then q0 <= mem0(CONV_INTEGER(addr0_tmp)); end if; if (ce1 = '1') then q1 <= mem0(CONV_INTEGER(addr1_tmp)); end if; if (ce2 = '1') then q2 <= mem1(CONV_INTEGER(addr2_tmp)); end if; if (ce3 = '1') then q3 <= mem1(CONV_INTEGER(addr3_tmp)); end if; if (ce4 = '1') then q4 <= mem2(CONV_INTEGER(addr4_tmp)); end if; if (ce5 = '1') then q5 <= mem2(CONV_INTEGER(addr5_tmp)); end if; if (ce6 = '1') then q6 <= mem3(CONV_INTEGER(addr6_tmp)); end if; if (ce7 = '1') then q7 <= mem3(CONV_INTEGER(addr7_tmp)); end if; if (ce8 = '1') then q8 <= mem4(CONV_INTEGER(addr8_tmp)); end if; if (ce9 = '1') then q9 <= mem4(CONV_INTEGER(addr9_tmp)); end if; if (ce10 = '1') then q10 <= mem5(CONV_INTEGER(addr10_tmp)); end if; if (ce11 = '1') then q11 <= mem5(CONV_INTEGER(addr11_tmp)); end if; if (ce12 = '1') then q12 <= mem6(CONV_INTEGER(addr12_tmp)); end if; if (ce13 = '1') then q13 <= mem6(CONV_INTEGER(addr13_tmp)); end if; if (ce14 = '1') then q14 <= mem7(CONV_INTEGER(addr14_tmp)); end if; if (ce15 = '1') then q15 <= mem7(CONV_INTEGER(addr15_tmp)); end if; if (ce16 = '1') then q16 <= mem8(CONV_INTEGER(addr16_tmp)); end if; if (ce17 = '1') then q17 <= mem8(CONV_INTEGER(addr17_tmp)); end if; if (ce18 = '1') then q18 <= mem9(CONV_INTEGER(addr18_tmp)); end if; if (ce19 = '1') then q19 <= mem9(CONV_INTEGER(addr19_tmp)); end if; if (ce20 = '1') then q20 <= mem10(CONV_INTEGER(addr20_tmp)); end if; if (ce21 = '1') then q21 <= mem10(CONV_INTEGER(addr21_tmp)); end if; if (ce22 = '1') then q22 <= mem11(CONV_INTEGER(addr22_tmp)); end if; if (ce23 = '1') then q23 <= mem11(CONV_INTEGER(addr23_tmp)); end if; if (ce24 = '1') then q24 <= mem12(CONV_INTEGER(addr24_tmp)); end if; if (ce25 = '1') then q25 <= mem12(CONV_INTEGER(addr25_tmp)); end if; if (ce26 = '1') then q26 <= mem13(CONV_INTEGER(addr26_tmp)); end if; if (ce27 = '1') then q27 <= mem13(CONV_INTEGER(addr27_tmp)); end if; if (ce28 = '1') then q28 <= mem14(CONV_INTEGER(addr28_tmp)); end if; if (ce29 = '1') then q29 <= mem14(CONV_INTEGER(addr29_tmp)); end if; if (ce30 = '1') then q30 <= mem15(CONV_INTEGER(addr30_tmp)); end if; if (ce31 = '1') then q31 <= mem15(CONV_INTEGER(addr31_tmp)); end if; if (ce32 = '1') then q32 <= mem16(CONV_INTEGER(addr32_tmp)); end if; if (ce33 = '1') then q33 <= mem16(CONV_INTEGER(addr33_tmp)); end if; if (ce34 = '1') then q34 <= mem17(CONV_INTEGER(addr34_tmp)); end if; if (ce35 = '1') then q35 <= mem17(CONV_INTEGER(addr35_tmp)); end if; if (ce36 = '1') then q36 <= mem18(CONV_INTEGER(addr36_tmp)); end if; if (ce37 = '1') then q37 <= mem18(CONV_INTEGER(addr37_tmp)); end if; if (ce38 = '1') then q38 <= mem19(CONV_INTEGER(addr38_tmp)); end if; if (ce39 = '1') then q39 <= mem19(CONV_INTEGER(addr39_tmp)); end if; if (ce40 = '1') then q40 <= mem20(CONV_INTEGER(addr40_tmp)); end if; if (ce41 = '1') then q41 <= mem20(CONV_INTEGER(addr41_tmp)); end if; if (ce42 = '1') then q42 <= mem21(CONV_INTEGER(addr42_tmp)); end if; if (ce43 = '1') then q43 <= mem21(CONV_INTEGER(addr43_tmp)); end if; if (ce44 = '1') then q44 <= mem22(CONV_INTEGER(addr44_tmp)); end if; if (ce45 = '1') then q45 <= mem22(CONV_INTEGER(addr45_tmp)); end if; if (ce46 = '1') then q46 <= mem23(CONV_INTEGER(addr46_tmp)); end if; if (ce47 = '1') then q47 <= mem23(CONV_INTEGER(addr47_tmp)); end if; if (ce48 = '1') then q48 <= mem24(CONV_INTEGER(addr48_tmp)); end if; if (ce49 = '1') then q49 <= mem24(CONV_INTEGER(addr49_tmp)); end if; if (ce50 = '1') then q50 <= mem25(CONV_INTEGER(addr50_tmp)); end if; if (ce51 = '1') then q51 <= mem25(CONV_INTEGER(addr51_tmp)); end if; if (ce52 = '1') then q52 <= mem26(CONV_INTEGER(addr52_tmp)); end if; if (ce53 = '1') then q53 <= mem26(CONV_INTEGER(addr53_tmp)); end if; if (ce54 = '1') then q54 <= mem27(CONV_INTEGER(addr54_tmp)); end if; if (ce55 = '1') then q55 <= mem27(CONV_INTEGER(addr55_tmp)); end if; if (ce56 = '1') then q56 <= mem28(CONV_INTEGER(addr56_tmp)); end if; if (ce57 = '1') then q57 <= mem28(CONV_INTEGER(addr57_tmp)); end if; if (ce58 = '1') then q58 <= mem29(CONV_INTEGER(addr58_tmp)); end if; if (ce59 = '1') then q59 <= mem29(CONV_INTEGER(addr59_tmp)); end if; if (ce60 = '1') then q60 <= mem30(CONV_INTEGER(addr60_tmp)); end if; if (ce61 = '1') then q61 <= mem30(CONV_INTEGER(addr61_tmp)); end if; if (ce62 = '1') then q62 <= mem31(CONV_INTEGER(addr62_tmp)); end if; if (ce63 = '1') then q63 <= mem31(CONV_INTEGER(addr63_tmp)); end if; if (ce64 = '1') then q64 <= mem32(CONV_INTEGER(addr64_tmp)); end if; if (ce65 = '1') then q65 <= mem32(CONV_INTEGER(addr65_tmp)); end if; if (ce66 = '1') then q66 <= mem33(CONV_INTEGER(addr66_tmp)); end if; if (ce67 = '1') then q67 <= mem33(CONV_INTEGER(addr67_tmp)); end if; if (ce68 = '1') then q68 <= mem34(CONV_INTEGER(addr68_tmp)); end if; if (ce69 = '1') then q69 <= mem34(CONV_INTEGER(addr69_tmp)); end if; if (ce70 = '1') then q70 <= mem35(CONV_INTEGER(addr70_tmp)); end if; if (ce71 = '1') then q71 <= mem35(CONV_INTEGER(addr71_tmp)); end if; if (ce72 = '1') then q72 <= mem36(CONV_INTEGER(addr72_tmp)); end if; if (ce73 = '1') then q73 <= mem36(CONV_INTEGER(addr73_tmp)); end if; if (ce74 = '1') then q74 <= mem37(CONV_INTEGER(addr74_tmp)); end if; if (ce75 = '1') then q75 <= mem37(CONV_INTEGER(addr75_tmp)); end if; if (ce76 = '1') then q76 <= mem38(CONV_INTEGER(addr76_tmp)); end if; if (ce77 = '1') then q77 <= mem38(CONV_INTEGER(addr77_tmp)); end if; if (ce78 = '1') then q78 <= mem39(CONV_INTEGER(addr78_tmp)); end if; if (ce79 = '1') then q79 <= mem39(CONV_INTEGER(addr79_tmp)); end if; if (ce80 = '1') then q80 <= mem40(CONV_INTEGER(addr80_tmp)); end if; if (ce81 = '1') then q81 <= mem40(CONV_INTEGER(addr81_tmp)); end if; if (ce82 = '1') then q82 <= mem41(CONV_INTEGER(addr82_tmp)); end if; if (ce83 = '1') then q83 <= mem41(CONV_INTEGER(addr83_tmp)); end if; if (ce84 = '1') then q84 <= mem42(CONV_INTEGER(addr84_tmp)); end if; if (ce85 = '1') then q85 <= mem42(CONV_INTEGER(addr85_tmp)); end if; if (ce86 = '1') then q86 <= mem43(CONV_INTEGER(addr86_tmp)); end if; if (ce87 = '1') then q87 <= mem43(CONV_INTEGER(addr87_tmp)); end if; if (ce88 = '1') then q88 <= mem44(CONV_INTEGER(addr88_tmp)); end if; if (ce89 = '1') then q89 <= mem44(CONV_INTEGER(addr89_tmp)); end if; if (ce90 = '1') then q90 <= mem45(CONV_INTEGER(addr90_tmp)); end if; if (ce91 = '1') then q91 <= mem45(CONV_INTEGER(addr91_tmp)); end if; if (ce92 = '1') then q92 <= mem46(CONV_INTEGER(addr92_tmp)); end if; if (ce93 = '1') then q93 <= mem46(CONV_INTEGER(addr93_tmp)); end if; if (ce94 = '1') then q94 <= mem47(CONV_INTEGER(addr94_tmp)); end if; if (ce95 = '1') then q95 <= mem47(CONV_INTEGER(addr95_tmp)); end if; if (ce96 = '1') then q96 <= mem48(CONV_INTEGER(addr96_tmp)); end if; if (ce97 = '1') then q97 <= mem48(CONV_INTEGER(addr97_tmp)); end if; if (ce98 = '1') then q98 <= mem49(CONV_INTEGER(addr98_tmp)); end if; if (ce99 = '1') then q99 <= mem49(CONV_INTEGER(addr99_tmp)); end if; if (ce100 = '1') then q100 <= mem50(CONV_INTEGER(addr100_tmp)); end if; if (ce101 = '1') then q101 <= mem50(CONV_INTEGER(addr101_tmp)); end if; if (ce102 = '1') then q102 <= mem51(CONV_INTEGER(addr102_tmp)); end if; if (ce103 = '1') then q103 <= mem51(CONV_INTEGER(addr103_tmp)); end if; if (ce104 = '1') then q104 <= mem52(CONV_INTEGER(addr104_tmp)); end if; if (ce105 = '1') then q105 <= mem52(CONV_INTEGER(addr105_tmp)); end if; if (ce106 = '1') then q106 <= mem53(CONV_INTEGER(addr106_tmp)); end if; if (ce107 = '1') then q107 <= mem53(CONV_INTEGER(addr107_tmp)); end if; if (ce108 = '1') then q108 <= mem54(CONV_INTEGER(addr108_tmp)); end if; if (ce109 = '1') then q109 <= mem54(CONV_INTEGER(addr109_tmp)); end if; if (ce110 = '1') then q110 <= mem55(CONV_INTEGER(addr110_tmp)); end if; if (ce111 = '1') then q111 <= mem55(CONV_INTEGER(addr111_tmp)); end if; if (ce112 = '1') then q112 <= mem56(CONV_INTEGER(addr112_tmp)); end if; if (ce113 = '1') then q113 <= mem56(CONV_INTEGER(addr113_tmp)); end if; if (ce114 = '1') then q114 <= mem57(CONV_INTEGER(addr114_tmp)); end if; if (ce115 = '1') then q115 <= mem57(CONV_INTEGER(addr115_tmp)); end if; if (ce116 = '1') then q116 <= mem58(CONV_INTEGER(addr116_tmp)); end if; if (ce117 = '1') then q117 <= mem58(CONV_INTEGER(addr117_tmp)); end if; if (ce118 = '1') then q118 <= mem59(CONV_INTEGER(addr118_tmp)); end if; if (ce119 = '1') then q119 <= mem59(CONV_INTEGER(addr119_tmp)); end if; if (ce120 = '1') then q120 <= mem60(CONV_INTEGER(addr120_tmp)); end if; if (ce121 = '1') then q121 <= mem60(CONV_INTEGER(addr121_tmp)); end if; if (ce122 = '1') then q122 <= mem61(CONV_INTEGER(addr122_tmp)); end if; if (ce123 = '1') then q123 <= mem61(CONV_INTEGER(addr123_tmp)); end if; if (ce124 = '1') then q124 <= mem62(CONV_INTEGER(addr124_tmp)); end if; if (ce125 = '1') then q125 <= mem62(CONV_INTEGER(addr125_tmp)); end if; if (ce126 = '1') then q126 <= mem63(CONV_INTEGER(addr126_tmp)); end if; if (ce127 = '1') then q127 <= mem63(CONV_INTEGER(addr127_tmp)); end if; if (ce128 = '1') then q128 <= mem64(CONV_INTEGER(addr128_tmp)); end if; if (ce129 = '1') then q129 <= mem64(CONV_INTEGER(addr129_tmp)); end if; if (ce130 = '1') then q130 <= mem65(CONV_INTEGER(addr130_tmp)); end if; if (ce131 = '1') then q131 <= mem65(CONV_INTEGER(addr131_tmp)); end if; if (ce132 = '1') then q132 <= mem66(CONV_INTEGER(addr132_tmp)); end if; if (ce133 = '1') then q133 <= mem66(CONV_INTEGER(addr133_tmp)); end if; if (ce134 = '1') then q134 <= mem67(CONV_INTEGER(addr134_tmp)); end if; if (ce135 = '1') then q135 <= mem67(CONV_INTEGER(addr135_tmp)); end if; if (ce136 = '1') then q136 <= mem68(CONV_INTEGER(addr136_tmp)); end if; if (ce137 = '1') then q137 <= mem68(CONV_INTEGER(addr137_tmp)); end if; if (ce138 = '1') then q138 <= mem69(CONV_INTEGER(addr138_tmp)); end if; if (ce139 = '1') then q139 <= mem69(CONV_INTEGER(addr139_tmp)); end if; if (ce140 = '1') then q140 <= mem70(CONV_INTEGER(addr140_tmp)); end if; if (ce141 = '1') then q141 <= mem70(CONV_INTEGER(addr141_tmp)); end if; if (ce142 = '1') then q142 <= mem71(CONV_INTEGER(addr142_tmp)); end if; if (ce143 = '1') then q143 <= mem71(CONV_INTEGER(addr143_tmp)); end if; if (ce144 = '1') then q144 <= mem72(CONV_INTEGER(addr144_tmp)); end if; if (ce145 = '1') then q145 <= mem72(CONV_INTEGER(addr145_tmp)); end if; if (ce146 = '1') then q146 <= mem73(CONV_INTEGER(addr146_tmp)); end if; if (ce147 = '1') then q147 <= mem73(CONV_INTEGER(addr147_tmp)); end if; if (ce148 = '1') then q148 <= mem74(CONV_INTEGER(addr148_tmp)); end if; if (ce149 = '1') then q149 <= mem74(CONV_INTEGER(addr149_tmp)); end if; if (ce150 = '1') then q150 <= mem75(CONV_INTEGER(addr150_tmp)); end if; if (ce151 = '1') then q151 <= mem75(CONV_INTEGER(addr151_tmp)); end if; if (ce152 = '1') then q152 <= mem76(CONV_INTEGER(addr152_tmp)); end if; if (ce153 = '1') then q153 <= mem76(CONV_INTEGER(addr153_tmp)); end if; if (ce154 = '1') then q154 <= mem77(CONV_INTEGER(addr154_tmp)); end if; if (ce155 = '1') then q155 <= mem77(CONV_INTEGER(addr155_tmp)); end if; if (ce156 = '1') then q156 <= mem78(CONV_INTEGER(addr156_tmp)); end if; if (ce157 = '1') then q157 <= mem78(CONV_INTEGER(addr157_tmp)); end if; if (ce158 = '1') then q158 <= mem79(CONV_INTEGER(addr158_tmp)); end if; if (ce159 = '1') then q159 <= mem79(CONV_INTEGER(addr159_tmp)); end if; if (ce160 = '1') then q160 <= mem80(CONV_INTEGER(addr160_tmp)); end if; if (ce161 = '1') then q161 <= mem80(CONV_INTEGER(addr161_tmp)); end if; if (ce162 = '1') then q162 <= mem81(CONV_INTEGER(addr162_tmp)); end if; if (ce163 = '1') then q163 <= mem81(CONV_INTEGER(addr163_tmp)); end if; if (ce164 = '1') then q164 <= mem82(CONV_INTEGER(addr164_tmp)); end if; if (ce165 = '1') then q165 <= mem82(CONV_INTEGER(addr165_tmp)); end if; if (ce166 = '1') then q166 <= mem83(CONV_INTEGER(addr166_tmp)); end if; if (ce167 = '1') then q167 <= mem83(CONV_INTEGER(addr167_tmp)); end if; if (ce168 = '1') then q168 <= mem84(CONV_INTEGER(addr168_tmp)); end if; if (ce169 = '1') then q169 <= mem84(CONV_INTEGER(addr169_tmp)); end if; if (ce170 = '1') then q170 <= mem85(CONV_INTEGER(addr170_tmp)); end if; if (ce171 = '1') then q171 <= mem85(CONV_INTEGER(addr171_tmp)); end if; if (ce172 = '1') then q172 <= mem86(CONV_INTEGER(addr172_tmp)); end if; if (ce173 = '1') then q173 <= mem86(CONV_INTEGER(addr173_tmp)); end if; if (ce174 = '1') then q174 <= mem87(CONV_INTEGER(addr174_tmp)); end if; if (ce175 = '1') then q175 <= mem87(CONV_INTEGER(addr175_tmp)); end if; if (ce176 = '1') then q176 <= mem88(CONV_INTEGER(addr176_tmp)); end if; if (ce177 = '1') then q177 <= mem88(CONV_INTEGER(addr177_tmp)); end if; if (ce178 = '1') then q178 <= mem89(CONV_INTEGER(addr178_tmp)); end if; if (ce179 = '1') then q179 <= mem89(CONV_INTEGER(addr179_tmp)); end if; if (ce180 = '1') then q180 <= mem90(CONV_INTEGER(addr180_tmp)); end if; if (ce181 = '1') then q181 <= mem90(CONV_INTEGER(addr181_tmp)); end if; if (ce182 = '1') then q182 <= mem91(CONV_INTEGER(addr182_tmp)); end if; if (ce183 = '1') then q183 <= mem91(CONV_INTEGER(addr183_tmp)); end if; if (ce184 = '1') then q184 <= mem92(CONV_INTEGER(addr184_tmp)); end if; if (ce185 = '1') then q185 <= mem92(CONV_INTEGER(addr185_tmp)); end if; if (ce186 = '1') then q186 <= mem93(CONV_INTEGER(addr186_tmp)); end if; if (ce187 = '1') then q187 <= mem93(CONV_INTEGER(addr187_tmp)); end if; if (ce188 = '1') then q188 <= mem94(CONV_INTEGER(addr188_tmp)); end if; if (ce189 = '1') then q189 <= mem94(CONV_INTEGER(addr189_tmp)); end if; if (ce190 = '1') then q190 <= mem95(CONV_INTEGER(addr190_tmp)); end if; if (ce191 = '1') then q191 <= mem95(CONV_INTEGER(addr191_tmp)); end if; if (ce192 = '1') then q192 <= mem96(CONV_INTEGER(addr192_tmp)); end if; if (ce193 = '1') then q193 <= mem96(CONV_INTEGER(addr193_tmp)); end if; if (ce194 = '1') then q194 <= mem97(CONV_INTEGER(addr194_tmp)); end if; if (ce195 = '1') then q195 <= mem97(CONV_INTEGER(addr195_tmp)); end if; if (ce196 = '1') then q196 <= mem98(CONV_INTEGER(addr196_tmp)); end if; if (ce197 = '1') then q197 <= mem98(CONV_INTEGER(addr197_tmp)); end if; if (ce198 = '1') then q198 <= mem99(CONV_INTEGER(addr198_tmp)); end if; if (ce199 = '1') then q199 <= mem99(CONV_INTEGER(addr199_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity aestest_sboxes is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 256; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce2 : IN STD_LOGIC; q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address3 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce3 : IN STD_LOGIC; q3 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address4 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce4 : IN STD_LOGIC; q4 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address5 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce5 : IN STD_LOGIC; q5 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address6 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce6 : IN STD_LOGIC; q6 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address7 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce7 : IN STD_LOGIC; q7 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address8 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce8 : IN STD_LOGIC; q8 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address9 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce9 : IN STD_LOGIC; q9 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address10 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce10 : IN STD_LOGIC; q10 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address11 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce11 : IN STD_LOGIC; q11 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address12 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce12 : IN STD_LOGIC; q12 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address13 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce13 : IN STD_LOGIC; q13 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address14 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce14 : IN STD_LOGIC; q14 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address15 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce15 : IN STD_LOGIC; q15 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address16 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce16 : IN STD_LOGIC; q16 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address17 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce17 : IN STD_LOGIC; q17 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address18 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce18 : IN STD_LOGIC; q18 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address19 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce19 : IN STD_LOGIC; q19 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address20 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce20 : IN STD_LOGIC; q20 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address21 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce21 : IN STD_LOGIC; q21 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address22 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce22 : IN STD_LOGIC; q22 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address23 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce23 : IN STD_LOGIC; q23 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address24 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce24 : IN STD_LOGIC; q24 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address25 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce25 : IN STD_LOGIC; q25 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address26 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce26 : IN STD_LOGIC; q26 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address27 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce27 : IN STD_LOGIC; q27 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address28 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce28 : IN STD_LOGIC; q28 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address29 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce29 : IN STD_LOGIC; q29 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address30 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce30 : IN STD_LOGIC; q30 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address31 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce31 : IN STD_LOGIC; q31 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address32 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce32 : IN STD_LOGIC; q32 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address33 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce33 : IN STD_LOGIC; q33 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address34 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce34 : IN STD_LOGIC; q34 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address35 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce35 : IN STD_LOGIC; q35 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address36 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce36 : IN STD_LOGIC; q36 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address37 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce37 : IN STD_LOGIC; q37 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address38 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce38 : IN STD_LOGIC; q38 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address39 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce39 : IN STD_LOGIC; q39 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address40 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce40 : IN STD_LOGIC; q40 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address41 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce41 : IN STD_LOGIC; q41 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address42 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce42 : IN STD_LOGIC; q42 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address43 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce43 : IN STD_LOGIC; q43 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address44 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce44 : IN STD_LOGIC; q44 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address45 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce45 : IN STD_LOGIC; q45 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address46 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce46 : IN STD_LOGIC; q46 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address47 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce47 : IN STD_LOGIC; q47 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address48 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce48 : IN STD_LOGIC; q48 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address49 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce49 : IN STD_LOGIC; q49 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address50 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce50 : IN STD_LOGIC; q50 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address51 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce51 : IN STD_LOGIC; q51 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address52 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce52 : IN STD_LOGIC; q52 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address53 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce53 : IN STD_LOGIC; q53 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address54 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce54 : IN STD_LOGIC; q54 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address55 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce55 : IN STD_LOGIC; q55 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address56 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce56 : IN STD_LOGIC; q56 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address57 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce57 : IN STD_LOGIC; q57 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address58 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce58 : IN STD_LOGIC; q58 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address59 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce59 : IN STD_LOGIC; q59 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address60 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce60 : IN STD_LOGIC; q60 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address61 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce61 : IN STD_LOGIC; q61 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address62 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce62 : IN STD_LOGIC; q62 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address63 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce63 : IN STD_LOGIC; q63 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address64 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce64 : IN STD_LOGIC; q64 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address65 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce65 : IN STD_LOGIC; q65 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address66 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce66 : IN STD_LOGIC; q66 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address67 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce67 : IN STD_LOGIC; q67 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address68 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce68 : IN STD_LOGIC; q68 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address69 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce69 : IN STD_LOGIC; q69 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address70 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce70 : IN STD_LOGIC; q70 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address71 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce71 : IN STD_LOGIC; q71 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address72 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce72 : IN STD_LOGIC; q72 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address73 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce73 : IN STD_LOGIC; q73 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address74 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce74 : IN STD_LOGIC; q74 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address75 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce75 : IN STD_LOGIC; q75 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address76 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce76 : IN STD_LOGIC; q76 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address77 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce77 : IN STD_LOGIC; q77 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address78 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce78 : IN STD_LOGIC; q78 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address79 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce79 : IN STD_LOGIC; q79 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address80 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce80 : IN STD_LOGIC; q80 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address81 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce81 : IN STD_LOGIC; q81 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address82 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce82 : IN STD_LOGIC; q82 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address83 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce83 : IN STD_LOGIC; q83 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address84 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce84 : IN STD_LOGIC; q84 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address85 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce85 : IN STD_LOGIC; q85 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address86 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce86 : IN STD_LOGIC; q86 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address87 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce87 : IN STD_LOGIC; q87 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address88 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce88 : IN STD_LOGIC; q88 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address89 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce89 : IN STD_LOGIC; q89 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address90 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce90 : IN STD_LOGIC; q90 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address91 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce91 : IN STD_LOGIC; q91 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address92 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce92 : IN STD_LOGIC; q92 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address93 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce93 : IN STD_LOGIC; q93 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address94 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce94 : IN STD_LOGIC; q94 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address95 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce95 : IN STD_LOGIC; q95 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address96 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce96 : IN STD_LOGIC; q96 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address97 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce97 : IN STD_LOGIC; q97 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address98 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce98 : IN STD_LOGIC; q98 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address99 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce99 : IN STD_LOGIC; q99 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address100 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce100 : IN STD_LOGIC; q100 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address101 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce101 : IN STD_LOGIC; q101 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address102 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce102 : IN STD_LOGIC; q102 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address103 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce103 : IN STD_LOGIC; q103 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address104 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce104 : IN STD_LOGIC; q104 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address105 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce105 : IN STD_LOGIC; q105 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address106 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce106 : IN STD_LOGIC; q106 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address107 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce107 : IN STD_LOGIC; q107 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address108 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce108 : IN STD_LOGIC; q108 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address109 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce109 : IN STD_LOGIC; q109 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address110 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce110 : IN STD_LOGIC; q110 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address111 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce111 : IN STD_LOGIC; q111 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address112 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce112 : IN STD_LOGIC; q112 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address113 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce113 : IN STD_LOGIC; q113 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address114 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce114 : IN STD_LOGIC; q114 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address115 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce115 : IN STD_LOGIC; q115 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address116 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce116 : IN STD_LOGIC; q116 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address117 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce117 : IN STD_LOGIC; q117 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address118 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce118 : IN STD_LOGIC; q118 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address119 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce119 : IN STD_LOGIC; q119 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address120 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce120 : IN STD_LOGIC; q120 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address121 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce121 : IN STD_LOGIC; q121 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address122 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce122 : IN STD_LOGIC; q122 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address123 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce123 : IN STD_LOGIC; q123 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address124 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce124 : IN STD_LOGIC; q124 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address125 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce125 : IN STD_LOGIC; q125 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address126 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce126 : IN STD_LOGIC; q126 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address127 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce127 : IN STD_LOGIC; q127 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address128 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce128 : IN STD_LOGIC; q128 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address129 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce129 : IN STD_LOGIC; q129 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address130 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce130 : IN STD_LOGIC; q130 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address131 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce131 : IN STD_LOGIC; q131 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address132 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce132 : IN STD_LOGIC; q132 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address133 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce133 : IN STD_LOGIC; q133 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address134 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce134 : IN STD_LOGIC; q134 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address135 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce135 : IN STD_LOGIC; q135 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address136 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce136 : IN STD_LOGIC; q136 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address137 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce137 : IN STD_LOGIC; q137 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address138 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce138 : IN STD_LOGIC; q138 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address139 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce139 : IN STD_LOGIC; q139 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address140 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce140 : IN STD_LOGIC; q140 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address141 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce141 : IN STD_LOGIC; q141 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address142 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce142 : IN STD_LOGIC; q142 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address143 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce143 : IN STD_LOGIC; q143 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address144 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce144 : IN STD_LOGIC; q144 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address145 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce145 : IN STD_LOGIC; q145 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address146 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce146 : IN STD_LOGIC; q146 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address147 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce147 : IN STD_LOGIC; q147 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address148 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce148 : IN STD_LOGIC; q148 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address149 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce149 : IN STD_LOGIC; q149 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address150 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce150 : IN STD_LOGIC; q150 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address151 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce151 : IN STD_LOGIC; q151 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address152 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce152 : IN STD_LOGIC; q152 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address153 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce153 : IN STD_LOGIC; q153 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address154 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce154 : IN STD_LOGIC; q154 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address155 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce155 : IN STD_LOGIC; q155 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address156 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce156 : IN STD_LOGIC; q156 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address157 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce157 : IN STD_LOGIC; q157 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address158 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce158 : IN STD_LOGIC; q158 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address159 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce159 : IN STD_LOGIC; q159 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address160 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce160 : IN STD_LOGIC; q160 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address161 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce161 : IN STD_LOGIC; q161 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address162 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce162 : IN STD_LOGIC; q162 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address163 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce163 : IN STD_LOGIC; q163 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address164 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce164 : IN STD_LOGIC; q164 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address165 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce165 : IN STD_LOGIC; q165 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address166 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce166 : IN STD_LOGIC; q166 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address167 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce167 : IN STD_LOGIC; q167 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address168 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce168 : IN STD_LOGIC; q168 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address169 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce169 : IN STD_LOGIC; q169 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address170 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce170 : IN STD_LOGIC; q170 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address171 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce171 : IN STD_LOGIC; q171 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address172 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce172 : IN STD_LOGIC; q172 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address173 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce173 : IN STD_LOGIC; q173 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address174 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce174 : IN STD_LOGIC; q174 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address175 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce175 : IN STD_LOGIC; q175 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address176 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce176 : IN STD_LOGIC; q176 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address177 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce177 : IN STD_LOGIC; q177 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address178 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce178 : IN STD_LOGIC; q178 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address179 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce179 : IN STD_LOGIC; q179 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address180 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce180 : IN STD_LOGIC; q180 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address181 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce181 : IN STD_LOGIC; q181 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address182 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce182 : IN STD_LOGIC; q182 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address183 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce183 : IN STD_LOGIC; q183 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address184 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce184 : IN STD_LOGIC; q184 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address185 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce185 : IN STD_LOGIC; q185 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address186 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce186 : IN STD_LOGIC; q186 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address187 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce187 : IN STD_LOGIC; q187 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address188 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce188 : IN STD_LOGIC; q188 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address189 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce189 : IN STD_LOGIC; q189 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address190 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce190 : IN STD_LOGIC; q190 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address191 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce191 : IN STD_LOGIC; q191 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address192 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce192 : IN STD_LOGIC; q192 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address193 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce193 : IN STD_LOGIC; q193 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address194 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce194 : IN STD_LOGIC; q194 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address195 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce195 : IN STD_LOGIC; q195 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address196 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce196 : IN STD_LOGIC; q196 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address197 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce197 : IN STD_LOGIC; q197 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address198 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce198 : IN STD_LOGIC; q198 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address199 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce199 : IN STD_LOGIC; q199 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of aestest_sboxes is component aestest_sboxes_rom is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR; addr2 : IN STD_LOGIC_VECTOR; ce2 : IN STD_LOGIC; q2 : OUT STD_LOGIC_VECTOR; addr3 : IN STD_LOGIC_VECTOR; ce3 : IN STD_LOGIC; q3 : OUT STD_LOGIC_VECTOR; addr4 : IN STD_LOGIC_VECTOR; ce4 : IN STD_LOGIC; q4 : OUT STD_LOGIC_VECTOR; addr5 : IN STD_LOGIC_VECTOR; ce5 : IN STD_LOGIC; q5 : OUT STD_LOGIC_VECTOR; addr6 : IN STD_LOGIC_VECTOR; ce6 : IN STD_LOGIC; q6 : OUT STD_LOGIC_VECTOR; addr7 : IN STD_LOGIC_VECTOR; ce7 : IN STD_LOGIC; q7 : OUT STD_LOGIC_VECTOR; addr8 : IN STD_LOGIC_VECTOR; ce8 : IN STD_LOGIC; q8 : OUT STD_LOGIC_VECTOR; addr9 : IN STD_LOGIC_VECTOR; ce9 : IN STD_LOGIC; q9 : OUT STD_LOGIC_VECTOR; addr10 : IN STD_LOGIC_VECTOR; ce10 : IN STD_LOGIC; q10 : OUT STD_LOGIC_VECTOR; addr11 : IN STD_LOGIC_VECTOR; ce11 : IN STD_LOGIC; q11 : OUT STD_LOGIC_VECTOR; addr12 : IN STD_LOGIC_VECTOR; ce12 : IN STD_LOGIC; q12 : OUT STD_LOGIC_VECTOR; addr13 : IN STD_LOGIC_VECTOR; ce13 : IN STD_LOGIC; q13 : OUT STD_LOGIC_VECTOR; addr14 : IN STD_LOGIC_VECTOR; ce14 : IN STD_LOGIC; q14 : OUT STD_LOGIC_VECTOR; addr15 : IN STD_LOGIC_VECTOR; ce15 : IN STD_LOGIC; q15 : OUT STD_LOGIC_VECTOR; addr16 : IN STD_LOGIC_VECTOR; ce16 : IN STD_LOGIC; q16 : OUT STD_LOGIC_VECTOR; addr17 : IN STD_LOGIC_VECTOR; ce17 : IN STD_LOGIC; q17 : OUT STD_LOGIC_VECTOR; addr18 : IN STD_LOGIC_VECTOR; ce18 : IN STD_LOGIC; q18 : OUT STD_LOGIC_VECTOR; addr19 : IN STD_LOGIC_VECTOR; ce19 : IN STD_LOGIC; q19 : OUT STD_LOGIC_VECTOR; addr20 : IN STD_LOGIC_VECTOR; ce20 : IN STD_LOGIC; q20 : OUT STD_LOGIC_VECTOR; addr21 : IN STD_LOGIC_VECTOR; ce21 : IN STD_LOGIC; q21 : OUT STD_LOGIC_VECTOR; addr22 : IN STD_LOGIC_VECTOR; ce22 : IN STD_LOGIC; q22 : OUT STD_LOGIC_VECTOR; addr23 : IN STD_LOGIC_VECTOR; ce23 : IN STD_LOGIC; q23 : OUT STD_LOGIC_VECTOR; addr24 : IN STD_LOGIC_VECTOR; ce24 : IN STD_LOGIC; q24 : OUT STD_LOGIC_VECTOR; addr25 : IN STD_LOGIC_VECTOR; ce25 : IN STD_LOGIC; q25 : OUT STD_LOGIC_VECTOR; addr26 : IN STD_LOGIC_VECTOR; ce26 : IN STD_LOGIC; q26 : OUT STD_LOGIC_VECTOR; addr27 : IN STD_LOGIC_VECTOR; ce27 : IN STD_LOGIC; q27 : OUT STD_LOGIC_VECTOR; addr28 : IN STD_LOGIC_VECTOR; ce28 : IN STD_LOGIC; q28 : OUT STD_LOGIC_VECTOR; addr29 : IN STD_LOGIC_VECTOR; ce29 : IN STD_LOGIC; q29 : OUT STD_LOGIC_VECTOR; addr30 : IN STD_LOGIC_VECTOR; ce30 : IN STD_LOGIC; q30 : OUT STD_LOGIC_VECTOR; addr31 : IN STD_LOGIC_VECTOR; ce31 : IN STD_LOGIC; q31 : OUT STD_LOGIC_VECTOR; addr32 : IN STD_LOGIC_VECTOR; ce32 : IN STD_LOGIC; q32 : OUT STD_LOGIC_VECTOR; addr33 : IN STD_LOGIC_VECTOR; ce33 : IN STD_LOGIC; q33 : OUT STD_LOGIC_VECTOR; addr34 : IN STD_LOGIC_VECTOR; ce34 : IN STD_LOGIC; q34 : OUT STD_LOGIC_VECTOR; addr35 : IN STD_LOGIC_VECTOR; ce35 : IN STD_LOGIC; q35 : OUT STD_LOGIC_VECTOR; addr36 : IN STD_LOGIC_VECTOR; ce36 : IN STD_LOGIC; q36 : OUT STD_LOGIC_VECTOR; addr37 : IN STD_LOGIC_VECTOR; ce37 : IN STD_LOGIC; q37 : OUT STD_LOGIC_VECTOR; addr38 : IN STD_LOGIC_VECTOR; ce38 : IN STD_LOGIC; q38 : OUT STD_LOGIC_VECTOR; addr39 : IN STD_LOGIC_VECTOR; ce39 : IN STD_LOGIC; q39 : OUT STD_LOGIC_VECTOR; addr40 : IN STD_LOGIC_VECTOR; ce40 : IN STD_LOGIC; q40 : OUT STD_LOGIC_VECTOR; addr41 : IN STD_LOGIC_VECTOR; ce41 : IN STD_LOGIC; q41 : OUT STD_LOGIC_VECTOR; addr42 : IN STD_LOGIC_VECTOR; ce42 : IN STD_LOGIC; q42 : OUT STD_LOGIC_VECTOR; addr43 : IN STD_LOGIC_VECTOR; ce43 : IN STD_LOGIC; q43 : OUT STD_LOGIC_VECTOR; addr44 : IN STD_LOGIC_VECTOR; ce44 : IN STD_LOGIC; q44 : OUT STD_LOGIC_VECTOR; addr45 : IN STD_LOGIC_VECTOR; ce45 : IN STD_LOGIC; q45 : OUT STD_LOGIC_VECTOR; addr46 : IN STD_LOGIC_VECTOR; ce46 : IN STD_LOGIC; q46 : OUT STD_LOGIC_VECTOR; addr47 : IN STD_LOGIC_VECTOR; ce47 : IN STD_LOGIC; q47 : OUT STD_LOGIC_VECTOR; addr48 : IN STD_LOGIC_VECTOR; ce48 : IN STD_LOGIC; q48 : OUT STD_LOGIC_VECTOR; addr49 : IN STD_LOGIC_VECTOR; ce49 : IN STD_LOGIC; q49 : OUT STD_LOGIC_VECTOR; addr50 : IN STD_LOGIC_VECTOR; ce50 : IN STD_LOGIC; q50 : OUT STD_LOGIC_VECTOR; addr51 : IN STD_LOGIC_VECTOR; ce51 : IN STD_LOGIC; q51 : OUT STD_LOGIC_VECTOR; addr52 : IN STD_LOGIC_VECTOR; ce52 : IN STD_LOGIC; q52 : OUT STD_LOGIC_VECTOR; addr53 : IN STD_LOGIC_VECTOR; ce53 : IN STD_LOGIC; q53 : OUT STD_LOGIC_VECTOR; addr54 : IN STD_LOGIC_VECTOR; ce54 : IN STD_LOGIC; q54 : OUT STD_LOGIC_VECTOR; addr55 : IN STD_LOGIC_VECTOR; ce55 : IN STD_LOGIC; q55 : OUT STD_LOGIC_VECTOR; addr56 : IN STD_LOGIC_VECTOR; ce56 : IN STD_LOGIC; q56 : OUT STD_LOGIC_VECTOR; addr57 : IN STD_LOGIC_VECTOR; ce57 : IN STD_LOGIC; q57 : OUT STD_LOGIC_VECTOR; addr58 : IN STD_LOGIC_VECTOR; ce58 : IN STD_LOGIC; q58 : OUT STD_LOGIC_VECTOR; addr59 : IN STD_LOGIC_VECTOR; ce59 : IN STD_LOGIC; q59 : OUT STD_LOGIC_VECTOR; addr60 : IN STD_LOGIC_VECTOR; ce60 : IN STD_LOGIC; q60 : OUT STD_LOGIC_VECTOR; addr61 : IN STD_LOGIC_VECTOR; ce61 : IN STD_LOGIC; q61 : OUT STD_LOGIC_VECTOR; addr62 : IN STD_LOGIC_VECTOR; ce62 : IN STD_LOGIC; q62 : OUT STD_LOGIC_VECTOR; addr63 : IN STD_LOGIC_VECTOR; ce63 : IN STD_LOGIC; q63 : OUT STD_LOGIC_VECTOR; addr64 : IN STD_LOGIC_VECTOR; ce64 : IN STD_LOGIC; q64 : OUT STD_LOGIC_VECTOR; addr65 : IN STD_LOGIC_VECTOR; ce65 : IN STD_LOGIC; q65 : OUT STD_LOGIC_VECTOR; addr66 : IN STD_LOGIC_VECTOR; ce66 : IN STD_LOGIC; q66 : OUT STD_LOGIC_VECTOR; addr67 : IN STD_LOGIC_VECTOR; ce67 : IN STD_LOGIC; q67 : OUT STD_LOGIC_VECTOR; addr68 : IN STD_LOGIC_VECTOR; ce68 : IN STD_LOGIC; q68 : OUT STD_LOGIC_VECTOR; addr69 : IN STD_LOGIC_VECTOR; ce69 : IN STD_LOGIC; q69 : OUT STD_LOGIC_VECTOR; addr70 : IN STD_LOGIC_VECTOR; ce70 : IN STD_LOGIC; q70 : OUT STD_LOGIC_VECTOR; addr71 : IN STD_LOGIC_VECTOR; ce71 : IN STD_LOGIC; q71 : OUT STD_LOGIC_VECTOR; addr72 : IN STD_LOGIC_VECTOR; ce72 : IN STD_LOGIC; q72 : OUT STD_LOGIC_VECTOR; addr73 : IN STD_LOGIC_VECTOR; ce73 : IN STD_LOGIC; q73 : OUT STD_LOGIC_VECTOR; addr74 : IN STD_LOGIC_VECTOR; ce74 : IN STD_LOGIC; q74 : OUT STD_LOGIC_VECTOR; addr75 : IN STD_LOGIC_VECTOR; ce75 : IN STD_LOGIC; q75 : OUT STD_LOGIC_VECTOR; addr76 : IN STD_LOGIC_VECTOR; ce76 : IN STD_LOGIC; q76 : OUT STD_LOGIC_VECTOR; addr77 : IN STD_LOGIC_VECTOR; ce77 : IN STD_LOGIC; q77 : OUT STD_LOGIC_VECTOR; addr78 : IN STD_LOGIC_VECTOR; ce78 : IN STD_LOGIC; q78 : OUT STD_LOGIC_VECTOR; addr79 : IN STD_LOGIC_VECTOR; ce79 : IN STD_LOGIC; q79 : OUT STD_LOGIC_VECTOR; addr80 : IN STD_LOGIC_VECTOR; ce80 : IN STD_LOGIC; q80 : OUT STD_LOGIC_VECTOR; addr81 : IN STD_LOGIC_VECTOR; ce81 : IN STD_LOGIC; q81 : OUT STD_LOGIC_VECTOR; addr82 : IN STD_LOGIC_VECTOR; ce82 : IN STD_LOGIC; q82 : OUT STD_LOGIC_VECTOR; addr83 : IN STD_LOGIC_VECTOR; ce83 : IN STD_LOGIC; q83 : OUT STD_LOGIC_VECTOR; addr84 : IN STD_LOGIC_VECTOR; ce84 : IN STD_LOGIC; q84 : OUT STD_LOGIC_VECTOR; addr85 : IN STD_LOGIC_VECTOR; ce85 : IN STD_LOGIC; q85 : OUT STD_LOGIC_VECTOR; addr86 : IN STD_LOGIC_VECTOR; ce86 : IN STD_LOGIC; q86 : OUT STD_LOGIC_VECTOR; addr87 : IN STD_LOGIC_VECTOR; ce87 : IN STD_LOGIC; q87 : OUT STD_LOGIC_VECTOR; addr88 : IN STD_LOGIC_VECTOR; ce88 : IN STD_LOGIC; q88 : OUT STD_LOGIC_VECTOR; addr89 : IN STD_LOGIC_VECTOR; ce89 : IN STD_LOGIC; q89 : OUT STD_LOGIC_VECTOR; addr90 : IN STD_LOGIC_VECTOR; ce90 : IN STD_LOGIC; q90 : OUT STD_LOGIC_VECTOR; addr91 : IN STD_LOGIC_VECTOR; ce91 : IN STD_LOGIC; q91 : OUT STD_LOGIC_VECTOR; addr92 : IN STD_LOGIC_VECTOR; ce92 : IN STD_LOGIC; q92 : OUT STD_LOGIC_VECTOR; addr93 : IN STD_LOGIC_VECTOR; ce93 : IN STD_LOGIC; q93 : OUT STD_LOGIC_VECTOR; addr94 : IN STD_LOGIC_VECTOR; ce94 : IN STD_LOGIC; q94 : OUT STD_LOGIC_VECTOR; addr95 : IN STD_LOGIC_VECTOR; ce95 : IN STD_LOGIC; q95 : OUT STD_LOGIC_VECTOR; addr96 : IN STD_LOGIC_VECTOR; ce96 : IN STD_LOGIC; q96 : OUT STD_LOGIC_VECTOR; addr97 : IN STD_LOGIC_VECTOR; ce97 : IN STD_LOGIC; q97 : OUT STD_LOGIC_VECTOR; addr98 : IN STD_LOGIC_VECTOR; ce98 : IN STD_LOGIC; q98 : OUT STD_LOGIC_VECTOR; addr99 : IN STD_LOGIC_VECTOR; ce99 : IN STD_LOGIC; q99 : OUT STD_LOGIC_VECTOR; addr100 : IN STD_LOGIC_VECTOR; ce100 : IN STD_LOGIC; q100 : OUT STD_LOGIC_VECTOR; addr101 : IN STD_LOGIC_VECTOR; ce101 : IN STD_LOGIC; q101 : OUT STD_LOGIC_VECTOR; addr102 : IN STD_LOGIC_VECTOR; ce102 : IN STD_LOGIC; q102 : OUT STD_LOGIC_VECTOR; addr103 : IN STD_LOGIC_VECTOR; ce103 : IN STD_LOGIC; q103 : OUT STD_LOGIC_VECTOR; addr104 : IN STD_LOGIC_VECTOR; ce104 : IN STD_LOGIC; q104 : OUT STD_LOGIC_VECTOR; addr105 : IN STD_LOGIC_VECTOR; ce105 : IN STD_LOGIC; q105 : OUT STD_LOGIC_VECTOR; addr106 : IN STD_LOGIC_VECTOR; ce106 : IN STD_LOGIC; q106 : OUT STD_LOGIC_VECTOR; addr107 : IN STD_LOGIC_VECTOR; ce107 : IN STD_LOGIC; q107 : OUT STD_LOGIC_VECTOR; addr108 : IN STD_LOGIC_VECTOR; ce108 : IN STD_LOGIC; q108 : OUT STD_LOGIC_VECTOR; addr109 : IN STD_LOGIC_VECTOR; ce109 : IN STD_LOGIC; q109 : OUT STD_LOGIC_VECTOR; addr110 : IN STD_LOGIC_VECTOR; ce110 : IN STD_LOGIC; q110 : OUT STD_LOGIC_VECTOR; addr111 : IN STD_LOGIC_VECTOR; ce111 : IN STD_LOGIC; q111 : OUT STD_LOGIC_VECTOR; addr112 : IN STD_LOGIC_VECTOR; ce112 : IN STD_LOGIC; q112 : OUT STD_LOGIC_VECTOR; addr113 : IN STD_LOGIC_VECTOR; ce113 : IN STD_LOGIC; q113 : OUT STD_LOGIC_VECTOR; addr114 : IN STD_LOGIC_VECTOR; ce114 : IN STD_LOGIC; q114 : OUT STD_LOGIC_VECTOR; addr115 : IN STD_LOGIC_VECTOR; ce115 : IN STD_LOGIC; q115 : OUT STD_LOGIC_VECTOR; addr116 : IN STD_LOGIC_VECTOR; ce116 : IN STD_LOGIC; q116 : OUT STD_LOGIC_VECTOR; addr117 : IN STD_LOGIC_VECTOR; ce117 : IN STD_LOGIC; q117 : OUT STD_LOGIC_VECTOR; addr118 : IN STD_LOGIC_VECTOR; ce118 : IN STD_LOGIC; q118 : OUT STD_LOGIC_VECTOR; addr119 : IN STD_LOGIC_VECTOR; ce119 : IN STD_LOGIC; q119 : OUT STD_LOGIC_VECTOR; addr120 : IN STD_LOGIC_VECTOR; ce120 : IN STD_LOGIC; q120 : OUT STD_LOGIC_VECTOR; addr121 : IN STD_LOGIC_VECTOR; ce121 : IN STD_LOGIC; q121 : OUT STD_LOGIC_VECTOR; addr122 : IN STD_LOGIC_VECTOR; ce122 : IN STD_LOGIC; q122 : OUT STD_LOGIC_VECTOR; addr123 : IN STD_LOGIC_VECTOR; ce123 : IN STD_LOGIC; q123 : OUT STD_LOGIC_VECTOR; addr124 : IN STD_LOGIC_VECTOR; ce124 : IN STD_LOGIC; q124 : OUT STD_LOGIC_VECTOR; addr125 : IN STD_LOGIC_VECTOR; ce125 : IN STD_LOGIC; q125 : OUT STD_LOGIC_VECTOR; addr126 : IN STD_LOGIC_VECTOR; ce126 : IN STD_LOGIC; q126 : OUT STD_LOGIC_VECTOR; addr127 : IN STD_LOGIC_VECTOR; ce127 : IN STD_LOGIC; q127 : OUT STD_LOGIC_VECTOR; addr128 : IN STD_LOGIC_VECTOR; ce128 : IN STD_LOGIC; q128 : OUT STD_LOGIC_VECTOR; addr129 : IN STD_LOGIC_VECTOR; ce129 : IN STD_LOGIC; q129 : OUT STD_LOGIC_VECTOR; addr130 : IN STD_LOGIC_VECTOR; ce130 : IN STD_LOGIC; q130 : OUT STD_LOGIC_VECTOR; addr131 : IN STD_LOGIC_VECTOR; ce131 : IN STD_LOGIC; q131 : OUT STD_LOGIC_VECTOR; addr132 : IN STD_LOGIC_VECTOR; ce132 : IN STD_LOGIC; q132 : OUT STD_LOGIC_VECTOR; addr133 : IN STD_LOGIC_VECTOR; ce133 : IN STD_LOGIC; q133 : OUT STD_LOGIC_VECTOR; addr134 : IN STD_LOGIC_VECTOR; ce134 : IN STD_LOGIC; q134 : OUT STD_LOGIC_VECTOR; addr135 : IN STD_LOGIC_VECTOR; ce135 : IN STD_LOGIC; q135 : OUT STD_LOGIC_VECTOR; addr136 : IN STD_LOGIC_VECTOR; ce136 : IN STD_LOGIC; q136 : OUT STD_LOGIC_VECTOR; addr137 : IN STD_LOGIC_VECTOR; ce137 : IN STD_LOGIC; q137 : OUT STD_LOGIC_VECTOR; addr138 : IN STD_LOGIC_VECTOR; ce138 : IN STD_LOGIC; q138 : OUT STD_LOGIC_VECTOR; addr139 : IN STD_LOGIC_VECTOR; ce139 : IN STD_LOGIC; q139 : OUT STD_LOGIC_VECTOR; addr140 : IN STD_LOGIC_VECTOR; ce140 : IN STD_LOGIC; q140 : OUT STD_LOGIC_VECTOR; addr141 : IN STD_LOGIC_VECTOR; ce141 : IN STD_LOGIC; q141 : OUT STD_LOGIC_VECTOR; addr142 : IN STD_LOGIC_VECTOR; ce142 : IN STD_LOGIC; q142 : OUT STD_LOGIC_VECTOR; addr143 : IN STD_LOGIC_VECTOR; ce143 : IN STD_LOGIC; q143 : OUT STD_LOGIC_VECTOR; addr144 : IN STD_LOGIC_VECTOR; ce144 : IN STD_LOGIC; q144 : OUT STD_LOGIC_VECTOR; addr145 : IN STD_LOGIC_VECTOR; ce145 : IN STD_LOGIC; q145 : OUT STD_LOGIC_VECTOR; addr146 : IN STD_LOGIC_VECTOR; ce146 : IN STD_LOGIC; q146 : OUT STD_LOGIC_VECTOR; addr147 : IN STD_LOGIC_VECTOR; ce147 : IN STD_LOGIC; q147 : OUT STD_LOGIC_VECTOR; addr148 : IN STD_LOGIC_VECTOR; ce148 : IN STD_LOGIC; q148 : OUT STD_LOGIC_VECTOR; addr149 : IN STD_LOGIC_VECTOR; ce149 : IN STD_LOGIC; q149 : OUT STD_LOGIC_VECTOR; addr150 : IN STD_LOGIC_VECTOR; ce150 : IN STD_LOGIC; q150 : OUT STD_LOGIC_VECTOR; addr151 : IN STD_LOGIC_VECTOR; ce151 : IN STD_LOGIC; q151 : OUT STD_LOGIC_VECTOR; addr152 : IN STD_LOGIC_VECTOR; ce152 : IN STD_LOGIC; q152 : OUT STD_LOGIC_VECTOR; addr153 : IN STD_LOGIC_VECTOR; ce153 : IN STD_LOGIC; q153 : OUT STD_LOGIC_VECTOR; addr154 : IN STD_LOGIC_VECTOR; ce154 : IN STD_LOGIC; q154 : OUT STD_LOGIC_VECTOR; addr155 : IN STD_LOGIC_VECTOR; ce155 : IN STD_LOGIC; q155 : OUT STD_LOGIC_VECTOR; addr156 : IN STD_LOGIC_VECTOR; ce156 : IN STD_LOGIC; q156 : OUT STD_LOGIC_VECTOR; addr157 : IN STD_LOGIC_VECTOR; ce157 : IN STD_LOGIC; q157 : OUT STD_LOGIC_VECTOR; addr158 : IN STD_LOGIC_VECTOR; ce158 : IN STD_LOGIC; q158 : OUT STD_LOGIC_VECTOR; addr159 : IN STD_LOGIC_VECTOR; ce159 : IN STD_LOGIC; q159 : OUT STD_LOGIC_VECTOR; addr160 : IN STD_LOGIC_VECTOR; ce160 : IN STD_LOGIC; q160 : OUT STD_LOGIC_VECTOR; addr161 : IN STD_LOGIC_VECTOR; ce161 : IN STD_LOGIC; q161 : OUT STD_LOGIC_VECTOR; addr162 : IN STD_LOGIC_VECTOR; ce162 : IN STD_LOGIC; q162 : OUT STD_LOGIC_VECTOR; addr163 : IN STD_LOGIC_VECTOR; ce163 : IN STD_LOGIC; q163 : OUT STD_LOGIC_VECTOR; addr164 : IN STD_LOGIC_VECTOR; ce164 : IN STD_LOGIC; q164 : OUT STD_LOGIC_VECTOR; addr165 : IN STD_LOGIC_VECTOR; ce165 : IN STD_LOGIC; q165 : OUT STD_LOGIC_VECTOR; addr166 : IN STD_LOGIC_VECTOR; ce166 : IN STD_LOGIC; q166 : OUT STD_LOGIC_VECTOR; addr167 : IN STD_LOGIC_VECTOR; ce167 : IN STD_LOGIC; q167 : OUT STD_LOGIC_VECTOR; addr168 : IN STD_LOGIC_VECTOR; ce168 : IN STD_LOGIC; q168 : OUT STD_LOGIC_VECTOR; addr169 : IN STD_LOGIC_VECTOR; ce169 : IN STD_LOGIC; q169 : OUT STD_LOGIC_VECTOR; addr170 : IN STD_LOGIC_VECTOR; ce170 : IN STD_LOGIC; q170 : OUT STD_LOGIC_VECTOR; addr171 : IN STD_LOGIC_VECTOR; ce171 : IN STD_LOGIC; q171 : OUT STD_LOGIC_VECTOR; addr172 : IN STD_LOGIC_VECTOR; ce172 : IN STD_LOGIC; q172 : OUT STD_LOGIC_VECTOR; addr173 : IN STD_LOGIC_VECTOR; ce173 : IN STD_LOGIC; q173 : OUT STD_LOGIC_VECTOR; addr174 : IN STD_LOGIC_VECTOR; ce174 : IN STD_LOGIC; q174 : OUT STD_LOGIC_VECTOR; addr175 : IN STD_LOGIC_VECTOR; ce175 : IN STD_LOGIC; q175 : OUT STD_LOGIC_VECTOR; addr176 : IN STD_LOGIC_VECTOR; ce176 : IN STD_LOGIC; q176 : OUT STD_LOGIC_VECTOR; addr177 : IN STD_LOGIC_VECTOR; ce177 : IN STD_LOGIC; q177 : OUT STD_LOGIC_VECTOR; addr178 : IN STD_LOGIC_VECTOR; ce178 : IN STD_LOGIC; q178 : OUT STD_LOGIC_VECTOR; addr179 : IN STD_LOGIC_VECTOR; ce179 : IN STD_LOGIC; q179 : OUT STD_LOGIC_VECTOR; addr180 : IN STD_LOGIC_VECTOR; ce180 : IN STD_LOGIC; q180 : OUT STD_LOGIC_VECTOR; addr181 : IN STD_LOGIC_VECTOR; ce181 : IN STD_LOGIC; q181 : OUT STD_LOGIC_VECTOR; addr182 : IN STD_LOGIC_VECTOR; ce182 : IN STD_LOGIC; q182 : OUT STD_LOGIC_VECTOR; addr183 : IN STD_LOGIC_VECTOR; ce183 : IN STD_LOGIC; q183 : OUT STD_LOGIC_VECTOR; addr184 : IN STD_LOGIC_VECTOR; ce184 : IN STD_LOGIC; q184 : OUT STD_LOGIC_VECTOR; addr185 : IN STD_LOGIC_VECTOR; ce185 : IN STD_LOGIC; q185 : OUT STD_LOGIC_VECTOR; addr186 : IN STD_LOGIC_VECTOR; ce186 : IN STD_LOGIC; q186 : OUT STD_LOGIC_VECTOR; addr187 : IN STD_LOGIC_VECTOR; ce187 : IN STD_LOGIC; q187 : OUT STD_LOGIC_VECTOR; addr188 : IN STD_LOGIC_VECTOR; ce188 : IN STD_LOGIC; q188 : OUT STD_LOGIC_VECTOR; addr189 : IN STD_LOGIC_VECTOR; ce189 : IN STD_LOGIC; q189 : OUT STD_LOGIC_VECTOR; addr190 : IN STD_LOGIC_VECTOR; ce190 : IN STD_LOGIC; q190 : OUT STD_LOGIC_VECTOR; addr191 : IN STD_LOGIC_VECTOR; ce191 : IN STD_LOGIC; q191 : OUT STD_LOGIC_VECTOR; addr192 : IN STD_LOGIC_VECTOR; ce192 : IN STD_LOGIC; q192 : OUT STD_LOGIC_VECTOR; addr193 : IN STD_LOGIC_VECTOR; ce193 : IN STD_LOGIC; q193 : OUT STD_LOGIC_VECTOR; addr194 : IN STD_LOGIC_VECTOR; ce194 : IN STD_LOGIC; q194 : OUT STD_LOGIC_VECTOR; addr195 : IN STD_LOGIC_VECTOR; ce195 : IN STD_LOGIC; q195 : OUT STD_LOGIC_VECTOR; addr196 : IN STD_LOGIC_VECTOR; ce196 : IN STD_LOGIC; q196 : OUT STD_LOGIC_VECTOR; addr197 : IN STD_LOGIC_VECTOR; ce197 : IN STD_LOGIC; q197 : OUT STD_LOGIC_VECTOR; addr198 : IN STD_LOGIC_VECTOR; ce198 : IN STD_LOGIC; q198 : OUT STD_LOGIC_VECTOR; addr199 : IN STD_LOGIC_VECTOR; ce199 : IN STD_LOGIC; q199 : OUT STD_LOGIC_VECTOR); end component; begin aestest_sboxes_rom_U : component aestest_sboxes_rom port map ( clk => clk, addr0 => address0, ce0 => ce0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1, addr2 => address2, ce2 => ce2, q2 => q2, addr3 => address3, ce3 => ce3, q3 => q3, addr4 => address4, ce4 => ce4, q4 => q4, addr5 => address5, ce5 => ce5, q5 => q5, addr6 => address6, ce6 => ce6, q6 => q6, addr7 => address7, ce7 => ce7, q7 => q7, addr8 => address8, ce8 => ce8, q8 => q8, addr9 => address9, ce9 => ce9, q9 => q9, addr10 => address10, ce10 => ce10, q10 => q10, addr11 => address11, ce11 => ce11, q11 => q11, addr12 => address12, ce12 => ce12, q12 => q12, addr13 => address13, ce13 => ce13, q13 => q13, addr14 => address14, ce14 => ce14, q14 => q14, addr15 => address15, ce15 => ce15, q15 => q15, addr16 => address16, ce16 => ce16, q16 => q16, addr17 => address17, ce17 => ce17, q17 => q17, addr18 => address18, ce18 => ce18, q18 => q18, addr19 => address19, ce19 => ce19, q19 => q19, addr20 => address20, ce20 => ce20, q20 => q20, addr21 => address21, ce21 => ce21, q21 => q21, addr22 => address22, ce22 => ce22, q22 => q22, addr23 => address23, ce23 => ce23, q23 => q23, addr24 => address24, ce24 => ce24, q24 => q24, addr25 => address25, ce25 => ce25, q25 => q25, addr26 => address26, ce26 => ce26, q26 => q26, addr27 => address27, ce27 => ce27, q27 => q27, addr28 => address28, ce28 => ce28, q28 => q28, addr29 => address29, ce29 => ce29, q29 => q29, addr30 => address30, ce30 => ce30, q30 => q30, addr31 => address31, ce31 => ce31, q31 => q31, addr32 => address32, ce32 => ce32, q32 => q32, addr33 => address33, ce33 => ce33, q33 => q33, addr34 => address34, ce34 => ce34, q34 => q34, addr35 => address35, ce35 => ce35, q35 => q35, addr36 => address36, ce36 => ce36, q36 => q36, addr37 => address37, ce37 => ce37, q37 => q37, addr38 => address38, ce38 => ce38, q38 => q38, addr39 => address39, ce39 => ce39, q39 => q39, addr40 => address40, ce40 => ce40, q40 => q40, addr41 => address41, ce41 => ce41, q41 => q41, addr42 => address42, ce42 => ce42, q42 => q42, addr43 => address43, ce43 => ce43, q43 => q43, addr44 => address44, ce44 => ce44, q44 => q44, addr45 => address45, ce45 => ce45, q45 => q45, addr46 => address46, ce46 => ce46, q46 => q46, addr47 => address47, ce47 => ce47, q47 => q47, addr48 => address48, ce48 => ce48, q48 => q48, addr49 => address49, ce49 => ce49, q49 => q49, addr50 => address50, ce50 => ce50, q50 => q50, addr51 => address51, ce51 => ce51, q51 => q51, addr52 => address52, ce52 => ce52, q52 => q52, addr53 => address53, ce53 => ce53, q53 => q53, addr54 => address54, ce54 => ce54, q54 => q54, addr55 => address55, ce55 => ce55, q55 => q55, addr56 => address56, ce56 => ce56, q56 => q56, addr57 => address57, ce57 => ce57, q57 => q57, addr58 => address58, ce58 => ce58, q58 => q58, addr59 => address59, ce59 => ce59, q59 => q59, addr60 => address60, ce60 => ce60, q60 => q60, addr61 => address61, ce61 => ce61, q61 => q61, addr62 => address62, ce62 => ce62, q62 => q62, addr63 => address63, ce63 => ce63, q63 => q63, addr64 => address64, ce64 => ce64, q64 => q64, addr65 => address65, ce65 => ce65, q65 => q65, addr66 => address66, ce66 => ce66, q66 => q66, addr67 => address67, ce67 => ce67, q67 => q67, addr68 => address68, ce68 => ce68, q68 => q68, addr69 => address69, ce69 => ce69, q69 => q69, addr70 => address70, ce70 => ce70, q70 => q70, addr71 => address71, ce71 => ce71, q71 => q71, addr72 => address72, ce72 => ce72, q72 => q72, addr73 => address73, ce73 => ce73, q73 => q73, addr74 => address74, ce74 => ce74, q74 => q74, addr75 => address75, ce75 => ce75, q75 => q75, addr76 => address76, ce76 => ce76, q76 => q76, addr77 => address77, ce77 => ce77, q77 => q77, addr78 => address78, ce78 => ce78, q78 => q78, addr79 => address79, ce79 => ce79, q79 => q79, addr80 => address80, ce80 => ce80, q80 => q80, addr81 => address81, ce81 => ce81, q81 => q81, addr82 => address82, ce82 => ce82, q82 => q82, addr83 => address83, ce83 => ce83, q83 => q83, addr84 => address84, ce84 => ce84, q84 => q84, addr85 => address85, ce85 => ce85, q85 => q85, addr86 => address86, ce86 => ce86, q86 => q86, addr87 => address87, ce87 => ce87, q87 => q87, addr88 => address88, ce88 => ce88, q88 => q88, addr89 => address89, ce89 => ce89, q89 => q89, addr90 => address90, ce90 => ce90, q90 => q90, addr91 => address91, ce91 => ce91, q91 => q91, addr92 => address92, ce92 => ce92, q92 => q92, addr93 => address93, ce93 => ce93, q93 => q93, addr94 => address94, ce94 => ce94, q94 => q94, addr95 => address95, ce95 => ce95, q95 => q95, addr96 => address96, ce96 => ce96, q96 => q96, addr97 => address97, ce97 => ce97, q97 => q97, addr98 => address98, ce98 => ce98, q98 => q98, addr99 => address99, ce99 => ce99, q99 => q99, addr100 => address100, ce100 => ce100, q100 => q100, addr101 => address101, ce101 => ce101, q101 => q101, addr102 => address102, ce102 => ce102, q102 => q102, addr103 => address103, ce103 => ce103, q103 => q103, addr104 => address104, ce104 => ce104, q104 => q104, addr105 => address105, ce105 => ce105, q105 => q105, addr106 => address106, ce106 => ce106, q106 => q106, addr107 => address107, ce107 => ce107, q107 => q107, addr108 => address108, ce108 => ce108, q108 => q108, addr109 => address109, ce109 => ce109, q109 => q109, addr110 => address110, ce110 => ce110, q110 => q110, addr111 => address111, ce111 => ce111, q111 => q111, addr112 => address112, ce112 => ce112, q112 => q112, addr113 => address113, ce113 => ce113, q113 => q113, addr114 => address114, ce114 => ce114, q114 => q114, addr115 => address115, ce115 => ce115, q115 => q115, addr116 => address116, ce116 => ce116, q116 => q116, addr117 => address117, ce117 => ce117, q117 => q117, addr118 => address118, ce118 => ce118, q118 => q118, addr119 => address119, ce119 => ce119, q119 => q119, addr120 => address120, ce120 => ce120, q120 => q120, addr121 => address121, ce121 => ce121, q121 => q121, addr122 => address122, ce122 => ce122, q122 => q122, addr123 => address123, ce123 => ce123, q123 => q123, addr124 => address124, ce124 => ce124, q124 => q124, addr125 => address125, ce125 => ce125, q125 => q125, addr126 => address126, ce126 => ce126, q126 => q126, addr127 => address127, ce127 => ce127, q127 => q127, addr128 => address128, ce128 => ce128, q128 => q128, addr129 => address129, ce129 => ce129, q129 => q129, addr130 => address130, ce130 => ce130, q130 => q130, addr131 => address131, ce131 => ce131, q131 => q131, addr132 => address132, ce132 => ce132, q132 => q132, addr133 => address133, ce133 => ce133, q133 => q133, addr134 => address134, ce134 => ce134, q134 => q134, addr135 => address135, ce135 => ce135, q135 => q135, addr136 => address136, ce136 => ce136, q136 => q136, addr137 => address137, ce137 => ce137, q137 => q137, addr138 => address138, ce138 => ce138, q138 => q138, addr139 => address139, ce139 => ce139, q139 => q139, addr140 => address140, ce140 => ce140, q140 => q140, addr141 => address141, ce141 => ce141, q141 => q141, addr142 => address142, ce142 => ce142, q142 => q142, addr143 => address143, ce143 => ce143, q143 => q143, addr144 => address144, ce144 => ce144, q144 => q144, addr145 => address145, ce145 => ce145, q145 => q145, addr146 => address146, ce146 => ce146, q146 => q146, addr147 => address147, ce147 => ce147, q147 => q147, addr148 => address148, ce148 => ce148, q148 => q148, addr149 => address149, ce149 => ce149, q149 => q149, addr150 => address150, ce150 => ce150, q150 => q150, addr151 => address151, ce151 => ce151, q151 => q151, addr152 => address152, ce152 => ce152, q152 => q152, addr153 => address153, ce153 => ce153, q153 => q153, addr154 => address154, ce154 => ce154, q154 => q154, addr155 => address155, ce155 => ce155, q155 => q155, addr156 => address156, ce156 => ce156, q156 => q156, addr157 => address157, ce157 => ce157, q157 => q157, addr158 => address158, ce158 => ce158, q158 => q158, addr159 => address159, ce159 => ce159, q159 => q159, addr160 => address160, ce160 => ce160, q160 => q160, addr161 => address161, ce161 => ce161, q161 => q161, addr162 => address162, ce162 => ce162, q162 => q162, addr163 => address163, ce163 => ce163, q163 => q163, addr164 => address164, ce164 => ce164, q164 => q164, addr165 => address165, ce165 => ce165, q165 => q165, addr166 => address166, ce166 => ce166, q166 => q166, addr167 => address167, ce167 => ce167, q167 => q167, addr168 => address168, ce168 => ce168, q168 => q168, addr169 => address169, ce169 => ce169, q169 => q169, addr170 => address170, ce170 => ce170, q170 => q170, addr171 => address171, ce171 => ce171, q171 => q171, addr172 => address172, ce172 => ce172, q172 => q172, addr173 => address173, ce173 => ce173, q173 => q173, addr174 => address174, ce174 => ce174, q174 => q174, addr175 => address175, ce175 => ce175, q175 => q175, addr176 => address176, ce176 => ce176, q176 => q176, addr177 => address177, ce177 => ce177, q177 => q177, addr178 => address178, ce178 => ce178, q178 => q178, addr179 => address179, ce179 => ce179, q179 => q179, addr180 => address180, ce180 => ce180, q180 => q180, addr181 => address181, ce181 => ce181, q181 => q181, addr182 => address182, ce182 => ce182, q182 => q182, addr183 => address183, ce183 => ce183, q183 => q183, addr184 => address184, ce184 => ce184, q184 => q184, addr185 => address185, ce185 => ce185, q185 => q185, addr186 => address186, ce186 => ce186, q186 => q186, addr187 => address187, ce187 => ce187, q187 => q187, addr188 => address188, ce188 => ce188, q188 => q188, addr189 => address189, ce189 => ce189, q189 => q189, addr190 => address190, ce190 => ce190, q190 => q190, addr191 => address191, ce191 => ce191, q191 => q191, addr192 => address192, ce192 => ce192, q192 => q192, addr193 => address193, ce193 => ce193, q193 => q193, addr194 => address194, ce194 => ce194, q194 => q194, addr195 => address195, ce195 => ce195, q195 => q195, addr196 => address196, ce196 => ce196, q196 => q196, addr197 => address197, ce197 => ce197, q197 => q197, addr198 => address198, ce198 => ce198, q198 => q198, addr199 => address199, ce199 => ce199, q199 => q199); end architecture;
-------------------------------------------------------------------------------- -- Company: CPE233 -- Engineer: Jacob Hladky -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY rat_sim_tb IS END rat_sim_tb; ARCHITECTURE behavior OF rat_sim_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT rat_wrapper PORT( leds, seg : OUT std_logic_vector(7 downto 0); sel : OUT std_logic_vector(3 downto 0); tx : OUT std_logic; switches : IN std_logic_vector(7 downto 0); rst, clk : IN std_logic; int, rx : IN std_logic); END COMPONENT; --Inputs signal switches : std_logic_vector(7 downto 0) := (others => '0'); signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal int : std_logic := '0'; signal rx : std_logic := '0'; --Outputs signal leds : std_logic_vector(7 downto 0); signal seg : std_logic_vector(7 downto 0); signal sel : std_logic_vector(3 downto 0); signal tx : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: RAT_wrapper PORT MAP ( leds => leds, switches => switches, seg => seg, rx => rx, tx => tx, sel => sel, int => int, rst => rst, clk => clk); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 20 ns rst <= '1'; wait for 20 ns; rst <= '0'; wait for 50 ns; -- let the loop start for i in 0 to 19 loop switches <= x"FF"; -- send the first data int <= '1'; wait for 20 ns; int <= '0'; wait for 120 ns; -- wait for it to be processed switches <= x"aa"; -- send the first data int <= '1'; wait for 20 ns; int <= '0'; wait for 120 ns; -- wait for it to be processed end loop; -- wait for clk_period5; -- switches <= x"aa"; -- int <= '1'; -- wait for clk_period12; -- switches <= x"00"; -- wait for clk_period*10; -- switches <= x"FC"; wait; end process; END;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.myTypes.all; entity cw_mem is generic ( MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size OP_CODE_SIZE : integer := 6; -- Op Code Size CW_SIZE : integer := 13); -- Control Word Size port ( OPCODE_IN : in std_logic_vector(5 downto 0); -- Instruction Register CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0) ); end cw_mem; architecture bhe of cw_mem is -- signal OPC : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory type mem_array is array (integer range 0 to 63) of std_logic_vector(12 downto 0); signal cw_mem : mem_array := ( "0000000010001", -- (0X00) R type "0000000010001", -- (0X01) F type "1011000000000", -- (0X02) J "1011011110001", -- (0X03) JAL "1101000000000", -- (0X04) BEQZ "1101100000000", -- (0X05) BNEZ "0000000000000", -- (0X06) BFPT "0000000000000", -- (0X07) BFPT "0001001100001", -- (0X08) ADDI "0000001100001", -- (0X09) ADDUI "0001001100001", -- (0X0A) SUBI "0000001100001", -- (0X0B) SUBUI "0000001100001", -- (0X0C) ANDI "0000001100001", -- (0X0D) ORI "0000001100001", -- (0X0E) XORI "0000000000000", -- (0X0F) LHI -- NOT IMPLEMENTED "0000000000000", -- (0X10) RFE -- NOT IMPLEMENTED "0000000000000", -- (0X11) TRAP -- NOT IMPLEMENTED "0100000000000", -- (0X12) JR "0100011100001", -- (0X13) JALR "0000001100001", -- (0X14) SLLI "0000000000000", -- (0X15) NOP "0000001100001", -- (0X16) SRLI "0000001100001", -- (0X17) SRAI "0000001100001", -- (0X18) SEQI "0000001100001", -- (0X19) SNEI "0000001100001", -- (0X1A) SLTI "0000001100001", -- (0X1B) SGTI "0000001100001", -- (0X1C) SLEI "0000001100001", -- (0X1D) SGEI "0000000000000", -- (0X1E) "0000000000000", -- (0X1F) "0000000000000", -- (0X20) LB -- NOT IMPLEMENTED "0000000000000", -- (0X21) LH -- NOT IMPLEMENTED "0000000000000", -- (0X22) "0000001101011", -- (0X23) LW "0000000000000", -- (0X24) LBU -- NOT IMPLEMENTED "0000000000000", -- (0X25) LHU -- NOT IMPLEMENTED "0000000000000", -- (0X26) LF -- NOT IMPLEMENTED "0000000000000", -- (0X27) LD -- NOT IMPLEMENTED "0000000000000", -- (0X28) SB -- NOT IMPLEMENTED "0000000000000", -- (0X29) SH -- NOT IMPLEMENTED "0000000000000", -- (0X2A) "0000001101100", -- (0X2B) SW "0000000000000", -- (0X2C) "0000000000000", -- (0X2D) "0000000000000", -- (0X2E) SF -- NOT IMPLEMENTED "0000000000000", -- (0X2F) SD -- NOT IMPLEMENTED "0000000000000", -- (0X30) "0000000000000", -- (0X31) "0000000000000", -- (0X32) "0000000000000", -- (0X33) "0000000000000", -- (0X34) "0000000000000", -- (0X35) "0000000000000", -- (0X36) "0000000000000", -- (0X37) "0000000000000", -- (0X38) ITLB -- NOT IMPLEMENTED "0000000000000", -- (0X39) "0000001100001", -- (0X3A) SLTUI "0000001100001", -- (0X3B) SGTUI "0000001100001", -- (0X3C) SLEUI "0000001100001", -- (0X3D) SGEUI "0000000000000", -- (0X3E) "0000000000000" -- (0X3F) ); begin -- CW_OUT <= cw_mem(to_integer(unsigned(OPCODE_IN))); -- CW_OUT <= cw_mem(0) when OPCODE_IN = "0X00" else -- cw_mem(1) when OPCODE_IN = "0X01" else -- NULL; process (OPCODE_IN) begin case to_integer(unsigned(OPCODE_IN)) is when 0 => CW_OUT <= "0000000010001"; when 1 => CW_OUT <= "0000000010001"; when 2 => CW_OUT <= "1011000000000"; when 3 => CW_OUT <= "1011011110001"; when 4 => CW_OUT <= "1101000000000"; when 5 => CW_OUT <= "1101100000000"; when 6 => CW_OUT <= "0000000000000"; when 7 => CW_OUT <= "0000000000000"; when 8 => CW_OUT <= "0001001100001"; when 9 => CW_OUT <= "0000001100001"; when 10 => CW_OUT <="0001001100001"; when 11 => CW_OUT <="0000001100001"; when 12 => CW_OUT <="0000001100001"; when 13 => CW_OUT <="0000001100001"; when 14 => CW_OUT <="0000001100001"; when 15 => CW_OUT <="0000000000000"; when 16 => CW_OUT <="0000000000000"; when 17 => CW_OUT <="0000000000000"; when 18 => CW_OUT <="0100000000000"; when 19 => CW_OUT <="0100011100001"; when 20 => CW_OUT <="0000001100001"; when 21 => CW_OUT <="0000000000000"; when 22 => CW_OUT <="0000001100001"; when 23 => CW_OUT <="0000001100001"; when 24 => CW_OUT <="0000001100001"; when 25 => CW_OUT <="0000001100001"; when 26 => CW_OUT <="0000001100001"; when 27 => CW_OUT <="0000001100001"; when 28 => CW_OUT <="0000001100001"; when 29 => CW_OUT <="0000001100001"; when 30 => CW_OUT <="0000000000000"; when 31 => CW_OUT <="0000000000000"; when 32 => CW_OUT <="0000000000000"; when 33 => CW_OUT <="0000000000000"; when 34 => CW_OUT <="0000000000000"; when 35 => CW_OUT <="0000001101011"; when 36 => CW_OUT <="0000000000000"; when 37 => CW_OUT <="0000000000000"; when 38 => CW_OUT <="0000000000000"; when 39 => CW_OUT <="0000000000000"; when 40 => CW_OUT <="0000000000000"; when 41 => CW_OUT <="0000000000000"; when 42 => CW_OUT <="0000000000000"; when 43 => CW_OUT <="0000001101100"; when 44 => CW_OUT <="0000000000000"; when 45 => CW_OUT <="0000000000000"; when 46 => CW_OUT <="0000000000000"; when 47 => CW_OUT <="0000000000000"; when 48 => CW_OUT <="0000000000000"; when 49 => CW_OUT <="0000000000000"; when 50 => CW_OUT <="0000000000000"; when 51 => CW_OUT <="0000000000000"; when 52 => CW_OUT <="0000000000000"; when 53 => CW_OUT <="0000000000000"; when 54 => CW_OUT <="0000000000000"; when 55 => CW_OUT <="0000000000000"; when 56 => CW_OUT <="0000000000000"; when 57 => CW_OUT <="0000000000000"; when 58 => CW_OUT <="0000001100001"; when 59 => CW_OUT <="0000001100001"; when 60 => CW_OUT <="0000001100001"; when 61 => CW_OUT <="0000001100001"; when 62 => CW_OUT <="0000000000000"; when 63 => CW_OUT <="0000000000000"; when others => NULL; end case; end process; end bhe;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.myTypes.all; entity cw_mem is generic ( MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size OP_CODE_SIZE : integer := 6; -- Op Code Size CW_SIZE : integer := 13); -- Control Word Size port ( OPCODE_IN : in std_logic_vector(5 downto 0); -- Instruction Register CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0) ); end cw_mem; architecture bhe of cw_mem is -- signal OPC : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory type mem_array is array (integer range 0 to 63) of std_logic_vector(12 downto 0); signal cw_mem : mem_array := ( "0000000010001", -- (0X00) R type "0000000010001", -- (0X01) F type "1011000000000", -- (0X02) J "1011011110001", -- (0X03) JAL "1101000000000", -- (0X04) BEQZ "1101100000000", -- (0X05) BNEZ "0000000000000", -- (0X06) BFPT "0000000000000", -- (0X07) BFPT "0001001100001", -- (0X08) ADDI "0000001100001", -- (0X09) ADDUI "0001001100001", -- (0X0A) SUBI "0000001100001", -- (0X0B) SUBUI "0000001100001", -- (0X0C) ANDI "0000001100001", -- (0X0D) ORI "0000001100001", -- (0X0E) XORI "0000000000000", -- (0X0F) LHI -- NOT IMPLEMENTED "0000000000000", -- (0X10) RFE -- NOT IMPLEMENTED "0000000000000", -- (0X11) TRAP -- NOT IMPLEMENTED "0100000000000", -- (0X12) JR "0100011100001", -- (0X13) JALR "0000001100001", -- (0X14) SLLI "0000000000000", -- (0X15) NOP "0000001100001", -- (0X16) SRLI "0000001100001", -- (0X17) SRAI "0000001100001", -- (0X18) SEQI "0000001100001", -- (0X19) SNEI "0000001100001", -- (0X1A) SLTI "0000001100001", -- (0X1B) SGTI "0000001100001", -- (0X1C) SLEI "0000001100001", -- (0X1D) SGEI "0000000000000", -- (0X1E) "0000000000000", -- (0X1F) "0000000000000", -- (0X20) LB -- NOT IMPLEMENTED "0000000000000", -- (0X21) LH -- NOT IMPLEMENTED "0000000000000", -- (0X22) "0000001101011", -- (0X23) LW "0000000000000", -- (0X24) LBU -- NOT IMPLEMENTED "0000000000000", -- (0X25) LHU -- NOT IMPLEMENTED "0000000000000", -- (0X26) LF -- NOT IMPLEMENTED "0000000000000", -- (0X27) LD -- NOT IMPLEMENTED "0000000000000", -- (0X28) SB -- NOT IMPLEMENTED "0000000000000", -- (0X29) SH -- NOT IMPLEMENTED "0000000000000", -- (0X2A) "0000001101100", -- (0X2B) SW "0000000000000", -- (0X2C) "0000000000000", -- (0X2D) "0000000000000", -- (0X2E) SF -- NOT IMPLEMENTED "0000000000000", -- (0X2F) SD -- NOT IMPLEMENTED "0000000000000", -- (0X30) "0000000000000", -- (0X31) "0000000000000", -- (0X32) "0000000000000", -- (0X33) "0000000000000", -- (0X34) "0000000000000", -- (0X35) "0000000000000", -- (0X36) "0000000000000", -- (0X37) "0000000000000", -- (0X38) ITLB -- NOT IMPLEMENTED "0000000000000", -- (0X39) "0000001100001", -- (0X3A) SLTUI "0000001100001", -- (0X3B) SGTUI "0000001100001", -- (0X3C) SLEUI "0000001100001", -- (0X3D) SGEUI "0000000000000", -- (0X3E) "0000000000000" -- (0X3F) ); begin -- CW_OUT <= cw_mem(to_integer(unsigned(OPCODE_IN))); -- CW_OUT <= cw_mem(0) when OPCODE_IN = "0X00" else -- cw_mem(1) when OPCODE_IN = "0X01" else -- NULL; process (OPCODE_IN) begin case to_integer(unsigned(OPCODE_IN)) is when 0 => CW_OUT <= "0000000010001"; when 1 => CW_OUT <= "0000000010001"; when 2 => CW_OUT <= "1011000000000"; when 3 => CW_OUT <= "1011011110001"; when 4 => CW_OUT <= "1101000000000"; when 5 => CW_OUT <= "1101100000000"; when 6 => CW_OUT <= "0000000000000"; when 7 => CW_OUT <= "0000000000000"; when 8 => CW_OUT <= "0001001100001"; when 9 => CW_OUT <= "0000001100001"; when 10 => CW_OUT <="0001001100001"; when 11 => CW_OUT <="0000001100001"; when 12 => CW_OUT <="0000001100001"; when 13 => CW_OUT <="0000001100001"; when 14 => CW_OUT <="0000001100001"; when 15 => CW_OUT <="0000000000000"; when 16 => CW_OUT <="0000000000000"; when 17 => CW_OUT <="0000000000000"; when 18 => CW_OUT <="0100000000000"; when 19 => CW_OUT <="0100011100001"; when 20 => CW_OUT <="0000001100001"; when 21 => CW_OUT <="0000000000000"; when 22 => CW_OUT <="0000001100001"; when 23 => CW_OUT <="0000001100001"; when 24 => CW_OUT <="0000001100001"; when 25 => CW_OUT <="0000001100001"; when 26 => CW_OUT <="0000001100001"; when 27 => CW_OUT <="0000001100001"; when 28 => CW_OUT <="0000001100001"; when 29 => CW_OUT <="0000001100001"; when 30 => CW_OUT <="0000000000000"; when 31 => CW_OUT <="0000000000000"; when 32 => CW_OUT <="0000000000000"; when 33 => CW_OUT <="0000000000000"; when 34 => CW_OUT <="0000000000000"; when 35 => CW_OUT <="0000001101011"; when 36 => CW_OUT <="0000000000000"; when 37 => CW_OUT <="0000000000000"; when 38 => CW_OUT <="0000000000000"; when 39 => CW_OUT <="0000000000000"; when 40 => CW_OUT <="0000000000000"; when 41 => CW_OUT <="0000000000000"; when 42 => CW_OUT <="0000000000000"; when 43 => CW_OUT <="0000001101100"; when 44 => CW_OUT <="0000000000000"; when 45 => CW_OUT <="0000000000000"; when 46 => CW_OUT <="0000000000000"; when 47 => CW_OUT <="0000000000000"; when 48 => CW_OUT <="0000000000000"; when 49 => CW_OUT <="0000000000000"; when 50 => CW_OUT <="0000000000000"; when 51 => CW_OUT <="0000000000000"; when 52 => CW_OUT <="0000000000000"; when 53 => CW_OUT <="0000000000000"; when 54 => CW_OUT <="0000000000000"; when 55 => CW_OUT <="0000000000000"; when 56 => CW_OUT <="0000000000000"; when 57 => CW_OUT <="0000000000000"; when 58 => CW_OUT <="0000001100001"; when 59 => CW_OUT <="0000001100001"; when 60 => CW_OUT <="0000001100001"; when 61 => CW_OUT <="0000001100001"; when 62 => CW_OUT <="0000000000000"; when 63 => CW_OUT <="0000000000000"; when others => NULL; end case; end process; end bhe;
-- -- File Name: AlertLogPkg.vhd -- Design Unit Name: AlertLogPkg -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: [email protected] -- Contributor(s): -- Jim Lewis [email protected] -- -- -- Description: -- Alert handling and log filtering (verbosity control) -- Alert handling provides a method to count failures, errors, and warnings -- To accumlate counts, a data structure is created in a shared variable -- It is of type AlertLogStructPType which is defined in AlertLogBasePkg -- Log filtering provides verbosity control for logs (display or do not display) -- AlertLogPkg provides a simplified interface to the shared variable -- -- -- Developed for: -- SynthWorks Design Inc. -- VHDL Training Classes -- 11898 SW 128th Ave. Tigard, Or 97223 -- http://www.SynthWorks.com -- -- Revision History: -- Date Version Description -- 01/2015: 2015.01 Initial revision -- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail, -- ReportNonZeroAlerts, ReadLogEnables -- 05/2015 2015.06 Added IncAlertCount, AffirmIf -- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs -- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel) -- Created LocalInitialize -- -- Copyright (c) 2015 - 2016 by SynthWorks Design Inc. All rights reserved. -- -- Verbatim copies of this source file may be used and -- distributed without restriction. -- -- This source file is free software; you can redistribute it -- and/or modify it under the terms of the ARTISTIC License -- as published by The Perl Foundation; either version 2.0 of -- the License, or (at your option) any later version. -- -- This source is distributed in the hope that it will be -- useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- PURPOSE. See the Artistic License for details. -- -- You should have received a copy of the license with this source. -- If not download it from, -- http://www.perlfoundation.org/artistic_license_2_0 -- use std.textio.all ; use work.OsvvmGlobalPkg.all ; use work.TranscriptPkg.all ; use work.TextUtilPkg.all ; library IEEE ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; package AlertLogPkg is subtype AlertLogIDType is integer ; type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER subtype AlertIndexType is AlertType range FAILURE to WARNING ; type AlertCountType is array (AlertIndexType) of integer ; type AlertEnableType is array(AlertIndexType) of boolean ; type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType subtype LogIndexType is LogType range DEBUG to PASSED ; type LogEnableType is array (LogIndexType) of boolean ; constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0. constant ALERTLOG_DEFAULT_ID : AlertLogIDType := 1 ; constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant OSVVM_ALERTLOG_ID : AlertLogIDType := 2 ; constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ; -- NUM_PREDEFINED_AL_IDS intended to be local, but depends on others -- constant NUM_PREDEFINED_AL_IDS : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID - ALERTLOG_BASE_ID ; -- Not including base constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ; constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ; ------------------------------------------------------------ -- Alert always goes to the transcript file procedure Alert( AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; procedure Alert( Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount( -- A silent form of alert AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) ; procedure IncAlertCount( Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Similar to assert, except condition is positive procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- Direct replacement for assert procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- overloading for common functionality procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Simple Diff for file comparisons procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR ) ; procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) ; ------------------------------------------------------------ procedure SetAlertLogJustify ; procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ClearAlerts ; function "ABS" (L : AlertCountType) return AlertCountType ; function "+" (L, R : AlertCountType) return AlertCountType ; function "-" (L, R : AlertCountType) return AlertCountType ; function "-" (R : AlertCountType) return AlertCountType ; impure function SumAlertCount(AlertCount: AlertCountType) return integer ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount return integer ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ; ------------------------------------------------------------ -- log filtering for verbosity control, optionally has a separate file parameter procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ; ------------------------------------------------------------ -- Accessor Methods procedure SetAlertLogName(Name : string ) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ; procedure DeallocateAlertLogStruct ; procedure InitializeAlertLogStruct ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; ------------------------------------------------------------ -- Accessor Methods procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCheckCount ; impure function GetAffirmCheckCount return natural ; --?? procedure IncAffirmPassCount ; --?? impure function GetAffirmPassCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; procedure SetAlertStopCount(Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; impure function GetAlertStopCount(Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; impure function GetAlertEnable(Level : AlertType) return boolean ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; impure function GetLogEnable(Level : LogType) return boolean ; impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; -- same as GetLogEnable impure function IsLoggingEnabled(Level : LogType) return boolean ; procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; -- File Reading Utilities function IsLogEnableType (Name : String) return boolean ; procedure ReadLogEnables (file AlertLogInitFile : text) ; procedure ReadLogEnables (FileName : string) ; -- String Helper Functions -- This should be in a more general string package function PathTail (A : string) return string ; end AlertLogPkg ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// use work.NamePkg.all ; package body AlertLogPkg is -- instead of justify(to_upper(to_string())), just look up the upper case, left justified values type AlertNameType is array(AlertType) of string(1 to 7) ; constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER " type LogNameType is array(LogType) of string(1 to 7) ; constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER " type AlertLogStructPType is protected ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ; procedure SetJustify ; procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ; procedure ClearAlerts ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; ------------------------------------------------------------ -- FILE IO Controls -- procedure SetTranscriptEnable (A : boolean := TRUE) ; -- impure function IsTranscriptEnabled return boolean ; -- procedure MirrorTranscript (A : boolean := TRUE) ; -- impure function IsTranscriptMirrored return boolean ; ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) ; procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) ; procedure Deallocate ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCheckCount ; impure function GetAffirmCheckCount return natural ; --?? procedure IncAffirmPassCount ; --?? impure function GetAffirmPassCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; procedure ReportLogEnables ; ------------------------------------------------------------ -- Reporting Accessor procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; end protected AlertLogStructPType ; --- /////////////////////////////////////////////////////////////////////////// type AlertLogStructPType is protected body variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on variable AffirmCheckCountVar : natural := 0 ; --?? variable AffirmPassedCountVar : natural := 0 ; ------------------------------------------------------------ type AlertLogRecType is record ------------------------------------------------------------ Name : Line ; ParentID : AlertLogIDType ; AlertCount : AlertCountType ; AlertStopCount : AlertCountType ; AlertEnabled : AlertEnableType ; LogEnabled : LogEnableType ; end record AlertLogRecType ; ------------------------------------------------------------ -- Basis for AlertLog Data Structure variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ; --xx variable NumPredefinedAlIDsVar : AlertLogIDType := 0 ; -- defined by initialize type AlertLogRecPtrType is access AlertLogRecType ; type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ; type AlertLogArrayPtrType is access AlertLogArrayType ; variable AlertLogPtr : AlertLogArrayPtrType ; ------------------------------------------------------------ -- Report formatting settings, with defaults variable FailOnWarningVar : boolean := TRUE ; variable FailOnDisabledErrorsVar : boolean := TRUE ; variable ReportHierarchyVar : boolean := TRUE ; variable FoundReportHierVar : boolean := FALSE ; variable FoundAlertHierVar : boolean := FALSE ; variable WriteAlertLevelVar : boolean := TRUE ; variable WriteAlertNameVar : boolean := TRUE ; variable WriteAlertTimeVar : boolean := TRUE ; variable WriteLogLevelVar : boolean := TRUE ; variable WriteLogNameVar : boolean := TRUE ; variable WriteLogTimeVar : boolean := TRUE ; variable AlertPrefixVar : NamePType ; variable LogPrefixVar : NamePType ; variable ReportPrefixVar : NamePType ; variable DoneNameVar : NamePType ; variable PassNameVar : NamePType ; variable FailNameVar : NamePType ; variable AlertLogJustifyAmountVar : integer := 0 ; variable ReportJustifyAmountVar : integer := 0 ; ------------------------------------------------------------ -- PT Local impure function LeftJustify(A : String; Amount : integer) return string is ------------------------------------------------------------ constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ; begin if A'length >= Amount then return A ; else return A & Spaces(1 to Amount - A'length) ; end if ; end function LeftJustify ; ------------------------------------------------------------ -- PT Local procedure IncrementAlertCount( ------------------------------------------------------------ constant AlertLogID : in AlertLogIDType ; constant Level : in AlertType ; variable StopDueToCount : inout boolean ) is begin -- Always Count at this level AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + 1 ; -- Only do remaining actions if enabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- Exceeded Stop Count at this level? if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then StopDueToCount := TRUE ; end if ; -- Propagate counts to parent(s) -- Ascend Hierarchy if AlertLogID /= ALERTLOG_BASE_ID then IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount) ; end if ; end if ; end procedure IncrementAlertCount ; ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then -- Do not write or count when GlobalAlertEnabledVar is disabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- do not write when disabled write(buf, AlertPrefix) ; if WriteAlertLevelVar then -- write(buf, " " & to_string(Level) ) ; write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup end if ; --xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteAlertNameVar then -- print hierarchy names even when silent if FoundAlertHierVar and WriteAlertNameVar then -- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ; write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteAlertTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end if ; -- Always Count IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; --xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop(1) ; end if ; end if ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; --xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop ; end if ; end if ; end procedure IncAlertCount ; ------------------------------------------------------------ -- PT Local impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is ------------------------------------------------------------ variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then LowerLevelValues := CalcJustify(i, AlertLogPtr(i).Name'length, IndentAmount + 2) ; ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ; ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ; end if ; end loop ; return ResultValues ; end function CalcJustify ; ------------------------------------------------------------ procedure SetJustify is ------------------------------------------------------------ variable ResultValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues := CalcJustify(ALERTLOG_BASE_ID, 0, 0) ; AlertLogJustifyAmountVar := ResultValues(1) ; ReportJustifyAmountVar := ResultValues(2) ; end procedure SetJustify ; ------------------------------------------------------------ -- PT Local impure function GetEnabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return AlertLogPtr(AlertLogID).AlertCount ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ -- PT Local impure function GetDisabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if not AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if not AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and not AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Count := Count + GetDisabledAlertCount(AlertLogPtr(i).AlertCount, AlertLogPtr(i).AlertEnabled) ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin Count := GetDisabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then Count := Count + GetDisabledAlertCount(i) ; end if ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ -- PT Local procedure PrintTopAlerts ( ------------------------------------------------------------ NumErrors : integer ; AlertCount : AlertCountType ; Name : string ; NumDisabledErrors : integer ) is constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ; constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ; constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ; constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ; variable buf : line ; begin if NumErrors = 0 then if NumDisabledErrors = 0 then -- Passed write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; else -- Failed Due to Disabled Errors write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; write(buf, " Failed Due to Disabled Error(s) = " & to_string(NumDisabledErrors)) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; else -- Failed write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ; write(buf, " Total Error(s) = " & to_string(NumErrors) ) ; write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ; write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ; if AffirmCheckCountVar > 0 then --?? write(buf, " Affirmations Passed: " & to_string(AffirmPassedCountVar)) ; --?? write(buf, " Checked: " & to_string(AffirmCheckCountVar)) ; write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; Write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; end procedure PrintTopAlerts ; ------------------------------------------------------------ -- PT Local procedure PrintChild( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ; ReportAll : boolean ) is variable buf : line ; begin for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then if ReportAll or SumAlertCount(AlertLogPtr(i).AlertCount) > 0 then Write(buf, Prefix & " " & LeftJustify(AlertLogPtr(i).Name.all, ReportJustifyAmountVar - IndentAmount)) ; write(buf, " Failures: " & to_string(AlertLogPtr(i).AlertCount(FAILURE) ) ) ; write(buf, " Errors: " & to_string(AlertLogPtr(i).AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertLogPtr(i).AlertCount(WARNING) ) ) ; WriteLine(buf) ; end if ; PrintChild( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2, ReportAll => ReportAll ) ; end if ; end loop ; end procedure PrintChild ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE) is ------------------------------------------------------------ variable NumErrors : integer ; variable NumDisabledErrors : integer ; constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; NumErrors := SumAlertCount( ExternalErrors + GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ) ; if FailOnDisabledErrorsVar then NumDisabledErrors := SumAlertCount( GetDisabledAlertCount(AlertLogID) ) ; else NumDisabledErrors := 0 ; end if ; if IsOsvvmStringSet(Name) then PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => Name, NumDisabledErrors => NumDisabledErrors ) ; else PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => AlertLogPtr(AlertLogID).Name.all, NumDisabledErrors => NumDisabledErrors ) ; end if ; --Print Hierarchy when enabled and error or disabled error if (FoundReportHierVar and ReportHierarchyVar) and (NumErrors /= 0 or NumDisabledErrors /=0) then PrintChild( AlertLogID => AlertLogID, Prefix => ReportPrefix & " ", IndentAmount => 2, ReportAll => ReportAll ) ; end if ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin PrintTopAlerts ( NumErrors => SumAlertCount(AlertCount), AlertCount => AlertCount, Name => Name, NumDisabledErrors => 0 ) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AffirmCheckCountVar := 0 ; --?? AffirmPassedCountVar := 0 ; AlertLogPtr(ALERTLOG_BASE_ID).AlertCount := (0, 0, 0) ; AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop AlertLogPtr(i).AlertCount := (0, 0, 0) ; AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end loop ; end procedure ClearAlerts ; ------------------------------------------------------------ -- PT Local procedure LocalLog ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType ) is variable buf : line ; constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; begin write(buf, LogPrefix) ; if WriteLogLevelVar then write(buf, " " & LOG_NAME(Level) ) ; end if ; --xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteLogNameVar then -- print hierarchy names even when silent if FoundAlertHierVar and WriteLogNameVar then -- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ; write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteLogTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end procedure LocalLog ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin if Level = ALWAYS or Enable then LocalLog(AlertLogID, Message, Level) ; elsif AlertLogPtr(AlertLogID).LogEnabled(Level) then LocalLog(AlertLogID, Message, Level) ; end if ; end procedure log ; ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ; AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).Name.all ; end function GetAlertLogName ; ------------------------------------------------------------ -- PT Local procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is ------------------------------------------------------------ variable AlertEnabled : AlertEnableType ; variable AlertStopCount : AlertCountType ; variable LogEnabled : LogEnableType ; begin if AlertLogID = ALERTLOG_BASE_ID then AlertEnabled := (TRUE, TRUE, TRUE) ; LogEnabled := (others => FALSE) ; AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; else if ParentID < ALERTLOG_BASE_ID then AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ; LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ; else AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ; LogEnabled := AlertLogPtr(ParentID).LogEnabled ; end if ; AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end if ; AlertLogPtr(AlertLogID) := new AlertLogRecType ; AlertLogPtr(AlertLogID).Name := new string'(NAME) ; AlertLogPtr(AlertLogID).ParentID := ParentID ; AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ; AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ; AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ; AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ; -- AlertLogPtr(AlertLogID) := new AlertLogRecType'( -- Name => new string'(NAME), -- ParentID => ParentID, -- AlertCount => (0, 0, 0), -- AlertEnabled => AlertEnabled, -- AlertStopCount => AlertStopCount, -- LogEnabled => LogEnabled -- ) ; end procedure NewAlertLogRec ; ------------------------------------------------------------ -- PT Local -- Construct initial data structure procedure LocalInitialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin if NumAllocatedAlertLogIDsVar /= 0 then Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ; return ; end if ; -- Initialize Pointer AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; -- Create BASE AlertLogID (if it differs from DEFAULT if ALERTLOG_BASE_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ; end if ; -- Create DEFAULT AlertLogID NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := ALERT_DEFAULT_ID ; -- Create OSVVM AlertLogID (if it differs from DEFAULT if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; end procedure LocalInitialize ; ------------------------------------------------------------ -- Construct initial data structure procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin LocalInitialize(NewNumAlertLogIDs) ; end procedure Initialize ; ------------------------------------------------------------ -- PT Local -- Constructs initial data structure using constant below impure function LocalInitialize return boolean is ------------------------------------------------------------ begin LocalInitialize(MIN_NUM_AL_IDS) ; return TRUE ; end function LocalInitialize ; constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ; ------------------------------------------------------------ procedure Deallocate is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Deallocate(AlertLogPtr(i).Name) ; Deallocate(AlertLogPtr(i)) ; end loop ; deallocate(AlertLogPtr) ; -- Free up space used by protected types within AlertLogPkg AlertPrefixVar.Deallocate ; LogPrefixVar.Deallocate ; ReportPrefixVar.Deallocate ; DoneNameVar.Deallocate ; PassNameVar.Deallocate ; FailNameVar.Deallocate ; -- Restore variables to their initial state NumAlertLogIDsVar := 0 ; NumAllocatedAlertLogIDsVar := 0 ; GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on AffirmCheckCountVar := 0 ; --?? AffirmPassedCountVar := 0 ; FailOnWarningVar := TRUE ; FailOnDisabledErrorsVar := TRUE ; ReportHierarchyVar := TRUE ; FoundReportHierVar := FALSE ; FoundAlertHierVar := FALSE ; WriteAlertLevelVar := TRUE ; WriteAlertNameVar := TRUE ; WriteAlertTimeVar := TRUE ; WriteLogLevelVar := TRUE ; WriteLogNameVar := TRUE ; WriteLogTimeVar := TRUE ; end procedure Deallocate ; ------------------------------------------------------------ -- PT Local. procedure GrowAlertStructure (NewNumAlertLogIDs : integer) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NumAllocatedAlertLogIDsVar = 0 then Initialize (NewNumAlertLogIDs) ; -- Construct initial structure else oldAlertLogPtr := AlertLogPtr ; AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ; AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ; deallocate(oldAlertLogPtr) ; end if ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; end procedure GrowAlertStructure ; ------------------------------------------------------------ -- Sets a AlertLogPtr to a particular size -- Use for small bins to save space or large bins to -- suppress the resize and copy as a CovBin autosizes. procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NewNumAlertLogIDs) ; end if; end procedure SetNumAlertLogIDs ; ------------------------------------------------------------ -- PT Local impure function GetNextAlertLogID return AlertLogIDType is ------------------------------------------------------------ variable NewNumAlertLogIDs : AlertLogIDType ; begin NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ; if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ; end if ; NumAlertLogIDsVar := NewNumAlertLogIDs ; return NumAlertLogIDsVar ; end function GetNextAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop if Name = AlertLogPtr(i).Name.all then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ variable CurParentID : AlertLogIDType ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop CurParentID := AlertLogPtr(i).ParentID ; if Name = AlertLogPtr(i).Name.all and (CurParentID = ParentID or CurParentID = ALERTLOG_ID_NOT_ASSIGNED or ParentID = ALERTLOG_ID_NOT_ASSIGNED) then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is ------------------------------------------------------------ variable ResultID : AlertLogIDType ; begin ResultID := FindAlertLogID(Name, ParentID) ; if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set ParentID if AlertLogPtr(ResultID).ParentID = ALERTLOG_ID_NOT_ASSIGNED then AlertLogPtr(ResultID).ParentID := ParentID ; -- else -- do not update as ParentIDs are either same or input ParentID = ALERTLOG_ID_NOT_ASSIGNED end if ; else ResultID := GetNextAlertLogID ; NewAlertLogRec(ResultID, Name, ParentID) ; FoundAlertHierVar := TRUE ; if CreateHierarchy then FoundReportHierVar := TRUE ; end if ; end if ; return ResultID ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).ParentID ; end function GetAlertLogParentID ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin GlobalAlertEnabledVar := A ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return GlobalAlertEnabledVar ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCheckCount is ------------------------------------------------------------ begin if GlobalAlertEnabledVar then AffirmCheckCountVar := AffirmCheckCountVar + 1 ; end if ; end procedure IncAffirmCheckCount ; ------------------------------------------------------------ impure function GetAffirmCheckCount return natural is ------------------------------------------------------------ begin return AffirmCheckCountVar ; end function GetAffirmCheckCount ; --?? ------------------------------------------------------------ --?? procedure IncAffirmPassCount is --?? ------------------------------------------------------------ --?? begin --?? if GlobalAlertEnabledVar then --?? AffirmCheckCountVar := AffirmCheckCountVar + 1 ; --?? AffirmPassedCountVar := AffirmPassedCountVar + 1 ; --?? end if ; --?? end procedure IncAffirmPassCount ; --?? --?? ------------------------------------------------------------ --?? impure function GetAffirmPassCount return natural is --?? ------------------------------------------------------------ --?? begin --?? return AffirmPassedCountVar ; --?? end function GetAffirmPassCount ; ------------------------------------------------------------ -- PT LOCAL procedure SetOneStopCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer ) is begin if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ; else AlertLogPtr(AlertLogID).AlertStopCount(Level) := AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ; end if ; end procedure SetOneStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin SetOneStopCount(AlertLogID, Level, Count) ; if AlertLogID /= ALERTLOG_BASE_ID then SetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ; end if ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertStopCount(Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).AlertEnabled(Level) := Enable ; end loop ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetAlertEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertEnabled(Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).LogEnabled(Level) := Enable ; end loop ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetLogEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin if Level = ALWAYS then return TRUE ; else return AlertLogPtr(AlertLogID).LogEnabled(Level) ; end if ; end function GetLogEnable ; ------------------------------------------------------------ -- PT Local procedure PrintLogLevels( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ) is variable buf : line ; begin write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ; for i in LogIndexType loop if AlertLogPtr(AlertLogID).LogEnabled(i) then -- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ; write(buf, " " & to_string(i)) ; end if ; end loop ; WriteLine(buf) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then PrintLogLevels( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2 ) ; end if ; end loop ; end procedure PrintLogLevels ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ; end procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if FailOnWarning /= OPT_INIT_PARM_DETECT then FailOnWarningVar := IsEnabled(FailOnWarning) ; end if ; if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ; end if ; if ReportHierarchy /= OPT_INIT_PARM_DETECT then ReportHierarchyVar := IsEnabled(ReportHierarchy) ; end if ; if WriteAlertLevel /= OPT_INIT_PARM_DETECT then WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ; end if ; if WriteAlertName /= OPT_INIT_PARM_DETECT then WriteAlertNameVar := IsEnabled(WriteAlertName) ; end if ; if WriteAlertTime /= OPT_INIT_PARM_DETECT then WriteAlertTimeVar := IsEnabled(WriteAlertTime) ; end if ; if WriteLogLevel /= OPT_INIT_PARM_DETECT then WriteLogLevelVar := IsEnabled(WriteLogLevel) ; end if ; if WriteLogName /= OPT_INIT_PARM_DETECT then WriteLogNameVar := IsEnabled(WriteLogName) ; end if ; if WriteLogTime /= OPT_INIT_PARM_DETECT then WriteLogTimeVar := IsEnabled(WriteLogTime) ; end if ; if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then AlertPrefixVar.Set(AlertPrefix) ; end if ; if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then LogPrefixVar.Set(LogPrefix) ; end if ; if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then ReportPrefixVar.Set(ReportPrefix) ; end if ; if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then DoneNameVar.Set(DoneName) ; end if ; if PassName /= OSVVM_STRING_INIT_PARM_DETECT then PassNameVar.Set(PassName) ; end if ; if FailName /= OSVVM_STRING_INIT_PARM_DETECT then FailNameVar.Set(FailName) ; end if ; end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ variable buf : line ; begin -- Boolean Values swrite(buf, "ReportAlertLogOptions" & LF ) ; swrite(buf, "---------------------" & LF ) ; swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ; swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ; swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ; swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ; swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ; swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ; swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ; swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ; swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ; -- String swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ; swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ; swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ; swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ; swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ; swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ; writeline(buf) ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnWarningVar) ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(ReportHierarchyVar) ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return FoundReportHierVar ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return FoundAlertHierVar ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertLevelVar) ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertNameVar) ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertTimeVar) ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogLevelVar) ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogNameVar) ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogTimeVar) ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return ResolveOsvvmPassName(PassNameVar.GetOpt) ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return ResolveOsvvmFailName(FailNameVar.GetOpt) ; end function GetAlertLogFailName ; end protected body AlertLogStructPType ; shared variable AlertLogStruct : AlertLogStructPType ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------ procedure Alert( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is begin AlertLogStruct.Alert(AlertLogID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure Alert( Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) is begin AlertLogStruct.IncAlertCount(AlertLogID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure IncAlertCount( Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIf( AlertLogID, condition, Message, Level) ; end procedure AlertIf ; ------------------------------------------------------------ procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ -- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ -- deprecated impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin return AlertIf( AlertLogID, condition, Message, Level) ; end function AlertIf ; ------------------------------------------------------------ impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfNot( AlertLogID, condition, Message, Level) ; end procedure AlertIfNot ; ------------------------------------------------------------ procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ -- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; ------------------------------------------------------------ -- deprecated impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin return AlertIfNot( AlertLogID, condition, Message, Level) ; end function AlertIfNot ; ------------------------------------------------------------ impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; -- With AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; -- Without AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; -- With AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; -- Without AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is -- Open files and call AlertIfDiff[text, ...] ------------------------------------------------------------ file FileID1, FileID2 : text ; variable status1, status2 : file_open_status ; begin file_open(status1, FileID1, Name1, READ_MODE) ; file_open(status2, FileID2, Name2, READ_MODE) ; if status1 = OPEN_OK and status2 = OPEN_OK then AlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level) ; else if status1 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ; end if ; if status2 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ; end if ; end if; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is -- Simple diff. ------------------------------------------------------------ variable Buf1, Buf2 : line ; variable File1Done, File2Done : boolean ; variable LineCount : integer := 0 ; begin ReadLoop : loop File1Done := EndFile(File1) ; File2Done := EndFile(File2) ; exit ReadLoop when File1Done or File2Done ; ReadLine(File1, Buf1) ; ReadLine(File2, Buf2) ; LineCount := LineCount + 1 ; if Buf1.all /= Buf2.all then AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ; exit ReadLoop ; end if ; end loop ReadLoop ; if File1Done /= File2Done then if not File1Done then AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ; end if ; if not File2Done then AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ; end if ; end if; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AffirmIf( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR ) is begin AlertLogStruct.IncAffirmCheckCount ; -- increment check count if condition then -- passed AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log -- AlertLogStruct.IncAffirmPassCount ; -- increment pass & check count else AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure end if ; end procedure AffirmIf ; ------------------------------------------------------------ procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ; end procedure AffirmIf; ------------------------------------------------------------ procedure SetAlertLogJustify is ------------------------------------------------------------ begin AlertLogStruct.SetJustify ; end procedure SetAlertLogJustify ; ------------------------------------------------------------ procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertCount) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ; end procedure ReportNonZeroAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AlertLogStruct.ClearAlerts ; end procedure ClearAlerts ; ------------------------------------------------------------ function "ABS" (L : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := ABS( L(FAILURE) ) ; Result(ERROR) := ABS( L(ERROR) ) ; Result(WARNING) := ABS( L(WARNING) ); return Result ; end function "ABS" ; ------------------------------------------------------------ function "+" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) + R(FAILURE) ; Result(ERROR) := L(ERROR) + R(ERROR) ; Result(WARNING) := L(WARNING) + R(WARNING) ; return Result ; end function "+" ; ------------------------------------------------------------ function "-" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) - R(FAILURE) ; Result(ERROR) := L(ERROR) - R(ERROR) ; Result(WARNING) := L(WARNING) - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ function "-" (R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := - R(FAILURE) ; Result(ERROR) := - R(ERROR) ; Result(WARNING) := - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ impure function SumAlertCount(AlertCount: AlertCountType) return integer is ------------------------------------------------------------ begin -- Using ABS ensures correct expected error handling. return abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ; end function SumAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertCount(AlertLogID) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetEnabledAlertCount(AlertLogID) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount(AlertLogID) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is ------------------------------------------------------------ begin AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertLogName(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogName(AlertLogID) ; end GetAlertLogName ; ------------------------------------------------------------ procedure DeallocateAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Deallocate ; end procedure DeallocateAlertLogStruct ; ------------------------------------------------------------ procedure InitializeAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Initialize ; end procedure InitializeAlertLogStruct ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name, ParentID) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogParentID(AlertLogID) ; end function GetAlertLogParentID ; ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ -- Set using constant. Set before code runs. impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; return A ; end function SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetGlobalAlertEnable ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCheckCount is ------------------------------------------------------------ begin AlertLogStruct.IncAffirmCheckCount ; end procedure IncAffirmCheckCount ; ------------------------------------------------------------ impure function GetAffirmCheckCount return natural is ------------------------------------------------------------ begin return AlertLogStruct.GetAffirmCheckCount ; end function GetAffirmCheckCount ; --?? ------------------------------------------------------------ --?? procedure IncAffirmPassCount is --?? ------------------------------------------------------------ --?? begin --?? AlertLogStruct.IncAffirmPassCount ; --?? end procedure IncAffirmPassCount ; --?? --?? ------------------------------------------------------------ --?? impure function GetAffirmPassCount return natural is --?? ------------------------------------------------------------ --?? begin --?? return AlertLogStruct.GetAffirmPassCount ; --?? end function GetAffirmPassCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(Level, Enable) ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(AlertLogID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(Level, Enable) ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(AlertLogID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(AlertLogID, Level) ; end function IsLoggingEnabled ; ------------------------------------------------------------ impure function IsLoggingEnabled(Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ; end function IsLoggingEnabled ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin AlertLogStruct.ReportLogEnables ; end ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin AlertLogStruct.SetAlertLogOptions ( FailOnWarning => FailOnWarning , FailOnDisabledErrors => FailOnDisabledErrors, ReportHierarchy => ReportHierarchy , WriteAlertLevel => WriteAlertLevel , WriteAlertName => WriteAlertName , WriteAlertTime => WriteAlertTime , WriteLogLevel => WriteLogLevel , WriteLogName => WriteLogName , WriteLogTime => WriteLogTime , AlertPrefix => AlertPrefix , LogPrefix => LogPrefix , ReportPrefix => ReportPrefix , DoneName => DoneName , PassName => PassName , FailName => FailName ); end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ begin AlertLogStruct.ReportAlertLogOptions ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnWarning ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnDisabledErrors ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportHierarchy ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundReportHier ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundAlertHier ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertLevel ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertName ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertTime ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogLevel ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogName ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogTime ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogAlertPrefix ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogLogPrefix ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportPrefix ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogDoneName ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogPassName ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailName ; end function GetAlertLogFailName ; ------------------------------------------------------------ function IsLogEnableType (Name : String) return boolean is ------------------------------------------------------------ -- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER begin if Name = "PASSED" then return TRUE ; elsif Name = "DEBUG" then return TRUE ; elsif Name = "FINAL" then return TRUE ; elsif Name = "INFO" then return TRUE ; end if ; return FALSE ; end function IsLogEnableType ; ------------------------------------------------------------ procedure ReadLogEnables (file AlertLogInitFile : text) is -- Preferred Read format -- Line 1: instance1_name log_enable log_enable log_enable -- Line 2: instance2_name log_enable log_enable log_enable -- when reading multiple log_enables on a line, they must be separated by a space -- --- Also supports alternate format from Lyle/.... -- Line 1: instance1_name -- Line 2: log enable -- Line 3: instance2_name -- Line 4: log enable -- ------------------------------------------------------------ type ReadStateType is (GET_ID, GET_ENABLE) ; variable ReadState : ReadStateType := GET_ID ; variable buf : line ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; variable Name : string(1 to 80) ; variable NameLen : integer ; variable AlertLogID : AlertLogIDType ; variable ReadAnEnable : boolean ; variable LogLevel : LogType ; begin ReadState := GET_ID ; ReadLineLoop : while not EndFile(AlertLogInitFile) loop ReadLine(AlertLogInitFile, buf) ; if ReadAnEnable then -- Read one or more enable values, next line read AlertLog name -- Note that any newline with ReadAnEnable TRUE will result in -- searching for another AlertLogID name - this includes multi-line comments. ReadState := GET_ID ; end if ; ReadNameLoop : loop EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next ReadLineLoop when Empty ; case ReadState is when GET_ID => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ; ReadState := GET_ENABLE ; ReadAnEnable := FALSE ; when GET_ENABLE => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; ReadAnEnable := TRUE ; if not IsLogEnableType(Name(1 to NameLen)) then Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ; exit ReadNameLoop ; end if ; LogLevel := LogType'value(Name(1 to NameLen)) ; SetLogEnable(AlertLogID, LogLevel, TRUE) ; end case ; end loop ReadNameLoop ; end loop ReadLineLoop ; end procedure ReadLogEnables ; ------------------------------------------------------------ procedure ReadLogEnables (FileName : string) is ------------------------------------------------------------ file AlertLogInitFile : text open READ_MODE is FileName ; begin ReadLogEnables(AlertLogInitFile) ; end procedure ReadLogEnables ; ------------------------------------------------------------ function PathTail (A : string) return string is ------------------------------------------------------------ alias aA : string(1 to A'length) is A ; begin for i in aA'length - 1 downto 1 loop if aA(i) = ':' then return aA(i+1 to aA'length-1) ; end if ; end loop ; return aA ; end function PathTail ; end package body AlertLogPkg ;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: inpad -- File: inpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: input pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity inpad is generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v; filter : integer := 0; strength : integer := 0); port (pad : in std_ulogic; o : out std_ulogic); end; architecture rtl of inpad is begin gen0 : if has_pads(tech) = 0 generate o <= transport to_X01(pad) -- pragma translate_off after 1 ns -- pragma translate_on ; end generate; xcv : if (is_unisim(tech) = 1) generate x0 : unisim_inpad generic map (level, voltage) port map (pad, o); end generate; axc : if (tech = axcel) or (tech = axdsp) generate x0 : axcel_inpad generic map (level, voltage) port map (pad, o); end generate; pa3 : if (tech = proasic) or (tech = apa3) generate x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o); end generate; pa3e : if (tech = apa3e) generate x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o); end generate; igl2 : if (tech = igloo2) generate x0 : igloo2_inpad port map (pad, o); end generate; pa3l : if (tech = apa3l) generate x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o); end generate; fus : if (tech = actfus) generate x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o); end generate; atc : if (tech = atc18s) generate x0 : atc18_inpad generic map (level, voltage) port map (pad, o); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o); end generate; um : if (tech = umc) generate x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; saed : if (tech = saed32) generate x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o); end generate; rhs : if (tech = rhs65) generate x0 : rhs65_inpad generic map (level, voltage, filter) port map (pad, o); end generate; dar : if (tech = dare) generate x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_inpad generic map(level, voltage) port map(pad, o); end generate; ihprh : if (tech = ihp25rh) generate x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o); end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o); end generate; ut13 : if (tech = ut130) generate x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; pereg : if (tech = peregrine) generate x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o); end generate; eas : if (tech = easic90) generate x0 : nextreme_inpad generic map (level, voltage) port map (pad, o); end generate; n2x : if (tech = easic45) generate x0 : n2x_inpad generic map (level, voltage) port map (pad, o); end generate; ut90nhbd : if (tech = ut90) generate x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity inpadv is generic (tech : integer := 0; level : integer := 0; voltage : integer := 0; width : integer := 1; filter : integer := 0; strength : integer := 0); port ( pad : in std_logic_vector(width-1 downto 0); o : out std_logic_vector(width-1 downto 0)); end; architecture rtl of inpadv is begin v : for i in width-1 downto 0 generate x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i)); end generate; end;
---------------------------------------------------------------------------------- -- Engineer: Longofono -- -- Create Date: 02/04/2018 02:45:16 PM -- Module Name: load_store - Behavioral -- Description: Handles loading, storing, and signalling between core, control, and MMU -- -- Additional Comments: -- If storing, addr will be the MMU destination address and data will be the data to be written there -- If loading, addr will be the MMU source address and data will be an encoding of the number of bytes to load -- Encoding is as follows: -- One byte (LB, LBU) -> 0x0 -- Two bytes (LH, LHU) -> 0x1 -- Four bytes (LW, LWU) -> 0x2 -- Eight bytes (LD) -> 0x3 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library config; use work.config.all; -- If loading, we need to know: -- Memory address to load from (register file holds base, instruction holds offset -- Register address to load to -- If storing, we need to know: -- Register address to store from -- Memory address to store to (register file holds base, instruction holds offset entity load_store is Port( instr: in instr_t; -- Current instruction type imm12: in std_logic_vector(11 downto 0); -- offset value rs1: in reg_t; -- rs1 for S-type and I-type rs2: in reg_t; -- rs2 for S-type addr: out doubleword; -- Destination address data: out doubleword -- Data to be stored ); end load_store; architecture Behavioral of load_store is -- Latch for modifying data and address piecewise signal s_data: doubleword; signal s_addr: doubleword; begin process(instr) begin -- Encoding for load data is as follows: -- One byte (LB, LBU) -> 0x0 -- Two bytes (LH, LHU) -> 0x1 -- Four bytes (LW, LWU) -> 0x2 -- Eight bytes (LD) -> 0x3 case instr is when instr_LB => -- Load byte s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (others => '0'); when instr_LBU => -- Load byte, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (others => '0'); when instr_LD => -- Load doubleword s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 downto 0 => '1', others => '0'); when instr_LH => -- Load half word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (0 => '1', others => '0'); when instr_LHU => -- Load half word, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (0 => '1', others => '0'); when instr_LW => -- Load word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 => '1', others => '0'); when instr_LWU => -- Load word, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 => '1', others => '0'); when instr_SB => -- Store byte s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 8) <= (others => '0'); s_data(7 downto 0) <= rs2(7 downto 0); when instr_SD => -- Store doubleword s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= rs2; when instr_SH => -- Store half word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 16) <= (others => '0'); s_data(15 downto 0) <= rs2(15 downto 0); when instr_SW => -- Store word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 32) <= (others => '0'); s_data(31 downto 0) <= rs2(31 downto 0); when others => s_addr <= (others => '0'); s_data <= (others => '0'); end case; data <= s_data; addr <= s_addr; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.plasoc_gpio_pack.all; entity koc_lock is generic ( axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width. axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width. axi_control_offset : integer := 0; --! Defines the offset for the Control register. control_default : integer := 1 ); port ( aclk : in std_logic; --! Clock. Tested with 50 MHz. aresetn : in std_logic; -- Slave AXI4-Lite Write interface. axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal. axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal. axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal. axi_awready : out std_logic; --! AXI4-Lite Address Write signal. axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal. axi_wready : out std_logic; --! AXI4-Lite Write Data signal. axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal. axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal. axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal. axi_bready : in std_logic; --! AXI4-Lite Write Response signal. axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal. -- Slave AXI4-Lite Read interface. axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal. axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal. axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal. axi_arready : out std_logic; --! AXI4-Lite Address Read signal. axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal. axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal. axi_rready : in std_logic; --! AXI4-Lite Read Data signal. axi_rresp : out std_logic_vector(1 downto 0) ); end koc_lock; architecture Behavioral of koc_lock is component koc_lock_axi4_write_cntrl is generic ( axi_address_width : integer := 16; axi_data_width : integer := 32; reg_control_offset : std_logic_vector := X"0000"; reg_control_default : std_logic_vector := X"00000001" ); port ( aclk : in std_logic; aresetn : in std_logic; axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); axi_awprot : in std_logic_vector(2 downto 0); axi_awvalid : in std_logic; axi_awready : out std_logic; axi_wvalid : in std_logic; axi_wready : out std_logic; axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); axi_bvalid : out std_logic; axi_bready : in std_logic; axi_bresp : out std_logic_vector(1 downto 0); reg_control : out std_logic_vector(axi_data_width-1 downto 0) ); end component; component koc_lock_axi4_read_cntrl is generic ( axi_address_width : integer := 16; axi_data_width : integer := 32; reg_control_offset : std_logic_vector := X"0000" ); port ( aclk : in std_logic; aresetn : in std_logic; axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal. axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal. axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal. axi_arready : out std_logic; --! AXI4-Lite Address Read signal. axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal. axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal. axi_rready : in std_logic; --! AXI4-Lite Read Data signal. axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal. reg_control : in std_logic_vector(axi_data_width-1 downto 0) ); end component; constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width)); constant control_default_slv : std_logic_vector := std_logic_vector(to_unsigned(control_default,axi_data_width)); signal reg_control : std_logic_vector(axi_data_width-1 downto 0); begin koc_lock_axi4_write_cntrl_inst : koc_lock_axi4_write_cntrl generic map ( axi_address_width => axi_address_width, axi_data_width => axi_data_width, reg_control_offset => axi_control_offset_slv, reg_control_default => control_default_slv) port map ( aclk => aclk, aresetn => aresetn, axi_awaddr => axi_awaddr, axi_awprot => axi_awprot, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_wvalid => axi_wvalid, axi_wready => axi_wready, axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bresp => axi_bresp, reg_control => reg_control); koc_lock_axi4_read_cntrl_inst : koc_lock_axi4_read_cntrl generic map ( axi_address_width => axi_address_width, axi_data_width => axi_data_width, reg_control_offset => axi_control_offset_slv) port map ( aclk => aclk, aresetn => aresetn, axi_araddr => axi_araddr, axi_arprot => axi_arprot, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_rdata => axi_rdata, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rresp => axi_rresp, reg_control => reg_control); end Behavioral;
-------------------------------------------------------------------------------- --Author: Jay Aurabind --Email : [email protected] -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity synchro is Port ( x1 : in STD_LOGIC; x2 : in STD_LOGIC; x3 : in STD_LOGIC; y1 : in STD_LOGIC; y2 : in STD_LOGIC; y3 : in STD_LOGIC; vcomp, rst : in STD_LOGIC; phase : inout STD_LOGIC; freq : inout STD_LOGIC; voltage : inout STD_LOGIC; inst : out STD_LOGIC; clock : in std_logic); end synchro; architecture Behavioral of synchro is COMPONENT pulse_counter PORT( Pulse_I : IN std_logic; CLK_I : IN std_logic; DAT_O : OUT std_logic_vector(63 downto 0); ERR_O : OUT std_logic ); END COMPONENT; signal error_x, error_y, freq_temp,posedge_x, posedge_y : std_logic; signal x1_store, y1_store : std_logic; signal countx,county : std_logic_vector(63 downto 0) :=(others => '0'); begin --architecture begins Inst_pulse_counter_X1: pulse_counter PORT MAP( DAT_O => countx, ERR_O => error_x, Pulse_I => x1, CLK_I => clock ); Inst_pulse_counter_Y1: pulse_counter PORT MAP( DAT_O => county, ERR_O => error_y, Pulse_I => y1, CLK_I => clock ); --phase seq process(x1,x2,x3, y1,y2,y3) variable xph, yph : std_logic_vector(1 downto 0) := "00"; begin if x1'event and x1='1' then xph := x2 & x3; end if; if y1'event and y1='1' then yph := y2 & y3; end if; if xph=yph then phase <= '1'; else phase <= '0'; end if; end process; --comparasion-- process(countx,county,rst) variable temp_var, temp : std_logic_vector(63 downto 0); begin if rst = '1' then freq_temp <= '0'; else --flag1 comes from a component instantiation statement at the top temp_var := (countx - county); temp := "000000" & countx(63 downto 6); if (temp_var <= temp) then freq_temp <= '1'; else freq_temp <='0'; end if; end if; end process; freq <= freq_temp and (not error_x) and (not error_y); --rdy is high when division is completed --voltage-- voltage <= vcomp; --instant inphase-- process(clock) --process to store x1 and y1 begin if clock'event and clock ='1' then if rst = '1' then x1_store <= '0'; y1_store <= '0'; else x1_store <= x1; y1_store <= y1; end if; end if; end process; --process to create a pulse at positive edge of both x1 and y1 process(x1_store, x1, y1_store, y1) begin posedge_x <= x1 and (not x1_store); posedge_y <= y1 and (not y1_store); end process; process(phase,freq,voltage,posedge_x, posedge_y,error_x,error_y) begin inst <= posedge_x and posedge_y and phase and freq and voltage; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity idreadback is Generic ( id : std_logic_vector(31 downto 0); mc : std_logic_vector(31 downto 0)); Port ( readid : in std_logic; readmc : in std_logic; obus : out std_logic_vector(31 downto 0)); end idreadback; architecture Behavioral of idreadback is begin areadidprocess: process (readid, readmc) begin if readid = '1' and readmc = '0' then obus <= id; elsif readmc = '1' and readid = '0' then obus <= mc; else obus <= (others => 'Z'); end if; end process areadidprocess; end Behavioral;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY async_fifo_align_64in_out IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; valid : OUT STD_LOGIC ); END async_fifo_align_64in_out; ARCHITECTURE async_fifo_align_64in_out_arch OF async_fifo_align_64in_out IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF async_fifo_align_64in_out_arch : ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=510,C_PROG_FULL_THRESH_NEGATE_VAL=509,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 9, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "virtex7", C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 1, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 510, C_PROG_FULL_THRESH_NEGATE_VAL => 509, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 9, C_RD_DEPTH => 512, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 9, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 9, C_WR_DEPTH => 512, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 9, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => rst, srst => '0', wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, valid => valid, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END async_fifo_align_64in_out_arch;
package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;
package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;
package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;
package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;
package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
architecture rtl of fifo is begin connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow ); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow ); connect_ports ( port_1 => data , port_2 => enable, port_3 => overflow , port_4 => underflow ); process begin connect_ports( port_1 => data, port_2=> enable, port_3 => overflow, port_4 => underflow ); end process; end architecture;
-- -- This file is part of the lafw16 project. -- -- Copyright (C) 2014-2015 Gregor Anich -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_clockmux is end test_clockmux; architecture behavior of test_clockmux is -- Component Declaration for the Unit Under Test (UUT) component clockmux port( clk_ctl : in std_logic; clk_sel : in std_logic_vector(1 downto 0); clk_in : in std_logic_vector(3 downto 0); clk_out : out std_logic ); end component; --Inputs signal clk_ctl : std_logic := '0'; signal clk_sel : unsigned(1 downto 0) := (others => '0'); signal clk_in : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal clk_out : std_logic; -- Clock period definitions constant clk_ctl_period : time := 10 ns; constant clk_in_0_period : time := 3 ns; constant clk_in_1_period : time := 17 ns; constant clk_in_2_period : time := 37 ns; constant clk_in_3_period : time := 113 ns; begin -- Instantiate the Unit Under Test (UUT) uut: clockmux port map ( clk_ctl => clk_ctl, clk_sel => std_logic_vector(clk_sel), clk_in => clk_in, clk_out => clk_out ); -- Clock process definitions clk_ctl_process :process begin clk_ctl <= '0'; wait for clk_ctl_period/2; clk_ctl <= '1'; wait for clk_ctl_period/2; end process; clk_in_0_process :process begin clk_in(0) <= '0'; wait for clk_in_0_period/2; clk_in(0) <= '1'; wait for clk_in_0_period/2; end process; clk_in_1_process :process begin clk_in(1) <= '0'; wait for clk_in_1_period/2; clk_in(1) <= '1'; wait for clk_in_1_period/2; end process; clk_in_2_process :process begin clk_in(2) <= '0'; wait for clk_in_2_period/2; clk_in(2) <= '1'; wait for clk_in_2_period/2; end process; clk_in_3_process :process begin clk_in(3) <= '0'; wait for clk_in_3_period/2; clk_in(3) <= '1'; wait for clk_in_3_period/2; end process; -- Stimulus process stim_proc: process begin clk_sel <= to_unsigned(0, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(1, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(2, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(3, clk_sel'length); wait for 1 us; wait; end process; end;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_07_01 is end entity ch_07_01; ---------------------------------------------------------------- architecture test of ch_07_01 is begin process_07_2_a : process is type t1 is (t1_1, t1_2); type t2 is (t2_1, t2_2); type t3 is (t3_1, t3_2); type t4 is (t4_1, t4_2); constant v4 : t4 := t4_1; constant val1 : t1 := t1_1; constant val2 : t2 := t2_1; variable var3 : t3 := t3_1; constant val4 : t4 := t4_1; -- code from book: procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is begin -- . . . end procedure p; -- end of code from book begin -- code from book: p ( val1, val2, var3, val4 ); p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 ); p ( val1, val2, f4 => open, f3 => var3 ); p ( val1, val2, var3 ); -- end of code from book wait; end process process_07_2_a; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_07_01 is end entity ch_07_01; ---------------------------------------------------------------- architecture test of ch_07_01 is begin process_07_2_a : process is type t1 is (t1_1, t1_2); type t2 is (t2_1, t2_2); type t3 is (t3_1, t3_2); type t4 is (t4_1, t4_2); constant v4 : t4 := t4_1; constant val1 : t1 := t1_1; constant val2 : t2 := t2_1; variable var3 : t3 := t3_1; constant val4 : t4 := t4_1; -- code from book: procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is begin -- . . . end procedure p; -- end of code from book begin -- code from book: p ( val1, val2, var3, val4 ); p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 ); p ( val1, val2, f4 => open, f3 => var3 ); p ( val1, val2, var3 ); -- end of code from book wait; end process process_07_2_a; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_07_01 is end entity ch_07_01; ---------------------------------------------------------------- architecture test of ch_07_01 is begin process_07_2_a : process is type t1 is (t1_1, t1_2); type t2 is (t2_1, t2_2); type t3 is (t3_1, t3_2); type t4 is (t4_1, t4_2); constant v4 : t4 := t4_1; constant val1 : t1 := t1_1; constant val2 : t2 := t2_1; variable var3 : t3 := t3_1; constant val4 : t4 := t4_1; -- code from book: procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is begin -- . . . end procedure p; -- end of code from book begin -- code from book: p ( val1, val2, var3, val4 ); p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 ); p ( val1, val2, f4 => open, f3 => var3 ); p ( val1, val2, var3 ); -- end of code from book wait; end process process_07_2_a; end architecture test;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PuPIP0VhRYOvmy3YQKBtmK2n6y8D0dWiKhfOFbgKPAexbIleKocvnRl8Y184WIBVZmvl7McO6xqh oSNkJUw1rw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bmWXy3fu5Cr8p9ffB3MhQuVIAxp3JSY9+rqQTwkcvIRwgJOQ1p+ZmYgQfTBIrKURt1Xa0KLubUnA 4EPlmILaIIwaoYgJK3KOShUZWEZt28lTZjreYRdC2SYMsT1E5Uia0fI/FUmtjfEQWKDVmgyTGBsb /k/6l6ocSG4L6fNbp1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block WmqfpMmbXQfU2YRufkLgK09mJpEAJbZF5nSHz9WR7unOpyiYZQczRy4AtWqL1tgnVC57J8rF3jY+ OXslCKFoqLCbTHyEpCKEAYFABHey1DDk+n3JP8jqWkeUbVpmHy6D/Gisy+nx2NsiXtkhfRJqeYyJ Ar0PRgROgNLIYnYH3Ko/CfukjGauLqyjUixZ1ZjqlXZTczot5SEnyuUy2OrDJU+VyrC/pVlt+ed1 QZ1RVmGXnlyEATObg44m+8kLdvNVZ7qnHea0cpJX/gS/SUUtrIZAT5VCGfaN74HB1Q+98xjn2vag DvRPTBDdbmzKYMn+A4VWqaWgfBDu+yerU5ElMw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block xlQC4c0ATnsrb9hZyDH1Ac/lKNHa6X1E+DtMc58EVNeiHtJuPvZDKwAuLpndAyOrDlw/v7RpuRco oiFeiyUvAg5m4JcVX/6P/ZUTd4u9ezRCXDJlHtlSFyoghKzHOqP85Pgr17glzp0YY+1LD7Z1C6YU 6JfuWQhwjf9PeaQki8c= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block UCkL2mBglOLzuPuHAcPj+nhS7wzoMsgL8YLVs45sPzz7+nHPjPcBObryn3a5WTYET2zyAelRdGW6 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PuPIP0VhRYOvmy3YQKBtmK2n6y8D0dWiKhfOFbgKPAexbIleKocvnRl8Y184WIBVZmvl7McO6xqh oSNkJUw1rw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bmWXy3fu5Cr8p9ffB3MhQuVIAxp3JSY9+rqQTwkcvIRwgJOQ1p+ZmYgQfTBIrKURt1Xa0KLubUnA 4EPlmILaIIwaoYgJK3KOShUZWEZt28lTZjreYRdC2SYMsT1E5Uia0fI/FUmtjfEQWKDVmgyTGBsb /k/6l6ocSG4L6fNbp1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PuPIP0VhRYOvmy3YQKBtmK2n6y8D0dWiKhfOFbgKPAexbIleKocvnRl8Y184WIBVZmvl7McO6xqh oSNkJUw1rw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bmWXy3fu5Cr8p9ffB3MhQuVIAxp3JSY9+rqQTwkcvIRwgJOQ1p+ZmYgQfTBIrKURt1Xa0KLubUnA 4EPlmILaIIwaoYgJK3KOShUZWEZt28lTZjreYRdC2SYMsT1E5Uia0fI/FUmtjfEQWKDVmgyTGBsb /k/6l6ocSG4L6fNbp1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block WmqfpMmbXQfU2YRufkLgK09mJpEAJbZF5nSHz9WR7unOpyiYZQczRy4AtWqL1tgnVC57J8rF3jY+ OXslCKFoqLCbTHyEpCKEAYFABHey1DDk+n3JP8jqWkeUbVpmHy6D/Gisy+nx2NsiXtkhfRJqeYyJ Ar0PRgROgNLIYnYH3Ko/CfukjGauLqyjUixZ1ZjqlXZTczot5SEnyuUy2OrDJU+VyrC/pVlt+ed1 QZ1RVmGXnlyEATObg44m+8kLdvNVZ7qnHea0cpJX/gS/SUUtrIZAT5VCGfaN74HB1Q+98xjn2vag DvRPTBDdbmzKYMn+A4VWqaWgfBDu+yerU5ElMw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block xlQC4c0ATnsrb9hZyDH1Ac/lKNHa6X1E+DtMc58EVNeiHtJuPvZDKwAuLpndAyOrDlw/v7RpuRco oiFeiyUvAg5m4JcVX/6P/ZUTd4u9ezRCXDJlHtlSFyoghKzHOqP85Pgr17glzp0YY+1LD7Z1C6YU 6JfuWQhwjf9PeaQki8c= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block UCkL2mBglOLzuPuHAcPj+nhS7wzoMsgL8YLVs45sPzz7+nHPjPcBObryn3a5WTYET2zyAelRdGW6 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PuPIP0VhRYOvmy3YQKBtmK2n6y8D0dWiKhfOFbgKPAexbIleKocvnRl8Y184WIBVZmvl7McO6xqh oSNkJUw1rw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bmWXy3fu5Cr8p9ffB3MhQuVIAxp3JSY9+rqQTwkcvIRwgJOQ1p+ZmYgQfTBIrKURt1Xa0KLubUnA 4EPlmILaIIwaoYgJK3KOShUZWEZt28lTZjreYRdC2SYMsT1E5Uia0fI/FUmtjfEQWKDVmgyTGBsb /k/6l6ocSG4L6fNbp1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_timer:2.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_timer_v2_0; USE axi_timer_v2_0.axi_timer; ENTITY system_axi_timer_0_0 IS PORT ( capturetrig0 : IN STD_LOGIC; capturetrig1 : IN STD_LOGIC; generateout0 : OUT STD_LOGIC; generateout1 : OUT STD_LOGIC; pwm0 : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; freeze : IN STD_LOGIC; s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC ); END system_axi_timer_0_0; ARCHITECTURE system_axi_timer_0_0_arch OF system_axi_timer_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_timer_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_timer IS GENERIC ( C_FAMILY : STRING; C_COUNT_WIDTH : INTEGER; C_ONE_TIMER_ONLY : INTEGER; C_TRIG0_ASSERT : STD_LOGIC; C_TRIG1_ASSERT : STD_LOGIC; C_GEN0_ASSERT : STD_LOGIC; C_GEN1_ASSERT : STD_LOGIC; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER ); PORT ( capturetrig0 : IN STD_LOGIC; capturetrig1 : IN STD_LOGIC; generateout0 : OUT STD_LOGIC; generateout1 : OUT STD_LOGIC; pwm0 : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; freeze : IN STD_LOGIC; s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC ); END COMPONENT axi_timer; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; BEGIN U0 : axi_timer GENERIC MAP ( C_FAMILY => "zynq", C_COUNT_WIDTH => 32, C_ONE_TIMER_ONLY => 0, C_TRIG0_ASSERT => '1', C_TRIG1_ASSERT => '1', C_GEN0_ASSERT => '1', C_GEN1_ASSERT => '1', C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ADDR_WIDTH => 5 ) PORT MAP ( capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, generateout0 => generateout0, generateout1 => generateout1, pwm0 => pwm0, interrupt => interrupt, freeze => freeze, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); END system_axi_timer_0_0_arch;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity convolve_kernel is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_EN_A : OUT STD_LOGIC; bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufw_Clk_A : OUT STD_LOGIC; bufw_Rst_A : OUT STD_LOGIC; bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_EN_A : OUT STD_LOGIC; bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufi_Clk_A : OUT STD_LOGIC; bufi_Rst_A : OUT STD_LOGIC; bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_EN_A : OUT STD_LOGIC; bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufo_Clk_A : OUT STD_LOGIC; bufo_Rst_A : OUT STD_LOGIC ); end; architecture behav of convolve_kernel is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=38509,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=1433,HLS_SYN_LUT=1252}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000100000"; constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000001000000"; constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000010000000"; constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000100000000"; constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000001000000000"; constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000010000000000"; constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000100000000000"; constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000001000000000000"; constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000010000000000000"; constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000100000000000000"; constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000001000000000000000"; constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000010000000000000000"; constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000100000000000000000"; constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (29 downto 0) := "000000000001000000000000000000"; constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (29 downto 0) := "000000000010000000000000000000"; constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (29 downto 0) := "000000000100000000000000000000"; constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (29 downto 0) := "000000001000000000000000000000"; constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (29 downto 0) := "000000010000000000000000000000"; constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (29 downto 0) := "000000100000000000000000000000"; constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (29 downto 0) := "000001000000000000000000000000"; constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (29 downto 0) := "000010000000000000000000000000"; constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (29 downto 0) := "000100000000000000000000000000"; constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (29 downto 0) := "001000000000000000000000000000"; constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (29 downto 0) := "010000000000000000000000000000"; constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (29 downto 0) := "100000000000000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101"; constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_CS_fsm : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal to_b_V_fu_201_p2 : STD_LOGIC_VECTOR (1 downto 0); signal to_b_V_reg_479 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal tmp_16_cast_fu_229_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_cast_reg_484 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_fu_195_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ti_b_V_fu_239_p2 : STD_LOGIC_VECTOR (1 downto 0); signal ti_b_V_reg_493 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none"; signal tmp_4_fu_249_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_4_reg_498 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_2_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_266_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_reg_504 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_11_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_11_reg_509 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none"; signal tmp_21_cast_fu_292_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_21_cast_reg_514 : STD_LOGIC_VECTOR (6 downto 0); signal row_b_V_fu_301_p2 : STD_LOGIC_VECTOR (1 downto 0); signal row_b_V_reg_522 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none"; signal tmp_17_fu_311_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_17_reg_527 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_5_fu_295_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_321_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_19_reg_533 : STD_LOGIC_VECTOR (5 downto 0); signal ap_CS_fsm_state6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none"; signal tmp_7_cast_fu_326_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_7_cast_reg_538 : STD_LOGIC_VECTOR (2 downto 0); signal col_b_V_fu_336_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_b_V_reg_546 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none"; signal bufo_addr_reg_551 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_8_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_cast_fu_356_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_cast_reg_556 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none"; signal i_V_fu_366_p2 : STD_LOGIC_VECTOR (2 downto 0); signal i_V_reg_569 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none"; signal tmp_22_fu_381_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_22_reg_574 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_3_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_385_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_23_reg_579 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_9_fu_389_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_9_reg_584 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_24_fu_401_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_24_reg_589 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none"; signal tmp_25_fu_409_p2 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_25_reg_594 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_26_fu_414_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_26_reg_599 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_27_fu_428_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_27_reg_604 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none"; signal j_V_fu_440_p2 : STD_LOGIC_VECTOR (2 downto 0); signal j_V_reg_612 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none"; signal tmp_28_fu_450_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_28_reg_617 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_10_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_fu_455_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_12_reg_622 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_29_fu_463_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_reg_627 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none"; signal ap_CS_fsm_state15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none"; signal bufw_load_reg_642 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none"; signal bufi_load_reg_647 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_191_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_reg_652 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none"; signal grp_fu_186_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none"; signal p_s_reg_95 : STD_LOGIC_VECTOR (1 downto 0); signal p_1_reg_106 : STD_LOGIC_VECTOR (1 downto 0); signal p_2_reg_117 : STD_LOGIC_VECTOR (1 downto 0); signal p_3_reg_129 : STD_LOGIC_VECTOR (1 downto 0); signal p_4_reg_141 : STD_LOGIC_VECTOR (2 downto 0); signal temp1_reg_152 : STD_LOGIC_VECTOR (31 downto 0); signal p_5_reg_162 : STD_LOGIC_VECTOR (2 downto 0); signal temp_1_reg_173 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_25_cast_fu_351_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_32_cast_fu_468_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_33_cast_fu_472_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none"; signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none"; signal ap_CS_fsm_state17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none"; signal tmp_s_fu_211_p3 : STD_LOGIC_VECTOR (3 downto 0); signal p_shl_cast_fu_219_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_cast_fu_207_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_fu_223_p2 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_4_cast_fu_245_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_15_fu_254_p3 : STD_LOGIC_VECTOR (4 downto 0); signal p_shl1_cast_fu_262_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_7_fu_275_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_cast_fu_272_p1 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl2_fu_282_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_cast8_fu_307_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_18_fu_316_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_cast7_fu_342_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_20_fu_346_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_6_fu_372_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_21_fu_376_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl5_cast_fu_394_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_9_cast_cast_fu_406_p1 : STD_LOGIC_VECTOR (6 downto 0); signal p_shl4_cast_fu_421_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_cast_fu_418_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_11_cast_fu_446_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_12_cast_cast_fu_460_p1 : STD_LOGIC_VECTOR (8 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (29 downto 0); component convolve_kernel_fbkb IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component convolve_kernel_fcud IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin convolve_kernel_fbkb_U0 : component convolve_kernel_fbkb generic map ( ID => 1, NUM_STAGE => 9, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => temp_1_reg_173, din1 => tmp_13_reg_652, ce => ap_const_logic_1, dout => grp_fu_186_p2); convolve_kernel_fcud_U1 : component convolve_kernel_fcud generic map ( ID => 1, NUM_STAGE => 5, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => bufw_load_reg_642, din1 => bufi_load_reg_647, ce => ap_const_logic_1, dout => grp_fu_191_p2); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; p_1_reg_106_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then p_1_reg_106 <= ti_b_V_reg_493; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then p_1_reg_106 <= ap_const_lv2_0; end if; end if; end process; p_2_reg_117_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then p_2_reg_117 <= row_b_V_reg_522; elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then p_2_reg_117 <= ap_const_lv2_0; end if; end if; end process; p_3_reg_129_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then p_3_reg_129 <= col_b_V_reg_546; elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then p_3_reg_129 <= ap_const_lv2_0; end if; end if; end process; p_4_reg_141_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then p_4_reg_141 <= i_V_reg_569; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then p_4_reg_141 <= ap_const_lv3_0; end if; end if; end process; p_5_reg_162_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then p_5_reg_162 <= j_V_reg_612; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then p_5_reg_162 <= ap_const_lv3_0; end if; end if; end process; p_s_reg_95_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then p_s_reg_95 <= to_b_V_reg_479; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then p_s_reg_95 <= ap_const_lv2_0; end if; end if; end process; temp1_reg_152_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then temp1_reg_152 <= temp_1_reg_173; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then temp1_reg_152 <= bufo_Dout_A; end if; end if; end process; temp_1_reg_173_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then temp_1_reg_173 <= grp_fu_186_p2; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then temp_1_reg_173 <= temp1_reg_152; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state16)) then bufi_load_reg_647 <= bufi_Dout_A; bufw_load_reg_642 <= bufw_Dout_A; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_0 = tmp_8_fu_330_p2))) then bufo_addr_reg_551 <= tmp_25_cast_fu_351_p1(5 - 1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state7)) then col_b_V_reg_546 <= col_b_V_fu_336_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state10)) then i_V_reg_569 <= i_V_fu_366_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state13)) then j_V_reg_612 <= j_V_fu_440_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state5)) then row_b_V_reg_522 <= row_b_V_fu_301_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state3)) then ti_b_V_reg_493 <= ti_b_V_fu_239_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state4)) then tmp_11_reg_509 <= tmp_11_fu_286_p2; tmp_21_cast_reg_514 <= tmp_21_cast_fu_292_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = tmp_10_fu_434_p2))) then tmp_12_reg_622 <= tmp_12_fu_455_p2; tmp_28_reg_617 <= tmp_28_fu_450_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state21)) then tmp_13_reg_652 <= grp_fu_191_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then tmp_16_cast_reg_484 <= tmp_16_cast_fu_229_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_2_fu_233_p2))) then tmp_16_reg_504 <= tmp_16_fu_266_p2; tmp_4_reg_498 <= tmp_4_fu_249_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_5_fu_295_p2))) then tmp_17_reg_527 <= tmp_17_fu_311_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state6)) then tmp_19_reg_533 <= tmp_19_fu_321_p2; tmp_7_cast_reg_538(1 downto 0) <= tmp_7_cast_fu_326_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (ap_const_lv1_0 = tmp_3_fu_360_p2))) then tmp_22_reg_574 <= tmp_22_fu_381_p1; tmp_23_reg_579 <= tmp_23_fu_385_p1; tmp_9_reg_584 <= tmp_9_fu_389_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state11)) then tmp_24_reg_589 <= tmp_24_fu_401_p2; tmp_25_reg_594 <= tmp_25_fu_409_p2; tmp_26_reg_599 <= tmp_26_fu_414_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state12)) then tmp_27_reg_604 <= tmp_27_fu_428_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state14)) then tmp_29_reg_627 <= tmp_29_fu_463_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state9)) then tmp_cast_reg_556(1 downto 0) <= tmp_cast_fu_356_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state2)) then to_b_V_reg_479 <= to_b_V_fu_201_p2; end if; end if; end process; tmp_7_cast_reg_538(2) <= '0'; tmp_cast_reg_556(2) <= '0'; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_195_p2, ap_CS_fsm_state3, tmp_2_fu_233_p2, ap_CS_fsm_state5, tmp_5_fu_295_p2, ap_CS_fsm_state7, tmp_8_fu_330_p2, ap_CS_fsm_state10, tmp_3_fu_360_p2, ap_CS_fsm_state13, tmp_10_fu_434_p2) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state3; end if; when ap_ST_fsm_state3 => if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state4; end if; when ap_ST_fsm_state4 => ap_NS_fsm <= ap_ST_fsm_state5; when ap_ST_fsm_state5 => if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state3; else ap_NS_fsm <= ap_ST_fsm_state6; end if; when ap_ST_fsm_state6 => ap_NS_fsm <= ap_ST_fsm_state7; when ap_ST_fsm_state7 => if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state5; else ap_NS_fsm <= ap_ST_fsm_state8; end if; when ap_ST_fsm_state8 => ap_NS_fsm <= ap_ST_fsm_state9; when ap_ST_fsm_state9 => ap_NS_fsm <= ap_ST_fsm_state10; when ap_ST_fsm_state10 => if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state7; else ap_NS_fsm <= ap_ST_fsm_state11; end if; when ap_ST_fsm_state11 => ap_NS_fsm <= ap_ST_fsm_state12; when ap_ST_fsm_state12 => ap_NS_fsm <= ap_ST_fsm_state13; when ap_ST_fsm_state13 => if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state10; else ap_NS_fsm <= ap_ST_fsm_state14; end if; when ap_ST_fsm_state14 => ap_NS_fsm <= ap_ST_fsm_state15; when ap_ST_fsm_state15 => ap_NS_fsm <= ap_ST_fsm_state16; when ap_ST_fsm_state16 => ap_NS_fsm <= ap_ST_fsm_state17; when ap_ST_fsm_state17 => ap_NS_fsm <= ap_ST_fsm_state18; when ap_ST_fsm_state18 => ap_NS_fsm <= ap_ST_fsm_state19; when ap_ST_fsm_state19 => ap_NS_fsm <= ap_ST_fsm_state20; when ap_ST_fsm_state20 => ap_NS_fsm <= ap_ST_fsm_state21; when ap_ST_fsm_state21 => ap_NS_fsm <= ap_ST_fsm_state22; when ap_ST_fsm_state22 => ap_NS_fsm <= ap_ST_fsm_state23; when ap_ST_fsm_state23 => ap_NS_fsm <= ap_ST_fsm_state24; when ap_ST_fsm_state24 => ap_NS_fsm <= ap_ST_fsm_state25; when ap_ST_fsm_state25 => ap_NS_fsm <= ap_ST_fsm_state26; when ap_ST_fsm_state26 => ap_NS_fsm <= ap_ST_fsm_state27; when ap_ST_fsm_state27 => ap_NS_fsm <= ap_ST_fsm_state28; when ap_ST_fsm_state28 => ap_NS_fsm <= ap_ST_fsm_state29; when ap_ST_fsm_state29 => ap_NS_fsm <= ap_ST_fsm_state30; when ap_ST_fsm_state30 => ap_NS_fsm <= ap_ST_fsm_state13; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state10 <= ap_CS_fsm(9); ap_CS_fsm_state11 <= ap_CS_fsm(10); ap_CS_fsm_state12 <= ap_CS_fsm(11); ap_CS_fsm_state13 <= ap_CS_fsm(12); ap_CS_fsm_state14 <= ap_CS_fsm(13); ap_CS_fsm_state15 <= ap_CS_fsm(14); ap_CS_fsm_state16 <= ap_CS_fsm(15); ap_CS_fsm_state17 <= ap_CS_fsm(16); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state21 <= ap_CS_fsm(20); ap_CS_fsm_state22 <= ap_CS_fsm(21); ap_CS_fsm_state3 <= ap_CS_fsm(2); ap_CS_fsm_state30 <= ap_CS_fsm(29); ap_CS_fsm_state4 <= ap_CS_fsm(3); ap_CS_fsm_state5 <= ap_CS_fsm(4); ap_CS_fsm_state6 <= ap_CS_fsm(5); ap_CS_fsm_state7 <= ap_CS_fsm(6); ap_CS_fsm_state8 <= ap_CS_fsm(7); ap_CS_fsm_state9 <= ap_CS_fsm(8); ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; bufi_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_33_cast_fu_472_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufi_Clk_A <= ap_clk; bufi_Din_A <= ap_const_lv32_0; bufi_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufi_EN_A <= ap_const_logic_1; else bufi_EN_A <= ap_const_logic_0; end if; end process; bufi_Rst_A <= ap_rst; bufi_WEN_A <= ap_const_lv4_0; bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_551),32)); bufo_Clk_A <= ap_clk; bufo_Din_A <= temp_1_reg_173; bufo_EN_A_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state8) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state8))) then bufo_EN_A <= ap_const_logic_1; else bufo_EN_A <= ap_const_logic_0; end if; end process; bufo_Rst_A <= ap_rst; bufo_WEN_A_assign_proc : process(ap_CS_fsm_state13, tmp_10_fu_434_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then bufo_WEN_A <= ap_const_lv4_F; else bufo_WEN_A <= ap_const_lv4_0; end if; end process; bufw_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_32_cast_fu_468_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufw_Clk_A <= ap_clk; bufw_Din_A <= ap_const_lv32_0; bufw_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufw_EN_A <= ap_const_logic_1; else bufw_EN_A <= ap_const_logic_0; end if; end process; bufw_Rst_A <= ap_rst; bufw_WEN_A <= ap_const_lv4_0; col_b_V_fu_336_p2 <= std_logic_vector(unsigned(p_3_reg_129) + unsigned(ap_const_lv2_1)); i_V_fu_366_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(ap_const_lv3_1)); j_V_fu_440_p2 <= std_logic_vector(unsigned(p_5_reg_162) + unsigned(ap_const_lv3_1)); p_shl1_cast_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_254_p3),6)); p_shl2_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_7_fu_275_p3),32)); p_shl4_cast_fu_421_p3 <= (tmp_26_reg_599 & ap_const_lv3_0); p_shl5_cast_fu_394_p3 <= (tmp_23_reg_579 & ap_const_lv2_0); p_shl_cast_fu_219_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_211_p3),5)); row_b_V_fu_301_p2 <= std_logic_vector(unsigned(p_2_reg_117) + unsigned(ap_const_lv2_1)); ti_b_V_fu_239_p2 <= std_logic_vector(unsigned(p_1_reg_106) + unsigned(ap_const_lv2_1)); tmp_10_fu_434_p2 <= "1" when (p_5_reg_162 = ap_const_lv3_5) else "0"; tmp_11_cast_fu_446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_5_reg_162),9)); tmp_11_fu_286_p2 <= std_logic_vector(signed(tmp_17_cast_fu_272_p1) + signed(p_shl2_fu_282_p1)); tmp_12_cast_cast_fu_460_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_reg_622),9)); tmp_12_fu_455_p2 <= std_logic_vector(unsigned(tmp_cast_reg_556) + unsigned(p_5_reg_162)); tmp_15_fu_254_p3 <= (p_1_reg_106 & ap_const_lv3_0); tmp_16_cast_fu_229_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_1_fu_223_p2),6)); tmp_16_fu_266_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_262_p1) - unsigned(tmp_4_cast_fu_245_p1)); tmp_17_cast_fu_272_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_4_reg_498),32)); tmp_17_fu_311_p2 <= std_logic_vector(unsigned(tmp_7_cast8_fu_307_p1) + unsigned(tmp_16_cast_reg_484)); tmp_18_fu_316_p2 <= std_logic_vector(shift_left(unsigned(tmp_17_reg_527),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0))))); tmp_19_fu_321_p2 <= std_logic_vector(unsigned(tmp_18_fu_316_p2) - unsigned(tmp_17_reg_527)); tmp_1_cast_fu_207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_s_reg_95),5)); tmp_1_fu_223_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_219_p1) - unsigned(tmp_1_cast_fu_207_p1)); tmp_20_fu_346_p2 <= std_logic_vector(unsigned(tmp_19_reg_533) + unsigned(tmp_cast7_fu_342_p1)); tmp_21_cast_fu_292_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_reg_504),7)); tmp_21_fu_376_p2 <= std_logic_vector(unsigned(tmp_6_fu_372_p1) + unsigned(tmp_11_reg_509)); tmp_22_fu_381_p1 <= tmp_21_fu_376_p2(9 - 1 downto 0); tmp_23_fu_385_p1 <= tmp_21_fu_376_p2(7 - 1 downto 0); tmp_24_fu_401_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_394_p3) + unsigned(tmp_22_reg_574)); tmp_25_cast_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_20_fu_346_p2),32)); tmp_25_fu_409_p2 <= std_logic_vector(unsigned(tmp_9_cast_cast_fu_406_p1) + unsigned(tmp_21_cast_reg_514)); tmp_26_fu_414_p1 <= tmp_25_fu_409_p2(6 - 1 downto 0); tmp_27_fu_428_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_421_p3) - unsigned(tmp_29_cast_fu_418_p1)); tmp_28_fu_450_p2 <= std_logic_vector(unsigned(tmp_24_reg_589) + unsigned(tmp_11_cast_fu_446_p1)); tmp_29_cast_fu_418_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_25_reg_594),9)); tmp_29_fu_463_p2 <= std_logic_vector(unsigned(tmp_27_reg_604) + unsigned(tmp_12_cast_cast_fu_460_p1)); tmp_2_fu_233_p2 <= "1" when (p_1_reg_106 = ap_const_lv2_3) else "0"; tmp_32_cast_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_28_reg_617),32)); tmp_33_cast_fu_472_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_627),32)); tmp_3_fu_360_p2 <= "1" when (p_4_reg_141 = ap_const_lv3_5) else "0"; tmp_4_cast_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_1_reg_106),6)); tmp_4_fu_249_p2 <= std_logic_vector(signed(tmp_16_cast_reg_484) + signed(tmp_4_cast_fu_245_p1)); tmp_5_fu_295_p2 <= "1" when (p_2_reg_117 = ap_const_lv2_3) else "0"; tmp_6_fu_372_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_4_reg_141),32)); tmp_7_cast8_fu_307_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),6)); tmp_7_cast_fu_326_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),3)); tmp_7_fu_275_p3 <= (tmp_4_reg_498 & ap_const_lv2_0); tmp_8_fu_330_p2 <= "1" when (p_3_reg_129 = ap_const_lv2_3) else "0"; tmp_9_cast_cast_fu_406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_584),7)); tmp_9_fu_389_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(tmp_7_cast_reg_538)); tmp_cast7_fu_342_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),6)); tmp_cast_fu_356_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),3)); tmp_fu_195_p2 <= "1" when (p_s_reg_95 = ap_const_lv2_3) else "0"; tmp_s_fu_211_p3 <= (p_s_reg_95 & ap_const_lv2_0); to_b_V_fu_201_p2 <= std_logic_vector(unsigned(p_s_reg_95) + unsigned(ap_const_lv2_1)); end behav;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is Port ( button : in std_logic; LED : out std_logic); end test; architecture Behavioral of test is begin LED <= button; end Behavioral;
lpm_divide0_inst : lpm_divide0 PORT MAP ( denom => denom_sig, numer => numer_sig, quotient => quotient_sig, remain => remain_sig );
library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu is generic( W : natural := 4 ); port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A i_data_b : in std_logic_vector(W-1 downto 0); -- input data B i_data_carry : in std_logic; -- carry in or borrow in i_ctrl : in std_logic_vector(3 downto 0); -- control signals o_data_c : out std_logic_vector(W-1 downto 0); -- output data C o_data_carry : out std_logic; -- carry out or borrow out o_data_comp : out std_logic_vector(1 downto 0) -- output comparison ); end alu; architecture behavioral of alu is begin comb_memless_process: process ( i_data_a, i_data_b, i_data_carry, i_ctrl ) variable temp_carry: std_logic_vector(W downto 0) := ( others => '0' ); begin o_data_c <= (others => '0'); o_data_carry <= '0'; o_data_comp <= (others => '0'); case i_ctrl is when "0001" => -- ripple carry adder: {sum, cout} = a+b+cin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- sum(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- cout(k+1) = a(k).b(k) + b(k).c(k) + c(k).a(k) temp_carry(i+1) := ( i_data_a(i) and i_data_b(i) ) or ( i_data_b(i) and temp_carry(i) ) or ( temp_carry(i) and i_data_a(i) ); end loop; o_data_carry <= temp_carry(W); when "0010" => -- full subtraction: {diff, bout} = a-b-bin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- diff(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- bout(k+1) = !a(k).b(k) + b(k).c(k) + c(k).!a(k) temp_carry(i+1) := ( ( NOT i_data_a(i) ) AND i_data_b(i) ) OR ( i_data_b(i) AND temp_carry(i) ) OR ( temp_carry(i) AND ( NOT i_data_a(i) ) ); end loop; o_data_carry <= temp_carry(W); when "0011" => -- comparator: comp_out = 1 if A > B if( i_data_a > i_data_b ) then o_data_comp <= "01"; else o_data_comp <= "00"; end if; when "0100" => -- comparator: comp_out = 1 if A < B if( i_data_a < i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0101" => -- comparator: comp_out = 1 if A = B if( i_data_a = i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0110" => -- logical right shift A by B[1:0] o_data_c <= std_logic_vector( unsigned(i_data_a) srl to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when "0111" => -- logical left shift A by B o_data_c <= std_logic_vector( unsigned(i_data_a) sll to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when others => -- NOP end case; end process comb_memless_process; end behavioral;
---- Controller -------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.processor_functions.all; ------------------------------------------------------------------------------------------------------------------ ENTITY controller IS PORT (clk, nrst: IN std_logic; CONTROL_bus: INOUT std_logic_vector(n-1 DOWNTO 0); state_7seg: OUT std_logic_vector(0 TO 7); -- IR IR_opcode: IN opcode; IR_load: OUT std_logic; IR_valid: OUT std_logic; -- PC PC_inc: OUT std_logic; PC_load: OUT std_logic; PC_valid: OUT std_logic; -- Memory MDR_load: OUT std_logic; MAR_load: OUT std_logic; MEM_valid: OUT std_logic; MEM_en: OUT std_logic; MEM_rw: OUT std_logic; -- ALU ALU_zero: IN std_logic; ALU_valid: OUT std_logic; ALU_slt: IN std_logic; ALU_enable: OUT std_logic; ALU_cmd: OUT std_logic_vector(3 DOWNTO 0); -- IO IODR_load: OUT STD_LOGIC; IOAR_load: OUT STD_LOGIC; IO_valid: OUT STD_LOGIC; IO_en: OUT STD_LOGIC; IO_rw: OUT STD_LOGIC; -- WAKE WAKE_signal: IN STD_LOGIC; waiting: OUT STD_LOGIC); END ENTITY controller; ------------------------------------------------------------------------------------------------------------------ ARCHITECTURE RTL OF controller IS TYPE states IS (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10); SIGNAL current_state, next_state: states; SIGNAL BRANCH_trigger: std_logic; SIGNAL state_vector: STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT bcd_to_7seg IS PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0); en: IN std_logic; output: OUT STD_LOGIC_VECTOR (0 TO 7)); END COMPONENT; BEGIN -- Converte o estado atual para um std_logic_vector com sua posicao na lista state_vector <= std_logic_vector(to_unsigned(states'pos(current_state), 4)); -- Gera a visualizacao 7seg state7seg: bcd_to_7seg PORT MAP(state_vector, seg_en, state_7seg); -- Indicador de se o branch deve ser aceito BRANCH_trigger <= '1' WHEN ((IR_opcode = BZERO AND ALU_zero = '1') OR (IR_opcode = BLESS AND ALU_slt = '1') OR (IR_opcode = BGREATER AND ALU_zero = '0' AND ALU_slt = '0')) ELSE '0'; -- Esta em waiting? waiting <= '1' WHEN current_state = s10 ELSE '0'; -- Processo que gerencia a transicao do current_state para o next_state -- e a configuracao de reset state_sequence: PROCESS (clk, nrst) BEGIN IF nrst = '0' THEN -- reset assincrono current_state <= s0; ELSE IF rising_edge(clk) THEN -- mudanca de estado eh sincrona current_state <= next_state; END IF; END IF; END PROCESS state_sequence; -- espera a mudanca de estado ou opcode -- processo que de fato mudam os sinais de controle conforme a transicao state_machine: PROCESS ( current_state, IR_opcode ) IS BEGIN -- Reset all the control SIGNALs IR_load <= '0'; IR_valid <= '0'; PC_inc <= '0'; PC_load <= '0'; PC_valid <= '0'; MDR_load <= '0'; MAR_load <= '0'; MEM_valid <= '0'; MEM_en <= '0'; MEM_rw <= '0'; ALU_valid <= '0'; ALU_enable <= '0'; ALU_cmd <= "0000"; IODR_load <= '0'; IOAR_load <= '0'; IO_valid <= '0'; IO_en <= '0'; IO_rw <= '0'; CASE current_state IS WHEN s0 => MAR_load <= '1'; PC_valid <= '1'; PC_inc <= '1'; next_state <= s1; WHEN s1 => MEM_en <='1'; next_state <= s2; WHEN s2 => MEM_valid <= '1'; IR_load <= '1'; next_state <= s3; WHEN s3 => IR_valid <= '1'; MAR_load <= '1'; IOAR_load <= '1'; IF (IR_opcode = INC) THEN next_state <= s7; ELSIF (IR_opcode = JUMP) THEN next_state <= s9; ELSIF (IR_opcode = BZERO OR IR_opcode = BGREATER OR IR_opcode = BLESS) THEN next_state <= s8; ELSIF (IR_opcode = NOP) THEN next_state <= s0; ELSIF (IR_opcode = WAITT) THEN next_state <= s10; ELSIF (IR_opcode = STORE) THEN next_state <= s4; ELSE next_state <= s6; END IF; WHEN s4 => ALU_valid <= '1'; MDR_load <= '1'; IODR_load <= '1'; next_state <= s5; WHEN s5 => MEM_en <= '1'; MEM_rw <= '1'; IO_en <= '1'; IO_rw <= '1'; next_state <= s0; WHEN s6 => MEM_en <= '1'; IO_en <= '1'; next_state <= s7; WHEN s7 => MEM_valid <= '1'; IO_valid <= '1'; ALU_enable <= '1'; ALU_cmd <= cmdDecode(IR_opcode); next_state <= s0; WHEN s8 => IF (BRANCH_trigger = '1') THEN next_state <= s9; ELSE next_state <= s0; END IF; WHEN s9 => PC_load <= '1'; IR_valid <= '1'; next_state <= s0; WHEN s10 => IF (WAKE_signal = '0') THEN next_state <= s0; END IF; END CASE; END PROCESS state_machine; END ARCHITECTURE; ------------------------------------------------------------------------------------------------------------------
package foo is -- Declaration attribute LOCATION: COORDINATE; attribute PIN_NO: POSITIVE; -- Specification attribute PIN_NO of CIN: signal is 10; attribute PIN_NO of COUT: signal is 5; attribute LOCATION of ADDER1: label is (10,15); attribute LOCATION of others: label is (25,77); attribute CAPACITANCE of all: signal is 15 pF; attribute IMPLEMENTATION of G1: group is "74LS152"; attribute RISING_DELAY of C2Q: group is 7.2 ns; attribute FOREIGN of F: function is "implementation-dependent information"; --attribute BuiltIn of "or" [MVL, MVL return MVL]: function is TRUE; --attribute Mapping of JMP [return OpCode] :literal is "001"; end;
-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ConstRAM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ********************************************************** -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version -- ********************************************************** --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ConstRAM IS PORT ( clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (35 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) ); END ConstRAM; ARCHITECTURE SYN OF constram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_b : STRING; address_reg_b : STRING; clock_enable_input_a : STRING; clock_enable_input_b : STRING; clock_enable_output_b : STRING; intended_device_family : STRING; lpm_type : STRING; numwords_a : NATURAL; numwords_b : NATURAL; operation_mode : STRING; outdata_aclr_b : STRING; outdata_reg_b : STRING; power_up_uninitialized : STRING; read_during_write_mode_mixed_ports : STRING; widthad_a : NATURAL; widthad_b : NATURAL; width_a : NATURAL; width_b : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); wren_a : IN STD_LOGIC ; address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(35 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", intended_device_family => "Cyclone IV E", lpm_type => "altsyncram", numwords_a => 1024, numwords_b => 1024, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_mixed_ports => "OLD_DATA", widthad_a => 10, widthad_b => 10, width_a => 36, width_b => 36, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, clock0 => clock, data_a => data, wren_a => wren, address_b => rdaddress, q_b => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]" -- Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]" -- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]" -- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" -- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0 -- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY CDiv IS PORT ( Cin : IN std_logic ; Cout : OUT std_logic ) ; END CDiv ; ARCHITECTURE Behavior OF CDiv IS constant TC: integer := 12; --Time Constant signal c0,c1,c2,c3: integer range 0 to 1000; signal D: std_logic := '0'; BEGIN PROCESS(Cin) BEGIN if (Cin'event and Cin='1') then c0 <= c0 + 1; if c0 = TC then c0 <= 0; c1 <= c1 + 1; elsif c1 = TC then c1 <= 0; c2 <= c2 + 1; elsif c2 = TC then c2 <= 0; c3 <= c3 + 1; elsif c3 = TC then c3 <= 0; D <= NOT D; end if; end if; Cout <= D; END PROCESS ; END Behavior ;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mc6847_ntsc is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of mc6847_ntsc is signal rom_addr : std_logic_vector(9 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(9 downto 0) <= ADDR(9 downto 0); end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); if rom_addr(9 downto 8) = "00" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"1C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"02"; when x"06" => DATA <= x"1A"; when x"07" => DATA <= x"2A"; when x"08" => DATA <= x"2A"; when x"09" => DATA <= x"1C"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"14"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"3E"; when x"18" => DATA <= x"22"; when x"19" => DATA <= x"22"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"12"; when x"25" => DATA <= x"12"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"12"; when x"28" => DATA <= x"12"; when x"29" => DATA <= x"3C"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"20"; when x"36" => DATA <= x"20"; when x"37" => DATA <= x"20"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3C"; when x"44" => DATA <= x"12"; when x"45" => DATA <= x"12"; when x"46" => DATA <= x"12"; when x"47" => DATA <= x"12"; when x"48" => DATA <= x"12"; when x"49" => DATA <= x"3C"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"20"; when x"56" => DATA <= x"38"; when x"57" => DATA <= x"20"; when x"58" => DATA <= x"20"; when x"59" => DATA <= x"3E"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"3E"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"38"; when x"67" => DATA <= x"20"; when x"68" => DATA <= x"20"; when x"69" => DATA <= x"20"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"1E"; when x"74" => DATA <= x"20"; when x"75" => DATA <= x"20"; when x"76" => DATA <= x"26"; when x"77" => DATA <= x"22"; when x"78" => DATA <= x"22"; when x"79" => DATA <= x"1E"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"3E"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"08"; when x"95" => DATA <= x"08"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"02"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"02"; when x"A6" => DATA <= x"02"; when x"A7" => DATA <= x"22"; when x"A8" => DATA <= x"22"; when x"A9" => DATA <= x"1C"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"22"; when x"B4" => DATA <= x"24"; when x"B5" => DATA <= x"28"; when x"B6" => DATA <= x"30"; when x"B7" => DATA <= x"28"; when x"B8" => DATA <= x"24"; when x"B9" => DATA <= x"22"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"20"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"20"; when x"C8" => DATA <= x"20"; when x"C9" => DATA <= x"3E"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"22"; when x"D4" => DATA <= x"36"; when x"D5" => DATA <= x"2A"; when x"D6" => DATA <= x"2A"; when x"D7" => DATA <= x"22"; when x"D8" => DATA <= x"22"; when x"D9" => DATA <= x"22"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"22"; when x"E4" => DATA <= x"32"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"26"; when x"E7" => DATA <= x"22"; when x"E8" => DATA <= x"22"; when x"E9" => DATA <= x"22"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"3E"; when x"F4" => DATA <= x"22"; when x"F5" => DATA <= x"22"; when x"F6" => DATA <= x"22"; when x"F7" => DATA <= x"22"; when x"F8" => DATA <= x"22"; when x"F9" => DATA <= x"3E"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "01" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"3C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"22"; when x"06" => DATA <= x"3C"; when x"07" => DATA <= x"20"; when x"08" => DATA <= x"20"; when x"09" => DATA <= x"20"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"1C"; when x"14" => DATA <= x"22"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"2A"; when x"18" => DATA <= x"24"; when x"19" => DATA <= x"1A"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"22"; when x"26" => DATA <= x"3C"; when x"27" => DATA <= x"28"; when x"28" => DATA <= x"24"; when x"29" => DATA <= x"22"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"10"; when x"36" => DATA <= x"08"; when x"37" => DATA <= x"04"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3E"; when x"44" => DATA <= x"08"; when x"45" => DATA <= x"08"; when x"46" => DATA <= x"08"; when x"47" => DATA <= x"08"; when x"48" => DATA <= x"08"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"22"; when x"54" => DATA <= x"22"; when x"55" => DATA <= x"22"; when x"56" => DATA <= x"22"; when x"57" => DATA <= x"22"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"22"; when x"64" => DATA <= x"22"; when x"65" => DATA <= x"22"; when x"66" => DATA <= x"14"; when x"67" => DATA <= x"14"; when x"68" => DATA <= x"08"; when x"69" => DATA <= x"08"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"22"; when x"74" => DATA <= x"22"; when x"75" => DATA <= x"22"; when x"76" => DATA <= x"2A"; when x"77" => DATA <= x"2A"; when x"78" => DATA <= x"36"; when x"79" => DATA <= x"22"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"14"; when x"86" => DATA <= x"08"; when x"87" => DATA <= x"14"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"22"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"14"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"3E"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"04"; when x"A6" => DATA <= x"08"; when x"A7" => DATA <= x"10"; when x"A8" => DATA <= x"20"; when x"A9" => DATA <= x"3E"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"38"; when x"B4" => DATA <= x"20"; when x"B5" => DATA <= x"20"; when x"B6" => DATA <= x"20"; when x"B7" => DATA <= x"20"; when x"B8" => DATA <= x"20"; when x"B9" => DATA <= x"38"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"08"; when x"C7" => DATA <= x"04"; when x"C8" => DATA <= x"02"; when x"C9" => DATA <= x"02"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"0E"; when x"D4" => DATA <= x"02"; when x"D5" => DATA <= x"02"; when x"D6" => DATA <= x"02"; when x"D7" => DATA <= x"02"; when x"D8" => DATA <= x"02"; when x"D9" => DATA <= x"0E"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"08"; when x"E4" => DATA <= x"1C"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"08"; when x"E7" => DATA <= x"08"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"08"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"00"; when x"F4" => DATA <= x"08"; when x"F5" => DATA <= x"10"; when x"F6" => DATA <= x"3E"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"08"; when x"F9" => DATA <= x"00"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "10" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"00"; when x"04" => DATA <= x"00"; when x"05" => DATA <= x"00"; when x"06" => DATA <= x"00"; when x"07" => DATA <= x"00"; when x"08" => DATA <= x"00"; when x"09" => DATA <= x"00"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"08"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"00"; when x"19" => DATA <= x"08"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"14"; when x"24" => DATA <= x"14"; when x"25" => DATA <= x"14"; when x"26" => DATA <= x"00"; when x"27" => DATA <= x"00"; when x"28" => DATA <= x"00"; when x"29" => DATA <= x"00"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"14"; when x"34" => DATA <= x"14"; when x"35" => DATA <= x"36"; when x"36" => DATA <= x"00"; when x"37" => DATA <= x"36"; when x"38" => DATA <= x"14"; when x"39" => DATA <= x"14"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"08"; when x"44" => DATA <= x"1E"; when x"45" => DATA <= x"20"; when x"46" => DATA <= x"1C"; when x"47" => DATA <= x"02"; when x"48" => DATA <= x"3C"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"32"; when x"54" => DATA <= x"32"; when x"55" => DATA <= x"04"; when x"56" => DATA <= x"08"; when x"57" => DATA <= x"10"; when x"58" => DATA <= x"26"; when x"59" => DATA <= x"26"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"10"; when x"64" => DATA <= x"28"; when x"65" => DATA <= x"28"; when x"66" => DATA <= x"10"; when x"67" => DATA <= x"2A"; when x"68" => DATA <= x"24"; when x"69" => DATA <= x"1A"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"18"; when x"74" => DATA <= x"18"; when x"75" => DATA <= x"18"; when x"76" => DATA <= x"00"; when x"77" => DATA <= x"00"; when x"78" => DATA <= x"00"; when x"79" => DATA <= x"00"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"08"; when x"84" => DATA <= x"10"; when x"85" => DATA <= x"20"; when x"86" => DATA <= x"20"; when x"87" => DATA <= x"20"; when x"88" => DATA <= x"10"; when x"89" => DATA <= x"08"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"08"; when x"94" => DATA <= x"04"; when x"95" => DATA <= x"02"; when x"96" => DATA <= x"02"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"04"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"08"; when x"A5" => DATA <= x"1C"; when x"A6" => DATA <= x"3E"; when x"A7" => DATA <= x"1C"; when x"A8" => DATA <= x"08"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"00"; when x"B4" => DATA <= x"08"; when x"B5" => DATA <= x"08"; when x"B6" => DATA <= x"3E"; when x"B7" => DATA <= x"08"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"00"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"00"; when x"C4" => DATA <= x"00"; when x"C5" => DATA <= x"00"; when x"C6" => DATA <= x"30"; when x"C7" => DATA <= x"30"; when x"C8" => DATA <= x"10"; when x"C9" => DATA <= x"20"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"00"; when x"D6" => DATA <= x"3E"; when x"D7" => DATA <= x"00"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"00"; when x"E4" => DATA <= x"00"; when x"E5" => DATA <= x"00"; when x"E6" => DATA <= x"00"; when x"E7" => DATA <= x"00"; when x"E8" => DATA <= x"30"; when x"E9" => DATA <= x"30"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"02"; when x"F4" => DATA <= x"02"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"20"; when x"F9" => DATA <= x"20"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "11" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"18"; when x"04" => DATA <= x"24"; when x"05" => DATA <= x"24"; when x"06" => DATA <= x"24"; when x"07" => DATA <= x"24"; when x"08" => DATA <= x"24"; when x"09" => DATA <= x"18"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"18"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"08"; when x"19" => DATA <= x"1C"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"1C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"02"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"20"; when x"28" => DATA <= x"20"; when x"29" => DATA <= x"3E"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"02"; when x"36" => DATA <= x"04"; when x"37" => DATA <= x"02"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"04"; when x"44" => DATA <= x"0C"; when x"45" => DATA <= x"14"; when x"46" => DATA <= x"3E"; when x"47" => DATA <= x"04"; when x"48" => DATA <= x"04"; when x"49" => DATA <= x"04"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"3C"; when x"56" => DATA <= x"02"; when x"57" => DATA <= x"02"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"1C"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"3C"; when x"67" => DATA <= x"22"; when x"68" => DATA <= x"22"; when x"69" => DATA <= x"1C"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"3E"; when x"74" => DATA <= x"02"; when x"75" => DATA <= x"04"; when x"76" => DATA <= x"08"; when x"77" => DATA <= x"10"; when x"78" => DATA <= x"20"; when x"79" => DATA <= x"20"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"1C"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"1C"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"1C"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"22"; when x"96" => DATA <= x"1E"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"02"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"18"; when x"A5" => DATA <= x"18"; when x"A6" => DATA <= x"00"; when x"A7" => DATA <= x"18"; when x"A8" => DATA <= x"18"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"18"; when x"B4" => DATA <= x"18"; when x"B5" => DATA <= x"00"; when x"B6" => DATA <= x"18"; when x"B7" => DATA <= x"18"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"10"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"04"; when x"C4" => DATA <= x"08"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"10"; when x"C8" => DATA <= x"08"; when x"C9" => DATA <= x"04"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"3E"; when x"D6" => DATA <= x"00"; when x"D7" => DATA <= x"3E"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"10"; when x"E4" => DATA <= x"08"; when x"E5" => DATA <= x"04"; when x"E6" => DATA <= x"02"; when x"E7" => DATA <= x"04"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"10"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"18"; when x"F4" => DATA <= x"24"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"08"; when x"F8" => DATA <= x"00"; when x"F9" => DATA <= x"08"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; end process; end RTL;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mc6847_ntsc is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of mc6847_ntsc is signal rom_addr : std_logic_vector(9 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(9 downto 0) <= ADDR(9 downto 0); end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); if rom_addr(9 downto 8) = "00" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"1C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"02"; when x"06" => DATA <= x"1A"; when x"07" => DATA <= x"2A"; when x"08" => DATA <= x"2A"; when x"09" => DATA <= x"1C"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"14"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"3E"; when x"18" => DATA <= x"22"; when x"19" => DATA <= x"22"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"12"; when x"25" => DATA <= x"12"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"12"; when x"28" => DATA <= x"12"; when x"29" => DATA <= x"3C"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"20"; when x"36" => DATA <= x"20"; when x"37" => DATA <= x"20"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3C"; when x"44" => DATA <= x"12"; when x"45" => DATA <= x"12"; when x"46" => DATA <= x"12"; when x"47" => DATA <= x"12"; when x"48" => DATA <= x"12"; when x"49" => DATA <= x"3C"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"20"; when x"56" => DATA <= x"38"; when x"57" => DATA <= x"20"; when x"58" => DATA <= x"20"; when x"59" => DATA <= x"3E"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"3E"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"38"; when x"67" => DATA <= x"20"; when x"68" => DATA <= x"20"; when x"69" => DATA <= x"20"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"1E"; when x"74" => DATA <= x"20"; when x"75" => DATA <= x"20"; when x"76" => DATA <= x"26"; when x"77" => DATA <= x"22"; when x"78" => DATA <= x"22"; when x"79" => DATA <= x"1E"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"3E"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"08"; when x"95" => DATA <= x"08"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"02"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"02"; when x"A6" => DATA <= x"02"; when x"A7" => DATA <= x"22"; when x"A8" => DATA <= x"22"; when x"A9" => DATA <= x"1C"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"22"; when x"B4" => DATA <= x"24"; when x"B5" => DATA <= x"28"; when x"B6" => DATA <= x"30"; when x"B7" => DATA <= x"28"; when x"B8" => DATA <= x"24"; when x"B9" => DATA <= x"22"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"20"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"20"; when x"C8" => DATA <= x"20"; when x"C9" => DATA <= x"3E"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"22"; when x"D4" => DATA <= x"36"; when x"D5" => DATA <= x"2A"; when x"D6" => DATA <= x"2A"; when x"D7" => DATA <= x"22"; when x"D8" => DATA <= x"22"; when x"D9" => DATA <= x"22"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"22"; when x"E4" => DATA <= x"32"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"26"; when x"E7" => DATA <= x"22"; when x"E8" => DATA <= x"22"; when x"E9" => DATA <= x"22"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"3E"; when x"F4" => DATA <= x"22"; when x"F5" => DATA <= x"22"; when x"F6" => DATA <= x"22"; when x"F7" => DATA <= x"22"; when x"F8" => DATA <= x"22"; when x"F9" => DATA <= x"3E"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "01" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"3C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"22"; when x"06" => DATA <= x"3C"; when x"07" => DATA <= x"20"; when x"08" => DATA <= x"20"; when x"09" => DATA <= x"20"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"1C"; when x"14" => DATA <= x"22"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"2A"; when x"18" => DATA <= x"24"; when x"19" => DATA <= x"1A"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"22"; when x"26" => DATA <= x"3C"; when x"27" => DATA <= x"28"; when x"28" => DATA <= x"24"; when x"29" => DATA <= x"22"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"10"; when x"36" => DATA <= x"08"; when x"37" => DATA <= x"04"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3E"; when x"44" => DATA <= x"08"; when x"45" => DATA <= x"08"; when x"46" => DATA <= x"08"; when x"47" => DATA <= x"08"; when x"48" => DATA <= x"08"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"22"; when x"54" => DATA <= x"22"; when x"55" => DATA <= x"22"; when x"56" => DATA <= x"22"; when x"57" => DATA <= x"22"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"22"; when x"64" => DATA <= x"22"; when x"65" => DATA <= x"22"; when x"66" => DATA <= x"14"; when x"67" => DATA <= x"14"; when x"68" => DATA <= x"08"; when x"69" => DATA <= x"08"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"22"; when x"74" => DATA <= x"22"; when x"75" => DATA <= x"22"; when x"76" => DATA <= x"2A"; when x"77" => DATA <= x"2A"; when x"78" => DATA <= x"36"; when x"79" => DATA <= x"22"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"14"; when x"86" => DATA <= x"08"; when x"87" => DATA <= x"14"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"22"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"14"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"3E"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"04"; when x"A6" => DATA <= x"08"; when x"A7" => DATA <= x"10"; when x"A8" => DATA <= x"20"; when x"A9" => DATA <= x"3E"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"38"; when x"B4" => DATA <= x"20"; when x"B5" => DATA <= x"20"; when x"B6" => DATA <= x"20"; when x"B7" => DATA <= x"20"; when x"B8" => DATA <= x"20"; when x"B9" => DATA <= x"38"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"08"; when x"C7" => DATA <= x"04"; when x"C8" => DATA <= x"02"; when x"C9" => DATA <= x"02"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"0E"; when x"D4" => DATA <= x"02"; when x"D5" => DATA <= x"02"; when x"D6" => DATA <= x"02"; when x"D7" => DATA <= x"02"; when x"D8" => DATA <= x"02"; when x"D9" => DATA <= x"0E"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"08"; when x"E4" => DATA <= x"1C"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"08"; when x"E7" => DATA <= x"08"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"08"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"00"; when x"F4" => DATA <= x"08"; when x"F5" => DATA <= x"10"; when x"F6" => DATA <= x"3E"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"08"; when x"F9" => DATA <= x"00"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "10" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"00"; when x"04" => DATA <= x"00"; when x"05" => DATA <= x"00"; when x"06" => DATA <= x"00"; when x"07" => DATA <= x"00"; when x"08" => DATA <= x"00"; when x"09" => DATA <= x"00"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"08"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"00"; when x"19" => DATA <= x"08"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"14"; when x"24" => DATA <= x"14"; when x"25" => DATA <= x"14"; when x"26" => DATA <= x"00"; when x"27" => DATA <= x"00"; when x"28" => DATA <= x"00"; when x"29" => DATA <= x"00"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"14"; when x"34" => DATA <= x"14"; when x"35" => DATA <= x"36"; when x"36" => DATA <= x"00"; when x"37" => DATA <= x"36"; when x"38" => DATA <= x"14"; when x"39" => DATA <= x"14"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"08"; when x"44" => DATA <= x"1E"; when x"45" => DATA <= x"20"; when x"46" => DATA <= x"1C"; when x"47" => DATA <= x"02"; when x"48" => DATA <= x"3C"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"32"; when x"54" => DATA <= x"32"; when x"55" => DATA <= x"04"; when x"56" => DATA <= x"08"; when x"57" => DATA <= x"10"; when x"58" => DATA <= x"26"; when x"59" => DATA <= x"26"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"10"; when x"64" => DATA <= x"28"; when x"65" => DATA <= x"28"; when x"66" => DATA <= x"10"; when x"67" => DATA <= x"2A"; when x"68" => DATA <= x"24"; when x"69" => DATA <= x"1A"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"18"; when x"74" => DATA <= x"18"; when x"75" => DATA <= x"18"; when x"76" => DATA <= x"00"; when x"77" => DATA <= x"00"; when x"78" => DATA <= x"00"; when x"79" => DATA <= x"00"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"08"; when x"84" => DATA <= x"10"; when x"85" => DATA <= x"20"; when x"86" => DATA <= x"20"; when x"87" => DATA <= x"20"; when x"88" => DATA <= x"10"; when x"89" => DATA <= x"08"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"08"; when x"94" => DATA <= x"04"; when x"95" => DATA <= x"02"; when x"96" => DATA <= x"02"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"04"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"08"; when x"A5" => DATA <= x"1C"; when x"A6" => DATA <= x"3E"; when x"A7" => DATA <= x"1C"; when x"A8" => DATA <= x"08"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"00"; when x"B4" => DATA <= x"08"; when x"B5" => DATA <= x"08"; when x"B6" => DATA <= x"3E"; when x"B7" => DATA <= x"08"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"00"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"00"; when x"C4" => DATA <= x"00"; when x"C5" => DATA <= x"00"; when x"C6" => DATA <= x"30"; when x"C7" => DATA <= x"30"; when x"C8" => DATA <= x"10"; when x"C9" => DATA <= x"20"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"00"; when x"D6" => DATA <= x"3E"; when x"D7" => DATA <= x"00"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"00"; when x"E4" => DATA <= x"00"; when x"E5" => DATA <= x"00"; when x"E6" => DATA <= x"00"; when x"E7" => DATA <= x"00"; when x"E8" => DATA <= x"30"; when x"E9" => DATA <= x"30"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"02"; when x"F4" => DATA <= x"02"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"20"; when x"F9" => DATA <= x"20"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "11" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"18"; when x"04" => DATA <= x"24"; when x"05" => DATA <= x"24"; when x"06" => DATA <= x"24"; when x"07" => DATA <= x"24"; when x"08" => DATA <= x"24"; when x"09" => DATA <= x"18"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"18"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"08"; when x"19" => DATA <= x"1C"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"1C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"02"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"20"; when x"28" => DATA <= x"20"; when x"29" => DATA <= x"3E"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"02"; when x"36" => DATA <= x"04"; when x"37" => DATA <= x"02"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"04"; when x"44" => DATA <= x"0C"; when x"45" => DATA <= x"14"; when x"46" => DATA <= x"3E"; when x"47" => DATA <= x"04"; when x"48" => DATA <= x"04"; when x"49" => DATA <= x"04"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"3C"; when x"56" => DATA <= x"02"; when x"57" => DATA <= x"02"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"1C"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"3C"; when x"67" => DATA <= x"22"; when x"68" => DATA <= x"22"; when x"69" => DATA <= x"1C"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"3E"; when x"74" => DATA <= x"02"; when x"75" => DATA <= x"04"; when x"76" => DATA <= x"08"; when x"77" => DATA <= x"10"; when x"78" => DATA <= x"20"; when x"79" => DATA <= x"20"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"1C"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"1C"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"1C"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"22"; when x"96" => DATA <= x"1E"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"02"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"18"; when x"A5" => DATA <= x"18"; when x"A6" => DATA <= x"00"; when x"A7" => DATA <= x"18"; when x"A8" => DATA <= x"18"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"18"; when x"B4" => DATA <= x"18"; when x"B5" => DATA <= x"00"; when x"B6" => DATA <= x"18"; when x"B7" => DATA <= x"18"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"10"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"04"; when x"C4" => DATA <= x"08"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"10"; when x"C8" => DATA <= x"08"; when x"C9" => DATA <= x"04"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"3E"; when x"D6" => DATA <= x"00"; when x"D7" => DATA <= x"3E"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"10"; when x"E4" => DATA <= x"08"; when x"E5" => DATA <= x"04"; when x"E6" => DATA <= x"02"; when x"E7" => DATA <= x"04"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"10"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"18"; when x"F4" => DATA <= x"24"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"08"; when x"F8" => DATA <= x"00"; when x"F9" => DATA <= x"08"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; end process; end RTL;
ARCHITECTURE RTL of ENT is begin end; ARCHITECTURE RTL of ENT is begin end; ARCHITECTURE RTL of ENT is begin end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: config -- File: config.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: GRLIB Global configuration package. Can be overriden -- by local config packages in template designs. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.config_types.all; package config is -- AHBDW - AHB data with -- -- Valid values are 32, 64, 128 and 256 -- -- The value here sets the width of the AMBA AHB data vectors for all -- cores in the library. -- constant CFG_AHBDW : integer := 64; -- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores -- -- Valid values are 0 and 1 -- -- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package -- will read their data from the low part of the AHB data vector. -- -- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package -- will select valid data, as defined in the AMBA AHB standard, from the -- AHB data vectors based on the address input. If a core uses a function -- that does not have the address input, a failure will be asserted. -- constant CFG_AHB_ACDM : integer := 0; -- GRLIB_CONFIG_ARRAY - Array of configuration values -- -- The length of this array and the meaning of different positions is defined -- in the grlib.config_types package. constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := ( grlib_debug_level => 0, grlib_debug_mask => 0, grlib_techmap_strict_ram => 0, others => 0); end;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:06:01 10/23/2013 -- Design Name: -- Module Name: practica1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity practica1 is port ( switch: in std_logic_vector(7 downto 0); leds: out std_logic_vector(7 downto 0) ); end practica1; architecture Behavioral of practica1 is begin leds <= not(switch); end Behavioral;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: syncfifo_2p -- File: syncfifo_2p.vhd -- Author: Andrea Gianarro - Aeroflex Gaisler AB -- Description: Syncronous 2-port fifo with tech selection ----------------------------------------------------------------------------- -- Revisions: -- 2014/12/16 Pascal Trotta: support for generic fifo -- Notes: Generic fifo has the following features & limitations: -- -almost full is driven only in write clock domain; -- -almost empty is driven only in read clock domain; -- -full and empty are driven in both clock domains; -- -usedw is re-computed in each clock domain; -- -in "first word fall through" mode empty should be observed as data -- valid signal. If renable is asserted while empty='0', and at the -- next read clock rising edge empty='1', then new read data is not -- valid because fifo is empty. This does not apply in standard fifo -- mode, i.e., when empty is asserted, the last read data is valid; -- -supports only sepclk=1, i.e., asynchronous read/write clocks. -- -it works also if rclk = wclk, but synchronization stages and gray -- encoder/decoder are always instantiated, even if not necessary. ------------------------------------------------------------------------------ library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; use work.allmem.all; library grlib; use grlib.config.all; use grlib.config_types.all; use grlib.stdlib.all; entity syncfifo_2p is generic ( tech : integer := 0; -- target technology abits : integer := 10; -- fifo address bits (actual fifo depth = 2abits) dbits : integer := 32; -- fifo data width sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks pfull : integer := 100; -- almost full threshold (max 2abits - 3) pempty : integer := 10; -- almost empty threshold (min 2) fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode ); port ( rclk : in std_logic; -- read clock rrstn : in std_logic; -- read clock domain synchronous reset wrstn : in std_logic; -- write clock domain synchronous reset renable : in std_logic; -- read enable rfull : out std_logic; -- fifo full (synchronized in read clock domain) rempty : out std_logic; -- fifo empty aempty : out std_logic; -- fifo almost empty (depending on pempty threshold) rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain) dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output wclk : in std_logic; -- write clock write : in std_logic; -- write enable wfull : out std_logic; -- fifo full afull : out std_logic; -- fifo almost full (depending on pfull threshold) wempty : out std_logic; -- fifo empty (synchronized in write clock domain) wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain) datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input end; architecture rtl of syncfifo_2p is begin -- Altera fifo alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or (tech = stratix3) or (tech = stratix4) generate x0 : altera_fifo_dp generic map (tech, abits, dbits) port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk, write, wfull, wempty, wusedw, datain); end generate; -- generic FIFO implemented using syncram_2p component inf : if (tech /= altera) and (tech /= stratix1) and (tech /= stratix2) and (tech /= stratix3) and (tech /= stratix4) generate x0: generic_fifo generic map (tech, abits, dbits, sepclk, pfull, pempty, fwft) port map (rclk, rrstn, wrstn, renable, rfull, rempty, aempty, rusedw, dataout, wclk, write, wfull, afull, wempty, wusedw, datain); end generate; -- pragma translate_off nofifo : if (has_2pfifo(tech) = 0) and (has_2pram(tech) = 0) generate x : process begin assert false report "syncfifo_2p: technology " & tech_table(tech) & " not supported" severity failure; wait; end process; end generate; dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate x : process begin assert false report "syncfifo_2p: " & tost(2**abits) & "x" & tost(dbits) & " (" & tech_table(tech) & ")" severity note; wait; end process; end generate; -- pragma translate_on end;
------------------------------------------------------------------------------ ---- ---- ---- I2C Master Testbench ---- ---- ---- ---- Internal file, can't be downloaded. ---- ---- ---- ---- Description: ---- ---- I2C module test bench. Connects a Wishbone handler and an I2C ---- ---- memory to the module. Then it makes some write/read operations. ---- ---- The test cases are the same performed by the Verilog test bench by ---- ---- Richard Herveille. ---- ---- ---- ---- To Do: ---- ---- - ---- ---- ---- ---- Author: ---- ---- - Salvador E. Tropea, salvador en inti gov ar ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ---- ---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Covered by the GPL license. ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: TB(TestBench) (Entity and architecture) ---- ---- File name: tst_bench_top.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: i2c_mwb ---- ---- Dependencies: IEEE.std_logic_1164 ---- ---- IEEE.numeric_std ---- ---- c.stdio_h ---- ---- wb_handler.WishboneTB ---- ---- irq_ctrl.I2C_TB ---- ---- irq_ctrl.I2C_Master ---- ---- Target FPGA: None ---- ---- Language: VHDL ---- ---- Wishbone: None ---- ---- Synthesis tools: None ---- ---- Simulation tools: GHDL [Sokcho edition] (0.1x) ---- ---- Text editor: SETEdit 0.5.x ---- ---- ---- ------------------------------------------------------------------------------ -- -- CVS Revision History -- -- $Log: tst_bench_top.vhdl,v $ -- Revision 1.11 2006/04/17 19:44:43 salvador -- * Modified: License to GPL. -- -- Revision 1.10 2005/05/20 14:39:05 salvador -- * Modificado: Mejorado el indentado usando bakalint 0.3.7. -- -- Revision 1.9 2005/05/18 14:50:20 salvador -- * Modificado: Los encabezados de los archivos para que cumplan con nuestras -- recomendaciones. -- -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library c; use c.stdio_h.all; library wb_handler; use wb_handler.WishboneTB.all; library Work; use Work.I2C_TB.all; use Work.I2C_Master.all; entity TB is end entity TB; architecture TestBench of TB is -- Clock=100000 KHz constant CLKPERIOD : time:=10 us; signal delay : integer:=5; signal veces : integer:=0; signal addr : std_logic_vector(8-1 downto 0); signal datai : std_logic_vector(8-1 downto 0); signal datao : std_logic_vector(8-1 downto 0); signal rd : std_logic:='0'; signal wr : std_logic:='0'; signal rde : std_logic; signal wre : std_logic; signal wb_rst : std_logic:='1'; signal wb_clk : std_logic;--:='0'; signal wb_adr : std_logic_vector(8-1 downto 0); signal adr_o3 : unsigned(2 downto 0); signal wb_dati : std_logic_vector(8-1 downto 0):=(others => 'Z'); signal wb_dato : std_logic_vector(8-1 downto 0); signal wb_we : std_logic; signal wb_stb : std_logic; signal wb_cyc : std_logic; signal wb_ack : std_logic:='0'; signal inta : std_logic; signal scl_padi : std_logic; -- i2c clock line input signal scl_pado : std_logic; -- i2c clock line output signal scl_padoen : std_logic; -- i2c clock line output enable, active low signal sda_padi : std_logic; -- i2c data line input signal sda_pado : std_logic; -- i2c data line output signal sda_padoen : std_logic; -- i2c data line output enable, active low signal scl : std_logic; -- i2c clock line signal sda : std_logic; -- i2c data line signal sdar : std_logic; -- i2c data line signal sclr : std_logic; -- i2c data line constant PREV_LO : std_logic_vector(8-1 downto 0):="00000001"; constant PREV_HI : std_logic_vector(8-1 downto 0):="00000000"; constant RD_B : std_logic:='1'; constant WR_B : std_logic:='0'; constant SADR : std_logic_vector(6 downto 0):="0010000"; --Constant FIXED_PRER : integer:=-1; constant FIXED_PRER : integer:=1; procedure DelayCk(signal wb_clk_i: in std_logic; constant TIMES : in integer) is variable count : integer; begin count:=TIMES; while count>0 loop wait until rising_edge(wb_clk_i); count:=count-1; end loop; end procedure DelayCk; procedure CheckTIP(signal addr_o : out std_logic_vector(8-1 downto 0); signal data_i : in std_logic_vector(8-1 downto 0); signal rd_o : out std_logic; signal rde_i : in std_logic; constant ACKV : in boolean:=true) is begin WBRead(addr_o,I2C_SR,rd_o,rde_i); while data_i(1)='1' loop WBRead(addr_o,I2C_SR,rd_o,rde_i); end loop; if ACKV then assert data_i(7)='0' report "Expected ACK, received NACK" severity failure; else assert data_i(7)='1' report "Expected NACK, received ACK" severity failure; end if; end procedure CheckTIP; begin -- Clock clock_generator: process begin wb_clk <= '0'; wait for CLKPERIOD/2; wb_clk <= '1'; wait for CLKPERIOD/2; veces <= veces+1; if veces=1500 then assert false report "Fin de la simulación" severity failure; end if; end process clock_generator; -- Reset pulse p_reset: process begin wb_rst <= '1'; wait until rising_edge(wb_clk); wb_rst <= '0' after 500 ns; wait; end process p_reset; -- Wishbone master simulator wb_master: WBHandler port map( addr_i => addr, data_i => datai, data_o => datao, rd_i => rd, wr_i => wr, rde_o => rde, wre_o => wre, wb_rst_i => wb_rst, wb_clk_i => wb_clk, wb_ack_i => wb_ack, wb_adr_o => wb_adr, wb_dat_i => wb_dati, wb_dat_o => wb_dato, wb_we_o => wb_we, wb_stb_o => wb_stb, wb_cyc_o => wb_cyc); -- I2C module (Wishbone slave, I2C master) adr_o3 <= unsigned(wb_adr(2 downto 0)); wb_i2c: I2C_MasterTop generic map(DEBUG => false, FULL_SYNC => false, FIXED_PRER => FIXED_PRER) port map(-- Wishbone signals wb_clk_i => wb_clk, wb_rst_i => wb_rst, wb_adr_i => adr_o3, wb_dat_i => wb_dato, wb_dat_o => wb_dati, wb_we_i => wb_we, wb_stb_i => wb_stb, wb_cyc_i => wb_cyc, wb_ack_o => wb_ack, wb_inta_o => inta, -- i2c lines scl_pad_i => scl_padi, scl_pad_o => scl_pado, scl_padoen_o => scl_padoen, sda_pad_i => sda_padi, sda_pad_o => sda_pado, sda_padoen_o => sda_padoen); -- SCL/SDA pads scl <= 'Z' when scl_padoen='1' else scl_pado;-- after 600 ns; scl_padi <= sclr; scl <= 'H'; -- Pull-up sda <= 'Z' when sda_padoen='1' else sda_pado;-- after 600 ns; sda_padi <= sdar; sda <= 'H'; -- Pull-up -- SCL/SDA values converted to X/0/1/Z -- The I2C module can't handle 'H' sdar <= to_x01z(sda); sclr <= to_x01z(scl); -- I2C memory (I2C slave) i2c_mem: I2C_Memory generic map( I2C_ADR => SADR, DEBUG => false) port map( scl_x_i => scl, sda_x_io => sda, rst_i => wb_rst); sequence: process begin wait until wb_rst='0'; if FIXED_PRER=-1 then -- load prescaler lo-byte DelayCk(wb_clk,1); WBWrite(addr,I2C_PRER_LO,datai,PREV_LO,wr,wre); -- load prescaler hi-byte WBWrite(addr,I2C_PRER_HI,datai,PREV_HI,wr,wre); assert false report "Programmed registers" severity note; -- verify WBRead(addr,I2C_PRER_LO,rd,rde); if not(datao=PREV_LO) then printf("Prescaler lo: %s\n",datao); assert false report "Wrong prescaler lo readback" severity failure; end if; WBRead(addr,I2C_PRER_HI,rd,rde); assert datao=PREV_HI report "Wrong prescaler hi readback" severity failure; else assert false report "Using fixed pre-scaler" severity note; end if; -- enable core WBWrite(addr,I2C_CTR,datai,"10000000",wr,wre); -- 0x80 assert false report "Core Enabled" severity note; -- present slave address, set write-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate Start" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 01" severity note; CheckTIP(addr,datao,rd,rde); -- send memory contents -- present data WBWrite(addr,I2C_TXR,datai,"10100101",wr,wre); -- 0xA5 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write data 0xA5" severity note; CheckTIP(addr,datao,rd,rde); -- send memory contents for next memory address (auto_inc) -- present data WBWrite(addr,I2C_TXR,datai,"01011010",wr,wre); -- 0x5A -- set command (stop, write) WBWrite(addr,I2C_CR,datai,"01010000",wr,wre); -- 0x50 assert false report "Write next data 0x5A, generate 'stop'" severity note; CheckTIP(addr,datao,rd,rde); DelayCk(wb_clk,30); -- present slave address, set write-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate Start" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 01" severity note; CheckTIP(addr,datao,rd,rde); -- present slave address, set read-bit WBWrite(addr,I2C_TXR,datai,SADR & RD_B,wr,wre); -- 0x21 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate 'Repeated Start' (RD)" severity note; CheckTIP(addr,datao,rd,rde); -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); if unsigned(datao)=16#A5# then assert false report "Received ok" severity note; else printf("Wrong value: %s\n",datao); assert false report "Wrong value received" severity failure; end if; -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); if unsigned(datao)=16#5A# then assert false report "Received ok" severity note; else printf("Wrong value: %s\n",datao); assert false report "Wrong value received" severity failure; end if; -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); printf("Received 0x%X from 3rd read address\n",to_integer(unsigned(datao))); -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); printf("Received 0x%X from 4th read address\n",to_integer(unsigned(datao))); -- present slave address, set read-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate 'Repeated Start' (RD)" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00010000",wr,wre); -- 0x10 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 0x10" severity note; CheckTIP(addr,datao,rd,rde,false); assert false report "OK, NACK received" severity note; -- set command (stop) WBWrite(addr,I2C_CR,datai,"01000000",wr,wre); -- 0x40 assert false report "Sending stop" severity note; wait; end process sequence; end architecture TestBench; -- of entity TB
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 --Date : Thu Mar 10 15:45:23 2016 --Host : minmi running 64-bit elementary OS Freya --Command : generate_target system_wrapper.bd --Design : system_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC; sw0 : in STD_LOGIC; sw1 : in STD_LOGIC; sw2 : in STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ); hdmi_out_en : out STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; sw0 : in STD_LOGIC; sw1 : in STD_LOGIC; sw2 : in STD_LOGIC ); end component system; begin system_i: component system port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, hdmi_cec => hdmi_cec, hdmi_hpd => hdmi_hpd, hdmi_out_en => hdmi_out_en, sw0 => sw0, sw1 => sw1, sw2 => sw2, tmds(3 downto 0) => tmds(3 downto 0), tmdsb(3 downto 0) => tmdsb(3 downto 0) ); end STRUCTURE;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity I2C_ADN2816 is port (clk_i : in std_logic; sub_i2c_i: in std_logic; reset_n_i : in std_logic; sda_o : out std_logic; sda_dir_o : out std_logic; sclen_o: out std_logic); end I2C_ADN2816; architecture rtl of I2C_ADN2816 is type t_state is (waiting, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_SA7, send_SA6, send_SA5, send_SA4, send_SA3, send_SA2, send_SA1, send_SA0, read_SA_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, send_ACK, send_STOPCLK, send_PAUS1, send_PAUS2, send_PAUS3, send_PAUS4, send_PAUS5, send_PAUS6, send_PAUS7, send_STOP); signal s_state : t_state; signal s_count : std_logic; begin p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) sda_dir_o <= '1'; sda_o <= '1'; sclen_o <= '0'; s_count <= '0'; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is when send_START => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sclen_o <= '1'; sda_o <= '1'; s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= s_count; --sda_o <= '1'; old PCB version s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= '0'; s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= '0'; s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= '0'; s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= '0'; s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= '0'; s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= '0'; s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_SA7; ------------------------------------------------------------------------- when send_SA7 => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_SA6; ------------------------------------------------------------------------- when send_SA6 => sda_o <= '0'; s_state <= send_SA5; ------------------------------------------------------------------------- when send_SA5 => sda_o <= '0'; s_state <= send_SA4; ------------------------------------------------------------------------- when send_SA4 => sda_o <= '0'; s_state <= send_SA3; ------------------------------------------------------------------------- when send_SA3 => sda_o <= '1'; s_state <= send_SA2; ------------------------------------------------------------------------- when send_SA2 => sda_o <= '0'; s_state <= send_SA1; ------------------------------------------------------------------------- when send_SA1 => sda_o <= '0'; s_state <= send_SA0; ----------------------------------------------------------------------- when send_SA0 => sda_o <= '0'; s_state <= read_SA_ACK; ------------------------------------------------------------------------- when read_SA_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_D7; ------------------------------------------------------------------------- when send_D7 => sda_dir_o <= '1'; sda_o <= '1'; s_state <= send_D6; ------------------------------------------------------------------------- when send_D6 => sda_o <= '1'; s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= '0'; s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= '1'; s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= '0'; s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= '1'; s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= '0'; s_state <= send_D0; ------------------------------------------------------------------------- when send_D0 => sda_o <= '1'; s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_STOPCLK; ------------------------------------------------------------------------- when send_STOPCLK => sda_dir_o <= '1'; sda_o <= '0'; --sclen_o <= '0'; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; s_state <= send_PAUS1; ------------------------------------------------------------------------- when send_PAUS1 => if (s_count ='0') then s_state <= send_PAUS2; else s_state <= waiting; end if; ------------------------------------------------------------------------- when send_PAUS2 => s_count <= '1'; s_state <= send_PAUS3; ------------------------------------------------------------------------- when send_PAUS3 => s_state <= send_PAUS4; ------------------------------------------------------------------------- when send_PAUS4 => s_state <= send_PAUS5; ------------------------------------------------------------------------- when send_PAUS5 => s_state <= send_PAUS6; ------------------------------------------------------------------------- when send_PAUS6 => s_state <= send_PAUS7; ------------------------------------------------------------------------- when send_PAUS7 => s_state <= send_START; ------------------------------------------------------ when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_count <= '0'; s_state <= send_START; end if; end case; end if; end process p_i2cmaster; end rtl;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity I2C_ADN2816 is port (clk_i : in std_logic; sub_i2c_i: in std_logic; reset_n_i : in std_logic; sda_o : out std_logic; sda_dir_o : out std_logic; sclen_o: out std_logic); end I2C_ADN2816; architecture rtl of I2C_ADN2816 is type t_state is (waiting, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_SA7, send_SA6, send_SA5, send_SA4, send_SA3, send_SA2, send_SA1, send_SA0, read_SA_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, send_ACK, send_STOPCLK, send_PAUS1, send_PAUS2, send_PAUS3, send_PAUS4, send_PAUS5, send_PAUS6, send_PAUS7, send_STOP); signal s_state : t_state; signal s_count : std_logic; begin p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) sda_dir_o <= '1'; sda_o <= '1'; sclen_o <= '0'; s_count <= '0'; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is when send_START => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sclen_o <= '1'; sda_o <= '1'; s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= s_count; --sda_o <= '1'; old PCB version s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= '0'; s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= '0'; s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= '0'; s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= '0'; s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= '0'; s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= '0'; s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_SA7; ------------------------------------------------------------------------- when send_SA7 => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_SA6; ------------------------------------------------------------------------- when send_SA6 => sda_o <= '0'; s_state <= send_SA5; ------------------------------------------------------------------------- when send_SA5 => sda_o <= '0'; s_state <= send_SA4; ------------------------------------------------------------------------- when send_SA4 => sda_o <= '0'; s_state <= send_SA3; ------------------------------------------------------------------------- when send_SA3 => sda_o <= '1'; s_state <= send_SA2; ------------------------------------------------------------------------- when send_SA2 => sda_o <= '0'; s_state <= send_SA1; ------------------------------------------------------------------------- when send_SA1 => sda_o <= '0'; s_state <= send_SA0; ----------------------------------------------------------------------- when send_SA0 => sda_o <= '0'; s_state <= read_SA_ACK; ------------------------------------------------------------------------- when read_SA_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_D7; ------------------------------------------------------------------------- when send_D7 => sda_dir_o <= '1'; sda_o <= '1'; s_state <= send_D6; ------------------------------------------------------------------------- when send_D6 => sda_o <= '1'; s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= '0'; s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= '1'; s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= '0'; s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= '1'; s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= '0'; s_state <= send_D0; ------------------------------------------------------------------------- when send_D0 => sda_o <= '1'; s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_STOPCLK; ------------------------------------------------------------------------- when send_STOPCLK => sda_dir_o <= '1'; sda_o <= '0'; --sclen_o <= '0'; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; s_state <= send_PAUS1; ------------------------------------------------------------------------- when send_PAUS1 => if (s_count ='0') then s_state <= send_PAUS2; else s_state <= waiting; end if; ------------------------------------------------------------------------- when send_PAUS2 => s_count <= '1'; s_state <= send_PAUS3; ------------------------------------------------------------------------- when send_PAUS3 => s_state <= send_PAUS4; ------------------------------------------------------------------------- when send_PAUS4 => s_state <= send_PAUS5; ------------------------------------------------------------------------- when send_PAUS5 => s_state <= send_PAUS6; ------------------------------------------------------------------------- when send_PAUS6 => s_state <= send_PAUS7; ------------------------------------------------------------------------- when send_PAUS7 => s_state <= send_START; ------------------------------------------------------ when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_count <= '0'; s_state <= send_START; end if; end case; end if; end process p_i2cmaster; end rtl;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1402.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01402ent IS END c08s05b00x00p06n01i01402ent; ARCHITECTURE c08s05b00x00p06n01i01402arch OF c08s05b00x00p06n01i01402ent IS BEGIN TESTING: PROCESS type PT is range INTEGER'LOW to INTEGER'HIGH units sbu; end units; subtype ST is PT range 1 sbu to 10 sbu; variable ILL : PT := 11 sbu; variable V : ST; BEGIN V := ILL; -- should catch error here assert FALSE report "***FAILED TEST: c08s05b00x00p06n01i01402 - Variable assignment scalar subtype (physical type) check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01402arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1402.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01402ent IS END c08s05b00x00p06n01i01402ent; ARCHITECTURE c08s05b00x00p06n01i01402arch OF c08s05b00x00p06n01i01402ent IS BEGIN TESTING: PROCESS type PT is range INTEGER'LOW to INTEGER'HIGH units sbu; end units; subtype ST is PT range 1 sbu to 10 sbu; variable ILL : PT := 11 sbu; variable V : ST; BEGIN V := ILL; -- should catch error here assert FALSE report "***FAILED TEST: c08s05b00x00p06n01i01402 - Variable assignment scalar subtype (physical type) check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01402arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1402.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01402ent IS END c08s05b00x00p06n01i01402ent; ARCHITECTURE c08s05b00x00p06n01i01402arch OF c08s05b00x00p06n01i01402ent IS BEGIN TESTING: PROCESS type PT is range INTEGER'LOW to INTEGER'HIGH units sbu; end units; subtype ST is PT range 1 sbu to 10 sbu; variable ILL : PT := 11 sbu; variable V : ST; BEGIN V := ILL; -- should catch error here assert FALSE report "***FAILED TEST: c08s05b00x00p06n01i01402 - Variable assignment scalar subtype (physical type) check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01402arch;
architecture RTL of FIFO is procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 is constant width : integer := 32; begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is constant width : integer := 32; begin end procedure proc1; -- Fixes follow procedure proc1 is constant width : integer := 32; begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is constant width : integer := 32; begin end procedure proc1; begin end architecture RTL;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Sumador is Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0); Operador2 : in STD_LOGIC_VECTOR (31 downto 0); Resultado : out STD_LOGIC_VECTOR (31 downto 0)); end Sumador; architecture Behavioral of sumador is begin process(Operador1,Operador2) begin Resultado <= Operador1 + Operador2; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Sumador is Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0); Operador2 : in STD_LOGIC_VECTOR (31 downto 0); Resultado : out STD_LOGIC_VECTOR (31 downto 0)); end Sumador; architecture Behavioral of sumador is begin process(Operador1,Operador2) begin Resultado <= Operador1 + Operador2; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity iq_ram is generic ( DATA_SIZE : integer := 16; ADDR_SIZE : integer := 13; AXI_SIZE : integer := 32 ); port ( -- AXi clk : in std_logic; rst : in std_logic; axi_addr : in std_logic_vector(AXI_SIZE-1 downto 0); axi_wrdata : in std_logic_vector(AXI_SIZE-1 downto 0); axi_rddata : out std_logic_vector(AXI_SIZE-1 downto 0); axi_cs : in std_logic_vector(1 downto 0); axi_rnw : in std_logic; axi_wrack : out std_logic; axi_rdack : out std_logic; axi_error : out std_logic; -- iQ SX1255 data_en : in std_logic; data_i : in std_logic_vector(DATA_SIZE-1 downto 0); data_q : in std_logic_vector(DATA_SIZE-1 downto 0); -- int CPU iRQ : out std_logic ); end entity; architecture rtl of iq_ram is component iq_ctrl is generic ( DATA_SIZE : integer := 16; ADDR_SIZE : integer := 13; AXI_SIZE : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; mux : out std_logic_vector(1 downto 0); new_sample : in std_logic; data_i_in : in std_logic_vector(DATA_SIZE-1 downto 0); data_q_in : in std_logic_vector(DATA_SIZE-1 downto 0); we_a : out std_logic; data_a : out std_logic_vector((2*DATA_SIZE)-1 downto 0); addr_a : out std_logic_vector(ADDR_SIZE-1 downto 0); irq : out std_logic ); end component; component iq_decim is generic ( DATA_SIZE : integer := 16; AXI_SIZE : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; start_acq : in std_logic; decim_in : in std_logic_vector(AXI_SIZE-1 downto 0); data_en : in std_logic; data_i_in : in std_logic_vector(DATA_SIZE-1 downto 0); data_q_in : in std_logic_vector(DATA_SIZE-1 downto 0); new_sample : out std_logic; data_i_out : out std_logic_vector(DATA_SIZE-1 downto 0); data_q_out : out std_logic_vector(DATA_SIZE-1 downto 0) ); end component; component iq_axi is generic ( AXI_SIZE : integer:= 32; ADDR_SIZE : integer := 13 ); port( -- AXi clk : in std_logic; rst : in std_logic; axi_addr : in std_logic_vector(AXI_SIZE-1 downto 0); axi_wrdata : in std_logic_vector(AXI_SIZE-1 downto 0); axi_rddata : out std_logic_vector(AXI_SIZE-1 downto 0); axi_cs : in std_logic_vector(1 downto 0); axi_rnw : in std_logic; axi_wrack : out std_logic; axi_rdack : out std_logic; axi_error : out std_logic; -- iQ FLOW start_acq : out std_logic; decim : out std_logic_vector(AXI_SIZE-1 downto 0); mux : in std_logic_vector(1 downto 0); -- RAM addr_b : out std_logic_vector(ADDR_SIZE-1 downto 0); data_b : in std_logic_vector(AXI_SIZE-1 downto 0) ); end component; component dual_port_ram is generic ( DATA : integer := 32; ADDR : integer := 13 ); port ( clk_a : in std_logic; clk_b : in std_logic; -- PORT A we_a : in std_logic; addr_a: in std_logic_vector(ADDR-1 downto 0); din_a : in std_logic_vector(DATA-1 downto 0); dout_a : out std_logic_vector(DATA-1 downto 0); -- PORT B we_b : in std_logic; addr_b: in std_logic_vector(ADDR-1 downto 0); din_b : in std_logic_vector(DATA-1 downto 0); dout_b: out std_logic_vector(DATA-1 downto 0) ); end component; signal start_acq_s : std_logic; signal we_a_s : std_logic; signal addr_a_s : std_logic_vector(ADDR_SIZE-1 downto 0); signal data_a_s : std_logic_vector(AXI_SIZE-1 downto 0); signal addr_b_s : std_logic_vector(ADDR_SIZE-1 downto 0); signal din_b_s : std_logic_vector(AXI_SIZE-1 downto 0); signal data_b_s : std_logic_vector(AXI_SIZE-1 downto 0); signal mux_s : std_logic_vector(1 downto 0); signal decim_s : std_logic_vector(AXI_SIZE-1 downto 0); signal new_sample_s : std_logic; signal data_i_s : std_logic_vector(DATA_SIZE-1 downto 0); signal data_q_s : std_logic_vector(DATA_SiZE-1 downto 0); begin CTRL: iq_ctrl generic map ( DATA_SIZE => DATA_SIZE, ADDR_SIZE => ADDR_SIZE, AXI_SIZE => AXI_SIZE ) port map ( -- Ctrl clk => clk, rst => rst, mux => mux_s, new_sample => new_sample_s, data_i_in => data_i_s, data_q_in => data_q_s, we_a => we_a_s, data_a => data_a_s, addr_a => addr_a_s, irq => irq ); DECIM: iq_decim generic map( DATA_SIZE => DATA_SIZE, AXI_SIZE => AXI_SIZE ) port map ( clk => clk, rst => rst, start_acq => start_acq_s, decim_in => decim_s, data_en => data_en, data_i_in => data_i, data_q_in => data_q, new_sample => new_sample_s, data_i_out => data_i_s, data_q_out => data_q_s ); AXI: iq_axi generic map ( AXI_SIZE => AXI_SIZE, ADDR_SIZE => ADDR_SIZE ) port map ( -- AXi clk => clk, rst => rst, axi_addr => axi_addr, axi_wrdata => axi_wrdata, axi_rddata => axi_rddata, axi_cs => axi_cs, axi_rnw => axi_rnw, axi_wrack => axi_wrack, axi_rdack => axi_rdack, axi_error => axi_error, -- IQ Ctrl start_acq => start_acq_s, decim => decim_s, mux => mux_s, -- RAM addr_b => addr_b_s, data_b => data_b_s ); din_b_s <= (others => '0'); RAM: dual_port_ram generic map ( DATA => AXI_SIZE, ADDR => ADDR_SIZE ) port map ( clk_a => clk, clk_b => clk, -- PORT A we_a => we_a_s, addr_a => addr_a_s, din_a => data_a_s, dout_a => open, -- PORT B we_b => '0', addr_b => addr_b_s, din_b => din_b_s, dout_b => data_b_s ); end rtl;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:08:42 06/06/2016 -- Design Name: -- Module Name: C:/Users/AlvaroMoreno/Desktop/PROCESADOR2016/Sacagawea-master/test_memes.vhd -- Project Name: Sacagawea -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Dispositivos -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_memes IS END test_memes; ARCHITECTURE behavior OF test_memes IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Dispositivos PORT( ar : IN std_logic_vector(11 downto 0); clk : IN std_logic; ram_w_r : IN std_logic; bus_datos : INOUT std_logic_vector(7 downto 0); sal_leds_spartan : OUT std_logic_vector(7 downto 0); in_switches_spartan : IN std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal ar : std_logic_vector(11 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal ram_w_r : std_logic := '0'; signal in_switches_spartan : std_logic_vector(7 downto 0) := (others => '0'); --BiDirs signal bus_datos : std_logic_vector(7 downto 0); --Outputs signal sal_leds_spartan : std_logic_vector(7 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: Dispositivos PORT MAP ( ar => ar, clk => clk, ram_w_r => ram_w_r, bus_datos => bus_datos, sal_leds_spartan => sal_leds_spartan, in_switches_spartan => in_switches_spartan ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; clk <= '0'; bus_datos <= X"53"; ram_w_r <= '1'; ar <= X"400"; wait for 100 ns; clk <= '1'; bus_datos <= X"53"; wait for 100 ns; wait; end process; END;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alu is port ( op1: in std_logic_vector(31 downto 0); op2: in std_logic_vector(31 downto 0); alu_op: in std_logic_vector(3 downto 0); result: out std_logic_vector(31 downto 0); zero: out std_logic; less_than: out std_logic ); end alu; architecture arch_alu of alu is signal r, shift: std_logic_vector(31 downto 0); signal shift_op2: std_logic_vector(4 downto 0); signal addsub: std_logic_vector(32 downto 0); signal less, left, logical: std_logic; begin process(op1, op2, alu_op, addsub, less, shift_op2, shift) begin case alu_op is when "0000" => r <= op1 and op2; when "0001" => r <= op1 or op2; when "0010" => r <= op1 xor op2; when "0011" => r <= op1 nor op2; when "0100" \| "0101" => r <= addsub(31 downto 0); when "0110" => r <= op2(15 downto 0) & x"0000"; when "0111" \| "1000" => r <= x"0000000" & "000" & less; when others => r <= shift; end case; end process; addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2); less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31); less_than <= less; zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0)); shift_op2 <= op2(10 downto 6) when alu_op < "1100" else op2(4 downto 0); left <= '1' when alu_op = "1001" or alu_op = "1100" else '0'; logical <= '0' when alu_op = "1011" or alu_op = "1110" else '1'; barrel_shifter: entity work.bshift port map( left => left, logical => logical, shift => shift_op2, input => op1, output => shift ); result <= r; end arch_alu;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
--*************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --*************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" ) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT to DQS_DELAY. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --***************************************** -- PLL_LOCK and RST signals --**************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --********************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --********************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --**************************************** -- SUSPEND Logic --**************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --**************************************** --Comparitor for Dynamic Calibration circuit --**************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --***************************************************************************************** --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --***************************************************************************************** process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --***************************************************************************************** -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --***************************************************************************************** process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --********************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --********************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*********************** -- IOB INPUT TERMINATION CAL --*********************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ***************** when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; -- when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ******************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*********************** --DYNAMIC CALIBRATION PORTION --************************* when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart is PORT( CLK_I : in std_logic; CLR : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); end uart; architecture Behavioral of uart is COMPONENT uart_tx PORT( CLK_I : IN std_logic; CLR : IN std_logic; CE_16 : IN std_logic; DATA : IN std_logic_vector(7 downto 0); DATA_FLAG : IN std_logic; SER_OUT : OUT std_logic; DATA_FLAGQ : OUT std_logic ); END COMPONENT; COMPONENT uart_rx PORT( CLK_I : IN std_logic; CLR : IN std_logic; CE_16 : IN std_logic; SER_IN : IN std_logic; DATA : OUT std_logic_vector(7 downto 0); DATA_FLAG : OUT std_logic ); END COMPONENT; begin tx: uart_tx PORT MAP( CLK_I => CLK_I, CLR => CLR, CE_16 => CE_16, DATA => TX_DATA, DATA_FLAG => TX_FLAG, SER_OUT => TX_SEROUT, DATA_FLAGQ => TX_FLAGQ ); rx: uart_rx PORT MAP( CLK_I => CLK_I, CLR => CLR, CE_16 => CE_16, DATA => RX_DATA, SER_IN => RX_SERIN, DATA_FLAG => RX_FLAG ); end Behavioral;
-- a_ng.vhd package TEST_TYPES is type WIDTH_TYPE is record DATA : integer; end record; end package; use work.TEST_TYPES.all; entity TEST_SUB is generic ( WIDTH : WIDTH_TYPE ); port ( DATA_I : in bit_vector(WIDTH.DATA-1 downto 0); DATA_O : out bit_vector(WIDTH.DATA-1 downto 0) ); end TEST_SUB; architecture MODEL of TEST_SUB is begin DATA_O <= DATA_I; end MODEL; use work.TEST_TYPES.all; entity TEST_NG is end TEST_NG; architecture MODEL of TEST_NG is constant WIDTH : WIDTH_TYPE := (DATA => 8); -- Could not fold this signal DATA_I : bit_vector(WIDTH.DATA-1 downto 0); signal DATA_O : bit_vector(WIDTH.DATA-1 downto 0); begin DUT: entity WORK.TEST_SUB generic map (WIDTH => WIDTH) port map (DATA_I => DATA_I, DATA_O => DATA_O); process begin DATA_I <= "00000000"; wait for 10 ns; assert(DATA_O /= "00000000") report "OK." severity NOTE; assert(DATA_O = "00000000") report "NG." severity ERROR; DATA_I <= "00000001"; wait for 10 ns; assert(DATA_O /= "00000001") report "OK." severity NOTE; assert(DATA_O = "00000001") report "NG." severity ERROR; assert FALSE report "Simulation complete." severity FAILURE; end process; end MODEL;
-- a_ng.vhd package TEST_TYPES is type WIDTH_TYPE is record DATA : integer; end record; end package; use work.TEST_TYPES.all; entity TEST_SUB is generic ( WIDTH : WIDTH_TYPE ); port ( DATA_I : in bit_vector(WIDTH.DATA-1 downto 0); DATA_O : out bit_vector(WIDTH.DATA-1 downto 0) ); end TEST_SUB; architecture MODEL of TEST_SUB is begin DATA_O <= DATA_I; end MODEL; use work.TEST_TYPES.all; entity TEST_NG is end TEST_NG; architecture MODEL of TEST_NG is constant WIDTH : WIDTH_TYPE := (DATA => 8); -- Could not fold this signal DATA_I : bit_vector(WIDTH.DATA-1 downto 0); signal DATA_O : bit_vector(WIDTH.DATA-1 downto 0); begin DUT: entity WORK.TEST_SUB generic map (WIDTH => WIDTH) port map (DATA_I => DATA_I, DATA_O => DATA_O); process begin DATA_I <= "00000000"; wait for 10 ns; assert(DATA_O /= "00000000") report "OK." severity NOTE; assert(DATA_O = "00000000") report "NG." severity ERROR; DATA_I <= "00000001"; wait for 10 ns; assert(DATA_O /= "00000001") report "OK." severity NOTE; assert(DATA_O = "00000001") report "NG." severity ERROR; assert FALSE report "Simulation complete." severity FAILURE; end process; end MODEL;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block FiRDw6U5z83hiay+R7/kE36EBhu9NTOgbGEuGmX/l+AzJ9q+qLxTSGaI44CZ6gJ2ITLhLIcrLjy0 Gj3sMAAsrw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XxJIyOmQ3LRxBn0+7R8dX7VuxfJSZ3WBZjmI23g2Kj6M4ksvO3qfawS3cUSKO2ZpMKJWu3KESMN3 j+FrdJOZ2T4yL2w1pgTVaqYCd1arF2PWvZ6S6ZO3eYJlyl1XgUoevC2qxcDypQZB8gFmnjjrVypS 0rO49wXStZs5nqI3XBo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Md1t2sbI8hjvsD0SKBXkLqSAPhLt67LGojsGIZYmYJW2k46K8lwTKuuy9g9INqIzmVoURRfd9Aab F9paMs4Jj2RW9iVypsrctlRZH7JIMtb3I1GA7YdKuIObWSg458evRgHlDnBkNLeKC4rZ9DiwiYvb LleALbOvq8+NLhUVpw3CwqlDwdqTxylVJKRks+bIhjSgQAeKBt7gmUFCB2+Y1bDNWY+gZaMKOez9 9ZVUfvbPZTyiDV8rhvvr5wk//Zs+sTBVwvPaTSoKQNLQTYVmac6T3ECPju8PAnygz1ZJ+jbEcBun xAMORCFN3oSNaxzB1Hn2PLfFjarv9TrJYfNzow== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KR9qweSer6wqBlOJkDXzgy1GQ5R1ZaCiKgJWVKTIjS/iOvu5ikSYJXoS6PYj45LRnSNOaZt14pzQ LMDZ+P55I42iOCs7zl+OfAL+PPO8i1VRB7GwDewISJ0+g7nJIIn4bAjJXGtVcOBR7u2mfpDMiMsb cj6Mi7JdeIJBVowm55Q= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IPrZTgrAaJEBXoqcbPkPvtrRJ3QY1Ba8hdSzZw0JL3mt/wn++mf/eEuARjlbsCIOUSmficaV3uIo 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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity filter_with_file_write is port( data_ext: in std_logic_vector( 7 downto 0); clock, start, rst: in std_logic; mem_b_out: out std_logic_vector( 7 downto 0); done: out std_logic); end filter_with_file_write; architecture behavior of filter_with_file_write is component datapath port( x: in std_logic_vector(7 downto 0); y: out std_logic_vector(7 downto 0); clock: in std_logic; rst_shift, enable_shift: in std_logic; rst_sum, enable_sum: in std_logic; rst_count, enable_count: in std_logic; count_out: out std_logic_vector(9 downto 0); module, cntrl: in std_logic; mux1_sel: in std_logic_vector(2 downto 0); terminal_count: out std_logic); end component; component control_unit port ( module: out std_logic; cntrl: out std_logic; enable_sum: out std_logic; enable_shift: out std_logic; clock: in std_logic; rst_shift: out std_logic; cs_a,cs_b,wr_rd_a,wr_rd_b: out std_logic; finished: out std_logic; rst_count: out std_logic; up_count: out std_logic; start: in std_logic; rst_sum: out std_logic; mux1_sel: out std_logic_vector(2 downto 0); reset: in std_logic; exceed: in std_logic); end component; component ram_1024X8 port( data_in: in std_logic_vector(7 downto 0); address: in integer range 1023 downto 0; cs: in std_logic; clk: in std_logic; wr_rd_n: in std_logic; data_out: out std_logic_vector (7 downto 0)); end component; signal mem_a_out, mem_b_in: std_logic_vector (7 downto 0); signal rst_shift, enable_shift: std_logic; signal rst_sum, enable_sum: std_logic; signal rst_count, enable_count: std_logic; signal count_out: std_logic_vector(9 downto 0); signal module, cntrl: std_logic; signal mux1_sel: std_logic_vector(2 downto 0); signal cs_a,cs_b,wr_rd_a,wr_rd_b: std_logic; signal exceed:std_logic; signal add: integer:=0; begin datapath: datapath port map(mem_a_out, mem_b_in, clock, rst_shift, enable_shift, rst_sum, enable_sum, rst_count,enable_count, count_out, module, cntrl, mux1_sel, exceed); cu: control_unit port map(module,cntrl,enable_sum, enable_shift, clock, rst_shift, cs_a, cs_b, wr_rd_a, wr_rd_b, done,rst_count,enable_count, start, rst_sum, mux1_sel, rst, exceed); add<= to_integer(unsigned(count_out)); ram_a: ram_1024x8 port map(data_ext,add, cs_a, clock, wr_rd_a, mem_a_out); ram_b: ram_1024x8 port map(mem_b_in,add, cs_b, clock, wr_rd_b, mem_b_out); process (clock) file ofile: TEXT is out "data_in_b"; variable buf:line; variable datab: integer; begin if(clock'event and clock='1') then if (cs_b = '1' and wr_rd_b = '0') then datab := to_integer(signed(mem_b_in)); write(buf,datab); writeline(ofile,buf); end if; end if; end process; end architecture;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity feedforward_p_uOut_ram is generic( mem_type : string := "block"; dwidth : integer := 64; awidth : integer := 8; mem_size : integer := 140 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of feedforward_p_uOut_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then q1 <= ram(CONV_INTEGER(addr1_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity feedforward_p_uOut is generic ( DataWidth : INTEGER := 64; AddressRange : INTEGER := 140; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of feedforward_p_uOut is component feedforward_p_uOut_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR); end component; begin feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1); end architecture;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity feedforward_p_uOut_ram is generic( mem_type : string := "block"; dwidth : integer := 64; awidth : integer := 8; mem_size : integer := 140 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of feedforward_p_uOut_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then q1 <= ram(CONV_INTEGER(addr1_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity feedforward_p_uOut is generic ( DataWidth : INTEGER := 64; AddressRange : INTEGER := 140; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of feedforward_p_uOut is component feedforward_p_uOut_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR); end component; begin feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1); end architecture;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:51:59 05/12/2014 -- Design Name: -- Module Name: encoder_interface - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity encoder_interface is generic(FREQ_DIV : positive := 100; SINGLE_CHANNEL : boolean := true); port( clk, reset : in std_logic ; channel_a, channel_b : in std_logic; period : out std_logic_vector(15 downto 0); pv : out std_logic ; count : out std_logic_vector(15 downto 0); reset_count : in std_logic ); end encoder_interface; architecture Behavioral of encoder_interface is constant DEBOUNCER_DIV : positive := 10 ; type enc_states is (IDLE, A_H, B_H, A_L, B_L); signal cur_state, next_state : enc_states ; signal period_counter, period_latched, pulse_counter : std_logic_vector(15 downto 0); signal divider_counter : std_logic_vector(15 downto 0); signal end_div : std_logic ; signal inc_counter, dec_counter, valid_cw, valid_ccw, latch_period : std_logic ; signal channel_a_deb, channel_b_deb : std_logic ; signal debouncer_counter : std_logic_vector(15 downto 0); begin -- simple debouncer process(clk, reset) begin if reset = '1' then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; else debouncer_counter <= debouncer_counter - 1 ; end if ; end if ; end process; gen_sing : if SINGLE_CHANNEL = true generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_a_deb; end if ; end if ; end process ; end generate ; gen_no_sing : if SINGLE_CHANNEL = false generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_b; end if ; end if ; end process ; end generate ; -- end of debouncer process(clk, reset) begin if reset = '1' then cur_state <= IDLE ; elsif clk'event and clk='1' then cur_state <= next_state ; end if ; end process ; process(cur_state, channel_a_deb, channel_b_deb) begin next_state <= cur_state ; case cur_state is when IDLE => if channel_a_deb = '1' and channel_b_deb='0' then next_state <= A_H ; end if ; if channel_b_deb = '1' and channel_a_deb='0' then next_state <= A_L ; end if ; when A_H => if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; when B_H => if channel_a_deb = '0' and channel_b_deb = '1' then next_state <= A_L ; end if ; if channel_b_deb = '0' and channel_a_deb = '1' then next_state <= A_H ; end if ; when A_L => if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; when others => next_state <= IDLE ; end case ; end process ; inc_counter <= '1' when cur_state = IDLE and next_state = A_H else '0' ; dec_counter <= '1' when cur_state = A_H and next_state = IDLE else '0' ; latch_period <= '1' when cur_state = IDLE and channel_a_deb = '1' else '1' when cur_state = IDLE and channel_b_deb = '1' else '0' ; process(clk, reset) begin if reset = '1' then valid_cw <= '0' ; valid_ccw <= '0' ; elsif clk'event and clk='1' then if cur_state = IDLE and channel_a_deb='1' then valid_cw <= '1' ; elsif cur_state = A_H and channel_a_deb='0' then valid_cw <= '0' ; elsif cur_state = B_H and channel_b_deb='0' then valid_cw <= '0' ; elsif cur_state = A_L and channel_a_deb='1' then valid_cw <= '0' ; elsif cur_state = IDLE and channel_b_deb='1' then valid_cw <= '0' ; end if ; if cur_state = IDLE and channel_b_deb='1' then valid_ccw <= '1' ; elsif cur_state = A_L and channel_b_deb='0' then valid_ccw <= '0' ; elsif cur_state = B_H and channel_a_deb='0' then valid_ccw <= '0' ; elsif cur_state = A_H and channel_b_deb='1' then valid_ccw <= '0' ; elsif cur_state = IDLE and channel_a_deb='1' then valid_ccw <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then divider_counter <= (others => '0') ; elsif clk'event and clk='1' then if end_div = '1' then divider_counter <= std_logic_vector(to_unsigned(FREQ_DIV-1, 16)) ; else divider_counter <= divider_counter - 1 ; end if ; end if ; end process ; end_div <= '1' when divider_counter = 0 else '0' ; process(clk, reset) begin if reset = '1' then period_counter <= (others => '0') ; elsif clk'event and clk='1' then if latch_period = '1' then period_counter <= (others => '0') ; elsif end_div = '1' and period_counter /= X"7FFF" and period_counter /= X"8000" then period_counter <= period_counter + 1 ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then period_latched <= (others => '0') ; pv <= '0' ; elsif clk'event and clk='1' then if latch_period = '1' and ((valid_ccw = '1' and channel_b_deb='1') or (valid_cw = '1' and channel_a_deb='1') ) then if valid_ccw = '0' and valid_cw = '1' then period_latched <= period_counter ; else period_latched <= (NOT period_counter) + 1 ; end if; pv <= '1' ; elsif period_counter = X"7FFF" or period_counter = X"8000" then period_latched <= X"8000" ; pv <= '1' ; else pv <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then pulse_counter <= (others => '0') ; elsif clk'event and clk='1' then if reset_count = '1' then pulse_counter <= (others => '0') ; elsif inc_counter = '1' then pulse_counter <= pulse_counter + 1 ; elsif dec_counter = '1' then pulse_counter <= pulse_counter - 1 ; end if ; end if ; end process ; period <= period_latched ; count <= pulse_counter ; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:51:59 05/12/2014 -- Design Name: -- Module Name: encoder_interface - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity encoder_interface is generic(FREQ_DIV : positive := 100; SINGLE_CHANNEL : boolean := true); port( clk, reset : in std_logic ; channel_a, channel_b : in std_logic; period : out std_logic_vector(15 downto 0); pv : out std_logic ; count : out std_logic_vector(15 downto 0); reset_count : in std_logic ); end encoder_interface; architecture Behavioral of encoder_interface is constant DEBOUNCER_DIV : positive := 10 ; type enc_states is (IDLE, A_H, B_H, A_L, B_L); signal cur_state, next_state : enc_states ; signal period_counter, period_latched, pulse_counter : std_logic_vector(15 downto 0); signal divider_counter : std_logic_vector(15 downto 0); signal end_div : std_logic ; signal inc_counter, dec_counter, valid_cw, valid_ccw, latch_period : std_logic ; signal channel_a_deb, channel_b_deb : std_logic ; signal debouncer_counter : std_logic_vector(15 downto 0); begin -- simple debouncer process(clk, reset) begin if reset = '1' then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; else debouncer_counter <= debouncer_counter - 1 ; end if ; end if ; end process; gen_sing : if SINGLE_CHANNEL = true generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_a_deb; end if ; end if ; end process ; end generate ; gen_no_sing : if SINGLE_CHANNEL = false generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_b; end if ; end if ; end process ; end generate ; -- end of debouncer process(clk, reset) begin if reset = '1' then cur_state <= IDLE ; elsif clk'event and clk='1' then cur_state <= next_state ; end if ; end process ; process(cur_state, channel_a_deb, channel_b_deb) begin next_state <= cur_state ; case cur_state is when IDLE => if channel_a_deb = '1' and channel_b_deb='0' then next_state <= A_H ; end if ; if channel_b_deb = '1' and channel_a_deb='0' then next_state <= A_L ; end if ; when A_H => if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; when B_H => if channel_a_deb = '0' and channel_b_deb = '1' then next_state <= A_L ; end if ; if channel_b_deb = '0' and channel_a_deb = '1' then next_state <= A_H ; end if ; when A_L => if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; when others => next_state <= IDLE ; end case ; end process ; inc_counter <= '1' when cur_state = IDLE and next_state = A_H else '0' ; dec_counter <= '1' when cur_state = A_H and next_state = IDLE else '0' ; latch_period <= '1' when cur_state = IDLE and channel_a_deb = '1' else '1' when cur_state = IDLE and channel_b_deb = '1' else '0' ; process(clk, reset) begin if reset = '1' then valid_cw <= '0' ; valid_ccw <= '0' ; elsif clk'event and clk='1' then if cur_state = IDLE and channel_a_deb='1' then valid_cw <= '1' ; elsif cur_state = A_H and channel_a_deb='0' then valid_cw <= '0' ; elsif cur_state = B_H and channel_b_deb='0' then valid_cw <= '0' ; elsif cur_state = A_L and channel_a_deb='1' then valid_cw <= '0' ; elsif cur_state = IDLE and channel_b_deb='1' then valid_cw <= '0' ; end if ; if cur_state = IDLE and channel_b_deb='1' then valid_ccw <= '1' ; elsif cur_state = A_L and channel_b_deb='0' then valid_ccw <= '0' ; elsif cur_state = B_H and channel_a_deb='0' then valid_ccw <= '0' ; elsif cur_state = A_H and channel_b_deb='1' then valid_ccw <= '0' ; elsif cur_state = IDLE and channel_a_deb='1' then valid_ccw <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then divider_counter <= (others => '0') ; elsif clk'event and clk='1' then if end_div = '1' then divider_counter <= std_logic_vector(to_unsigned(FREQ_DIV-1, 16)) ; else divider_counter <= divider_counter - 1 ; end if ; end if ; end process ; end_div <= '1' when divider_counter = 0 else '0' ; process(clk, reset) begin if reset = '1' then period_counter <= (others => '0') ; elsif clk'event and clk='1' then if latch_period = '1' then period_counter <= (others => '0') ; elsif end_div = '1' and period_counter /= X"7FFF" and period_counter /= X"8000" then period_counter <= period_counter + 1 ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then period_latched <= (others => '0') ; pv <= '0' ; elsif clk'event and clk='1' then if latch_period = '1' and ((valid_ccw = '1' and channel_b_deb='1') or (valid_cw = '1' and channel_a_deb='1') ) then if valid_ccw = '0' and valid_cw = '1' then period_latched <= period_counter ; else period_latched <= (NOT period_counter) + 1 ; end if; pv <= '1' ; elsif period_counter = X"7FFF" or period_counter = X"8000" then period_latched <= X"8000" ; pv <= '1' ; else pv <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then pulse_counter <= (others => '0') ; elsif clk'event and clk='1' then if reset_count = '1' then pulse_counter <= (others => '0') ; elsif inc_counter = '1' then pulse_counter <= pulse_counter + 1 ; elsif dec_counter = '1' then pulse_counter <= pulse_counter - 1 ; end if ; end if ; end process ; period <= period_latched ; count <= pulse_counter ; end Behavioral;
------------------------------------------------------------------------------- -- $Id:$ ------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and FIFO Generator when XST elaborated the client core -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd -- \| -- \|--- XilinxCoreLib.fifo_generator_v9_2 -- \|--- XilinxCoreLib.fifo_generator_v9_3 -- \| -- \|--- XilinxCoreLib.blk_mem_gen_v7_1 -- \|--- XilinxCoreLib.blk_mem_gen_v7_3 -- ------------------------------------------------------------------------------- -- Author: DET -- History: -- DET 02/01/2008 Initial Version -- -- DET 2/01/2008 for proc_common_v4_0 -- ~~~~~~ -- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create -- this file. -- - Changed instance of sync fifo to use new wrapper file that will adapt -- to FIFO Generator primitive. -- - Replaced "edk_generatecore" with "generatecore" utility call -- - Removed the CAM component -- ^^^^^^ -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 4.3 -- - Added Block Memory Generator Component Version 2.7 -- ^^^^^^ -- -- MSH 2/26/2009 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 5.1 -- - Added Block Memory Generator Component Version 3.1 -- ^^^^^^ -- -- DET 3/2/2009 for EDK 11.1 -- ~~~~~~ -- - Added new Parameters and ports for Fifo Generatore 5.1. -- ^^^^^^ -- -- DET 3/30/2009 EDK 11.2 -- ~~~~~~ -- - Had to reorder parameter list of FIFO Generator 4.3 component to match -- the corresponding Verilog model due to NCSIM positional order -- dependancy of parameters in vhdl/verilog use case. -- ^^^^^^ -- -- DET 4/8/2009 EDK 11.2 -- ~~~~~~ -- - Added blk_mem_gen_v3_2 -- ^^^^^^ -- -- DET 4/9/2009 EDK 11.2 -- ~~~~~~ -- - Added fifo_generator_v5_2 -- ^^^^^^ -- -- DET 2/9/2010 For EDK 12.1 -- ~~~~~~ -- - Added fifo_generator_v5_3 -- - Added blk_mem_gen_v3_3 -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Added fifo_generator_v6_1 -- - Added blk_mem_gen_v4_1 -- ^^^^^^ -- -- DET 3/17/2010 Initial -- ~~~~~~ -- -- Per CR554253 -- - Incorporated changes to comment out FLOP_DELAY parameter from the -- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib -- model for blk_mem_gen_v4_1 but is declared as a TIME type for the -- vhdl version and an integer for the verilog. -- ^^^^^^ -- -- DET 10/04/2010 EDK 13.1 -- ~~~~~~ -- - Added fifo_generator_v7_3 -- - Added blk_mem_gen_v5_2 -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Replaced fifo_generator v7.3 with v8.1 -- - Added blk_mem_gen_v6_1 -- ^^^^^^ -- -- DET 12/17/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR587494 -- - Removed blk_mem_gen v6_1 -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- - Update to use blk_mem_gen_v6_2 -- - Remove out of date components. -- ^^^^^^ -- -- DET 3/3/2011 EDK 13.2 -- ~~~~~~ -- - Removed C_ELABORATION_DIR parameter from the component decalarion -- ^^^^^^ -- -- DET 3/7/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR596052 -- - Added removed fifo generator and Blk Mem Gen components back into -- coregen_comp_defs. -- ^^^^^^ -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v11_0; use fifo_generator_v11_0.all; library blk_mem_gen_v8_0; use blk_mem_gen_v8_0.all; PACKAGE coregen_comp_defs IS -------------------------------------------------------- -- Declare general attributes used in this file -- for defining each component being used with -- the generatecore utility attribute box_type: string; attribute GENERATOR_DEFAULT: string; ------------------------------------------------------- ------------------------------------------------------------------------------------- -- Start FIFO Generator Component for fifo_generator_v11_0 -- The Component declaration for fifo_generator_v11_0 pulled from the -- Coregen version of -- file: fifo_generator_v11_0_comp.vhd. -- -- This component is used for both dual clock (async) and synchronous fifos -- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not -- be provided in FIFO Generator V10.0 so not supported here. -- -- Note: AXI ports and parameters added for this version of FIFO Generator. -- ------------------------------------------------------------------------------------- COMPONENT fifo_generator_v11_0 GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; C_FAMILY : string := "virtex6"; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; C_HAS_MEMINIT_FILE : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; C_OPTIMIZATION_MODE : integer := 0; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; C_MSGON_VAL : integer := 1; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_SYNCHRONIZER_STAGE : integer := 2; -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3 C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3 C_HAS_AXI_WR_CHANNEL : integer := 0; C_HAS_AXI_RD_CHANNEL : integer := 0; C_HAS_SLAVE_CE : integer := 0; C_HAS_MASTER_CE : integer := 0; C_ADD_NGC_CONSTRAINT : integer := 0; C_USE_COMMON_OVERFLOW : integer := 0; C_USE_COMMON_UNDERFLOW : integer := 0; C_USE_DEFAULT_SETTINGS : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH : integer := 4; C_AXI_ADDR_WIDTH : integer := 32; C_AXI_DATA_WIDTH : integer := 64; C_AXI_LEN_WIDTH : integer := 8; C_AXI_LOCK_WIDTH : integer := 2; C_HAS_AXI_ID : integer := 0; C_HAS_AXI_AWUSER : integer := 0; C_HAS_AXI_WUSER : integer := 0; C_HAS_AXI_BUSER : integer := 0; C_HAS_AXI_ARUSER : integer := 0; C_HAS_AXI_RUSER : integer := 0; C_AXI_ARUSER_WIDTH : integer := 1; C_AXI_AWUSER_WIDTH : integer := 1; C_AXI_WUSER_WIDTH : integer := 1; C_AXI_BUSER_WIDTH : integer := 1; C_AXI_RUSER_WIDTH : integer := 1; -- AXI Streaming C_HAS_AXIS_TDATA : integer := 0; C_HAS_AXIS_TID : integer := 0; C_HAS_AXIS_TDEST : integer := 0; C_HAS_AXIS_TUSER : integer := 0; C_HAS_AXIS_TREADY : integer := 1; C_HAS_AXIS_TLAST : integer := 0; C_HAS_AXIS_TSTRB : integer := 0; C_HAS_AXIS_TKEEP : integer := 0; C_AXIS_TDATA_WIDTH : integer := 64; C_AXIS_TID_WIDTH : integer := 8; C_AXIS_TDEST_WIDTH : integer := 4; C_AXIS_TUSER_WIDTH : integer := 4; C_AXIS_TSTRB_WIDTH : integer := 4; C_AXIS_TKEEP_WIDTH : integer := 4; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 5 = Common Clock Built-in FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH : integer := 1; C_IMPLEMENTATION_TYPE_WDCH : integer := 1; C_IMPLEMENTATION_TYPE_WRCH : integer := 1; C_IMPLEMENTATION_TYPE_RACH : integer := 1; C_IMPLEMENTATION_TYPE_RDCH : integer := 1; C_IMPLEMENTATION_TYPE_AXIS : integer := 1; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Sync FIFO -- 3 = Low Latency Async FIFO C_APPLICATION_TYPE_WACH : integer := 0; C_APPLICATION_TYPE_WDCH : integer := 0; C_APPLICATION_TYPE_WRCH : integer := 0; C_APPLICATION_TYPE_RACH : integer := 0; C_APPLICATION_TYPE_RDCH : integer := 0; C_APPLICATION_TYPE_AXIS : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH : integer := 0; C_USE_ECC_WDCH : integer := 0; C_USE_ECC_WRCH : integer := 0; C_USE_ECC_RACH : integer := 0; C_USE_ECC_RDCH : integer := 0; C_USE_ECC_AXIS : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH : integer := 0; C_ERROR_INJECTION_TYPE_WDCH : integer := 0; C_ERROR_INJECTION_TYPE_WRCH : integer := 0; C_ERROR_INJECTION_TYPE_RACH : integer := 0; C_ERROR_INJECTION_TYPE_RDCH : integer := 0; C_ERROR_INJECTION_TYPE_AXIS : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH : integer := 32; C_DIN_WIDTH_WDCH : integer := 64; C_DIN_WIDTH_WRCH : integer := 2; C_DIN_WIDTH_RACH : integer := 32; C_DIN_WIDTH_RDCH : integer := 64; C_DIN_WIDTH_AXIS : integer := 1; C_WR_DEPTH_WACH : integer := 16; C_WR_DEPTH_WDCH : integer := 1024; C_WR_DEPTH_WRCH : integer := 16; C_WR_DEPTH_RACH : integer := 16; C_WR_DEPTH_RDCH : integer := 1024; C_WR_DEPTH_AXIS : integer := 1024; C_WR_PNTR_WIDTH_WACH : integer := 4; C_WR_PNTR_WIDTH_WDCH : integer := 10; C_WR_PNTR_WIDTH_WRCH : integer := 4; C_WR_PNTR_WIDTH_RACH : integer := 4; C_WR_PNTR_WIDTH_RDCH : integer := 10; C_WR_PNTR_WIDTH_AXIS : integer := 10; C_HAS_DATA_COUNTS_WACH : integer := 0; C_HAS_DATA_COUNTS_WDCH : integer := 0; C_HAS_DATA_COUNTS_WRCH : integer := 0; C_HAS_DATA_COUNTS_RACH : integer := 0; C_HAS_DATA_COUNTS_RDCH : integer := 0; C_HAS_DATA_COUNTS_AXIS : integer := 0; C_HAS_PROG_FLAGS_WACH : integer := 0; C_HAS_PROG_FLAGS_WDCH : integer := 0; C_HAS_PROG_FLAGS_WRCH : integer := 0; C_HAS_PROG_FLAGS_RACH : integer := 0; C_HAS_PROG_FLAGS_RDCH : integer := 0; C_HAS_PROG_FLAGS_AXIS : integer := 0; -- 0: No Programmable FULL -- 1: Single Programmable FULL Threshold Constant -- 3: Single Programmable FULL Threshold Input Port C_PROG_FULL_TYPE_WACH : integer := 5; C_PROG_FULL_TYPE_WDCH : integer := 5; C_PROG_FULL_TYPE_WRCH : integer := 5; C_PROG_FULL_TYPE_RACH : integer := 5; C_PROG_FULL_TYPE_RDCH : integer := 5; C_PROG_FULL_TYPE_AXIS : integer := 5; -- Single Programmable FULL Threshold Constant Assert Value C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023; -- 0: No Programmable EMPTY -- 1: Single Programmable EMPTY Threshold Constant -- 3: Single Programmable EMPTY Threshold Input Port C_PROG_EMPTY_TYPE_WACH : integer := 5; C_PROG_EMPTY_TYPE_WDCH : integer := 5; C_PROG_EMPTY_TYPE_WRCH : integer := 5; C_PROG_EMPTY_TYPE_RACH : integer := 5; C_PROG_EMPTY_TYPE_RDCH : integer := 5; C_PROG_EMPTY_TYPE_AXIS : integer := 5; -- Single Programmable EMPTY Threshold Constant Assert Value C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022; C_REG_SLICE_MODE_WACH : integer := 0; C_REG_SLICE_MODE_WDCH : integer := 0; C_REG_SLICE_MODE_WRCH : integer := 0; C_REG_SLICE_MODE_RACH : integer := 0; C_REG_SLICE_MODE_RDCH : integer := 0; C_REG_SLICE_MODE_AXIS : integer := 0 ); PORT( ------------------------------------------------------------------------------ -- Input and Output Declarations ------------------------------------------------------------------------------ -- Conventional FIFO Interface Signals backup : in std_logic := '0'; backup_marker : in std_logic := '0'; clk : in std_logic := '0'; rst : in std_logic := '0'; srst : in std_logic := '0'; wr_clk : in std_logic := '0'; wr_rst : in std_logic := '0'; rd_clk : in std_logic := '0'; rd_rst : in std_logic := '0'; din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; rd_en : in std_logic := '0'; -- optional inputs prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); int_clk : in std_logic := '0'; injectdbiterr : in std_logic := '0'; injectsbiterr : in std_logic := '0'; dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0'); full : out std_logic := '0'; almost_full : out std_logic := '0'; wr_ack : out std_logic := '0'; overflow : out std_logic := '0'; empty : out std_logic := '1'; almost_empty : out std_logic := '1'; valid : out std_logic := '0'; underflow : out std_logic := '0'; data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); prog_full : out std_logic := '0'; prog_empty : out std_logic := '1'; sbiterr : out std_logic := '0'; dbiterr : out std_logic := '0'; -- axi global signal m_aclk : in std_logic := '0'; s_aclk : in std_logic := '0'; s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1 m_aclk_en : in std_logic := '0'; s_aclk_en : in std_logic := '0'; -- axi full/lite slave write channel (write side) s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_awvalid : in std_logic := '0'; s_axi_awready : out std_logic := '0'; s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); s_axi_wlast : in std_logic := '0'; s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_wvalid : in std_logic := '0'; s_axi_wready : out std_logic := '0'; s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_bvalid : out std_logic := '0'; s_axi_bready : in std_logic := '0'; -- axi full/lite master write channel (read side) m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_awvalid : out std_logic := '0'; m_axi_awready : in std_logic := '0'; m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); m_axi_wlast : out std_logic := '0'; m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_wvalid : out std_logic := '0'; m_axi_wready : in std_logic := '0'; m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_bvalid : in std_logic := '0'; m_axi_bready : out std_logic := '0'; -- axi full/lite slave read channel (write side) s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_arvalid : in std_logic := '0'; s_axi_arready : out std_logic := '0'; s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_rlast : out std_logic := '0'; s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_rvalid : out std_logic := '0'; s_axi_rready : in std_logic := '0'; -- axi full/lite master read channel (read side) m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_arvalid : out std_logic := '0'; m_axi_arready : in std_logic := '0'; m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_rlast : in std_logic := '0'; m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_rvalid : in std_logic := '0'; m_axi_rready : out std_logic := '0'; -- axi streaming slave signals (write side) s_axis_tvalid : in std_logic := '0'; s_axis_tready : out std_logic := '0'; s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); s_axis_tlast : in std_logic := '0'; s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi streaming master signals (read side) m_axis_tvalid : out std_logic := '0'; m_axis_tready : in std_logic := '0'; m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); m_axis_tlast : out std_logic := '0'; m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi full/lite write address channel signals axi_aw_injectsbiterr : in std_logic := '0'; axi_aw_injectdbiterr : in std_logic := '0'; axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_sbiterr : out std_logic := '0'; axi_aw_dbiterr : out std_logic := '0'; axi_aw_overflow : out std_logic := '0'; axi_aw_underflow : out std_logic := '0'; axi_aw_prog_full : out std_logic := '0'; axi_aw_prog_empty : out std_logic := '1'; -- axi_aw_almost_full : out std_logic := '0'; -- axi_aw_almost_empty : out std_logic := '1'; -- axi full/lite write data channel signals axi_w_injectsbiterr : in std_logic := '0'; axi_w_injectdbiterr : in std_logic := '0'; axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_sbiterr : out std_logic := '0'; axi_w_dbiterr : out std_logic := '0'; axi_w_overflow : out std_logic := '0'; axi_w_underflow : out std_logic := '0'; axi_w_prog_full : out std_logic := '0'; axi_w_prog_empty : out std_logic := '1'; -- axi_w_almost_full : out std_logic := '0'; -- axi_w_almost_empty : out std_logic := '1'; -- axi full/lite write response channel signals axi_b_injectsbiterr : in std_logic := '0'; axi_b_injectdbiterr : in std_logic := '0'; axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_sbiterr : out std_logic := '0'; axi_b_dbiterr : out std_logic := '0'; axi_b_overflow : out std_logic := '0'; axi_b_underflow : out std_logic := '0'; axi_b_prog_full : out std_logic := '0'; axi_b_prog_empty : out std_logic := '1'; -- axi_b_almost_full : out std_logic := '0'; -- axi_b_almost_empty : out std_logic := '1'; -- axi full/lite read address channel signals axi_ar_injectsbiterr : in std_logic := '0'; axi_ar_injectdbiterr : in std_logic := '0'; axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_sbiterr : out std_logic := '0'; axi_ar_dbiterr : out std_logic := '0'; axi_ar_overflow : out std_logic := '0'; axi_ar_underflow : out std_logic := '0'; axi_ar_prog_full : out std_logic := '0'; axi_ar_prog_empty : out std_logic := '1'; -- axi_ar_almost_full : out std_logic := '0'; -- axi_ar_almost_empty : out std_logic := '1'; -- axi full/lite read data channel signals axi_r_injectsbiterr : in std_logic := '0'; axi_r_injectdbiterr : in std_logic := '0'; axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_sbiterr : out std_logic := '0'; axi_r_dbiterr : out std_logic := '0'; axi_r_overflow : out std_logic := '0'; axi_r_underflow : out std_logic := '0'; axi_r_prog_full : out std_logic := '0'; axi_r_prog_empty : out std_logic := '1'; -- axi_r_almost_full : out std_logic := '0'; -- axi_r_almost_empty : out std_logic := '1'; -- axi streaming fifo related signals axis_injectsbiterr : in std_logic := '0'; axis_injectdbiterr : in std_logic := '0'; axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_sbiterr : out std_logic := '0'; axis_dbiterr : out std_logic := '0'; axis_overflow : out std_logic := '0'; axis_underflow : out std_logic := '0'; axis_prog_full : out std_logic := '0'; axis_prog_empty : out std_logic := '1' -- axis_almost_full : out std_logic := '0'; -- axis_almost_empty : out std_logic := '1' ); END COMPONENT; -- End FIFO Generator Component --------------------------------------- ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_0 -- Component declaration for blk_mem_gen_v8_0 pulled from the -- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib -- file: blk_mem_gen_v8_0.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_0 IS GENERIC ( C_FAMILY : STRING := "virtex6"; C_XDEVICEFAMILY : STRING := "virtex6"; C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_AXI_TYPE : INTEGER := 0; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC := '0'; DBITERR : OUT STD_LOGIC := '0'; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC := '0'; S_AXI_DBITERR : OUT STD_LOGIC := '0'; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; --blk_mem_gen_v8_0 -- The following tells XST that blk_mem_gen_v8_0 is a black box which -- should be generated command given by the value of this attribute -- Note the fully qualified SIM (JAVA class) name that forms the -- basis of the core -- ATTRIBUTE box_type OF blk_mem_gen_v8_0 : COMPONENT IS "black_box"; -- ATTRIBUTE generator_default OF blk_mem_gen_v8_0 : COMPONENT IS -- "generatecore com.xilinx.ip.blk_mem_gen_v8_0.blk_mem_gen_v8_0 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e "; -- End Block Memory Generator Component for v7_1 ------------------------------- END coregen_comp_defs;
------------------------------------------------------------------------------- -- $Id:$ ------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and FIFO Generator when XST elaborated the client core -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd -- \| -- \|--- XilinxCoreLib.fifo_generator_v9_2 -- \|--- XilinxCoreLib.fifo_generator_v9_3 -- \| -- \|--- XilinxCoreLib.blk_mem_gen_v7_1 -- \|--- XilinxCoreLib.blk_mem_gen_v7_3 -- ------------------------------------------------------------------------------- -- Author: DET -- History: -- DET 02/01/2008 Initial Version -- -- DET 2/01/2008 for proc_common_v4_0 -- ~~~~~~ -- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create -- this file. -- - Changed instance of sync fifo to use new wrapper file that will adapt -- to FIFO Generator primitive. -- - Replaced "edk_generatecore" with "generatecore" utility call -- - Removed the CAM component -- ^^^^^^ -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 4.3 -- - Added Block Memory Generator Component Version 2.7 -- ^^^^^^ -- -- MSH 2/26/2009 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 5.1 -- - Added Block Memory Generator Component Version 3.1 -- ^^^^^^ -- -- DET 3/2/2009 for EDK 11.1 -- ~~~~~~ -- - Added new Parameters and ports for Fifo Generatore 5.1. -- ^^^^^^ -- -- DET 3/30/2009 EDK 11.2 -- ~~~~~~ -- - Had to reorder parameter list of FIFO Generator 4.3 component to match -- the corresponding Verilog model due to NCSIM positional order -- dependancy of parameters in vhdl/verilog use case. -- ^^^^^^ -- -- DET 4/8/2009 EDK 11.2 -- ~~~~~~ -- - Added blk_mem_gen_v3_2 -- ^^^^^^ -- -- DET 4/9/2009 EDK 11.2 -- ~~~~~~ -- - Added fifo_generator_v5_2 -- ^^^^^^ -- -- DET 2/9/2010 For EDK 12.1 -- ~~~~~~ -- - Added fifo_generator_v5_3 -- - Added blk_mem_gen_v3_3 -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Added fifo_generator_v6_1 -- - Added blk_mem_gen_v4_1 -- ^^^^^^ -- -- DET 3/17/2010 Initial -- ~~~~~~ -- -- Per CR554253 -- - Incorporated changes to comment out FLOP_DELAY parameter from the -- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib -- model for blk_mem_gen_v4_1 but is declared as a TIME type for the -- vhdl version and an integer for the verilog. -- ^^^^^^ -- -- DET 10/04/2010 EDK 13.1 -- ~~~~~~ -- - Added fifo_generator_v7_3 -- - Added blk_mem_gen_v5_2 -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Replaced fifo_generator v7.3 with v8.1 -- - Added blk_mem_gen_v6_1 -- ^^^^^^ -- -- DET 12/17/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR587494 -- - Removed blk_mem_gen v6_1 -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- - Update to use blk_mem_gen_v6_2 -- - Remove out of date components. -- ^^^^^^ -- -- DET 3/3/2011 EDK 13.2 -- ~~~~~~ -- - Removed C_ELABORATION_DIR parameter from the component decalarion -- ^^^^^^ -- -- DET 3/7/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR596052 -- - Added removed fifo generator and Blk Mem Gen components back into -- coregen_comp_defs. -- ^^^^^^ -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v11_0; use fifo_generator_v11_0.all; library blk_mem_gen_v8_0; use blk_mem_gen_v8_0.all; PACKAGE coregen_comp_defs IS -------------------------------------------------------- -- Declare general attributes used in this file -- for defining each component being used with -- the generatecore utility attribute box_type: string; attribute GENERATOR_DEFAULT: string; ------------------------------------------------------- ------------------------------------------------------------------------------------- -- Start FIFO Generator Component for fifo_generator_v11_0 -- The Component declaration for fifo_generator_v11_0 pulled from the -- Coregen version of -- file: fifo_generator_v11_0_comp.vhd. -- -- This component is used for both dual clock (async) and synchronous fifos -- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not -- be provided in FIFO Generator V10.0 so not supported here. -- -- Note: AXI ports and parameters added for this version of FIFO Generator. -- ------------------------------------------------------------------------------------- COMPONENT fifo_generator_v11_0 GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; C_FAMILY : string := "virtex6"; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; C_HAS_MEMINIT_FILE : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; C_OPTIMIZATION_MODE : integer := 0; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; C_MSGON_VAL : integer := 1; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_SYNCHRONIZER_STAGE : integer := 2; -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3 C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3 C_HAS_AXI_WR_CHANNEL : integer := 0; C_HAS_AXI_RD_CHANNEL : integer := 0; C_HAS_SLAVE_CE : integer := 0; C_HAS_MASTER_CE : integer := 0; C_ADD_NGC_CONSTRAINT : integer := 0; C_USE_COMMON_OVERFLOW : integer := 0; C_USE_COMMON_UNDERFLOW : integer := 0; C_USE_DEFAULT_SETTINGS : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH : integer := 4; C_AXI_ADDR_WIDTH : integer := 32; C_AXI_DATA_WIDTH : integer := 64; C_AXI_LEN_WIDTH : integer := 8; C_AXI_LOCK_WIDTH : integer := 2; C_HAS_AXI_ID : integer := 0; C_HAS_AXI_AWUSER : integer := 0; C_HAS_AXI_WUSER : integer := 0; C_HAS_AXI_BUSER : integer := 0; C_HAS_AXI_ARUSER : integer := 0; C_HAS_AXI_RUSER : integer := 0; C_AXI_ARUSER_WIDTH : integer := 1; C_AXI_AWUSER_WIDTH : integer := 1; C_AXI_WUSER_WIDTH : integer := 1; C_AXI_BUSER_WIDTH : integer := 1; C_AXI_RUSER_WIDTH : integer := 1; -- AXI Streaming C_HAS_AXIS_TDATA : integer := 0; C_HAS_AXIS_TID : integer := 0; C_HAS_AXIS_TDEST : integer := 0; C_HAS_AXIS_TUSER : integer := 0; C_HAS_AXIS_TREADY : integer := 1; C_HAS_AXIS_TLAST : integer := 0; C_HAS_AXIS_TSTRB : integer := 0; C_HAS_AXIS_TKEEP : integer := 0; C_AXIS_TDATA_WIDTH : integer := 64; C_AXIS_TID_WIDTH : integer := 8; C_AXIS_TDEST_WIDTH : integer := 4; C_AXIS_TUSER_WIDTH : integer := 4; C_AXIS_TSTRB_WIDTH : integer := 4; C_AXIS_TKEEP_WIDTH : integer := 4; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 5 = Common Clock Built-in FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH : integer := 1; C_IMPLEMENTATION_TYPE_WDCH : integer := 1; C_IMPLEMENTATION_TYPE_WRCH : integer := 1; C_IMPLEMENTATION_TYPE_RACH : integer := 1; C_IMPLEMENTATION_TYPE_RDCH : integer := 1; C_IMPLEMENTATION_TYPE_AXIS : integer := 1; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Sync FIFO -- 3 = Low Latency Async FIFO C_APPLICATION_TYPE_WACH : integer := 0; C_APPLICATION_TYPE_WDCH : integer := 0; C_APPLICATION_TYPE_WRCH : integer := 0; C_APPLICATION_TYPE_RACH : integer := 0; C_APPLICATION_TYPE_RDCH : integer := 0; C_APPLICATION_TYPE_AXIS : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH : integer := 0; C_USE_ECC_WDCH : integer := 0; C_USE_ECC_WRCH : integer := 0; C_USE_ECC_RACH : integer := 0; C_USE_ECC_RDCH : integer := 0; C_USE_ECC_AXIS : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH : integer := 0; C_ERROR_INJECTION_TYPE_WDCH : integer := 0; C_ERROR_INJECTION_TYPE_WRCH : integer := 0; C_ERROR_INJECTION_TYPE_RACH : integer := 0; C_ERROR_INJECTION_TYPE_RDCH : integer := 0; C_ERROR_INJECTION_TYPE_AXIS : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH : integer := 32; C_DIN_WIDTH_WDCH : integer := 64; C_DIN_WIDTH_WRCH : integer := 2; C_DIN_WIDTH_RACH : integer := 32; C_DIN_WIDTH_RDCH : integer := 64; C_DIN_WIDTH_AXIS : integer := 1; C_WR_DEPTH_WACH : integer := 16; C_WR_DEPTH_WDCH : integer := 1024; C_WR_DEPTH_WRCH : integer := 16; C_WR_DEPTH_RACH : integer := 16; C_WR_DEPTH_RDCH : integer := 1024; C_WR_DEPTH_AXIS : integer := 1024; C_WR_PNTR_WIDTH_WACH : integer := 4; C_WR_PNTR_WIDTH_WDCH : integer := 10; C_WR_PNTR_WIDTH_WRCH : integer := 4; C_WR_PNTR_WIDTH_RACH : integer := 4; C_WR_PNTR_WIDTH_RDCH : integer := 10; C_WR_PNTR_WIDTH_AXIS : integer := 10; C_HAS_DATA_COUNTS_WACH : integer := 0; C_HAS_DATA_COUNTS_WDCH : integer := 0; C_HAS_DATA_COUNTS_WRCH : integer := 0; C_HAS_DATA_COUNTS_RACH : integer := 0; C_HAS_DATA_COUNTS_RDCH : integer := 0; C_HAS_DATA_COUNTS_AXIS : integer := 0; C_HAS_PROG_FLAGS_WACH : integer := 0; C_HAS_PROG_FLAGS_WDCH : integer := 0; C_HAS_PROG_FLAGS_WRCH : integer := 0; C_HAS_PROG_FLAGS_RACH : integer := 0; C_HAS_PROG_FLAGS_RDCH : integer := 0; C_HAS_PROG_FLAGS_AXIS : integer := 0; -- 0: No Programmable FULL -- 1: Single Programmable FULL Threshold Constant -- 3: Single Programmable FULL Threshold Input Port C_PROG_FULL_TYPE_WACH : integer := 5; C_PROG_FULL_TYPE_WDCH : integer := 5; C_PROG_FULL_TYPE_WRCH : integer := 5; C_PROG_FULL_TYPE_RACH : integer := 5; C_PROG_FULL_TYPE_RDCH : integer := 5; C_PROG_FULL_TYPE_AXIS : integer := 5; -- Single Programmable FULL Threshold Constant Assert Value C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023; -- 0: No Programmable EMPTY -- 1: Single Programmable EMPTY Threshold Constant -- 3: Single Programmable EMPTY Threshold Input Port C_PROG_EMPTY_TYPE_WACH : integer := 5; C_PROG_EMPTY_TYPE_WDCH : integer := 5; C_PROG_EMPTY_TYPE_WRCH : integer := 5; C_PROG_EMPTY_TYPE_RACH : integer := 5; C_PROG_EMPTY_TYPE_RDCH : integer := 5; C_PROG_EMPTY_TYPE_AXIS : integer := 5; -- Single Programmable EMPTY Threshold Constant Assert Value C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022; C_REG_SLICE_MODE_WACH : integer := 0; C_REG_SLICE_MODE_WDCH : integer := 0; C_REG_SLICE_MODE_WRCH : integer := 0; C_REG_SLICE_MODE_RACH : integer := 0; C_REG_SLICE_MODE_RDCH : integer := 0; C_REG_SLICE_MODE_AXIS : integer := 0 ); PORT( ------------------------------------------------------------------------------ -- Input and Output Declarations ------------------------------------------------------------------------------ -- Conventional FIFO Interface Signals backup : in std_logic := '0'; backup_marker : in std_logic := '0'; clk : in std_logic := '0'; rst : in std_logic := '0'; srst : in std_logic := '0'; wr_clk : in std_logic := '0'; wr_rst : in std_logic := '0'; rd_clk : in std_logic := '0'; rd_rst : in std_logic := '0'; din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; rd_en : in std_logic := '0'; -- optional inputs prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); int_clk : in std_logic := '0'; injectdbiterr : in std_logic := '0'; injectsbiterr : in std_logic := '0'; dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0'); full : out std_logic := '0'; almost_full : out std_logic := '0'; wr_ack : out std_logic := '0'; overflow : out std_logic := '0'; empty : out std_logic := '1'; almost_empty : out std_logic := '1'; valid : out std_logic := '0'; underflow : out std_logic := '0'; data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); prog_full : out std_logic := '0'; prog_empty : out std_logic := '1'; sbiterr : out std_logic := '0'; dbiterr : out std_logic := '0'; -- axi global signal m_aclk : in std_logic := '0'; s_aclk : in std_logic := '0'; s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1 m_aclk_en : in std_logic := '0'; s_aclk_en : in std_logic := '0'; -- axi full/lite slave write channel (write side) s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_awvalid : in std_logic := '0'; s_axi_awready : out std_logic := '0'; s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); s_axi_wlast : in std_logic := '0'; s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_wvalid : in std_logic := '0'; s_axi_wready : out std_logic := '0'; s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_bvalid : out std_logic := '0'; s_axi_bready : in std_logic := '0'; -- axi full/lite master write channel (read side) m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_awvalid : out std_logic := '0'; m_axi_awready : in std_logic := '0'; m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); m_axi_wlast : out std_logic := '0'; m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_wvalid : out std_logic := '0'; m_axi_wready : in std_logic := '0'; m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_bvalid : in std_logic := '0'; m_axi_bready : out std_logic := '0'; -- axi full/lite slave read channel (write side) s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_arvalid : in std_logic := '0'; s_axi_arready : out std_logic := '0'; s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_rlast : out std_logic := '0'; s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_rvalid : out std_logic := '0'; s_axi_rready : in std_logic := '0'; -- axi full/lite master read channel (read side) m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_arvalid : out std_logic := '0'; m_axi_arready : in std_logic := '0'; m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_rlast : in std_logic := '0'; m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_rvalid : in std_logic := '0'; m_axi_rready : out std_logic := '0'; -- axi streaming slave signals (write side) s_axis_tvalid : in std_logic := '0'; s_axis_tready : out std_logic := '0'; s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); s_axis_tlast : in std_logic := '0'; s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi streaming master signals (read side) m_axis_tvalid : out std_logic := '0'; m_axis_tready : in std_logic := '0'; m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); m_axis_tlast : out std_logic := '0'; m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi full/lite write address channel signals axi_aw_injectsbiterr : in std_logic := '0'; axi_aw_injectdbiterr : in std_logic := '0'; axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_sbiterr : out std_logic := '0'; axi_aw_dbiterr : out std_logic := '0'; axi_aw_overflow : out std_logic := '0'; axi_aw_underflow : out std_logic := '0'; axi_aw_prog_full : out std_logic := '0'; axi_aw_prog_empty : out std_logic := '1'; -- axi_aw_almost_full : out std_logic := '0'; -- axi_aw_almost_empty : out std_logic := '1'; -- axi full/lite write data channel signals axi_w_injectsbiterr : in std_logic := '0'; axi_w_injectdbiterr : in std_logic := '0'; axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_sbiterr : out std_logic := '0'; axi_w_dbiterr : out std_logic := '0'; axi_w_overflow : out std_logic := '0'; axi_w_underflow : out std_logic := '0'; axi_w_prog_full : out std_logic := '0'; axi_w_prog_empty : out std_logic := '1'; -- axi_w_almost_full : out std_logic := '0'; -- axi_w_almost_empty : out std_logic := '1'; -- axi full/lite write response channel signals axi_b_injectsbiterr : in std_logic := '0'; axi_b_injectdbiterr : in std_logic := '0'; axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_sbiterr : out std_logic := '0'; axi_b_dbiterr : out std_logic := '0'; axi_b_overflow : out std_logic := '0'; axi_b_underflow : out std_logic := '0'; axi_b_prog_full : out std_logic := '0'; axi_b_prog_empty : out std_logic := '1'; -- axi_b_almost_full : out std_logic := '0'; -- axi_b_almost_empty : out std_logic := '1'; -- axi full/lite read address channel signals axi_ar_injectsbiterr : in std_logic := '0'; axi_ar_injectdbiterr : in std_logic := '0'; axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_sbiterr : out std_logic := '0'; axi_ar_dbiterr : out std_logic := '0'; axi_ar_overflow : out std_logic := '0'; axi_ar_underflow : out std_logic := '0'; axi_ar_prog_full : out std_logic := '0'; axi_ar_prog_empty : out std_logic := '1'; -- axi_ar_almost_full : out std_logic := '0'; -- axi_ar_almost_empty : out std_logic := '1'; -- axi full/lite read data channel signals axi_r_injectsbiterr : in std_logic := '0'; axi_r_injectdbiterr : in std_logic := '0'; axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_sbiterr : out std_logic := '0'; axi_r_dbiterr : out std_logic := '0'; axi_r_overflow : out std_logic := '0'; axi_r_underflow : out std_logic := '0'; axi_r_prog_full : out std_logic := '0'; axi_r_prog_empty : out std_logic := '1'; -- axi_r_almost_full : out std_logic := '0'; -- axi_r_almost_empty : out std_logic := '1'; -- axi streaming fifo related signals axis_injectsbiterr : in std_logic := '0'; axis_injectdbiterr : in std_logic := '0'; axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_sbiterr : out std_logic := '0'; axis_dbiterr : out std_logic := '0'; axis_overflow : out std_logic := '0'; axis_underflow : out std_logic := '0'; axis_prog_full : out std_logic := '0'; axis_prog_empty : out std_logic := '1' -- axis_almost_full : out std_logic := '0'; -- axis_almost_empty : out std_logic := '1' ); END COMPONENT; -- End FIFO Generator Component --------------------------------------- ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_0 -- Component declaration for blk_mem_gen_v8_0 pulled from the -- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib -- file: blk_mem_gen_v8_0.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_0 IS GENERIC ( C_FAMILY : STRING := "virtex6"; C_XDEVICEFAMILY : STRING := "virtex6"; C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_AXI_TYPE : INTEGER := 0; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC := '0'; DBITERR : OUT STD_LOGIC := '0'; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC := '0'; S_AXI_DBITERR : OUT STD_LOGIC := '0'; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; --blk_mem_gen_v8_0 -- The following tells XST that blk_mem_gen_v8_0 is a black box which -- should be generated command given by the value of this attribute -- Note the fully qualified SIM (JAVA class) name that forms the -- basis of the core -- ATTRIBUTE box_type OF blk_mem_gen_v8_0 : COMPONENT IS "black_box"; -- ATTRIBUTE generator_default OF blk_mem_gen_v8_0 : COMPONENT IS -- "generatecore com.xilinx.ip.blk_mem_gen_v8_0.blk_mem_gen_v8_0 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e "; -- End Block Memory Generator Component for v7_1 ------------------------------- END coregen_comp_defs;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_2 Core - Top File for the Example Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Filename: ram_16x1k_dp_tb.vhd -- Description: -- Testbench Top -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY ram_16x1k_dp_tb IS END ENTITY; ARCHITECTURE ram_16x1k_dp_tb_ARCH OF ram_16x1k_dp_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL CLKB : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; CLKB_GEN: PROCESS BEGIN CLKB <= NOT CLKB; WAIT FOR 100 NS; CLKB <= NOT CLKB; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; --STOP_SIM: PROCESS BEGIN -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS -- ASSERT FALSE -- REPORT "END SIMULATION TIME REACHED" -- SEVERITY FAILURE; --END PROCESS; -- PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; ram_16x1k_dp_synth_inst:ENTITY work.ram_16x1k_dp_synth PORT MAP( CLK_IN => CLK, CLKB_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE;
library IEEE, LFSR; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -------------------------------------------------------------------------------- entity pulse_shreg is generic ( G_period : natural := 10000 ); port( CLK : in std_logic; RESET : in std_logic; PULSE : out std_logic ); end pulse_shreg; -------------------------------------------------------------------------------- architecture rtl of pulse_shreg is subtype T_SHIFTREG is std_logic_vector(G_period-1 downto 0); constant C_ZERO : T_SHIFTREG := (0 => '1', others => '0'); signal SHIFTREG : T_SHIFTREG; begin PULSE <= '1' when SHIFTREG = C_ZERO else '0'; shreg_proc: process (CLK) is begin if rising_edge(CLK) then if RESET = '1' then SHIFTREG <= C_ZERO; else SHIFTREG <= SHIFTREG(G_period-2 downto 0) & SHIFTREG(G_period-1); end if; end if; end process shreg_proc; end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity guarded_fifo is generic ( depth : integer; bit_width : integer ); port ( -- fast side interface clk_fast_i : in std_logic; rst_fast_i : in std_logic; push_i : in std_logic; full_o : out std_logic; d_i : in std_logic_vector ( bit_width-1 downto 0 ); -- slow side interface clk_i : in std_logic; rst_i : in std_logic; dack_i : in std_logic; drdy_o : out std_logic; q_o : out std_logic_vector ( bit_width-1 downto 0 ) ); end entity; -- Take a non-guarded fifo and take control over the -- push and pull lines and prevent illegal operations. -- Forward the full and empty signals. use work.fifo_pkg.all; architecture rtl of guarded_fifo is -- fast side signal type fast_state_t is (s_idle, s_getting_data_pop, s_getting_data_nopop, s_getting_data_latch, s_providing_data, s_start_pop, s_unknown); signal full, empty, push, pop : std_logic; signal pop_request_sync, pop_request_sync_1 : std_logic; signal q, fifo_out_data_fast : std_logic_vector ( bit_width-1 downto 0 ); signal data_ready : std_logic; signal state, next_state : fast_state_t; -- slow side signals type slow_state_t is (s_block, s_noblock); signal data_ready_sync, data_ready_sync_1 : std_logic; signal data_ready_block : std_logic; signal fifo_out_data_slow : std_logic_vector ( bit_width-1 downto 0 ); signal slow_state : slow_state_t; begin -- the fifo is located on the fast side fifo : work.fifo_pkg.fifo generic map ( depth => depth, bit_width => bit_width ) port map ( clk_i => clk_fast_i, rst_i => rst_fast_i, push_i => push, pop_i => pop, full_o => full, empty_o => empty, d_i => d_i, q_o => q ); -- fast side interface of this module can be forwarded directly to the fifo full_o <= full; push <= push_i and not full; -- the fast side process has a state machine that manages popping data from the fifo if it is available -- fast_side: process begin wait until rising_edge(clk_fast_i); if rst_fast_i = '1' then state <= s_idle; next_state <= s_idle; fifo_out_data_fast <= (others => 'U'); data_ready <= '0'; else -- signal synchroinzation on the fast side (look at slow signals) pop_request_sync_1 <= dack_i; -- data acknowledge => we make a pop request to the underlying fifo pop_request_sync <= pop_request_sync_1; fifo_out_data_fast <= fifo_out_data_fast; -- managing state machine case state is when s_idle => if empty = '0' and pop_request_sync = '0' then state <= s_getting_data_pop; else state <= s_idle; end if; -- create a single pulse to get next data when s_getting_data_pop => if empty = '1' then state <= s_idle; else pop <= '1'; state <= s_getting_data_nopop; end if; when s_getting_data_nopop => pop <= '0'; data_ready <= '1'; state <= s_getting_data_latch; when s_getting_data_latch => state <= s_providing_data; fifo_out_data_fast <= q; data_ready <= '1'; when s_providing_data => if pop_request_sync = '1' then state <= s_start_pop; data_ready <= '0'; end if; when s_start_pop => if pop_request_sync = '0' then state <= s_idle; end if; when others => state <= s_unknown; end case; end if; end process; slow_side: process begin wait until rising_edge(clk_i); if rst_i = '1' then drdy_o <= '0'; data_ready_sync_1 <= '0'; data_ready_sync <= '0'; q_o <= (others => 'U'); data_ready_block <= '0'; slow_state <= s_noblock; else -- signal synchronization on the slow side (looking at fast signals) data_ready_sync_1 <= data_ready; data_ready_sync <= data_ready_sync_1; drdy_o <= data_ready_sync and not data_ready_block; if data_ready_sync = '1' then q_o <= fifo_out_data_fast; end if; case slow_state is when s_noblock => if dack_i = '1' then slow_state <= s_block; data_ready_block <= '1'; end if; when s_block => if data_ready_sync = '1' and data_ready_sync_1 = '0' then slow_state <= s_noblock; data_ready_block <= '0'; end if; end case; end if; end process; end architecture;
architecture rtl of fifo is begin my_signal <= '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal <= '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal <= (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end architecture rtl;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity spi_sreg is generic ( size_g : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; --control signals shift : in std_logic; --shift left load : in std_logic; --load parallel --data signals din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched) dout : out std_logic_vector(size_g-1 downto 0); --parallel data out sin : in std_logic; --serial data in (to lsb) sout : out std_logic --serial data out (from msb) ); end spi_sreg; architecture rtl of spi_sreg is signal shiftReg : std_logic_vector(size_g-1 downto 0); begin theShiftRegister : process(clk, rst) begin if rst = '1' then shiftReg <= (others => '0'); elsif clk = '1' and clk'event then if shift = '1' then shiftReg <= shiftReg(size_g-2 downto 0) & sin; elsif load = '1' then shiftReg <= din; end if; end if; end process; dout <= shiftReg; sout <= shiftReg(size_g-1); end rtl;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity spi_sreg is generic ( size_g : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; --control signals shift : in std_logic; --shift left load : in std_logic; --load parallel --data signals din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched) dout : out std_logic_vector(size_g-1 downto 0); --parallel data out sin : in std_logic; --serial data in (to lsb) sout : out std_logic --serial data out (from msb) ); end spi_sreg; architecture rtl of spi_sreg is signal shiftReg : std_logic_vector(size_g-1 downto 0); begin theShiftRegister : process(clk, rst) begin if rst = '1' then shiftReg <= (others => '0'); elsif clk = '1' and clk'event then if shift = '1' then shiftReg <= shiftReg(size_g-2 downto 0) & sin; elsif load = '1' then shiftReg <= din; end if; end if; end process; dout <= shiftReg; sout <= shiftReg(size_g-1); end rtl;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity spi_sreg is generic ( size_g : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; --control signals shift : in std_logic; --shift left load : in std_logic; --load parallel --data signals din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched) dout : out std_logic_vector(size_g-1 downto 0); --parallel data out sin : in std_logic; --serial data in (to lsb) sout : out std_logic --serial data out (from msb) ); end spi_sreg; architecture rtl of spi_sreg is signal shiftReg : std_logic_vector(size_g-1 downto 0); begin theShiftRegister : process(clk, rst) begin if rst = '1' then shiftReg <= (others => '0'); elsif clk = '1' and clk'event then if shift = '1' then shiftReg <= shiftReg(size_g-2 downto 0) & sin; elsif load = '1' then shiftReg <= din; end if; end if; end process; dout <= shiftReg; sout <= shiftReg(size_g-1); end rtl;

-- -- pciradio.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A -- Author: Stephen A. Rodgers -- -- Copyright (c) 2004,2005 Stephen A. Rodgers -- -- Steve Rodgers <[email protected]> -- -- This program is free software, and the design, schematics, layout, -- and artwork for the hardware on which it runs is free, and all are -- distributed under the terms of the GNU General Public License. -- -- -- I/O Map -- -- Addr Read Write -- 0 MX_828_status_ch0 MX_828_address -- 1 MX_828_status_ch1 MX_828_first_byte/Xilinx programming -- 2 MX_828_status_ch2 MX_828 second byte -- 3 MX_828_status_ch3 MX_828_command -- 4 Uart Receive Data Uart Transmit Data -- 5 - - -- 6 - - -- 7 - - -- 8 UIO_AB UIO_AB -- 9 COR LED control -- A TEST/PTT TEST/PTT -- B RBS_Bytes_Queued RBS_Cmd -- C General_Status RBS_Data -- D IRQ_mask IRQ_mask -- E Control1 Control1 -- F Control2 Control2 -- -- *** Control1 *** -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- UIOBD3 UIOBD2 UIOBD1 UIOBD0 UIOAD3 UIOAD2 UIOAD1 UIOAD0 -- -- This register controls the direction of the UIOA and UIOB ports. -- Writing a 0 sets the port bit as an output, writing a 1 sets the -- port bit as an input. -- -- This register is cleared at power up. -- -- *** Control2 *** -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- SERSEL1 SERSEL0 SERC1 SERC0 TESTD3 TESTD2 TESTD1 TESTD0 -- -- This register controls the direction of the TEST port, and assigns the -- remote base serializer to a specific channel. -- -- SERSEL[1:0] -- -- Select which serializer to use: -- -- 00 - None -- 01 - RBI -- 10 - UART -- 11 - Reserved for future use -- -- -- SERC[1:0] -- Select the channel to assign the remote base serializer to using -- the following truth table: -- -- 00 - Channel 0 -- 01 - Channel 1 -- 10 - Channel 2 -- 11 - Channel 3 -- -- To use the remote base serializer on a given channel, that channel must -- have both its UIOA and UIOB direction bits set as output (0), and preferably -- have 0's programmed into the output register to prevent false clocking, if -- the serializer is dynamically shared between channels. -- -- -- TESTD[3:0] -- -- Writing a 0 sets the port bit as an output, writing a 1 sets the -- port bit as an input. This register is cleared at power up. -- -- This register is cleared at power up. -- -- *** USTAT/COR *** -- -- 7 6 5 4 3 2 1 0 -- UTXBUSY UOVRRUN UDIRTY UDAV COR3 COR2 COR1 COR0 -- -- -- These bits reflect the state of the UART and of the cor lines. -- -- -- *** General Status *** -- -- Read only -- -- 7 6 5 4 3 2 1 0 -- INT IMX828 RBSDN PLSDN - TXWTRIP RBSBSY PLSBSY -- -- -- -- INT - State of the interrupt line prior to reading this register -- IMX828 - Reflects the state of the MX828 wire-or interrupt -- PLSDN - Set to 1 when a command to the PL serializer completes -- RBSDN - Set to 1 when a command to the remote base serializer completes -- TXWTRIP - Set when the PTT's get inhibited by the TX watchdog -- RBSBSY - Set to 1 when the remote serializer is busy -- PLSBSY - Set to 1 when the PL serializer is busy -- -- To clear RBSDN and PLSDN, see the IRQ mask register. -- -- -- -- *** IRQ mask *** -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- MASTERM - - - - MMX828 MRBS MPLS -- -- MASTERM - Master mask. Masks the IRQ line when set to 1. -- MPLS - Masks the MX828 serializer completion interrupt -- MRBS - Masks the RBS serializer completion interrupt -- MMX828 - Masks the wire-or MX828 chip interrupt pins -- -- Mask = 1, Unmask = 0 -- This register will be set to 10000111 on power up -- -- Interrupts will be generated for the following events: -- -- High-to-low transition of the PLSBSY status bit (edge) -- High-to-low transition of the RBSBSY status bit (edge) -- When the IMX828 status bit is set (level). -- -- When the PLSDN or or RBSDN bits are set in the status -- register and you wish to clear them, you must mask then -- unmask them to clear them. -- -- -- -- *** LED control *** -- -- Write only -- -- 7 6 5 4 3 2 1 0 -- LED31 LED30 LED21 LED20 LED11 LED10 LED01 LED00 -- Where LEDx1 and LEDx0 are a truth table of: -- -- 00 - LED off -- 01 - LED green -- 10 - LED red -- 11 - LED yellow -- -- This register will be cleared on power up -- -- *** MX828 address *** -- -- Write only -- 7 6 5 4 3 2 1 0 -- - - - - - FREEZE MXA1 MXA0 -- This is the address used to select a particular MX828 device -- to issue a command to. This address doubles as the address used -- to program the Xilinx at initialization. -- The freeze bit is used to freeze the status update to the 4 MX828 status -- registers. Once the status has been read, the freeze bit should be cleared. -- -- Important: the freeze bit must be set and unset periodically to reset the -- TX watchdog. the TX watchdog will time out in 100 milliseconds if there is no -- freeze/unfreeze activity present. -- -- *** MX828_command *** -- -- Write only -- -- Command code to send to MX828 -- Refer to the MX828 data sheet -- -- Writing to this address starts the MX828 command serializer. -- -- *** MX828_first_byte *** -- -- Write only -- -- First data byte sent to MX828, also doubles as Xilinx programming write location. -- Refer to the MX828 data sheet. -- -- -- *** MX828_status_ch0 *** -- *** MX828_status_ch1 *** -- *** MX828_status_ch2 *** -- *** MX828_status_ch3 *** -- -- Read only -- -- Byte of data returned when MX828 read commands ar executed -- Refer to the MX828 data sheet -- -- *** MX828_second_byte *** -- -- Write only -- -- Second data byte sent to MX828. -- Refer to the MX828 data sheet -- -- -- *** TEST/PTT *** -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- -- TEST3 TEST2 TEST1 TEST0 PTT3 PTT2 PTT1 PTT0 -- -- Write a 1 to set PTT, 0 to clear PTT. -- Write 1 1 to set a test bit, and a 0 to clear a test bit -- This register will be cleared on power up. -- -- *** RBS_Bytes_Queued *** -- -- Read only -- -- 7 6 5 4 3 2 1 0 -- -- - - - - - BQ2 BQ1 BQ0 -- Indicates number of remote base serializer bytes queued in fifo (up to 6) -- This register will be cleared on power up. -- -- *** RBS_Cmd *** -- -- Write only -- -- 0x00 - Clear Queue -- 0x01 - Send bytes -- -- *** RBS_Data *** -- -- Write only -- -- Writing a byte to this register places it into the serializer FIFO. -- The FIFO can hold up to 6 bytes -- -- -- *** UIO_AB *** -- -- Read/Write -- -- 7 6 5 4 3 2 1 0 -- UIOB3 UIOB2 UIOB1 UIOB0 UIOA3 UIOA2 UIOA1 UIOA0 -- -- This register will be cleared on power up. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pciradio is port ( arn : in std_logic; -- global reset clko_tj : in std_logic; -- clock from TJ oscillator cell from_mx828 : in std_logic; -- serial data from MX828 chips irqn_mx828 : in std_logic; -- IRQ from MX828 rdn : in std_logic; -- read strobe in from tigerjet wrn : in std_logic; -- write strobe in from tigerjet cor : in std_logic_vector(3 downto 0); -- cor status bits in ha : in std_logic_vector(3 downto 0); -- tigerjet GPIO address bus in hd : inout std_logic_vector(7 downto 0); -- tigerjet GPIO data bus testhdr : inout std_logic_vector(3 downto 0); -- test header pins uioa : inout std_logic_vector(3 downto 0); -- uio port a uiob : inout std_logic_vector(3 downto 0); -- uio port b clk2048 : out std_logic; -- 2048 KHz clock out tjfsc : out std_logic; -- tigerjet frame sync out clk_mx828 : out std_logic; -- serial clock to MX828's to_mx828 : out std_logic; -- serial data to MX828's tjirq : out std_logic; -- IRQ to tigerjet fsync : out std_logic_vector(3 downto 0); -- frame syncs to codecs csbn_mx828 : out std_logic_vector(3 downto 0); -- low-true chip selects to MX828's pttn : out std_logic_vector(3 downto 0); -- low-true PTT outputs led0 : out std_logic_vector(1 downto 0); -- LED for channel 0 led1 : out std_logic_vector(1 downto 0); -- LED for channel 1 led2 : out std_logic_vector(1 downto 0); -- LED for channel 2 led3 : out std_logic_vector(1 downto 0) -- LED for channel 3 ); end pciradio; architecture rtl of pciradio is signal busy_mx828 : std_logic; signal rd : std_logic; signal clk : std_logic; signal cmdsel_mx828 : std_logic; signal fbsel_mx828 : std_logic; signal sbsel_mx828 : std_logic; signal adsel_mx828 : std_logic; signal sel_uio : std_logic; signal sel_testptt : std_logic; signal sel_ctrl1 : std_logic; signal sel_ctrl2 : std_logic; signal sel_leds : std_logic; signal sel_irqmask : std_logic; signal sel_uarttx : std_logic; signal ledpwm : std_logic; signal rbs_regsel : std_logic; signal rbs_cmdsel : std_logic; signal rbsclk : std_logic; signal rbsdata : std_logic; signal rbs_busy : std_logic; signal irq_mx828 : std_logic; signal mxaccess : std_logic; signal tjirqint : std_logic; signal rbs_bq : std_logic_vector(2 downto 0); signal csb_mx828 : std_logic_vector(3 downto 0); signal stat_mx8280 : std_logic_vector(7 downto 0); signal stat_mx8281 : std_logic_vector(7 downto 0); signal stat_mx8282 : std_logic_vector(7 downto 0); signal stat_mx8283 : std_logic_vector(7 downto 0); signal uart_rxdata : std_logic_vector(7 downto 0); signal uioin : std_logic_vector(7 downto 0); signal uioout : std_logic_vector(7 downto 0); signal testpttin : std_logic_vector(7 downto 0); signal testpttout : std_logic_vector(7 downto 0); signal wdb : std_logic_vector(7 downto 0); signal rdb : std_logic_vector(7 downto 0); signal statusreg : std_logic_vector(7 downto 0); signal ctrlout1 : std_logic_vector(7 downto 0); signal ctrlout2 : std_logic_vector(7 downto 0); signal corbits : std_logic_vector(7 downto 0); signal irqmaskbits : std_logic_vector(7 downto 0); component mx_seq port ( signal arn : in std_logic; signal clk : in std_logic; signal from_mx828 : in std_logic; signal wrn : in std_logic; signal cmdsel : in std_logic; signal fbsel : in std_logic; signal sbsel : in std_logic; signal adsel : in std_logic; signal wdb : in std_logic_vector(7 downto 0); signal busy : out std_logic; signal to_mx828 : out std_logic; signal clk_mx828 : out std_logic; signal mxaccess : out std_logic; signal csb_mx828 : out std_logic_vector(3 downto 0); signal stat_mx8280 : out std_logic_vector(7 downto 0); signal stat_mx8281 : out std_logic_vector(7 downto 0); signal stat_mx8282 : out std_logic_vector(7 downto 0); signal stat_mx8283 : out std_logic_vector(7 downto 0) ); end component; component io port ( arn : in std_logic; clk : in std_logic; wrn : in std_logic; rd : in std_logic; sel_uio : in std_logic; sel_testptt : in std_logic; sel_ctrl1 : in std_logic; sel_ctrl2 : in std_logic; sel_leds : in std_logic; sel_irqmask : in std_logic; sel_uarttx : in std_logic; rbsclk : in std_logic; rbsdata : in std_logic; irq_mx828 : in std_logic; ledpwm : in std_logic; rbs_busy : in std_logic; busy_mx828 : in std_logic; mxaccess : in std_logic; uioinlsb : in std_logic_vector(3 downto 0); cor : in std_logic_vector(3 downto 0); wdb : in std_logic_vector(7 downto 0); tjirq : out std_logic; led0 : out std_logic_vector(1 downto 0); led1 : out std_logic_vector(1 downto 0); led2 : out std_logic_vector(1 downto 0); led3 : out std_logic_vector(1 downto 0); uioout : out std_logic_vector(7 downto 0); testpttout : out std_logic_vector(7 downto 0); ctrlout1 : out std_logic_vector(7 downto 0); ctrlout2 : out std_logic_vector(7 downto 0); statusreg : out std_logic_vector(7 downto 0); corbits : out std_logic_vector(7 downto 0); irqmaskbits : out std_logic_vector(7 downto 0); uart_rxdata : out std_logic_vector(7 downto 0) ); end component; component frame port ( arn : in std_logic; clk : in std_logic; clk2048 : out std_logic; tjfsc : out std_logic; ledpwm : out std_logic; fsync : out std_logic_vector(3 downto 0) ); end component; component rbs port ( arn : in std_logic; clk : in std_logic; wrn : in std_logic; regsel : in std_logic; cmdsel : in std_logic; wdb : in std_logic_vector(7 downto 0); rbsclk : out std_logic; rbsdata : out std_logic; busy : out std_logic; bq : out std_logic_vector(2 downto 0) ); end component; begin mxseq_i : mx_seq port map ( arn => arn, clk => clk, from_mx828 => from_mx828, wrn => wrn, cmdsel => cmdsel_mx828, fbsel => fbsel_mx828, sbsel => sbsel_mx828, adsel => adsel_mx828, wdb => wdb, busy => busy_mx828, to_mx828 => to_mx828, clk_mx828 => clk_mx828, csb_mx828 => csb_mx828, mxaccess => mxaccess, stat_mx8280 => stat_mx8280, stat_mx8281 => stat_mx8281, stat_mx8282 => stat_mx8282, stat_mx8283 => stat_mx8283 ); io_i : io port map ( arn => arn, clk => clk, wrn => wrn, rd => rd, sel_uio => sel_uio, sel_testptt => sel_testptt, sel_ctrl1 => sel_ctrl1, sel_ctrl2 => sel_ctrl2, sel_leds => sel_leds, sel_irqmask => sel_irqmask, sel_uarttx => sel_uarttx, rbsclk => rbsclk, rbsdata => rbsdata, irq_mx828 => irq_mx828, ledpwm => ledpwm, rbs_busy => rbs_busy, busy_mx828 => busy_mx828, mxaccess => mxaccess, uioinlsb => uioin(3 downto 0), cor => cor, wdb => wdb, tjirq => tjirqint, led0 => led0, led1 => led1, led2 => led2, led3 => led3, uioout => uioout, testpttout => testpttout, ctrlout1 => ctrlout1, ctrlout2 => ctrlout2, statusreg => statusreg, corbits => corbits, irqmaskbits => irqmaskbits, uart_rxdata => uart_rxdata ); frame_i : frame port map ( arn => arn, clk => clk, clk2048 => clk2048, tjfsc => tjfsc, ledpwm => ledpwm, fsync => fsync ); rbs_i : rbs port map ( arn => arn, clk => clk, wrn => wrn, regsel => rbs_regsel, cmdsel => rbs_cmdsel, wdb => wdb, rbsclk => rbsclk, rbsdata => rbsdata, busy => rbs_busy, bq => rbs_bq ); -- multiplex all read ports rd_mux : process( ha, stat_mx8280, stat_mx8281, stat_mx8282, stat_mx8283, testpttin, uioin, ctrlout1, ctrlout2, rbs_bq, statusreg, corbits, irqmaskbits, uart_rxdata) begin case ha is when "0000" => rdb <= stat_mx8280; when "0001" => rdb <= stat_mx8281; when "0010" => rdb <= stat_mx8282; when "0011" => rdb <= stat_mx8283; when "0100" => rdb <= uart_rxdata; when "1000" => rdb <= uioin; when "1001" => rdb <= corbits; when "1010" => rdb <= testpttin; when "1011" => rdb <= "00000" & rbs_bq; when "1100" => rdb <= statusreg; when "1101" => rdb <= irqmaskbits; when "1110" => rdb <= ctrlout1; when "1111" => rdb <= ctrlout2; when others => rdb <= "00000000"; end case; end process rd_mux; -- decode individual selects sel_dec : process(ha) begin cmdsel_mx828 <= '0'; fbsel_mx828 <= '0'; sbsel_mx828 <= '0'; adsel_mx828 <= '0'; sel_uio <= '0'; sel_testptt <= '0'; sel_ctrl1 <= '0'; sel_ctrl2 <= '0'; sel_irqmask <= '0'; sel_uarttx <= '0'; sel_leds <= '0'; rbs_regsel <= '0'; rbs_cmdsel <= '0'; case ha is when "0000" => adsel_mx828 <= '1'; when "0001" => fbsel_mx828 <= '1'; when "0010" => sbsel_mx828 <= '1'; when "0011" => cmdsel_mx828 <= '1'; when "0100" => sel_uarttx <= '1'; when "1000" => sel_uio <= '1'; when "1001" => sel_leds <= '1'; when "1010" => sel_testptt <= '1'; when "1011" => rbs_cmdsel <= '1'; when "1100" => rbs_regsel <= '1'; when "1101" => sel_irqmask <= '1'; when "1110" => sel_ctrl1 <= '1'; when "1111" => sel_ctrl2 <= '1'; when others => null; end case; end process sel_dec; -- -- concurrent statements -- clk <= clko_tj; rd <= not rdn; irq_mx828 <= not irqn_mx828; -- data bus bidirect hd <= rdb when rd = '1' and wrn = '1' else "ZZZZZZZZ"; -- drive data bus on rd active; don't drive the bus during a reset wdb <= hd; -- interrupt tristate driver tjirq <= 'Z'; -- implement tristate control for bidirects GEN_testhdr : for I in 0 to 3 generate testhdr(I) <= testpttout(I+4) when ctrlout2(I) = '0' else 'Z'; end generate GEN_testhdr; GEN_uioa : for I in 0 to 3 generate uioa(I) <= uioout(I) when ctrlout1(I) = '0' else 'Z'; end generate GEN_uioa; GEN_uiob : for I in 0 to 3 generate uiob(I) <= uioout(I+4) when ctrlout1(I+4) = '0' else 'Z'; end generate GEN_uiob; uioin <= uiob(3 downto 0) & uioa(3 downto 0); testpttin <= testhdr(3 downto 0) & testpttout(3 downto 0); -- invert outputs which need to be csbn_mx828 <= not csb_mx828; pttn <= not testpttout(3 downto 0); end rtl;

use std.env.all; entity wave7 is end entity; architecture test of wave7 is signal x : integer; begin x <= 1 after 1 ns, 2 after 2 ns, 3 after 4 ns; process is begin wait for 3 ns; stop; end process; end architecture;

--------------------------------------------------------------------------- -- (c) 2013 mark watson -- I am happy for anyone to use this for non-commercial use. -- If my vhdl files are used commercially or otherwise sold, -- please contact me for explicit permission at scrameta (gmail). -- This applies for source and binary form and derived works. --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; -- KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code -- KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed -- SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held -- CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held -- BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers) ENTITY ps2_keyboard IS PORT ( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; PS2_CLK : IN STD_LOGIC; PS2_DAT : IN STD_LOGIC; KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code KEY_EXTENDED : OUT STD_LOGIC; -- valid on event, if scan code extended KEY_UP : OUT STD_LOGIC -- value on event, if key released ); END ps2_keyboard; ARCHITECTURE vhdl OF ps2_keyboard IS component enable_divider IS generic(COUNT : natural := 1); PORT ( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; ENABLE_IN : IN STD_LOGIC; ENABLE_OUT : OUT STD_LOGIC ); END component; function To_Std_Logic(L: BOOLEAN) return std_ulogic is begin if L then return('1'); else return('0'); end if; end function To_Std_Logic; -- PS2 keyboard sends on its own clock high->low transition -- start, 8 data bits, parity, stop -- Codes are either 1 bytes or 2 bytes (extended) on press -- XX -- EX YY -- Codes are eighter 2 bytes or 3 bytes (extended) on release -- F0 XX -- EX F0 YY -- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77 -- LSB first -- Start bit 0 -- Stop bit 1 -- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7)) -- e.g. -- '0 1100 0010 0 1' -- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0 -- Receive raw data from ps2 serial interface signal ps2_shiftreg_next : std_logic_vector(10 downto 0); signal ps2_shiftreg_reg : std_logic_vector(10 downto 0); signal idle_next : std_logic_vector(3 downto 0); signal idle_reg : std_logic_vector(3 downto 0); signal bitcount_next : std_logic_vector(3 downto 0); signal bitcount_reg : std_logic_vector(3 downto 0); signal enable_ps2 : std_logic; signal last_ps2_clk_next : std_logic; signal last_ps2_clk_reg : std_logic; signal ps2_clk_reg : std_logic; signal ps2_dat_reg : std_logic; signal parity : std_logic; -- Once we have whole parity checked bytes signal byte_next : std_logic_vector(7 downto 0); signal byte_reg : std_logic_vector(7 downto 0); signal byte_received_next : std_logic; signal byte_received_reg : std_logic; -- Decode if they are press(or repeat)/release or extended signal pending_extended_next : std_logic; signal pending_extended_reg : std_logic; signal pending_keyup_next : std_logic; signal pending_keyup_reg : std_logic; -- To eventually get the code itself signal key_event_next : std_logic; signal key_event_reg : std_logic; signal key_value_next : std_logic_vector(9 downto 0); signal key_value_reg : std_logic_vector(9 downto 0); -- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard signal key_value_last_next : std_logic_vector(9 downto 0); signal key_value_last_reg : std_logic_vector(9 downto 0); BEGIN -- register process(clk,reset_n) begin if (reset_n = '0') then ps2_clk_reg <= '0'; ps2_dat_reg <= '0'; -- Convert to bytes/verify last_ps2_clk_reg <= '0'; ps2_shiftreg_reg<= (others=>'0'); idle_reg <= (others=>'0'); bitcount_reg <= (others=>'0'); byte_received_reg <= '0'; byte_reg <= (others=>'0'); -- Handle simple byte strings (extended,byte extended,release,byte byte release,byte) pending_extended_reg <= '0'; pending_keyup_reg <= '0'; -- Output registers key_event_reg <= '0'; key_value_reg <= (others=>'0'); key_value_last_reg <= (others=>'0'); elsif (clk'event and clk='1') then -- Raw interface -- async - do we need some form of synchronizer? ps2_clk_reg <= ps2_clk; ps2_dat_reg <= ps2_dat; -- Convert to bytes/verify last_ps2_clk_reg <= last_ps2_clk_next; ps2_shiftreg_reg<= ps2_shiftreg_next; idle_reg <= idle_next; bitcount_reg <= bitcount_next; byte_received_reg <= byte_received_next; byte_reg <= byte_next; -- Handle simple byte strings (extended,byte extended,release,byte byte release,byte) pending_extended_reg <= pending_extended_next; pending_keyup_reg <= pending_keyup_next; -- Output registers key_event_reg <= key_event_next; key_value_reg <= key_value_next; key_value_last_reg <= key_value_last_next; end if; end process; -- Divide clock by 256 to get approx 4*ps2 clock enable_div : enable_divider generic map (COUNT=>256) port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2); -- capture bytes from ps2 parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1)); process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity) begin ps2_shiftreg_next <= ps2_shiftreg_reg; last_ps2_clk_next <= last_ps2_clk_reg; bitcount_next <= bitcount_reg; idle_next <= idle_reg; byte_received_next <= '0'; byte_next <= (others=>'0'); if (enable_ps2 = '1') then last_ps2_clk_next <= ps2_clk_reg; -- sample on falling edge if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1); bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1); end if; -- output to next stage when done if (bitcount_reg = X"B") then byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10); byte_next <= ps2_shiftreg_reg(8 downto 1); bitcount_next <= (others=>'0'); end if; -- reset if both high for a time period idle_next <= std_logic_vector(unsigned(idle_reg) +1); if (idle_reg = X"F") then ps2_shiftreg_next <= (others=>'0'); bitcount_next <= (others=>'0'); end if; if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then idle_next <= X"0"; end if; end if; end process; -- process bytes process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg) begin pending_extended_next <= pending_extended_reg; pending_keyup_next <= pending_keyup_reg; key_event_next <= '0'; key_value_next <= (others =>'0'); key_value_last_next <= key_value_last_reg; if (byte_received_reg = '1') then case byte_reg is when X"E0" => pending_extended_next <= '1'; when X"E1" => pending_extended_next <= '1'; when X"F0" => pending_keyup_next <= '1'; when others => pending_extended_next <= '0'; pending_keyup_next <= '0'; if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then key_event_next <= '1'; key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0); key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0); end if; end case; end if; end process; -- Output key_event <= key_event_reg; key_value <= key_value_reg(7 downto 0); key_extended <= key_value_reg(8); key_up <= key_value_reg(9); END vhdl;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Rb6OdOK5N2kns0OPFJ+v++CzW8nfRqW9kd0J9AvFumoKiqRN9RHtgeg+p+kC5+qKBEeV8v2CM3Mx xfOLSM2Cbw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k+/wkBwU+75iNI7Pd10nZcfLz44mnsMTesDjGv76vFtqR9MdNa8H8rqfcawbc0HbSX7oNM6fXhzb ZIl25X3rGOfwr0205uzvk8cI8UM31Lilzi8gh1sXYNzAv8MUxqbzKQuW2XpCt8tyVJ5kUhhrvFpU 7URPhIc62Py3y1k/gfo= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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architecture RTL of SPIShifter is signal EnableShiftReg : STD_LOGIC; signal ShiftRegister : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal NextShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal LoadShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataInRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataOut : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal DataOutRev : STD_LOGIC_VECTOR(DataWidth-1 downto 0); signal SampleRegister : STD_LOGIC; begin -- calculate DataInRev DataInputReversion: process (Data_i) begin for BitNumber in DataWidth-1 downto 0 loop DataInRev(BitNumber) <= Data_i((DataWidth-1) - BitNumber); end loop; end process DataInputReversion; -- combinational inputs EnableShiftReg <= LdShifter_i or EnShift_i; LoadShiftReg <= Data_i when LSBFE_i = '0' else DataInRev; NextShiftReg <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister when LdShifter_i = '0' else LoadShiftReg; -- sequential statements SPIShiftRegister: process (Reset_n, Clk) begin if Reset_n = '0' then ShiftRegister <= (others => '0'); elsif Clk'event and Clk = '1' then if EnableShiftReg = '1' then ShiftRegister <= NextShiftReg; end if; end if; end process SPIShiftRegister; SPISampleRegister: process (Reset_n, Clk) begin if Reset_n = '0' then SampleRegister <= '0'; elsif Clk'event and Clk = '1' then if EnSample_i = '1' then SampleRegister <= To_X01(MISO_i); end if; end if; end process SPISampleRegister; -- calculate DataOut DataOut <= ShiftRegister(DataWidth-2 downto 0) & SampleRegister; -- calculate DataOutRev DataOutputReversion: process (DataOut) begin for BitNumber in DataWidth-1 downto 0 loop DataOutRev(BitNumber) <= DataOut((DataWidth-1) - BitNumber); end loop; end process DataOutputReversion; -- combinational outputs MOSI_o <= ShiftRegister(DataWidth-1); Data_o <= DataOut when LSBFE_i = '0' else DataOutRev; end RTL;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity aestest_sboxes_rom is generic( dwidth : integer := 8; awidth : integer := 8; mem_size : integer := 256 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); addr2 : in std_logic_vector(awidth-1 downto 0); ce2 : in std_logic; q2 : out std_logic_vector(dwidth-1 downto 0); addr3 : in std_logic_vector(awidth-1 downto 0); ce3 : in std_logic; q3 : out std_logic_vector(dwidth-1 downto 0); addr4 : in std_logic_vector(awidth-1 downto 0); ce4 : in std_logic; q4 : out std_logic_vector(dwidth-1 downto 0); addr5 : in std_logic_vector(awidth-1 downto 0); ce5 : in std_logic; q5 : out std_logic_vector(dwidth-1 downto 0); addr6 : in std_logic_vector(awidth-1 downto 0); ce6 : in std_logic; q6 : out std_logic_vector(dwidth-1 downto 0); addr7 : in std_logic_vector(awidth-1 downto 0); ce7 : in std_logic; q7 : out std_logic_vector(dwidth-1 downto 0); addr8 : in std_logic_vector(awidth-1 downto 0); ce8 : in std_logic; q8 : out std_logic_vector(dwidth-1 downto 0); addr9 : in std_logic_vector(awidth-1 downto 0); ce9 : in std_logic; q9 : out std_logic_vector(dwidth-1 downto 0); addr10 : in std_logic_vector(awidth-1 downto 0); ce10 : in std_logic; q10 : out std_logic_vector(dwidth-1 downto 0); addr11 : in std_logic_vector(awidth-1 downto 0); ce11 : in std_logic; q11 : out std_logic_vector(dwidth-1 downto 0); addr12 : in std_logic_vector(awidth-1 downto 0); ce12 : in std_logic; q12 : out std_logic_vector(dwidth-1 downto 0); addr13 : in std_logic_vector(awidth-1 downto 0); ce13 : in std_logic; q13 : out std_logic_vector(dwidth-1 downto 0); addr14 : in std_logic_vector(awidth-1 downto 0); ce14 : in std_logic; q14 : out std_logic_vector(dwidth-1 downto 0); addr15 : in std_logic_vector(awidth-1 downto 0); ce15 : in std_logic; q15 : out std_logic_vector(dwidth-1 downto 0); addr16 : in std_logic_vector(awidth-1 downto 0); ce16 : in std_logic; q16 : out std_logic_vector(dwidth-1 downto 0); addr17 : in std_logic_vector(awidth-1 downto 0); ce17 : in std_logic; q17 : out std_logic_vector(dwidth-1 downto 0); addr18 : in std_logic_vector(awidth-1 downto 0); ce18 : in std_logic; q18 : out std_logic_vector(dwidth-1 downto 0); addr19 : in std_logic_vector(awidth-1 downto 0); ce19 : in std_logic; q19 : out std_logic_vector(dwidth-1 downto 0); addr20 : in std_logic_vector(awidth-1 downto 0); ce20 : in std_logic; q20 : out std_logic_vector(dwidth-1 downto 0); addr21 : in std_logic_vector(awidth-1 downto 0); ce21 : in std_logic; q21 : out std_logic_vector(dwidth-1 downto 0); addr22 : in std_logic_vector(awidth-1 downto 0); ce22 : in std_logic; q22 : out std_logic_vector(dwidth-1 downto 0); addr23 : in std_logic_vector(awidth-1 downto 0); ce23 : in std_logic; q23 : out std_logic_vector(dwidth-1 downto 0); addr24 : in std_logic_vector(awidth-1 downto 0); ce24 : in std_logic; q24 : out std_logic_vector(dwidth-1 downto 0); addr25 : in std_logic_vector(awidth-1 downto 0); ce25 : in std_logic; q25 : out std_logic_vector(dwidth-1 downto 0); addr26 : in std_logic_vector(awidth-1 downto 0); ce26 : in std_logic; q26 : out std_logic_vector(dwidth-1 downto 0); addr27 : in std_logic_vector(awidth-1 downto 0); ce27 : in std_logic; q27 : out std_logic_vector(dwidth-1 downto 0); addr28 : in std_logic_vector(awidth-1 downto 0); ce28 : in std_logic; q28 : out std_logic_vector(dwidth-1 downto 0); addr29 : in std_logic_vector(awidth-1 downto 0); ce29 : in std_logic; q29 : out std_logic_vector(dwidth-1 downto 0); addr30 : in std_logic_vector(awidth-1 downto 0); ce30 : in std_logic; q30 : out std_logic_vector(dwidth-1 downto 0); addr31 : in std_logic_vector(awidth-1 downto 0); ce31 : in std_logic; q31 : out std_logic_vector(dwidth-1 downto 0); addr32 : in std_logic_vector(awidth-1 downto 0); ce32 : in std_logic; q32 : out std_logic_vector(dwidth-1 downto 0); addr33 : in std_logic_vector(awidth-1 downto 0); ce33 : in std_logic; q33 : out std_logic_vector(dwidth-1 downto 0); addr34 : in std_logic_vector(awidth-1 downto 0); ce34 : in std_logic; q34 : out std_logic_vector(dwidth-1 downto 0); addr35 : in std_logic_vector(awidth-1 downto 0); ce35 : in std_logic; q35 : out std_logic_vector(dwidth-1 downto 0); addr36 : in std_logic_vector(awidth-1 downto 0); ce36 : in std_logic; q36 : out std_logic_vector(dwidth-1 downto 0); addr37 : in std_logic_vector(awidth-1 downto 0); ce37 : in std_logic; q37 : out std_logic_vector(dwidth-1 downto 0); addr38 : in std_logic_vector(awidth-1 downto 0); ce38 : in std_logic; q38 : out std_logic_vector(dwidth-1 downto 0); addr39 : in std_logic_vector(awidth-1 downto 0); ce39 : in std_logic; q39 : out std_logic_vector(dwidth-1 downto 0); addr40 : in std_logic_vector(awidth-1 downto 0); ce40 : in std_logic; q40 : out std_logic_vector(dwidth-1 downto 0); addr41 : in std_logic_vector(awidth-1 downto 0); ce41 : in std_logic; q41 : out std_logic_vector(dwidth-1 downto 0); addr42 : in std_logic_vector(awidth-1 downto 0); ce42 : in std_logic; q42 : out std_logic_vector(dwidth-1 downto 0); addr43 : in std_logic_vector(awidth-1 downto 0); ce43 : in std_logic; q43 : out std_logic_vector(dwidth-1 downto 0); addr44 : in std_logic_vector(awidth-1 downto 0); ce44 : in std_logic; q44 : out std_logic_vector(dwidth-1 downto 0); addr45 : in std_logic_vector(awidth-1 downto 0); ce45 : in std_logic; q45 : out std_logic_vector(dwidth-1 downto 0); addr46 : in std_logic_vector(awidth-1 downto 0); ce46 : in std_logic; q46 : out std_logic_vector(dwidth-1 downto 0); addr47 : in std_logic_vector(awidth-1 downto 0); ce47 : in std_logic; q47 : out std_logic_vector(dwidth-1 downto 0); addr48 : in std_logic_vector(awidth-1 downto 0); ce48 : in std_logic; q48 : out std_logic_vector(dwidth-1 downto 0); addr49 : in std_logic_vector(awidth-1 downto 0); ce49 : in std_logic; q49 : out std_logic_vector(dwidth-1 downto 0); addr50 : in std_logic_vector(awidth-1 downto 0); ce50 : in std_logic; q50 : out std_logic_vector(dwidth-1 downto 0); addr51 : in std_logic_vector(awidth-1 downto 0); ce51 : in std_logic; q51 : out std_logic_vector(dwidth-1 downto 0); addr52 : in std_logic_vector(awidth-1 downto 0); ce52 : in std_logic; q52 : out std_logic_vector(dwidth-1 downto 0); addr53 : in std_logic_vector(awidth-1 downto 0); ce53 : in std_logic; q53 : out std_logic_vector(dwidth-1 downto 0); addr54 : in std_logic_vector(awidth-1 downto 0); ce54 : in std_logic; q54 : out std_logic_vector(dwidth-1 downto 0); addr55 : in std_logic_vector(awidth-1 downto 0); ce55 : in std_logic; q55 : out std_logic_vector(dwidth-1 downto 0); addr56 : in std_logic_vector(awidth-1 downto 0); ce56 : in std_logic; q56 : out std_logic_vector(dwidth-1 downto 0); addr57 : in std_logic_vector(awidth-1 downto 0); ce57 : in std_logic; q57 : out std_logic_vector(dwidth-1 downto 0); addr58 : in std_logic_vector(awidth-1 downto 0); ce58 : in std_logic; q58 : out std_logic_vector(dwidth-1 downto 0); addr59 : in std_logic_vector(awidth-1 downto 0); ce59 : in std_logic; q59 : out std_logic_vector(dwidth-1 downto 0); addr60 : in std_logic_vector(awidth-1 downto 0); ce60 : in std_logic; q60 : out std_logic_vector(dwidth-1 downto 0); addr61 : in std_logic_vector(awidth-1 downto 0); ce61 : in std_logic; q61 : out std_logic_vector(dwidth-1 downto 0); addr62 : in std_logic_vector(awidth-1 downto 0); ce62 : in std_logic; q62 : out std_logic_vector(dwidth-1 downto 0); addr63 : in std_logic_vector(awidth-1 downto 0); ce63 : in std_logic; q63 : out std_logic_vector(dwidth-1 downto 0); addr64 : in std_logic_vector(awidth-1 downto 0); ce64 : in std_logic; q64 : out std_logic_vector(dwidth-1 downto 0); addr65 : in std_logic_vector(awidth-1 downto 0); ce65 : in std_logic; q65 : out std_logic_vector(dwidth-1 downto 0); addr66 : in std_logic_vector(awidth-1 downto 0); ce66 : in std_logic; q66 : out std_logic_vector(dwidth-1 downto 0); addr67 : in std_logic_vector(awidth-1 downto 0); ce67 : in std_logic; q67 : out std_logic_vector(dwidth-1 downto 0); addr68 : in std_logic_vector(awidth-1 downto 0); ce68 : in std_logic; q68 : out std_logic_vector(dwidth-1 downto 0); addr69 : in std_logic_vector(awidth-1 downto 0); ce69 : in std_logic; q69 : out std_logic_vector(dwidth-1 downto 0); addr70 : in std_logic_vector(awidth-1 downto 0); ce70 : in std_logic; q70 : out std_logic_vector(dwidth-1 downto 0); addr71 : in std_logic_vector(awidth-1 downto 0); ce71 : in std_logic; q71 : out std_logic_vector(dwidth-1 downto 0); addr72 : in std_logic_vector(awidth-1 downto 0); ce72 : in std_logic; q72 : out std_logic_vector(dwidth-1 downto 0); addr73 : in std_logic_vector(awidth-1 downto 0); ce73 : in std_logic; q73 : out std_logic_vector(dwidth-1 downto 0); addr74 : in std_logic_vector(awidth-1 downto 0); ce74 : in std_logic; q74 : out std_logic_vector(dwidth-1 downto 0); addr75 : in std_logic_vector(awidth-1 downto 0); ce75 : in std_logic; q75 : out std_logic_vector(dwidth-1 downto 0); addr76 : in std_logic_vector(awidth-1 downto 0); ce76 : in std_logic; q76 : out std_logic_vector(dwidth-1 downto 0); addr77 : in std_logic_vector(awidth-1 downto 0); ce77 : in std_logic; q77 : out std_logic_vector(dwidth-1 downto 0); addr78 : in std_logic_vector(awidth-1 downto 0); ce78 : in std_logic; q78 : out std_logic_vector(dwidth-1 downto 0); addr79 : in std_logic_vector(awidth-1 downto 0); ce79 : in std_logic; q79 : out std_logic_vector(dwidth-1 downto 0); addr80 : in std_logic_vector(awidth-1 downto 0); ce80 : in std_logic; q80 : out std_logic_vector(dwidth-1 downto 0); addr81 : in std_logic_vector(awidth-1 downto 0); ce81 : in std_logic; q81 : out std_logic_vector(dwidth-1 downto 0); addr82 : in std_logic_vector(awidth-1 downto 0); ce82 : in std_logic; q82 : out std_logic_vector(dwidth-1 downto 0); addr83 : in std_logic_vector(awidth-1 downto 0); ce83 : in std_logic; q83 : out std_logic_vector(dwidth-1 downto 0); addr84 : in std_logic_vector(awidth-1 downto 0); ce84 : in std_logic; q84 : out std_logic_vector(dwidth-1 downto 0); addr85 : in std_logic_vector(awidth-1 downto 0); ce85 : in std_logic; q85 : out std_logic_vector(dwidth-1 downto 0); addr86 : in std_logic_vector(awidth-1 downto 0); ce86 : in std_logic; q86 : out std_logic_vector(dwidth-1 downto 0); addr87 : in std_logic_vector(awidth-1 downto 0); ce87 : in std_logic; q87 : out std_logic_vector(dwidth-1 downto 0); addr88 : in std_logic_vector(awidth-1 downto 0); ce88 : in std_logic; q88 : out std_logic_vector(dwidth-1 downto 0); addr89 : in std_logic_vector(awidth-1 downto 0); ce89 : in std_logic; q89 : out std_logic_vector(dwidth-1 downto 0); addr90 : in std_logic_vector(awidth-1 downto 0); ce90 : in std_logic; q90 : out std_logic_vector(dwidth-1 downto 0); addr91 : in std_logic_vector(awidth-1 downto 0); ce91 : in std_logic; q91 : out std_logic_vector(dwidth-1 downto 0); addr92 : in std_logic_vector(awidth-1 downto 0); ce92 : in std_logic; q92 : out std_logic_vector(dwidth-1 downto 0); addr93 : in std_logic_vector(awidth-1 downto 0); ce93 : in std_logic; q93 : out std_logic_vector(dwidth-1 downto 0); addr94 : in std_logic_vector(awidth-1 downto 0); ce94 : in std_logic; q94 : out std_logic_vector(dwidth-1 downto 0); addr95 : in std_logic_vector(awidth-1 downto 0); ce95 : in std_logic; q95 : out std_logic_vector(dwidth-1 downto 0); addr96 : in std_logic_vector(awidth-1 downto 0); ce96 : in std_logic; q96 : out std_logic_vector(dwidth-1 downto 0); addr97 : in std_logic_vector(awidth-1 downto 0); ce97 : in std_logic; q97 : out std_logic_vector(dwidth-1 downto 0); addr98 : in std_logic_vector(awidth-1 downto 0); ce98 : in std_logic; q98 : out std_logic_vector(dwidth-1 downto 0); addr99 : in std_logic_vector(awidth-1 downto 0); ce99 : in std_logic; q99 : out std_logic_vector(dwidth-1 downto 0); addr100 : in std_logic_vector(awidth-1 downto 0); ce100 : in std_logic; q100 : out std_logic_vector(dwidth-1 downto 0); addr101 : in std_logic_vector(awidth-1 downto 0); ce101 : in std_logic; q101 : out std_logic_vector(dwidth-1 downto 0); addr102 : in std_logic_vector(awidth-1 downto 0); ce102 : in std_logic; q102 : out std_logic_vector(dwidth-1 downto 0); addr103 : in std_logic_vector(awidth-1 downto 0); ce103 : in std_logic; q103 : out std_logic_vector(dwidth-1 downto 0); addr104 : in std_logic_vector(awidth-1 downto 0); ce104 : in std_logic; q104 : out std_logic_vector(dwidth-1 downto 0); addr105 : in std_logic_vector(awidth-1 downto 0); ce105 : in std_logic; q105 : out std_logic_vector(dwidth-1 downto 0); addr106 : in std_logic_vector(awidth-1 downto 0); ce106 : in std_logic; q106 : out std_logic_vector(dwidth-1 downto 0); addr107 : in std_logic_vector(awidth-1 downto 0); ce107 : in std_logic; q107 : out std_logic_vector(dwidth-1 downto 0); addr108 : in std_logic_vector(awidth-1 downto 0); ce108 : in std_logic; q108 : out std_logic_vector(dwidth-1 downto 0); addr109 : in std_logic_vector(awidth-1 downto 0); ce109 : in std_logic; q109 : out std_logic_vector(dwidth-1 downto 0); addr110 : in std_logic_vector(awidth-1 downto 0); ce110 : in std_logic; q110 : out std_logic_vector(dwidth-1 downto 0); addr111 : in std_logic_vector(awidth-1 downto 0); ce111 : in std_logic; q111 : out std_logic_vector(dwidth-1 downto 0); addr112 : in std_logic_vector(awidth-1 downto 0); ce112 : in std_logic; q112 : out std_logic_vector(dwidth-1 downto 0); addr113 : in std_logic_vector(awidth-1 downto 0); ce113 : in std_logic; q113 : out std_logic_vector(dwidth-1 downto 0); addr114 : in std_logic_vector(awidth-1 downto 0); ce114 : in std_logic; q114 : out std_logic_vector(dwidth-1 downto 0); addr115 : in std_logic_vector(awidth-1 downto 0); ce115 : in std_logic; q115 : out std_logic_vector(dwidth-1 downto 0); addr116 : in std_logic_vector(awidth-1 downto 0); ce116 : in std_logic; q116 : out std_logic_vector(dwidth-1 downto 0); addr117 : in std_logic_vector(awidth-1 downto 0); ce117 : in std_logic; q117 : out std_logic_vector(dwidth-1 downto 0); addr118 : in std_logic_vector(awidth-1 downto 0); ce118 : in std_logic; q118 : out std_logic_vector(dwidth-1 downto 0); addr119 : in std_logic_vector(awidth-1 downto 0); ce119 : in std_logic; q119 : out std_logic_vector(dwidth-1 downto 0); addr120 : in std_logic_vector(awidth-1 downto 0); ce120 : in std_logic; q120 : out std_logic_vector(dwidth-1 downto 0); addr121 : in std_logic_vector(awidth-1 downto 0); ce121 : in std_logic; q121 : out std_logic_vector(dwidth-1 downto 0); addr122 : in std_logic_vector(awidth-1 downto 0); ce122 : in std_logic; q122 : out std_logic_vector(dwidth-1 downto 0); addr123 : in std_logic_vector(awidth-1 downto 0); ce123 : in std_logic; q123 : out std_logic_vector(dwidth-1 downto 0); addr124 : in std_logic_vector(awidth-1 downto 0); ce124 : in std_logic; q124 : out std_logic_vector(dwidth-1 downto 0); addr125 : in std_logic_vector(awidth-1 downto 0); ce125 : in std_logic; q125 : out std_logic_vector(dwidth-1 downto 0); addr126 : in std_logic_vector(awidth-1 downto 0); ce126 : in std_logic; q126 : out std_logic_vector(dwidth-1 downto 0); addr127 : in std_logic_vector(awidth-1 downto 0); ce127 : in std_logic; q127 : out std_logic_vector(dwidth-1 downto 0); addr128 : in std_logic_vector(awidth-1 downto 0); ce128 : in std_logic; q128 : out std_logic_vector(dwidth-1 downto 0); addr129 : in std_logic_vector(awidth-1 downto 0); ce129 : in std_logic; q129 : out std_logic_vector(dwidth-1 downto 0); addr130 : in std_logic_vector(awidth-1 downto 0); ce130 : in std_logic; q130 : out std_logic_vector(dwidth-1 downto 0); addr131 : in std_logic_vector(awidth-1 downto 0); ce131 : in std_logic; q131 : out std_logic_vector(dwidth-1 downto 0); addr132 : in std_logic_vector(awidth-1 downto 0); ce132 : in std_logic; q132 : out std_logic_vector(dwidth-1 downto 0); addr133 : in std_logic_vector(awidth-1 downto 0); ce133 : in std_logic; q133 : out std_logic_vector(dwidth-1 downto 0); addr134 : in std_logic_vector(awidth-1 downto 0); ce134 : in std_logic; q134 : out std_logic_vector(dwidth-1 downto 0); addr135 : in std_logic_vector(awidth-1 downto 0); ce135 : in std_logic; q135 : out std_logic_vector(dwidth-1 downto 0); addr136 : in std_logic_vector(awidth-1 downto 0); ce136 : in std_logic; q136 : out std_logic_vector(dwidth-1 downto 0); addr137 : in std_logic_vector(awidth-1 downto 0); ce137 : in std_logic; q137 : out std_logic_vector(dwidth-1 downto 0); addr138 : in std_logic_vector(awidth-1 downto 0); ce138 : in std_logic; q138 : out std_logic_vector(dwidth-1 downto 0); addr139 : in std_logic_vector(awidth-1 downto 0); ce139 : in std_logic; q139 : out std_logic_vector(dwidth-1 downto 0); addr140 : in std_logic_vector(awidth-1 downto 0); ce140 : in std_logic; q140 : out std_logic_vector(dwidth-1 downto 0); addr141 : in std_logic_vector(awidth-1 downto 0); ce141 : in std_logic; q141 : out std_logic_vector(dwidth-1 downto 0); addr142 : in std_logic_vector(awidth-1 downto 0); ce142 : in std_logic; q142 : out std_logic_vector(dwidth-1 downto 0); addr143 : in std_logic_vector(awidth-1 downto 0); ce143 : in std_logic; q143 : out std_logic_vector(dwidth-1 downto 0); addr144 : in std_logic_vector(awidth-1 downto 0); ce144 : in std_logic; q144 : out std_logic_vector(dwidth-1 downto 0); addr145 : in std_logic_vector(awidth-1 downto 0); ce145 : in std_logic; q145 : out std_logic_vector(dwidth-1 downto 0); addr146 : in std_logic_vector(awidth-1 downto 0); ce146 : in std_logic; q146 : out std_logic_vector(dwidth-1 downto 0); addr147 : in std_logic_vector(awidth-1 downto 0); ce147 : in std_logic; q147 : out std_logic_vector(dwidth-1 downto 0); addr148 : in std_logic_vector(awidth-1 downto 0); ce148 : in std_logic; q148 : out std_logic_vector(dwidth-1 downto 0); addr149 : in std_logic_vector(awidth-1 downto 0); ce149 : in std_logic; q149 : out std_logic_vector(dwidth-1 downto 0); addr150 : in std_logic_vector(awidth-1 downto 0); ce150 : in std_logic; q150 : out std_logic_vector(dwidth-1 downto 0); addr151 : in std_logic_vector(awidth-1 downto 0); ce151 : in std_logic; q151 : out std_logic_vector(dwidth-1 downto 0); addr152 : in std_logic_vector(awidth-1 downto 0); ce152 : in std_logic; q152 : out std_logic_vector(dwidth-1 downto 0); addr153 : in std_logic_vector(awidth-1 downto 0); ce153 : in std_logic; q153 : out std_logic_vector(dwidth-1 downto 0); addr154 : in std_logic_vector(awidth-1 downto 0); ce154 : in std_logic; q154 : out std_logic_vector(dwidth-1 downto 0); addr155 : in std_logic_vector(awidth-1 downto 0); ce155 : in std_logic; q155 : out std_logic_vector(dwidth-1 downto 0); addr156 : in std_logic_vector(awidth-1 downto 0); ce156 : in std_logic; q156 : out std_logic_vector(dwidth-1 downto 0); addr157 : in std_logic_vector(awidth-1 downto 0); ce157 : in std_logic; q157 : out std_logic_vector(dwidth-1 downto 0); addr158 : in std_logic_vector(awidth-1 downto 0); ce158 : in std_logic; q158 : out std_logic_vector(dwidth-1 downto 0); addr159 : in std_logic_vector(awidth-1 downto 0); ce159 : in std_logic; q159 : out std_logic_vector(dwidth-1 downto 0); addr160 : in std_logic_vector(awidth-1 downto 0); ce160 : in std_logic; q160 : out std_logic_vector(dwidth-1 downto 0); addr161 : in std_logic_vector(awidth-1 downto 0); ce161 : in std_logic; q161 : out std_logic_vector(dwidth-1 downto 0); addr162 : in std_logic_vector(awidth-1 downto 0); ce162 : in std_logic; q162 : out std_logic_vector(dwidth-1 downto 0); addr163 : in std_logic_vector(awidth-1 downto 0); ce163 : in std_logic; q163 : out std_logic_vector(dwidth-1 downto 0); addr164 : in std_logic_vector(awidth-1 downto 0); ce164 : in std_logic; q164 : out std_logic_vector(dwidth-1 downto 0); addr165 : in std_logic_vector(awidth-1 downto 0); ce165 : in std_logic; q165 : out std_logic_vector(dwidth-1 downto 0); addr166 : in std_logic_vector(awidth-1 downto 0); ce166 : in std_logic; q166 : out std_logic_vector(dwidth-1 downto 0); addr167 : in std_logic_vector(awidth-1 downto 0); ce167 : in std_logic; q167 : out std_logic_vector(dwidth-1 downto 0); addr168 : in std_logic_vector(awidth-1 downto 0); ce168 : in std_logic; q168 : out std_logic_vector(dwidth-1 downto 0); addr169 : in std_logic_vector(awidth-1 downto 0); ce169 : in std_logic; q169 : out std_logic_vector(dwidth-1 downto 0); addr170 : in std_logic_vector(awidth-1 downto 0); ce170 : in std_logic; q170 : out std_logic_vector(dwidth-1 downto 0); addr171 : in std_logic_vector(awidth-1 downto 0); ce171 : in std_logic; q171 : out std_logic_vector(dwidth-1 downto 0); addr172 : in std_logic_vector(awidth-1 downto 0); ce172 : in std_logic; q172 : out std_logic_vector(dwidth-1 downto 0); addr173 : in std_logic_vector(awidth-1 downto 0); ce173 : in std_logic; q173 : out std_logic_vector(dwidth-1 downto 0); addr174 : in std_logic_vector(awidth-1 downto 0); ce174 : in std_logic; q174 : out std_logic_vector(dwidth-1 downto 0); addr175 : in std_logic_vector(awidth-1 downto 0); ce175 : in std_logic; q175 : out std_logic_vector(dwidth-1 downto 0); addr176 : in std_logic_vector(awidth-1 downto 0); ce176 : in std_logic; q176 : out std_logic_vector(dwidth-1 downto 0); addr177 : in std_logic_vector(awidth-1 downto 0); ce177 : in std_logic; q177 : out std_logic_vector(dwidth-1 downto 0); addr178 : in std_logic_vector(awidth-1 downto 0); ce178 : in std_logic; q178 : out std_logic_vector(dwidth-1 downto 0); addr179 : in std_logic_vector(awidth-1 downto 0); ce179 : in std_logic; q179 : out std_logic_vector(dwidth-1 downto 0); addr180 : in std_logic_vector(awidth-1 downto 0); ce180 : in std_logic; q180 : out std_logic_vector(dwidth-1 downto 0); addr181 : in std_logic_vector(awidth-1 downto 0); ce181 : in std_logic; q181 : out std_logic_vector(dwidth-1 downto 0); addr182 : in std_logic_vector(awidth-1 downto 0); ce182 : in std_logic; q182 : out std_logic_vector(dwidth-1 downto 0); addr183 : in std_logic_vector(awidth-1 downto 0); ce183 : in std_logic; q183 : out std_logic_vector(dwidth-1 downto 0); addr184 : in std_logic_vector(awidth-1 downto 0); ce184 : in std_logic; q184 : out std_logic_vector(dwidth-1 downto 0); addr185 : in std_logic_vector(awidth-1 downto 0); ce185 : in std_logic; q185 : out std_logic_vector(dwidth-1 downto 0); addr186 : in std_logic_vector(awidth-1 downto 0); ce186 : in std_logic; q186 : out std_logic_vector(dwidth-1 downto 0); addr187 : in std_logic_vector(awidth-1 downto 0); ce187 : in std_logic; q187 : out std_logic_vector(dwidth-1 downto 0); addr188 : in std_logic_vector(awidth-1 downto 0); ce188 : in std_logic; q188 : out std_logic_vector(dwidth-1 downto 0); addr189 : in std_logic_vector(awidth-1 downto 0); ce189 : in std_logic; q189 : out std_logic_vector(dwidth-1 downto 0); addr190 : in std_logic_vector(awidth-1 downto 0); ce190 : in std_logic; q190 : out std_logic_vector(dwidth-1 downto 0); addr191 : in std_logic_vector(awidth-1 downto 0); ce191 : in std_logic; q191 : out std_logic_vector(dwidth-1 downto 0); addr192 : in std_logic_vector(awidth-1 downto 0); ce192 : in std_logic; q192 : out std_logic_vector(dwidth-1 downto 0); addr193 : in std_logic_vector(awidth-1 downto 0); ce193 : in std_logic; q193 : out std_logic_vector(dwidth-1 downto 0); addr194 : in std_logic_vector(awidth-1 downto 0); ce194 : in std_logic; q194 : out std_logic_vector(dwidth-1 downto 0); addr195 : in std_logic_vector(awidth-1 downto 0); ce195 : in std_logic; q195 : out std_logic_vector(dwidth-1 downto 0); addr196 : in std_logic_vector(awidth-1 downto 0); ce196 : in std_logic; q196 : out std_logic_vector(dwidth-1 downto 0); addr197 : in std_logic_vector(awidth-1 downto 0); ce197 : in std_logic; q197 : out std_logic_vector(dwidth-1 downto 0); addr198 : in std_logic_vector(awidth-1 downto 0); ce198 : in std_logic; q198 : out std_logic_vector(dwidth-1 downto 0); addr199 : in std_logic_vector(awidth-1 downto 0); ce199 : in std_logic; q199 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of aestest_sboxes_rom is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); signal addr2_tmp : std_logic_vector(awidth-1 downto 0); signal addr3_tmp : std_logic_vector(awidth-1 downto 0); signal addr4_tmp : std_logic_vector(awidth-1 downto 0); signal addr5_tmp : std_logic_vector(awidth-1 downto 0); signal addr6_tmp : std_logic_vector(awidth-1 downto 0); signal addr7_tmp : std_logic_vector(awidth-1 downto 0); signal addr8_tmp : std_logic_vector(awidth-1 downto 0); signal addr9_tmp : std_logic_vector(awidth-1 downto 0); signal addr10_tmp : std_logic_vector(awidth-1 downto 0); signal addr11_tmp : std_logic_vector(awidth-1 downto 0); signal addr12_tmp : std_logic_vector(awidth-1 downto 0); signal addr13_tmp : std_logic_vector(awidth-1 downto 0); signal addr14_tmp : std_logic_vector(awidth-1 downto 0); signal addr15_tmp : std_logic_vector(awidth-1 downto 0); signal addr16_tmp : std_logic_vector(awidth-1 downto 0); signal addr17_tmp : std_logic_vector(awidth-1 downto 0); signal addr18_tmp : std_logic_vector(awidth-1 downto 0); signal addr19_tmp : std_logic_vector(awidth-1 downto 0); signal addr20_tmp : std_logic_vector(awidth-1 downto 0); signal addr21_tmp : std_logic_vector(awidth-1 downto 0); signal addr22_tmp : std_logic_vector(awidth-1 downto 0); signal addr23_tmp : std_logic_vector(awidth-1 downto 0); signal addr24_tmp : std_logic_vector(awidth-1 downto 0); signal addr25_tmp : std_logic_vector(awidth-1 downto 0); signal addr26_tmp : std_logic_vector(awidth-1 downto 0); signal addr27_tmp : std_logic_vector(awidth-1 downto 0); signal addr28_tmp : std_logic_vector(awidth-1 downto 0); signal addr29_tmp : std_logic_vector(awidth-1 downto 0); signal addr30_tmp : std_logic_vector(awidth-1 downto 0); signal addr31_tmp : std_logic_vector(awidth-1 downto 0); signal addr32_tmp : std_logic_vector(awidth-1 downto 0); signal addr33_tmp : std_logic_vector(awidth-1 downto 0); signal addr34_tmp : std_logic_vector(awidth-1 downto 0); signal addr35_tmp : std_logic_vector(awidth-1 downto 0); signal addr36_tmp : std_logic_vector(awidth-1 downto 0); signal addr37_tmp : std_logic_vector(awidth-1 downto 0); signal addr38_tmp : std_logic_vector(awidth-1 downto 0); signal addr39_tmp : std_logic_vector(awidth-1 downto 0); signal addr40_tmp : std_logic_vector(awidth-1 downto 0); signal addr41_tmp : std_logic_vector(awidth-1 downto 0); signal addr42_tmp : std_logic_vector(awidth-1 downto 0); signal addr43_tmp : std_logic_vector(awidth-1 downto 0); signal addr44_tmp : std_logic_vector(awidth-1 downto 0); signal addr45_tmp : std_logic_vector(awidth-1 downto 0); signal addr46_tmp : std_logic_vector(awidth-1 downto 0); signal addr47_tmp : std_logic_vector(awidth-1 downto 0); signal addr48_tmp : std_logic_vector(awidth-1 downto 0); signal addr49_tmp : std_logic_vector(awidth-1 downto 0); signal addr50_tmp : std_logic_vector(awidth-1 downto 0); signal addr51_tmp : std_logic_vector(awidth-1 downto 0); signal addr52_tmp : std_logic_vector(awidth-1 downto 0); signal addr53_tmp : std_logic_vector(awidth-1 downto 0); signal addr54_tmp : std_logic_vector(awidth-1 downto 0); signal addr55_tmp : std_logic_vector(awidth-1 downto 0); signal addr56_tmp : std_logic_vector(awidth-1 downto 0); signal addr57_tmp : std_logic_vector(awidth-1 downto 0); signal addr58_tmp : std_logic_vector(awidth-1 downto 0); signal addr59_tmp : std_logic_vector(awidth-1 downto 0); signal addr60_tmp : std_logic_vector(awidth-1 downto 0); signal addr61_tmp : std_logic_vector(awidth-1 downto 0); signal addr62_tmp : std_logic_vector(awidth-1 downto 0); signal addr63_tmp : std_logic_vector(awidth-1 downto 0); signal addr64_tmp : std_logic_vector(awidth-1 downto 0); signal addr65_tmp : std_logic_vector(awidth-1 downto 0); signal addr66_tmp : std_logic_vector(awidth-1 downto 0); signal addr67_tmp : std_logic_vector(awidth-1 downto 0); signal addr68_tmp : std_logic_vector(awidth-1 downto 0); signal addr69_tmp : std_logic_vector(awidth-1 downto 0); signal addr70_tmp : std_logic_vector(awidth-1 downto 0); signal addr71_tmp : std_logic_vector(awidth-1 downto 0); signal addr72_tmp : std_logic_vector(awidth-1 downto 0); signal addr73_tmp : std_logic_vector(awidth-1 downto 0); signal addr74_tmp : std_logic_vector(awidth-1 downto 0); signal addr75_tmp : std_logic_vector(awidth-1 downto 0); signal addr76_tmp : std_logic_vector(awidth-1 downto 0); signal addr77_tmp : std_logic_vector(awidth-1 downto 0); signal addr78_tmp : std_logic_vector(awidth-1 downto 0); signal addr79_tmp : std_logic_vector(awidth-1 downto 0); signal addr80_tmp : std_logic_vector(awidth-1 downto 0); signal addr81_tmp : std_logic_vector(awidth-1 downto 0); signal addr82_tmp : std_logic_vector(awidth-1 downto 0); signal addr83_tmp : std_logic_vector(awidth-1 downto 0); signal addr84_tmp : std_logic_vector(awidth-1 downto 0); signal addr85_tmp : std_logic_vector(awidth-1 downto 0); signal addr86_tmp : std_logic_vector(awidth-1 downto 0); signal addr87_tmp : std_logic_vector(awidth-1 downto 0); signal addr88_tmp : std_logic_vector(awidth-1 downto 0); signal addr89_tmp : std_logic_vector(awidth-1 downto 0); signal addr90_tmp : std_logic_vector(awidth-1 downto 0); signal addr91_tmp : std_logic_vector(awidth-1 downto 0); signal addr92_tmp : std_logic_vector(awidth-1 downto 0); signal addr93_tmp : std_logic_vector(awidth-1 downto 0); signal addr94_tmp : std_logic_vector(awidth-1 downto 0); signal addr95_tmp : std_logic_vector(awidth-1 downto 0); signal addr96_tmp : std_logic_vector(awidth-1 downto 0); signal addr97_tmp : std_logic_vector(awidth-1 downto 0); signal addr98_tmp : std_logic_vector(awidth-1 downto 0); signal addr99_tmp : std_logic_vector(awidth-1 downto 0); signal addr100_tmp : std_logic_vector(awidth-1 downto 0); signal addr101_tmp : std_logic_vector(awidth-1 downto 0); signal addr102_tmp : std_logic_vector(awidth-1 downto 0); signal addr103_tmp : std_logic_vector(awidth-1 downto 0); signal addr104_tmp : std_logic_vector(awidth-1 downto 0); signal addr105_tmp : std_logic_vector(awidth-1 downto 0); signal addr106_tmp : std_logic_vector(awidth-1 downto 0); signal addr107_tmp : std_logic_vector(awidth-1 downto 0); signal addr108_tmp : std_logic_vector(awidth-1 downto 0); signal addr109_tmp : std_logic_vector(awidth-1 downto 0); signal addr110_tmp : std_logic_vector(awidth-1 downto 0); signal addr111_tmp : std_logic_vector(awidth-1 downto 0); signal addr112_tmp : std_logic_vector(awidth-1 downto 0); signal addr113_tmp : std_logic_vector(awidth-1 downto 0); signal addr114_tmp : std_logic_vector(awidth-1 downto 0); signal addr115_tmp : std_logic_vector(awidth-1 downto 0); signal addr116_tmp : std_logic_vector(awidth-1 downto 0); signal addr117_tmp : std_logic_vector(awidth-1 downto 0); signal addr118_tmp : std_logic_vector(awidth-1 downto 0); signal addr119_tmp : std_logic_vector(awidth-1 downto 0); signal addr120_tmp : std_logic_vector(awidth-1 downto 0); signal addr121_tmp : std_logic_vector(awidth-1 downto 0); signal addr122_tmp : std_logic_vector(awidth-1 downto 0); signal addr123_tmp : std_logic_vector(awidth-1 downto 0); signal addr124_tmp : std_logic_vector(awidth-1 downto 0); signal addr125_tmp : std_logic_vector(awidth-1 downto 0); signal addr126_tmp : std_logic_vector(awidth-1 downto 0); signal addr127_tmp : std_logic_vector(awidth-1 downto 0); signal addr128_tmp : std_logic_vector(awidth-1 downto 0); signal addr129_tmp : std_logic_vector(awidth-1 downto 0); signal addr130_tmp : std_logic_vector(awidth-1 downto 0); signal addr131_tmp : std_logic_vector(awidth-1 downto 0); signal addr132_tmp : std_logic_vector(awidth-1 downto 0); signal addr133_tmp : std_logic_vector(awidth-1 downto 0); signal addr134_tmp : std_logic_vector(awidth-1 downto 0); signal addr135_tmp : std_logic_vector(awidth-1 downto 0); signal addr136_tmp : std_logic_vector(awidth-1 downto 0); signal addr137_tmp : std_logic_vector(awidth-1 downto 0); signal addr138_tmp : std_logic_vector(awidth-1 downto 0); signal addr139_tmp : std_logic_vector(awidth-1 downto 0); signal addr140_tmp : std_logic_vector(awidth-1 downto 0); signal addr141_tmp : std_logic_vector(awidth-1 downto 0); signal addr142_tmp : std_logic_vector(awidth-1 downto 0); signal addr143_tmp : std_logic_vector(awidth-1 downto 0); signal addr144_tmp : std_logic_vector(awidth-1 downto 0); signal addr145_tmp : std_logic_vector(awidth-1 downto 0); signal addr146_tmp : std_logic_vector(awidth-1 downto 0); signal addr147_tmp : std_logic_vector(awidth-1 downto 0); signal addr148_tmp : std_logic_vector(awidth-1 downto 0); signal addr149_tmp : std_logic_vector(awidth-1 downto 0); signal addr150_tmp : std_logic_vector(awidth-1 downto 0); signal addr151_tmp : std_logic_vector(awidth-1 downto 0); signal addr152_tmp : std_logic_vector(awidth-1 downto 0); signal addr153_tmp : std_logic_vector(awidth-1 downto 0); signal addr154_tmp : std_logic_vector(awidth-1 downto 0); signal addr155_tmp : std_logic_vector(awidth-1 downto 0); signal addr156_tmp : std_logic_vector(awidth-1 downto 0); signal addr157_tmp : std_logic_vector(awidth-1 downto 0); signal addr158_tmp : std_logic_vector(awidth-1 downto 0); signal addr159_tmp : std_logic_vector(awidth-1 downto 0); signal addr160_tmp : std_logic_vector(awidth-1 downto 0); signal addr161_tmp : std_logic_vector(awidth-1 downto 0); signal addr162_tmp : std_logic_vector(awidth-1 downto 0); signal addr163_tmp : std_logic_vector(awidth-1 downto 0); signal addr164_tmp : std_logic_vector(awidth-1 downto 0); signal addr165_tmp : std_logic_vector(awidth-1 downto 0); signal addr166_tmp : std_logic_vector(awidth-1 downto 0); signal addr167_tmp : std_logic_vector(awidth-1 downto 0); signal addr168_tmp : std_logic_vector(awidth-1 downto 0); signal addr169_tmp : std_logic_vector(awidth-1 downto 0); signal addr170_tmp : std_logic_vector(awidth-1 downto 0); signal addr171_tmp : std_logic_vector(awidth-1 downto 0); signal addr172_tmp : std_logic_vector(awidth-1 downto 0); signal addr173_tmp : std_logic_vector(awidth-1 downto 0); signal addr174_tmp : std_logic_vector(awidth-1 downto 0); signal addr175_tmp : std_logic_vector(awidth-1 downto 0); signal addr176_tmp : std_logic_vector(awidth-1 downto 0); signal addr177_tmp : std_logic_vector(awidth-1 downto 0); signal addr178_tmp : std_logic_vector(awidth-1 downto 0); signal addr179_tmp : std_logic_vector(awidth-1 downto 0); signal addr180_tmp : std_logic_vector(awidth-1 downto 0); signal addr181_tmp : std_logic_vector(awidth-1 downto 0); signal addr182_tmp : std_logic_vector(awidth-1 downto 0); signal addr183_tmp : std_logic_vector(awidth-1 downto 0); signal addr184_tmp : std_logic_vector(awidth-1 downto 0); signal addr185_tmp : std_logic_vector(awidth-1 downto 0); signal addr186_tmp : std_logic_vector(awidth-1 downto 0); signal addr187_tmp : std_logic_vector(awidth-1 downto 0); signal addr188_tmp : std_logic_vector(awidth-1 downto 0); signal addr189_tmp : std_logic_vector(awidth-1 downto 0); signal addr190_tmp : std_logic_vector(awidth-1 downto 0); signal addr191_tmp : std_logic_vector(awidth-1 downto 0); signal addr192_tmp : std_logic_vector(awidth-1 downto 0); signal addr193_tmp : std_logic_vector(awidth-1 downto 0); signal addr194_tmp : std_logic_vector(awidth-1 downto 0); signal addr195_tmp : std_logic_vector(awidth-1 downto 0); signal addr196_tmp : std_logic_vector(awidth-1 downto 0); signal addr197_tmp : std_logic_vector(awidth-1 downto 0); signal addr198_tmp : std_logic_vector(awidth-1 downto 0); signal addr199_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); signal mem0 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem1 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem2 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem3 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem4 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem5 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem6 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem7 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem8 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem9 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem10 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem11 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem12 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem13 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem14 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem15 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem16 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem17 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem18 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem19 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem20 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem21 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem22 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem23 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem24 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem25 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem26 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem27 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem28 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem29 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem30 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem31 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem32 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem33 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem34 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem35 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem36 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem37 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem38 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem39 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem40 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem41 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem42 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem43 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem44 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem45 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem46 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem47 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem48 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem49 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem50 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem51 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem52 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem53 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem54 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem55 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem56 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem57 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem58 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem59 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem60 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem61 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem62 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem63 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem64 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem65 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem66 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem67 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem68 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem69 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem70 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem71 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem72 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem73 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem74 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem75 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem76 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem77 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem78 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem79 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem80 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem81 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem82 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem83 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem84 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem85 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem86 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem87 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem88 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem89 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem90 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem91 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem92 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem93 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem94 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem95 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem96 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem97 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem98 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); signal mem99 : mem_array := ( 0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011", 4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101", 8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011", 12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110", 16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101", 20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000", 24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111", 28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000", 32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110", 36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100", 40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001", 44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101", 48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011", 52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010", 56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010", 60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101", 64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010", 68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000", 72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011", 76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100", 80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101", 84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011", 88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001", 92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111", 96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011", 100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101", 104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111", 108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000", 112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111", 116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101", 120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001", 124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010", 128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100", 132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111", 136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101", 140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011", 144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100", 148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000", 152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100", 156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011", 160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010", 164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100", 168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010", 172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001", 176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101", 180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001", 184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010", 188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000", 192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110", 196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110", 200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111", 204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010", 208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110", 212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110", 216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001", 220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110", 224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001", 228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100", 232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001", 236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111", 240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101", 244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000", 248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111", 252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" ); attribute syn_rom_style : string; attribute syn_rom_style of mem0 : signal is "block_rom"; attribute syn_rom_style of mem1 : signal is "block_rom"; attribute syn_rom_style of mem2 : signal is "block_rom"; attribute syn_rom_style of mem3 : signal is "block_rom"; attribute syn_rom_style of mem4 : signal is "block_rom"; attribute syn_rom_style of mem5 : signal is "block_rom"; attribute syn_rom_style of mem6 : signal is "block_rom"; attribute syn_rom_style of mem7 : signal is "block_rom"; attribute syn_rom_style of mem8 : signal is "block_rom"; attribute syn_rom_style of mem9 : signal is "block_rom"; attribute syn_rom_style of mem10 : signal is "block_rom"; attribute syn_rom_style of mem11 : signal is "block_rom"; attribute syn_rom_style of mem12 : signal is "block_rom"; attribute syn_rom_style of mem13 : signal is "block_rom"; attribute syn_rom_style of mem14 : signal is "block_rom"; attribute syn_rom_style of mem15 : signal is "block_rom"; attribute syn_rom_style of mem16 : signal is "block_rom"; attribute syn_rom_style of mem17 : signal is "block_rom"; attribute syn_rom_style of mem18 : signal is "block_rom"; attribute syn_rom_style of mem19 : signal is "block_rom"; attribute syn_rom_style of mem20 : signal is "block_rom"; attribute syn_rom_style of mem21 : signal is "block_rom"; attribute syn_rom_style of mem22 : signal is "block_rom"; attribute syn_rom_style of mem23 : signal is "block_rom"; attribute syn_rom_style of mem24 : signal is "block_rom"; attribute syn_rom_style of mem25 : signal is "block_rom"; attribute syn_rom_style of mem26 : signal is "block_rom"; attribute syn_rom_style of mem27 : signal is "block_rom"; attribute syn_rom_style of mem28 : signal is "block_rom"; attribute syn_rom_style of mem29 : signal is "block_rom"; attribute syn_rom_style of mem30 : signal is "block_rom"; attribute syn_rom_style of mem31 : signal is "block_rom"; attribute syn_rom_style of mem32 : signal is "block_rom"; attribute syn_rom_style of mem33 : signal is "block_rom"; attribute syn_rom_style of mem34 : signal is "block_rom"; attribute syn_rom_style of mem35 : signal is "block_rom"; attribute syn_rom_style of mem36 : signal is "block_rom"; attribute syn_rom_style of mem37 : signal is "block_rom"; attribute syn_rom_style of mem38 : signal is "block_rom"; attribute syn_rom_style of mem39 : signal is "block_rom"; attribute syn_rom_style of mem40 : signal is "block_rom"; attribute syn_rom_style of mem41 : signal is "block_rom"; attribute syn_rom_style of mem42 : signal is "block_rom"; attribute syn_rom_style of mem43 : signal is "block_rom"; attribute syn_rom_style of mem44 : signal is "block_rom"; attribute syn_rom_style of mem45 : signal is "block_rom"; attribute syn_rom_style of mem46 : signal is "block_rom"; attribute syn_rom_style of mem47 : signal is "block_rom"; attribute syn_rom_style of mem48 : signal is "block_rom"; attribute syn_rom_style of mem49 : signal is "block_rom"; attribute syn_rom_style of mem50 : signal is "block_rom"; attribute syn_rom_style of mem51 : signal is "block_rom"; attribute syn_rom_style of mem52 : signal is "block_rom"; attribute syn_rom_style of mem53 : signal is "block_rom"; attribute syn_rom_style of mem54 : signal is "block_rom"; attribute syn_rom_style of mem55 : signal is "block_rom"; attribute syn_rom_style of mem56 : signal is "block_rom"; attribute syn_rom_style of mem57 : signal is "block_rom"; attribute syn_rom_style of mem58 : signal is "block_rom"; attribute syn_rom_style of mem59 : signal is "block_rom"; attribute syn_rom_style of mem60 : signal is "block_rom"; attribute syn_rom_style of mem61 : signal is "block_rom"; attribute syn_rom_style of mem62 : signal is "block_rom"; attribute syn_rom_style of mem63 : signal is "block_rom"; attribute syn_rom_style of mem64 : signal is "block_rom"; attribute syn_rom_style of mem65 : signal is "block_rom"; attribute syn_rom_style of mem66 : signal is "block_rom"; attribute syn_rom_style of mem67 : signal is "block_rom"; attribute syn_rom_style of mem68 : signal is "block_rom"; attribute syn_rom_style of mem69 : signal is "block_rom"; attribute syn_rom_style of mem70 : signal is "block_rom"; attribute syn_rom_style of mem71 : signal is "block_rom"; attribute syn_rom_style of mem72 : signal is "block_rom"; attribute syn_rom_style of mem73 : signal is "block_rom"; attribute syn_rom_style of mem74 : signal is "block_rom"; attribute syn_rom_style of mem75 : signal is "block_rom"; attribute syn_rom_style of mem76 : signal is "block_rom"; attribute syn_rom_style of mem77 : signal is "block_rom"; attribute syn_rom_style of mem78 : signal is "block_rom"; attribute syn_rom_style of mem79 : signal is "block_rom"; attribute syn_rom_style of mem80 : signal is "block_rom"; attribute syn_rom_style of mem81 : signal is "block_rom"; attribute syn_rom_style of mem82 : signal is "block_rom"; attribute syn_rom_style of mem83 : signal is "block_rom"; attribute syn_rom_style of mem84 : signal is "block_rom"; attribute syn_rom_style of mem85 : signal is "block_rom"; attribute syn_rom_style of mem86 : signal is "block_rom"; attribute syn_rom_style of mem87 : signal is "block_rom"; attribute syn_rom_style of mem88 : signal is "block_rom"; attribute syn_rom_style of mem89 : signal is "block_rom"; attribute syn_rom_style of mem90 : signal is "block_rom"; attribute syn_rom_style of mem91 : signal is "block_rom"; attribute syn_rom_style of mem92 : signal is "block_rom"; attribute syn_rom_style of mem93 : signal is "block_rom"; attribute syn_rom_style of mem94 : signal is "block_rom"; attribute syn_rom_style of mem95 : signal is "block_rom"; attribute syn_rom_style of mem96 : signal is "block_rom"; attribute syn_rom_style of mem97 : signal is "block_rom"; attribute syn_rom_style of mem98 : signal is "block_rom"; attribute syn_rom_style of mem99 : signal is "block_rom"; attribute ROM_STYLE : string; attribute ROM_STYLE of mem0 : signal is "block"; attribute ROM_STYLE of mem1 : signal is "block"; attribute ROM_STYLE of mem2 : signal is "block"; attribute ROM_STYLE of mem3 : signal is "block"; attribute ROM_STYLE of mem4 : signal is "block"; attribute ROM_STYLE of mem5 : signal is "block"; attribute ROM_STYLE of mem6 : signal is "block"; attribute ROM_STYLE of mem7 : signal is "block"; attribute ROM_STYLE of mem8 : signal is "block"; attribute ROM_STYLE of mem9 : signal is "block"; attribute ROM_STYLE of mem10 : signal is "block"; attribute ROM_STYLE of mem11 : signal is "block"; attribute ROM_STYLE of mem12 : signal is "block"; attribute ROM_STYLE of mem13 : signal is "block"; attribute ROM_STYLE of mem14 : signal is "block"; attribute ROM_STYLE of mem15 : signal is "block"; attribute ROM_STYLE of mem16 : signal is "block"; attribute ROM_STYLE of mem17 : signal is "block"; attribute ROM_STYLE of mem18 : signal is "block"; attribute ROM_STYLE of mem19 : signal is "block"; attribute ROM_STYLE of mem20 : signal is "block"; attribute ROM_STYLE of mem21 : signal is "block"; attribute ROM_STYLE of mem22 : signal is "block"; attribute ROM_STYLE of mem23 : signal is "block"; attribute ROM_STYLE of mem24 : signal is "block"; attribute ROM_STYLE of mem25 : signal is "block"; attribute ROM_STYLE of mem26 : signal is "block"; attribute ROM_STYLE of mem27 : signal is "block"; attribute ROM_STYLE of mem28 : signal is "block"; attribute ROM_STYLE of mem29 : signal is "block"; attribute ROM_STYLE of mem30 : signal is "block"; attribute ROM_STYLE of mem31 : signal is "block"; attribute ROM_STYLE of mem32 : signal is "block"; attribute ROM_STYLE of mem33 : signal is "block"; attribute ROM_STYLE of mem34 : signal is "block"; attribute ROM_STYLE of mem35 : signal is "block"; attribute ROM_STYLE of mem36 : signal is "block"; attribute ROM_STYLE of mem37 : signal is "block"; attribute ROM_STYLE of mem38 : signal is "block"; attribute ROM_STYLE of mem39 : signal is "block"; attribute ROM_STYLE of mem40 : signal is "block"; attribute ROM_STYLE of mem41 : signal is "block"; attribute ROM_STYLE of mem42 : signal is "block"; attribute ROM_STYLE of mem43 : signal is "block"; attribute ROM_STYLE of mem44 : signal is "block"; attribute ROM_STYLE of mem45 : signal is "block"; attribute ROM_STYLE of mem46 : signal is "block"; attribute ROM_STYLE of mem47 : signal is "block"; attribute ROM_STYLE of mem48 : signal is "block"; attribute ROM_STYLE of mem49 : signal is "block"; attribute ROM_STYLE of mem50 : signal is "block"; attribute ROM_STYLE of mem51 : signal is "block"; attribute ROM_STYLE of mem52 : signal is "block"; attribute ROM_STYLE of mem53 : signal is "block"; attribute ROM_STYLE of mem54 : signal is "block"; attribute ROM_STYLE of mem55 : signal is "block"; attribute ROM_STYLE of mem56 : signal is "block"; attribute ROM_STYLE of mem57 : signal is "block"; attribute ROM_STYLE of mem58 : signal is "block"; attribute ROM_STYLE of mem59 : signal is "block"; attribute ROM_STYLE of mem60 : signal is "block"; attribute ROM_STYLE of mem61 : signal is "block"; attribute ROM_STYLE of mem62 : signal is "block"; attribute ROM_STYLE of mem63 : signal is "block"; attribute ROM_STYLE of mem64 : signal is "block"; attribute ROM_STYLE of mem65 : signal is "block"; attribute ROM_STYLE of mem66 : signal is "block"; attribute ROM_STYLE of mem67 : signal is "block"; attribute ROM_STYLE of mem68 : signal is "block"; attribute ROM_STYLE of mem69 : signal is "block"; attribute ROM_STYLE of mem70 : signal is "block"; attribute ROM_STYLE of mem71 : signal is "block"; attribute ROM_STYLE of mem72 : signal is "block"; attribute ROM_STYLE of mem73 : signal is "block"; attribute ROM_STYLE of mem74 : signal is "block"; attribute ROM_STYLE of mem75 : signal is "block"; attribute ROM_STYLE of mem76 : signal is "block"; attribute ROM_STYLE of mem77 : signal is "block"; attribute ROM_STYLE of mem78 : signal is "block"; attribute ROM_STYLE of mem79 : signal is "block"; attribute ROM_STYLE of mem80 : signal is "block"; attribute ROM_STYLE of mem81 : signal is "block"; attribute ROM_STYLE of mem82 : signal is "block"; attribute ROM_STYLE of mem83 : signal is "block"; attribute ROM_STYLE of mem84 : signal is "block"; attribute ROM_STYLE of mem85 : signal is "block"; attribute ROM_STYLE of mem86 : signal is "block"; attribute ROM_STYLE of mem87 : signal is "block"; attribute ROM_STYLE of mem88 : signal is "block"; attribute ROM_STYLE of mem89 : signal is "block"; attribute ROM_STYLE of mem90 : signal is "block"; attribute ROM_STYLE of mem91 : signal is "block"; attribute ROM_STYLE of mem92 : signal is "block"; attribute ROM_STYLE of mem93 : signal is "block"; attribute ROM_STYLE of mem94 : signal is "block"; attribute ROM_STYLE of mem95 : signal is "block"; attribute ROM_STYLE of mem96 : signal is "block"; attribute ROM_STYLE of mem97 : signal is "block"; attribute ROM_STYLE of mem98 : signal is "block"; attribute ROM_STYLE of mem99 : signal is "block"; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; memory_access_guard_2: process (addr2) begin addr2_tmp <= addr2; --synthesis translate_off if (CONV_INTEGER(addr2) > mem_size-1) then addr2_tmp <= (others => '0'); else addr2_tmp <= addr2; end if; --synthesis translate_on end process; memory_access_guard_3: process (addr3) begin addr3_tmp <= addr3; --synthesis translate_off if (CONV_INTEGER(addr3) > mem_size-1) then addr3_tmp <= (others => '0'); else addr3_tmp <= addr3; end if; --synthesis translate_on end process; memory_access_guard_4: process (addr4) begin addr4_tmp <= addr4; --synthesis translate_off if (CONV_INTEGER(addr4) > mem_size-1) then addr4_tmp <= (others => '0'); else addr4_tmp <= addr4; end if; --synthesis translate_on end process; memory_access_guard_5: process (addr5) begin addr5_tmp <= addr5; --synthesis translate_off if (CONV_INTEGER(addr5) > mem_size-1) then addr5_tmp <= (others => '0'); else addr5_tmp <= addr5; end if; --synthesis translate_on end process; memory_access_guard_6: process (addr6) begin addr6_tmp <= addr6; --synthesis translate_off if (CONV_INTEGER(addr6) > mem_size-1) then addr6_tmp <= (others => '0'); else addr6_tmp <= addr6; end if; --synthesis translate_on end process; memory_access_guard_7: process (addr7) begin addr7_tmp <= addr7; --synthesis translate_off if (CONV_INTEGER(addr7) > mem_size-1) then addr7_tmp <= (others => '0'); else addr7_tmp <= addr7; end if; --synthesis translate_on end process; memory_access_guard_8: process (addr8) begin addr8_tmp <= addr8; --synthesis translate_off if (CONV_INTEGER(addr8) > mem_size-1) then addr8_tmp <= (others => '0'); else addr8_tmp <= addr8; end if; --synthesis translate_on end process; memory_access_guard_9: process (addr9) begin addr9_tmp <= addr9; --synthesis translate_off if (CONV_INTEGER(addr9) > mem_size-1) then addr9_tmp <= (others => '0'); else addr9_tmp <= addr9; end if; --synthesis translate_on end process; memory_access_guard_10: process (addr10) begin addr10_tmp <= addr10; --synthesis translate_off if (CONV_INTEGER(addr10) > mem_size-1) then addr10_tmp <= (others => '0'); else addr10_tmp <= addr10; end if; --synthesis translate_on end process; memory_access_guard_11: process (addr11) begin addr11_tmp <= addr11; --synthesis translate_off if (CONV_INTEGER(addr11) > mem_size-1) then addr11_tmp <= (others => '0'); else addr11_tmp <= addr11; end if; --synthesis translate_on end process; memory_access_guard_12: process (addr12) begin addr12_tmp <= addr12; --synthesis translate_off if (CONV_INTEGER(addr12) > mem_size-1) then addr12_tmp <= (others => '0'); else addr12_tmp <= addr12; end if; --synthesis translate_on end process; memory_access_guard_13: process (addr13) begin addr13_tmp <= addr13; --synthesis translate_off if (CONV_INTEGER(addr13) > mem_size-1) then addr13_tmp <= (others => '0'); else addr13_tmp <= addr13; end if; --synthesis translate_on end process; memory_access_guard_14: process (addr14) begin addr14_tmp <= addr14; --synthesis translate_off if (CONV_INTEGER(addr14) > mem_size-1) then addr14_tmp <= (others => '0'); else addr14_tmp <= addr14; end if; --synthesis translate_on end process; memory_access_guard_15: process (addr15) begin addr15_tmp <= addr15; --synthesis translate_off if (CONV_INTEGER(addr15) > mem_size-1) then addr15_tmp <= (others => '0'); else addr15_tmp <= addr15; end if; --synthesis translate_on end process; memory_access_guard_16: process (addr16) begin addr16_tmp <= addr16; --synthesis translate_off if (CONV_INTEGER(addr16) > mem_size-1) then addr16_tmp <= (others => '0'); else addr16_tmp <= addr16; end if; --synthesis translate_on end process; memory_access_guard_17: process (addr17) begin addr17_tmp <= addr17; --synthesis translate_off if (CONV_INTEGER(addr17) > mem_size-1) then addr17_tmp <= (others => '0'); else addr17_tmp <= addr17; end if; --synthesis translate_on end process; memory_access_guard_18: process (addr18) begin addr18_tmp <= addr18; --synthesis translate_off if (CONV_INTEGER(addr18) > mem_size-1) then addr18_tmp <= (others => '0'); else addr18_tmp <= addr18; end if; --synthesis translate_on end process; memory_access_guard_19: process (addr19) begin addr19_tmp <= addr19; --synthesis translate_off if (CONV_INTEGER(addr19) > mem_size-1) then addr19_tmp <= (others => '0'); else addr19_tmp <= addr19; end if; --synthesis translate_on end process; memory_access_guard_20: process (addr20) begin addr20_tmp <= addr20; --synthesis translate_off if (CONV_INTEGER(addr20) > mem_size-1) then addr20_tmp <= (others => '0'); else addr20_tmp <= addr20; end if; --synthesis translate_on end process; memory_access_guard_21: process (addr21) begin addr21_tmp <= addr21; --synthesis translate_off if (CONV_INTEGER(addr21) > mem_size-1) then addr21_tmp <= (others => '0'); else addr21_tmp <= addr21; end if; --synthesis translate_on end process; memory_access_guard_22: process (addr22) begin addr22_tmp <= addr22; --synthesis translate_off if (CONV_INTEGER(addr22) > mem_size-1) then addr22_tmp <= (others => '0'); else addr22_tmp <= addr22; end if; --synthesis translate_on end process; memory_access_guard_23: process (addr23) begin addr23_tmp <= addr23; --synthesis translate_off if (CONV_INTEGER(addr23) > mem_size-1) then addr23_tmp <= (others => '0'); else addr23_tmp <= addr23; end if; --synthesis translate_on end process; memory_access_guard_24: process (addr24) begin addr24_tmp <= addr24; --synthesis translate_off if (CONV_INTEGER(addr24) > mem_size-1) then addr24_tmp <= (others => '0'); else addr24_tmp <= addr24; end if; --synthesis translate_on end process; memory_access_guard_25: process (addr25) begin addr25_tmp <= addr25; --synthesis translate_off if (CONV_INTEGER(addr25) > mem_size-1) then addr25_tmp <= (others => '0'); else addr25_tmp <= addr25; end if; --synthesis translate_on end process; memory_access_guard_26: process (addr26) begin addr26_tmp <= addr26; --synthesis translate_off if (CONV_INTEGER(addr26) > mem_size-1) then addr26_tmp <= (others => '0'); else addr26_tmp <= addr26; end if; --synthesis translate_on end process; memory_access_guard_27: process (addr27) begin addr27_tmp <= addr27; --synthesis translate_off if (CONV_INTEGER(addr27) > mem_size-1) then addr27_tmp <= (others => '0'); else addr27_tmp <= addr27; end if; --synthesis translate_on end process; memory_access_guard_28: process (addr28) begin addr28_tmp <= addr28; --synthesis translate_off if (CONV_INTEGER(addr28) > mem_size-1) then addr28_tmp <= (others => '0'); else addr28_tmp <= addr28; end if; --synthesis translate_on end process; memory_access_guard_29: process (addr29) begin addr29_tmp <= addr29; --synthesis translate_off if (CONV_INTEGER(addr29) > mem_size-1) then addr29_tmp <= (others => '0'); else addr29_tmp <= addr29; end if; --synthesis translate_on end process; memory_access_guard_30: process (addr30) begin addr30_tmp <= addr30; --synthesis translate_off if (CONV_INTEGER(addr30) > mem_size-1) then addr30_tmp <= (others => '0'); else addr30_tmp <= addr30; end if; --synthesis translate_on end process; memory_access_guard_31: process (addr31) begin addr31_tmp <= addr31; --synthesis translate_off if (CONV_INTEGER(addr31) > mem_size-1) then addr31_tmp <= (others => '0'); else addr31_tmp <= addr31; end if; --synthesis translate_on end process; memory_access_guard_32: process (addr32) begin addr32_tmp <= addr32; --synthesis translate_off if (CONV_INTEGER(addr32) > mem_size-1) then addr32_tmp <= (others => '0'); else addr32_tmp <= addr32; end if; --synthesis translate_on end process; memory_access_guard_33: process (addr33) begin addr33_tmp <= addr33; --synthesis translate_off if (CONV_INTEGER(addr33) > mem_size-1) then addr33_tmp <= (others => '0'); else addr33_tmp <= addr33; end if; --synthesis translate_on end process; memory_access_guard_34: process (addr34) begin addr34_tmp <= addr34; --synthesis translate_off if (CONV_INTEGER(addr34) > mem_size-1) then addr34_tmp <= (others => '0'); else addr34_tmp <= addr34; end if; --synthesis translate_on end process; memory_access_guard_35: process (addr35) begin addr35_tmp <= addr35; --synthesis translate_off if (CONV_INTEGER(addr35) > mem_size-1) then addr35_tmp <= (others => '0'); else addr35_tmp <= addr35; end if; --synthesis translate_on end process; memory_access_guard_36: process (addr36) begin addr36_tmp <= addr36; --synthesis translate_off if (CONV_INTEGER(addr36) > mem_size-1) then addr36_tmp <= (others => '0'); else addr36_tmp <= addr36; end if; --synthesis translate_on end process; memory_access_guard_37: process (addr37) begin addr37_tmp <= addr37; --synthesis translate_off if (CONV_INTEGER(addr37) > mem_size-1) then addr37_tmp <= (others => '0'); else addr37_tmp <= addr37; end if; --synthesis translate_on end process; memory_access_guard_38: process (addr38) begin addr38_tmp <= addr38; --synthesis translate_off if (CONV_INTEGER(addr38) > mem_size-1) then addr38_tmp <= (others => '0'); else addr38_tmp <= addr38; end if; --synthesis translate_on end process; memory_access_guard_39: process (addr39) begin addr39_tmp <= addr39; --synthesis translate_off if (CONV_INTEGER(addr39) > mem_size-1) then addr39_tmp <= (others => '0'); else addr39_tmp <= addr39; end if; --synthesis translate_on end process; memory_access_guard_40: process (addr40) begin addr40_tmp <= addr40; --synthesis translate_off if (CONV_INTEGER(addr40) > mem_size-1) then addr40_tmp <= (others => '0'); else addr40_tmp <= addr40; end if; --synthesis translate_on end process; memory_access_guard_41: process (addr41) begin addr41_tmp <= addr41; --synthesis translate_off if (CONV_INTEGER(addr41) > mem_size-1) then addr41_tmp <= (others => '0'); else addr41_tmp <= addr41; end if; --synthesis translate_on end process; memory_access_guard_42: process (addr42) begin addr42_tmp <= addr42; --synthesis translate_off if (CONV_INTEGER(addr42) > mem_size-1) then addr42_tmp <= (others => '0'); else addr42_tmp <= addr42; end if; --synthesis translate_on end process; memory_access_guard_43: process (addr43) begin addr43_tmp <= addr43; --synthesis translate_off if (CONV_INTEGER(addr43) > mem_size-1) then addr43_tmp <= (others => '0'); else addr43_tmp <= addr43; end if; --synthesis translate_on end process; memory_access_guard_44: process (addr44) begin addr44_tmp <= addr44; --synthesis translate_off if (CONV_INTEGER(addr44) > mem_size-1) then addr44_tmp <= (others => '0'); else addr44_tmp <= addr44; end if; --synthesis translate_on end process; memory_access_guard_45: process (addr45) begin addr45_tmp <= addr45; --synthesis translate_off if (CONV_INTEGER(addr45) > mem_size-1) then addr45_tmp <= (others => '0'); else addr45_tmp <= addr45; end if; --synthesis translate_on end process; memory_access_guard_46: process (addr46) begin addr46_tmp <= addr46; --synthesis translate_off if (CONV_INTEGER(addr46) > mem_size-1) then addr46_tmp <= (others => '0'); else addr46_tmp <= addr46; end if; --synthesis translate_on end process; memory_access_guard_47: process (addr47) begin addr47_tmp <= addr47; --synthesis translate_off if (CONV_INTEGER(addr47) > mem_size-1) then addr47_tmp <= (others => '0'); else addr47_tmp <= addr47; end if; --synthesis translate_on end process; memory_access_guard_48: process (addr48) begin addr48_tmp <= addr48; --synthesis translate_off if (CONV_INTEGER(addr48) > mem_size-1) then addr48_tmp <= (others => '0'); else addr48_tmp <= addr48; end if; --synthesis translate_on end process; memory_access_guard_49: process (addr49) begin addr49_tmp <= addr49; --synthesis translate_off if (CONV_INTEGER(addr49) > mem_size-1) then addr49_tmp <= (others => '0'); else addr49_tmp <= addr49; end if; --synthesis translate_on end process; memory_access_guard_50: process (addr50) begin addr50_tmp <= addr50; --synthesis translate_off if (CONV_INTEGER(addr50) > mem_size-1) then addr50_tmp <= (others => '0'); else addr50_tmp <= addr50; end if; --synthesis translate_on end process; memory_access_guard_51: process (addr51) begin addr51_tmp <= addr51; --synthesis translate_off if (CONV_INTEGER(addr51) > mem_size-1) then addr51_tmp <= (others => '0'); else addr51_tmp <= addr51; end if; --synthesis translate_on end process; memory_access_guard_52: process (addr52) begin addr52_tmp <= addr52; --synthesis translate_off if (CONV_INTEGER(addr52) > mem_size-1) then addr52_tmp <= (others => '0'); else addr52_tmp <= addr52; end if; --synthesis translate_on end process; memory_access_guard_53: process (addr53) begin addr53_tmp <= addr53; --synthesis translate_off if (CONV_INTEGER(addr53) > mem_size-1) then addr53_tmp <= (others => '0'); else addr53_tmp <= addr53; end if; --synthesis translate_on end process; memory_access_guard_54: process (addr54) begin addr54_tmp <= addr54; --synthesis translate_off if (CONV_INTEGER(addr54) > mem_size-1) then addr54_tmp <= (others => '0'); else addr54_tmp <= addr54; end if; --synthesis translate_on end process; memory_access_guard_55: process (addr55) begin addr55_tmp <= addr55; --synthesis translate_off if (CONV_INTEGER(addr55) > mem_size-1) then addr55_tmp <= (others => '0'); else addr55_tmp <= addr55; end if; --synthesis translate_on end process; memory_access_guard_56: process (addr56) begin addr56_tmp <= addr56; --synthesis translate_off if (CONV_INTEGER(addr56) > mem_size-1) then addr56_tmp <= (others => '0'); else addr56_tmp <= addr56; end if; --synthesis translate_on end process; memory_access_guard_57: process (addr57) begin addr57_tmp <= addr57; --synthesis translate_off if (CONV_INTEGER(addr57) > mem_size-1) then addr57_tmp <= (others => '0'); else addr57_tmp <= addr57; end if; --synthesis translate_on end process; memory_access_guard_58: process (addr58) begin addr58_tmp <= addr58; --synthesis translate_off if (CONV_INTEGER(addr58) > mem_size-1) then addr58_tmp <= (others => '0'); else addr58_tmp <= addr58; end if; --synthesis translate_on end process; memory_access_guard_59: process (addr59) begin addr59_tmp <= addr59; --synthesis translate_off if (CONV_INTEGER(addr59) > mem_size-1) then addr59_tmp <= (others => '0'); else addr59_tmp <= addr59; end if; --synthesis translate_on end process; memory_access_guard_60: process (addr60) begin addr60_tmp <= addr60; --synthesis translate_off if (CONV_INTEGER(addr60) > mem_size-1) then addr60_tmp <= (others => '0'); else addr60_tmp <= addr60; end if; --synthesis translate_on end process; memory_access_guard_61: process (addr61) begin addr61_tmp <= addr61; --synthesis translate_off if (CONV_INTEGER(addr61) > mem_size-1) then addr61_tmp <= (others => '0'); else addr61_tmp <= addr61; end if; --synthesis translate_on end process; memory_access_guard_62: process (addr62) begin addr62_tmp <= addr62; --synthesis translate_off if (CONV_INTEGER(addr62) > mem_size-1) then addr62_tmp <= (others => '0'); else addr62_tmp <= addr62; end if; --synthesis translate_on end process; memory_access_guard_63: process (addr63) begin addr63_tmp <= addr63; --synthesis translate_off if (CONV_INTEGER(addr63) > mem_size-1) then addr63_tmp <= (others => '0'); else addr63_tmp <= addr63; end if; --synthesis translate_on end process; memory_access_guard_64: process (addr64) begin addr64_tmp <= addr64; --synthesis translate_off if (CONV_INTEGER(addr64) > mem_size-1) then addr64_tmp <= (others => '0'); else addr64_tmp <= addr64; end if; --synthesis translate_on end process; memory_access_guard_65: process (addr65) begin addr65_tmp <= addr65; --synthesis translate_off if (CONV_INTEGER(addr65) > mem_size-1) then addr65_tmp <= (others => '0'); else addr65_tmp <= addr65; end if; --synthesis translate_on end process; memory_access_guard_66: process (addr66) begin addr66_tmp <= addr66; --synthesis translate_off if (CONV_INTEGER(addr66) > mem_size-1) then addr66_tmp <= (others => '0'); else addr66_tmp <= addr66; end if; --synthesis translate_on end process; memory_access_guard_67: process (addr67) begin addr67_tmp <= addr67; --synthesis translate_off if (CONV_INTEGER(addr67) > mem_size-1) then addr67_tmp <= (others => '0'); else addr67_tmp <= addr67; end if; --synthesis translate_on end process; memory_access_guard_68: process (addr68) begin addr68_tmp <= addr68; --synthesis translate_off if (CONV_INTEGER(addr68) > mem_size-1) then addr68_tmp <= (others => '0'); else addr68_tmp <= addr68; end if; --synthesis translate_on end process; memory_access_guard_69: process (addr69) begin addr69_tmp <= addr69; --synthesis translate_off if (CONV_INTEGER(addr69) > mem_size-1) then addr69_tmp <= (others => '0'); else addr69_tmp <= addr69; end if; --synthesis translate_on end process; memory_access_guard_70: process (addr70) begin addr70_tmp <= addr70; --synthesis translate_off if (CONV_INTEGER(addr70) > mem_size-1) then addr70_tmp <= (others => '0'); else addr70_tmp <= addr70; end if; --synthesis translate_on end process; memory_access_guard_71: process (addr71) begin addr71_tmp <= addr71; --synthesis translate_off if (CONV_INTEGER(addr71) > mem_size-1) then addr71_tmp <= (others => '0'); else addr71_tmp <= addr71; end if; --synthesis translate_on end process; memory_access_guard_72: process (addr72) begin addr72_tmp <= addr72; --synthesis translate_off if (CONV_INTEGER(addr72) > mem_size-1) then addr72_tmp <= (others => '0'); else addr72_tmp <= addr72; end if; --synthesis translate_on end process; memory_access_guard_73: process (addr73) begin addr73_tmp <= addr73; --synthesis translate_off if (CONV_INTEGER(addr73) > mem_size-1) then addr73_tmp <= (others => '0'); else addr73_tmp <= addr73; end if; --synthesis translate_on end process; memory_access_guard_74: process (addr74) begin addr74_tmp <= addr74; --synthesis translate_off if (CONV_INTEGER(addr74) > mem_size-1) then addr74_tmp <= (others => '0'); else addr74_tmp <= addr74; end if; --synthesis translate_on end process; memory_access_guard_75: process (addr75) begin addr75_tmp <= addr75; --synthesis translate_off if (CONV_INTEGER(addr75) > mem_size-1) then addr75_tmp <= (others => '0'); else addr75_tmp <= addr75; end if; --synthesis translate_on end process; memory_access_guard_76: process (addr76) begin addr76_tmp <= addr76; --synthesis translate_off if (CONV_INTEGER(addr76) > mem_size-1) then addr76_tmp <= (others => '0'); else addr76_tmp <= addr76; end if; --synthesis translate_on end process; memory_access_guard_77: process (addr77) begin addr77_tmp <= addr77; --synthesis translate_off if (CONV_INTEGER(addr77) > mem_size-1) then addr77_tmp <= (others => '0'); else addr77_tmp <= addr77; end if; --synthesis translate_on end process; memory_access_guard_78: process (addr78) begin addr78_tmp <= addr78; --synthesis translate_off if (CONV_INTEGER(addr78) > mem_size-1) then addr78_tmp <= (others => '0'); else addr78_tmp <= addr78; end if; --synthesis translate_on end process; memory_access_guard_79: process (addr79) begin addr79_tmp <= addr79; --synthesis translate_off if (CONV_INTEGER(addr79) > mem_size-1) then addr79_tmp <= (others => '0'); else addr79_tmp <= addr79; end if; --synthesis translate_on end process; memory_access_guard_80: process (addr80) begin addr80_tmp <= addr80; --synthesis translate_off if (CONV_INTEGER(addr80) > mem_size-1) then addr80_tmp <= (others => '0'); else addr80_tmp <= addr80; end if; --synthesis translate_on end process; memory_access_guard_81: process (addr81) begin addr81_tmp <= addr81; --synthesis translate_off if (CONV_INTEGER(addr81) > mem_size-1) then addr81_tmp <= (others => '0'); else addr81_tmp <= addr81; end if; --synthesis translate_on end process; memory_access_guard_82: process (addr82) begin addr82_tmp <= addr82; --synthesis translate_off if (CONV_INTEGER(addr82) > mem_size-1) then addr82_tmp <= (others => '0'); else addr82_tmp <= addr82; end if; --synthesis translate_on end process; memory_access_guard_83: process (addr83) begin addr83_tmp <= addr83; --synthesis translate_off if (CONV_INTEGER(addr83) > mem_size-1) then addr83_tmp <= (others => '0'); else addr83_tmp <= addr83; end if; --synthesis translate_on end process; memory_access_guard_84: process (addr84) begin addr84_tmp <= addr84; --synthesis translate_off if (CONV_INTEGER(addr84) > mem_size-1) then addr84_tmp <= (others => '0'); else addr84_tmp <= addr84; end if; --synthesis translate_on end process; memory_access_guard_85: process (addr85) begin addr85_tmp <= addr85; --synthesis translate_off if (CONV_INTEGER(addr85) > mem_size-1) then addr85_tmp <= (others => '0'); else addr85_tmp <= addr85; end if; --synthesis translate_on end process; memory_access_guard_86: process (addr86) begin addr86_tmp <= addr86; --synthesis translate_off if (CONV_INTEGER(addr86) > mem_size-1) then addr86_tmp <= (others => '0'); else addr86_tmp <= addr86; end if; --synthesis translate_on end process; memory_access_guard_87: process (addr87) begin addr87_tmp <= addr87; --synthesis translate_off if (CONV_INTEGER(addr87) > mem_size-1) then addr87_tmp <= (others => '0'); else addr87_tmp <= addr87; end if; --synthesis translate_on end process; memory_access_guard_88: process (addr88) begin addr88_tmp <= addr88; --synthesis translate_off if (CONV_INTEGER(addr88) > mem_size-1) then addr88_tmp <= (others => '0'); else addr88_tmp <= addr88; end if; --synthesis translate_on end process; memory_access_guard_89: process (addr89) begin addr89_tmp <= addr89; --synthesis translate_off if (CONV_INTEGER(addr89) > mem_size-1) then addr89_tmp <= (others => '0'); else addr89_tmp <= addr89; end if; --synthesis translate_on end process; memory_access_guard_90: process (addr90) begin addr90_tmp <= addr90; --synthesis translate_off if (CONV_INTEGER(addr90) > mem_size-1) then addr90_tmp <= (others => '0'); else addr90_tmp <= addr90; end if; --synthesis translate_on end process; memory_access_guard_91: process (addr91) begin addr91_tmp <= addr91; --synthesis translate_off if (CONV_INTEGER(addr91) > mem_size-1) then addr91_tmp <= (others => '0'); else addr91_tmp <= addr91; end if; --synthesis translate_on end process; memory_access_guard_92: process (addr92) begin addr92_tmp <= addr92; --synthesis translate_off if (CONV_INTEGER(addr92) > mem_size-1) then addr92_tmp <= (others => '0'); else addr92_tmp <= addr92; end if; --synthesis translate_on end process; memory_access_guard_93: process (addr93) begin addr93_tmp <= addr93; --synthesis translate_off if (CONV_INTEGER(addr93) > mem_size-1) then addr93_tmp <= (others => '0'); else addr93_tmp <= addr93; end if; --synthesis translate_on end process; memory_access_guard_94: process (addr94) begin addr94_tmp <= addr94; --synthesis translate_off if (CONV_INTEGER(addr94) > mem_size-1) then addr94_tmp <= (others => '0'); else addr94_tmp <= addr94; end if; --synthesis translate_on end process; memory_access_guard_95: process (addr95) begin addr95_tmp <= addr95; --synthesis translate_off if (CONV_INTEGER(addr95) > mem_size-1) then addr95_tmp <= (others => '0'); else addr95_tmp <= addr95; end if; --synthesis translate_on end process; memory_access_guard_96: process (addr96) begin addr96_tmp <= addr96; --synthesis translate_off if (CONV_INTEGER(addr96) > mem_size-1) then addr96_tmp <= (others => '0'); else addr96_tmp <= addr96; end if; --synthesis translate_on end process; memory_access_guard_97: process (addr97) begin addr97_tmp <= addr97; --synthesis translate_off if (CONV_INTEGER(addr97) > mem_size-1) then addr97_tmp <= (others => '0'); else addr97_tmp <= addr97; end if; --synthesis translate_on end process; memory_access_guard_98: process (addr98) begin addr98_tmp <= addr98; --synthesis translate_off if (CONV_INTEGER(addr98) > mem_size-1) then addr98_tmp <= (others => '0'); else addr98_tmp <= addr98; end if; --synthesis translate_on end process; memory_access_guard_99: process (addr99) begin addr99_tmp <= addr99; --synthesis translate_off if (CONV_INTEGER(addr99) > mem_size-1) then addr99_tmp <= (others => '0'); else addr99_tmp <= addr99; end if; --synthesis translate_on end process; memory_access_guard_100: process (addr100) begin addr100_tmp <= addr100; --synthesis translate_off if (CONV_INTEGER(addr100) > mem_size-1) then addr100_tmp <= (others => '0'); else addr100_tmp <= addr100; end if; --synthesis translate_on end process; memory_access_guard_101: process (addr101) begin addr101_tmp <= addr101; --synthesis translate_off if (CONV_INTEGER(addr101) > mem_size-1) then addr101_tmp <= (others => '0'); else addr101_tmp <= addr101; end if; --synthesis translate_on end process; memory_access_guard_102: process (addr102) begin addr102_tmp <= addr102; --synthesis translate_off if (CONV_INTEGER(addr102) > mem_size-1) then addr102_tmp <= (others => '0'); else addr102_tmp <= addr102; end if; --synthesis translate_on end process; memory_access_guard_103: process (addr103) begin addr103_tmp <= addr103; --synthesis translate_off if (CONV_INTEGER(addr103) > mem_size-1) then addr103_tmp <= (others => '0'); else addr103_tmp <= addr103; end if; --synthesis translate_on end process; memory_access_guard_104: process (addr104) begin addr104_tmp <= addr104; --synthesis translate_off if (CONV_INTEGER(addr104) > mem_size-1) then addr104_tmp <= (others => '0'); else addr104_tmp <= addr104; end if; --synthesis translate_on end process; memory_access_guard_105: process (addr105) begin addr105_tmp <= addr105; --synthesis translate_off if (CONV_INTEGER(addr105) > mem_size-1) then addr105_tmp <= (others => '0'); else addr105_tmp <= addr105; end if; --synthesis translate_on end process; memory_access_guard_106: process (addr106) begin addr106_tmp <= addr106; --synthesis translate_off if (CONV_INTEGER(addr106) > mem_size-1) then addr106_tmp <= (others => '0'); else addr106_tmp <= addr106; end if; --synthesis translate_on end process; memory_access_guard_107: process (addr107) begin addr107_tmp <= addr107; --synthesis translate_off if (CONV_INTEGER(addr107) > mem_size-1) then addr107_tmp <= (others => '0'); else addr107_tmp <= addr107; end if; --synthesis translate_on end process; memory_access_guard_108: process (addr108) begin addr108_tmp <= addr108; --synthesis translate_off if (CONV_INTEGER(addr108) > mem_size-1) then addr108_tmp <= (others => '0'); else addr108_tmp <= addr108; end if; --synthesis translate_on end process; memory_access_guard_109: process (addr109) begin addr109_tmp <= addr109; --synthesis translate_off if (CONV_INTEGER(addr109) > mem_size-1) then addr109_tmp <= (others => '0'); else addr109_tmp <= addr109; end if; --synthesis translate_on end process; memory_access_guard_110: process (addr110) begin addr110_tmp <= addr110; --synthesis translate_off if (CONV_INTEGER(addr110) > mem_size-1) then addr110_tmp <= (others => '0'); else addr110_tmp <= addr110; end if; --synthesis translate_on end process; memory_access_guard_111: process (addr111) begin addr111_tmp <= addr111; --synthesis translate_off if (CONV_INTEGER(addr111) > mem_size-1) then addr111_tmp <= (others => '0'); else addr111_tmp <= addr111; end if; --synthesis translate_on end process; memory_access_guard_112: process (addr112) begin addr112_tmp <= addr112; --synthesis translate_off if (CONV_INTEGER(addr112) > mem_size-1) then addr112_tmp <= (others => '0'); else addr112_tmp <= addr112; end if; --synthesis translate_on end process; memory_access_guard_113: process (addr113) begin addr113_tmp <= addr113; --synthesis translate_off if (CONV_INTEGER(addr113) > mem_size-1) then addr113_tmp <= (others => '0'); else addr113_tmp <= addr113; end if; --synthesis translate_on end process; memory_access_guard_114: process (addr114) begin addr114_tmp <= addr114; --synthesis translate_off if (CONV_INTEGER(addr114) > mem_size-1) then addr114_tmp <= (others => '0'); else addr114_tmp <= addr114; end if; --synthesis translate_on end process; memory_access_guard_115: process (addr115) begin addr115_tmp <= addr115; --synthesis translate_off if (CONV_INTEGER(addr115) > mem_size-1) then addr115_tmp <= (others => '0'); else addr115_tmp <= addr115; end if; --synthesis translate_on end process; memory_access_guard_116: process (addr116) begin addr116_tmp <= addr116; --synthesis translate_off if (CONV_INTEGER(addr116) > mem_size-1) then addr116_tmp <= (others => '0'); else addr116_tmp <= addr116; end if; --synthesis translate_on end process; memory_access_guard_117: process (addr117) begin addr117_tmp <= addr117; --synthesis translate_off if (CONV_INTEGER(addr117) > mem_size-1) then addr117_tmp <= (others => '0'); else addr117_tmp <= addr117; end if; --synthesis translate_on end process; memory_access_guard_118: process (addr118) begin addr118_tmp <= addr118; --synthesis translate_off if (CONV_INTEGER(addr118) > mem_size-1) then addr118_tmp <= (others => '0'); else addr118_tmp <= addr118; end if; --synthesis translate_on end process; memory_access_guard_119: process (addr119) begin addr119_tmp <= addr119; --synthesis translate_off if (CONV_INTEGER(addr119) > mem_size-1) then addr119_tmp <= (others => '0'); else addr119_tmp <= addr119; end if; --synthesis translate_on end process; memory_access_guard_120: process (addr120) begin addr120_tmp <= addr120; --synthesis translate_off if (CONV_INTEGER(addr120) > mem_size-1) then addr120_tmp <= (others => '0'); else addr120_tmp <= addr120; end if; --synthesis translate_on end process; memory_access_guard_121: process (addr121) begin addr121_tmp <= addr121; --synthesis translate_off if (CONV_INTEGER(addr121) > mem_size-1) then addr121_tmp <= (others => '0'); else addr121_tmp <= addr121; end if; --synthesis translate_on end process; memory_access_guard_122: process (addr122) begin addr122_tmp <= addr122; --synthesis translate_off if (CONV_INTEGER(addr122) > mem_size-1) then addr122_tmp <= (others => '0'); else addr122_tmp <= addr122; end if; --synthesis translate_on end process; memory_access_guard_123: process (addr123) begin addr123_tmp <= addr123; --synthesis translate_off if (CONV_INTEGER(addr123) > mem_size-1) then addr123_tmp <= (others => '0'); else addr123_tmp <= addr123; end if; --synthesis translate_on end process; memory_access_guard_124: process (addr124) begin addr124_tmp <= addr124; --synthesis translate_off if (CONV_INTEGER(addr124) > mem_size-1) then addr124_tmp <= (others => '0'); else addr124_tmp <= addr124; end if; --synthesis translate_on end process; memory_access_guard_125: process (addr125) begin addr125_tmp <= addr125; --synthesis translate_off if (CONV_INTEGER(addr125) > mem_size-1) then addr125_tmp <= (others => '0'); else addr125_tmp <= addr125; end if; --synthesis translate_on end process; memory_access_guard_126: process (addr126) begin addr126_tmp <= addr126; --synthesis translate_off if (CONV_INTEGER(addr126) > mem_size-1) then addr126_tmp <= (others => '0'); else addr126_tmp <= addr126; end if; --synthesis translate_on end process; memory_access_guard_127: process (addr127) begin addr127_tmp <= addr127; --synthesis translate_off if (CONV_INTEGER(addr127) > mem_size-1) then addr127_tmp <= (others => '0'); else addr127_tmp <= addr127; end if; --synthesis translate_on end process; memory_access_guard_128: process (addr128) begin addr128_tmp <= addr128; --synthesis translate_off if (CONV_INTEGER(addr128) > mem_size-1) then addr128_tmp <= (others => '0'); else addr128_tmp <= addr128; end if; --synthesis translate_on end process; memory_access_guard_129: process (addr129) begin addr129_tmp <= addr129; --synthesis translate_off if (CONV_INTEGER(addr129) > mem_size-1) then addr129_tmp <= (others => '0'); else addr129_tmp <= addr129; end if; --synthesis translate_on end process; memory_access_guard_130: process (addr130) begin addr130_tmp <= addr130; --synthesis translate_off if (CONV_INTEGER(addr130) > mem_size-1) then addr130_tmp <= (others => '0'); else addr130_tmp <= addr130; end if; --synthesis translate_on end process; memory_access_guard_131: process (addr131) begin addr131_tmp <= addr131; --synthesis translate_off if (CONV_INTEGER(addr131) > mem_size-1) then addr131_tmp <= (others => '0'); else addr131_tmp <= addr131; end if; --synthesis translate_on end process; memory_access_guard_132: process (addr132) begin addr132_tmp <= addr132; --synthesis translate_off if (CONV_INTEGER(addr132) > mem_size-1) then addr132_tmp <= (others => '0'); else addr132_tmp <= addr132; end if; --synthesis translate_on end process; memory_access_guard_133: process (addr133) begin addr133_tmp <= addr133; --synthesis translate_off if (CONV_INTEGER(addr133) > mem_size-1) then addr133_tmp <= (others => '0'); else addr133_tmp <= addr133; end if; --synthesis translate_on end process; memory_access_guard_134: process (addr134) begin addr134_tmp <= addr134; --synthesis translate_off if (CONV_INTEGER(addr134) > mem_size-1) then addr134_tmp <= (others => '0'); else addr134_tmp <= addr134; end if; --synthesis translate_on end process; memory_access_guard_135: process (addr135) begin addr135_tmp <= addr135; --synthesis translate_off if (CONV_INTEGER(addr135) > mem_size-1) then addr135_tmp <= (others => '0'); else addr135_tmp <= addr135; end if; --synthesis translate_on end process; memory_access_guard_136: process (addr136) begin addr136_tmp <= addr136; --synthesis translate_off if (CONV_INTEGER(addr136) > mem_size-1) then addr136_tmp <= (others => '0'); else addr136_tmp <= addr136; end if; --synthesis translate_on end process; memory_access_guard_137: process (addr137) begin addr137_tmp <= addr137; --synthesis translate_off if (CONV_INTEGER(addr137) > mem_size-1) then addr137_tmp <= (others => '0'); else addr137_tmp <= addr137; end if; --synthesis translate_on end process; memory_access_guard_138: process (addr138) begin addr138_tmp <= addr138; --synthesis translate_off if (CONV_INTEGER(addr138) > mem_size-1) then addr138_tmp <= (others => '0'); else addr138_tmp <= addr138; end if; --synthesis translate_on end process; memory_access_guard_139: process (addr139) begin addr139_tmp <= addr139; --synthesis translate_off if (CONV_INTEGER(addr139) > mem_size-1) then addr139_tmp <= (others => '0'); else addr139_tmp <= addr139; end if; --synthesis translate_on end process; memory_access_guard_140: process (addr140) begin addr140_tmp <= addr140; --synthesis translate_off if (CONV_INTEGER(addr140) > mem_size-1) then addr140_tmp <= (others => '0'); else addr140_tmp <= addr140; end if; --synthesis translate_on end process; memory_access_guard_141: process (addr141) begin addr141_tmp <= addr141; --synthesis translate_off if (CONV_INTEGER(addr141) > mem_size-1) then addr141_tmp <= (others => '0'); else addr141_tmp <= addr141; end if; --synthesis translate_on end process; memory_access_guard_142: process (addr142) begin addr142_tmp <= addr142; --synthesis translate_off if (CONV_INTEGER(addr142) > mem_size-1) then addr142_tmp <= (others => '0'); else addr142_tmp <= addr142; end if; --synthesis translate_on end process; memory_access_guard_143: process (addr143) begin addr143_tmp <= addr143; --synthesis translate_off if (CONV_INTEGER(addr143) > mem_size-1) then addr143_tmp <= (others => '0'); else addr143_tmp <= addr143; end if; --synthesis translate_on end process; memory_access_guard_144: process (addr144) begin addr144_tmp <= addr144; --synthesis translate_off if (CONV_INTEGER(addr144) > mem_size-1) then addr144_tmp <= (others => '0'); else addr144_tmp <= addr144; end if; --synthesis translate_on end process; memory_access_guard_145: process (addr145) begin addr145_tmp <= addr145; --synthesis translate_off if (CONV_INTEGER(addr145) > mem_size-1) then addr145_tmp <= (others => '0'); else addr145_tmp <= addr145; end if; --synthesis translate_on end process; memory_access_guard_146: process (addr146) begin addr146_tmp <= addr146; --synthesis translate_off if (CONV_INTEGER(addr146) > mem_size-1) then addr146_tmp <= (others => '0'); else addr146_tmp <= addr146; end if; --synthesis translate_on end process; memory_access_guard_147: process (addr147) begin addr147_tmp <= addr147; --synthesis translate_off if (CONV_INTEGER(addr147) > mem_size-1) then addr147_tmp <= (others => '0'); else addr147_tmp <= addr147; end if; --synthesis translate_on end process; memory_access_guard_148: process (addr148) begin addr148_tmp <= addr148; --synthesis translate_off if (CONV_INTEGER(addr148) > mem_size-1) then addr148_tmp <= (others => '0'); else addr148_tmp <= addr148; end if; --synthesis translate_on end process; memory_access_guard_149: process (addr149) begin addr149_tmp <= addr149; --synthesis translate_off if (CONV_INTEGER(addr149) > mem_size-1) then addr149_tmp <= (others => '0'); else addr149_tmp <= addr149; end if; --synthesis translate_on end process; memory_access_guard_150: process (addr150) begin addr150_tmp <= addr150; --synthesis translate_off if (CONV_INTEGER(addr150) > mem_size-1) then addr150_tmp <= (others => '0'); else addr150_tmp <= addr150; end if; --synthesis translate_on end process; memory_access_guard_151: process (addr151) begin addr151_tmp <= addr151; --synthesis translate_off if (CONV_INTEGER(addr151) > mem_size-1) then addr151_tmp <= (others => '0'); else addr151_tmp <= addr151; end if; --synthesis translate_on end process; memory_access_guard_152: process (addr152) begin addr152_tmp <= addr152; --synthesis translate_off if (CONV_INTEGER(addr152) > mem_size-1) then addr152_tmp <= (others => '0'); else addr152_tmp <= addr152; end if; --synthesis translate_on end process; memory_access_guard_153: process (addr153) begin addr153_tmp <= addr153; --synthesis translate_off if (CONV_INTEGER(addr153) > mem_size-1) then addr153_tmp <= (others => '0'); else addr153_tmp <= addr153; end if; --synthesis translate_on end process; memory_access_guard_154: process (addr154) begin addr154_tmp <= addr154; --synthesis translate_off if (CONV_INTEGER(addr154) > mem_size-1) then addr154_tmp <= (others => '0'); else addr154_tmp <= addr154; end if; --synthesis translate_on end process; memory_access_guard_155: process (addr155) begin addr155_tmp <= addr155; --synthesis translate_off if (CONV_INTEGER(addr155) > mem_size-1) then addr155_tmp <= (others => '0'); else addr155_tmp <= addr155; end if; --synthesis translate_on end process; memory_access_guard_156: process (addr156) begin addr156_tmp <= addr156; --synthesis translate_off if (CONV_INTEGER(addr156) > mem_size-1) then addr156_tmp <= (others => '0'); else addr156_tmp <= addr156; end if; --synthesis translate_on end process; memory_access_guard_157: process (addr157) begin addr157_tmp <= addr157; --synthesis translate_off if (CONV_INTEGER(addr157) > mem_size-1) then addr157_tmp <= (others => '0'); else addr157_tmp <= addr157; end if; --synthesis translate_on end process; memory_access_guard_158: process (addr158) begin addr158_tmp <= addr158; --synthesis translate_off if (CONV_INTEGER(addr158) > mem_size-1) then addr158_tmp <= (others => '0'); else addr158_tmp <= addr158; end if; --synthesis translate_on end process; memory_access_guard_159: process (addr159) begin addr159_tmp <= addr159; --synthesis translate_off if (CONV_INTEGER(addr159) > mem_size-1) then addr159_tmp <= (others => '0'); else addr159_tmp <= addr159; end if; --synthesis translate_on end process; memory_access_guard_160: process (addr160) begin addr160_tmp <= addr160; --synthesis translate_off if (CONV_INTEGER(addr160) > mem_size-1) then addr160_tmp <= (others => '0'); else addr160_tmp <= addr160; end if; --synthesis translate_on end process; memory_access_guard_161: process (addr161) begin addr161_tmp <= addr161; --synthesis translate_off if (CONV_INTEGER(addr161) > mem_size-1) then addr161_tmp <= (others => '0'); else addr161_tmp <= addr161; end if; --synthesis translate_on end process; memory_access_guard_162: process (addr162) begin addr162_tmp <= addr162; --synthesis translate_off if (CONV_INTEGER(addr162) > mem_size-1) then addr162_tmp <= (others => '0'); else addr162_tmp <= addr162; end if; --synthesis translate_on end process; memory_access_guard_163: process (addr163) begin addr163_tmp <= addr163; --synthesis translate_off if (CONV_INTEGER(addr163) > mem_size-1) then addr163_tmp <= (others => '0'); else addr163_tmp <= addr163; end if; --synthesis translate_on end process; memory_access_guard_164: process (addr164) begin addr164_tmp <= addr164; --synthesis translate_off if (CONV_INTEGER(addr164) > mem_size-1) then addr164_tmp <= (others => '0'); else addr164_tmp <= addr164; end if; --synthesis translate_on end process; memory_access_guard_165: process (addr165) begin addr165_tmp <= addr165; --synthesis translate_off if (CONV_INTEGER(addr165) > mem_size-1) then addr165_tmp <= (others => '0'); else addr165_tmp <= addr165; end if; --synthesis translate_on end process; memory_access_guard_166: process (addr166) begin addr166_tmp <= addr166; --synthesis translate_off if (CONV_INTEGER(addr166) > mem_size-1) then addr166_tmp <= (others => '0'); else addr166_tmp <= addr166; end if; --synthesis translate_on end process; memory_access_guard_167: process (addr167) begin addr167_tmp <= addr167; --synthesis translate_off if (CONV_INTEGER(addr167) > mem_size-1) then addr167_tmp <= (others => '0'); else addr167_tmp <= addr167; end if; --synthesis translate_on end process; memory_access_guard_168: process (addr168) begin addr168_tmp <= addr168; --synthesis translate_off if (CONV_INTEGER(addr168) > mem_size-1) then addr168_tmp <= (others => '0'); else addr168_tmp <= addr168; end if; --synthesis translate_on end process; memory_access_guard_169: process (addr169) begin addr169_tmp <= addr169; --synthesis translate_off if (CONV_INTEGER(addr169) > mem_size-1) then addr169_tmp <= (others => '0'); else addr169_tmp <= addr169; end if; --synthesis translate_on end process; memory_access_guard_170: process (addr170) begin addr170_tmp <= addr170; --synthesis translate_off if (CONV_INTEGER(addr170) > mem_size-1) then addr170_tmp <= (others => '0'); else addr170_tmp <= addr170; end if; --synthesis translate_on end process; memory_access_guard_171: process (addr171) begin addr171_tmp <= addr171; --synthesis translate_off if (CONV_INTEGER(addr171) > mem_size-1) then addr171_tmp <= (others => '0'); else addr171_tmp <= addr171; end if; --synthesis translate_on end process; memory_access_guard_172: process (addr172) begin addr172_tmp <= addr172; --synthesis translate_off if (CONV_INTEGER(addr172) > mem_size-1) then addr172_tmp <= (others => '0'); else addr172_tmp <= addr172; end if; --synthesis translate_on end process; memory_access_guard_173: process (addr173) begin addr173_tmp <= addr173; --synthesis translate_off if (CONV_INTEGER(addr173) > mem_size-1) then addr173_tmp <= (others => '0'); else addr173_tmp <= addr173; end if; --synthesis translate_on end process; memory_access_guard_174: process (addr174) begin addr174_tmp <= addr174; --synthesis translate_off if (CONV_INTEGER(addr174) > mem_size-1) then addr174_tmp <= (others => '0'); else addr174_tmp <= addr174; end if; --synthesis translate_on end process; memory_access_guard_175: process (addr175) begin addr175_tmp <= addr175; --synthesis translate_off if (CONV_INTEGER(addr175) > mem_size-1) then addr175_tmp <= (others => '0'); else addr175_tmp <= addr175; end if; --synthesis translate_on end process; memory_access_guard_176: process (addr176) begin addr176_tmp <= addr176; --synthesis translate_off if (CONV_INTEGER(addr176) > mem_size-1) then addr176_tmp <= (others => '0'); else addr176_tmp <= addr176; end if; --synthesis translate_on end process; memory_access_guard_177: process (addr177) begin addr177_tmp <= addr177; --synthesis translate_off if (CONV_INTEGER(addr177) > mem_size-1) then addr177_tmp <= (others => '0'); else addr177_tmp <= addr177; end if; --synthesis translate_on end process; memory_access_guard_178: process (addr178) begin addr178_tmp <= addr178; --synthesis translate_off if (CONV_INTEGER(addr178) > mem_size-1) then addr178_tmp <= (others => '0'); else addr178_tmp <= addr178; end if; --synthesis translate_on end process; memory_access_guard_179: process (addr179) begin addr179_tmp <= addr179; --synthesis translate_off if (CONV_INTEGER(addr179) > mem_size-1) then addr179_tmp <= (others => '0'); else addr179_tmp <= addr179; end if; --synthesis translate_on end process; memory_access_guard_180: process (addr180) begin addr180_tmp <= addr180; --synthesis translate_off if (CONV_INTEGER(addr180) > mem_size-1) then addr180_tmp <= (others => '0'); else addr180_tmp <= addr180; end if; --synthesis translate_on end process; memory_access_guard_181: process (addr181) begin addr181_tmp <= addr181; --synthesis translate_off if (CONV_INTEGER(addr181) > mem_size-1) then addr181_tmp <= (others => '0'); else addr181_tmp <= addr181; end if; --synthesis translate_on end process; memory_access_guard_182: process (addr182) begin addr182_tmp <= addr182; --synthesis translate_off if (CONV_INTEGER(addr182) > mem_size-1) then addr182_tmp <= (others => '0'); else addr182_tmp <= addr182; end if; --synthesis translate_on end process; memory_access_guard_183: process (addr183) begin addr183_tmp <= addr183; --synthesis translate_off if (CONV_INTEGER(addr183) > mem_size-1) then addr183_tmp <= (others => '0'); else addr183_tmp <= addr183; end if; --synthesis translate_on end process; memory_access_guard_184: process (addr184) begin addr184_tmp <= addr184; --synthesis translate_off if (CONV_INTEGER(addr184) > mem_size-1) then addr184_tmp <= (others => '0'); else addr184_tmp <= addr184; end if; --synthesis translate_on end process; memory_access_guard_185: process (addr185) begin addr185_tmp <= addr185; --synthesis translate_off if (CONV_INTEGER(addr185) > mem_size-1) then addr185_tmp <= (others => '0'); else addr185_tmp <= addr185; end if; --synthesis translate_on end process; memory_access_guard_186: process (addr186) begin addr186_tmp <= addr186; --synthesis translate_off if (CONV_INTEGER(addr186) > mem_size-1) then addr186_tmp <= (others => '0'); else addr186_tmp <= addr186; end if; --synthesis translate_on end process; memory_access_guard_187: process (addr187) begin addr187_tmp <= addr187; --synthesis translate_off if (CONV_INTEGER(addr187) > mem_size-1) then addr187_tmp <= (others => '0'); else addr187_tmp <= addr187; end if; --synthesis translate_on end process; memory_access_guard_188: process (addr188) begin addr188_tmp <= addr188; --synthesis translate_off if (CONV_INTEGER(addr188) > mem_size-1) then addr188_tmp <= (others => '0'); else addr188_tmp <= addr188; end if; --synthesis translate_on end process; memory_access_guard_189: process (addr189) begin addr189_tmp <= addr189; --synthesis translate_off if (CONV_INTEGER(addr189) > mem_size-1) then addr189_tmp <= (others => '0'); else addr189_tmp <= addr189; end if; --synthesis translate_on end process; memory_access_guard_190: process (addr190) begin addr190_tmp <= addr190; --synthesis translate_off if (CONV_INTEGER(addr190) > mem_size-1) then addr190_tmp <= (others => '0'); else addr190_tmp <= addr190; end if; --synthesis translate_on end process; memory_access_guard_191: process (addr191) begin addr191_tmp <= addr191; --synthesis translate_off if (CONV_INTEGER(addr191) > mem_size-1) then addr191_tmp <= (others => '0'); else addr191_tmp <= addr191; end if; --synthesis translate_on end process; memory_access_guard_192: process (addr192) begin addr192_tmp <= addr192; --synthesis translate_off if (CONV_INTEGER(addr192) > mem_size-1) then addr192_tmp <= (others => '0'); else addr192_tmp <= addr192; end if; --synthesis translate_on end process; memory_access_guard_193: process (addr193) begin addr193_tmp <= addr193; --synthesis translate_off if (CONV_INTEGER(addr193) > mem_size-1) then addr193_tmp <= (others => '0'); else addr193_tmp <= addr193; end if; --synthesis translate_on end process; memory_access_guard_194: process (addr194) begin addr194_tmp <= addr194; --synthesis translate_off if (CONV_INTEGER(addr194) > mem_size-1) then addr194_tmp <= (others => '0'); else addr194_tmp <= addr194; end if; --synthesis translate_on end process; memory_access_guard_195: process (addr195) begin addr195_tmp <= addr195; --synthesis translate_off if (CONV_INTEGER(addr195) > mem_size-1) then addr195_tmp <= (others => '0'); else addr195_tmp <= addr195; end if; --synthesis translate_on end process; memory_access_guard_196: process (addr196) begin addr196_tmp <= addr196; --synthesis translate_off if (CONV_INTEGER(addr196) > mem_size-1) then addr196_tmp <= (others => '0'); else addr196_tmp <= addr196; end if; --synthesis translate_on end process; memory_access_guard_197: process (addr197) begin addr197_tmp <= addr197; --synthesis translate_off if (CONV_INTEGER(addr197) > mem_size-1) then addr197_tmp <= (others => '0'); else addr197_tmp <= addr197; end if; --synthesis translate_on end process; memory_access_guard_198: process (addr198) begin addr198_tmp <= addr198; --synthesis translate_off if (CONV_INTEGER(addr198) > mem_size-1) then addr198_tmp <= (others => '0'); else addr198_tmp <= addr198; end if; --synthesis translate_on end process; memory_access_guard_199: process (addr199) begin addr199_tmp <= addr199; --synthesis translate_off if (CONV_INTEGER(addr199) > mem_size-1) then addr199_tmp <= (others => '0'); else addr199_tmp <= addr199; end if; --synthesis translate_on end process; p_rom_access: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then q0 <= mem0(CONV_INTEGER(addr0_tmp)); end if; if (ce1 = '1') then q1 <= mem0(CONV_INTEGER(addr1_tmp)); end if; if (ce2 = '1') then q2 <= mem1(CONV_INTEGER(addr2_tmp)); end if; if (ce3 = '1') then q3 <= mem1(CONV_INTEGER(addr3_tmp)); end if; if (ce4 = '1') then q4 <= mem2(CONV_INTEGER(addr4_tmp)); end if; if (ce5 = '1') then q5 <= mem2(CONV_INTEGER(addr5_tmp)); end if; if (ce6 = '1') then q6 <= mem3(CONV_INTEGER(addr6_tmp)); end if; if (ce7 = '1') then q7 <= mem3(CONV_INTEGER(addr7_tmp)); end if; if (ce8 = '1') then q8 <= mem4(CONV_INTEGER(addr8_tmp)); end if; if (ce9 = '1') then q9 <= mem4(CONV_INTEGER(addr9_tmp)); end if; if (ce10 = '1') then q10 <= mem5(CONV_INTEGER(addr10_tmp)); end if; if (ce11 = '1') then q11 <= mem5(CONV_INTEGER(addr11_tmp)); end if; if (ce12 = '1') then q12 <= mem6(CONV_INTEGER(addr12_tmp)); end if; if (ce13 = '1') then q13 <= mem6(CONV_INTEGER(addr13_tmp)); end if; if (ce14 = '1') then q14 <= mem7(CONV_INTEGER(addr14_tmp)); end if; if (ce15 = '1') then q15 <= mem7(CONV_INTEGER(addr15_tmp)); end if; if (ce16 = '1') then q16 <= mem8(CONV_INTEGER(addr16_tmp)); end if; if (ce17 = '1') then q17 <= mem8(CONV_INTEGER(addr17_tmp)); end if; if (ce18 = '1') then q18 <= mem9(CONV_INTEGER(addr18_tmp)); end if; if (ce19 = '1') then q19 <= mem9(CONV_INTEGER(addr19_tmp)); end if; if (ce20 = '1') then q20 <= mem10(CONV_INTEGER(addr20_tmp)); end if; if (ce21 = '1') then q21 <= mem10(CONV_INTEGER(addr21_tmp)); end if; if (ce22 = '1') then q22 <= mem11(CONV_INTEGER(addr22_tmp)); end if; if (ce23 = '1') then q23 <= mem11(CONV_INTEGER(addr23_tmp)); end if; if (ce24 = '1') then q24 <= mem12(CONV_INTEGER(addr24_tmp)); end if; if (ce25 = '1') then q25 <= mem12(CONV_INTEGER(addr25_tmp)); end if; if (ce26 = '1') then q26 <= mem13(CONV_INTEGER(addr26_tmp)); end if; if (ce27 = '1') then q27 <= mem13(CONV_INTEGER(addr27_tmp)); end if; if (ce28 = '1') then q28 <= mem14(CONV_INTEGER(addr28_tmp)); end if; if (ce29 = '1') then q29 <= mem14(CONV_INTEGER(addr29_tmp)); end if; if (ce30 = '1') then q30 <= mem15(CONV_INTEGER(addr30_tmp)); end if; if (ce31 = '1') then q31 <= mem15(CONV_INTEGER(addr31_tmp)); end if; if (ce32 = '1') then q32 <= mem16(CONV_INTEGER(addr32_tmp)); end if; if (ce33 = '1') then q33 <= mem16(CONV_INTEGER(addr33_tmp)); end if; if (ce34 = '1') then q34 <= mem17(CONV_INTEGER(addr34_tmp)); end if; if (ce35 = '1') then q35 <= mem17(CONV_INTEGER(addr35_tmp)); end if; if (ce36 = '1') then q36 <= mem18(CONV_INTEGER(addr36_tmp)); end if; if (ce37 = '1') then q37 <= mem18(CONV_INTEGER(addr37_tmp)); end if; if (ce38 = '1') then q38 <= mem19(CONV_INTEGER(addr38_tmp)); end if; if (ce39 = '1') then q39 <= mem19(CONV_INTEGER(addr39_tmp)); end if; if (ce40 = '1') then q40 <= mem20(CONV_INTEGER(addr40_tmp)); end if; if (ce41 = '1') then q41 <= mem20(CONV_INTEGER(addr41_tmp)); end if; if (ce42 = '1') then q42 <= mem21(CONV_INTEGER(addr42_tmp)); end if; if (ce43 = '1') then q43 <= mem21(CONV_INTEGER(addr43_tmp)); end if; if (ce44 = '1') then q44 <= mem22(CONV_INTEGER(addr44_tmp)); end if; if (ce45 = '1') then q45 <= mem22(CONV_INTEGER(addr45_tmp)); end if; if (ce46 = '1') then q46 <= mem23(CONV_INTEGER(addr46_tmp)); end if; if (ce47 = '1') then q47 <= mem23(CONV_INTEGER(addr47_tmp)); end if; if (ce48 = '1') then q48 <= mem24(CONV_INTEGER(addr48_tmp)); end if; if (ce49 = '1') then q49 <= mem24(CONV_INTEGER(addr49_tmp)); end if; if (ce50 = '1') then q50 <= mem25(CONV_INTEGER(addr50_tmp)); end if; if (ce51 = '1') then q51 <= mem25(CONV_INTEGER(addr51_tmp)); end if; if (ce52 = '1') then q52 <= mem26(CONV_INTEGER(addr52_tmp)); end if; if (ce53 = '1') then q53 <= mem26(CONV_INTEGER(addr53_tmp)); end if; if (ce54 = '1') then q54 <= mem27(CONV_INTEGER(addr54_tmp)); end if; if (ce55 = '1') then q55 <= mem27(CONV_INTEGER(addr55_tmp)); end if; if (ce56 = '1') then q56 <= mem28(CONV_INTEGER(addr56_tmp)); end if; if (ce57 = '1') then q57 <= mem28(CONV_INTEGER(addr57_tmp)); end if; if (ce58 = '1') then q58 <= mem29(CONV_INTEGER(addr58_tmp)); end if; if (ce59 = '1') then q59 <= mem29(CONV_INTEGER(addr59_tmp)); end if; if (ce60 = '1') then q60 <= mem30(CONV_INTEGER(addr60_tmp)); end if; if (ce61 = '1') then q61 <= mem30(CONV_INTEGER(addr61_tmp)); end if; if (ce62 = '1') then q62 <= mem31(CONV_INTEGER(addr62_tmp)); end if; if (ce63 = '1') then q63 <= mem31(CONV_INTEGER(addr63_tmp)); end if; if (ce64 = '1') then q64 <= mem32(CONV_INTEGER(addr64_tmp)); end if; if (ce65 = '1') then q65 <= mem32(CONV_INTEGER(addr65_tmp)); end if; if (ce66 = '1') then q66 <= mem33(CONV_INTEGER(addr66_tmp)); end if; if (ce67 = '1') then q67 <= mem33(CONV_INTEGER(addr67_tmp)); end if; if (ce68 = '1') then q68 <= mem34(CONV_INTEGER(addr68_tmp)); end if; if (ce69 = '1') then q69 <= mem34(CONV_INTEGER(addr69_tmp)); end if; if (ce70 = '1') then q70 <= mem35(CONV_INTEGER(addr70_tmp)); end if; if (ce71 = '1') then q71 <= mem35(CONV_INTEGER(addr71_tmp)); end if; if (ce72 = '1') then q72 <= mem36(CONV_INTEGER(addr72_tmp)); end if; if (ce73 = '1') then q73 <= mem36(CONV_INTEGER(addr73_tmp)); end if; if (ce74 = '1') then q74 <= mem37(CONV_INTEGER(addr74_tmp)); end if; if (ce75 = '1') then q75 <= mem37(CONV_INTEGER(addr75_tmp)); end if; if (ce76 = '1') then q76 <= mem38(CONV_INTEGER(addr76_tmp)); end if; if (ce77 = '1') then q77 <= mem38(CONV_INTEGER(addr77_tmp)); end if; if (ce78 = '1') then q78 <= mem39(CONV_INTEGER(addr78_tmp)); end if; if (ce79 = '1') then q79 <= mem39(CONV_INTEGER(addr79_tmp)); end if; if (ce80 = '1') then q80 <= mem40(CONV_INTEGER(addr80_tmp)); end if; if (ce81 = '1') then q81 <= mem40(CONV_INTEGER(addr81_tmp)); end if; if (ce82 = '1') then q82 <= mem41(CONV_INTEGER(addr82_tmp)); end if; if (ce83 = '1') then q83 <= mem41(CONV_INTEGER(addr83_tmp)); end if; if (ce84 = '1') then q84 <= mem42(CONV_INTEGER(addr84_tmp)); end if; if (ce85 = '1') then q85 <= mem42(CONV_INTEGER(addr85_tmp)); end if; if (ce86 = '1') then q86 <= mem43(CONV_INTEGER(addr86_tmp)); end if; if (ce87 = '1') then q87 <= mem43(CONV_INTEGER(addr87_tmp)); end if; if (ce88 = '1') then q88 <= mem44(CONV_INTEGER(addr88_tmp)); end if; if (ce89 = '1') then q89 <= mem44(CONV_INTEGER(addr89_tmp)); end if; if (ce90 = '1') then q90 <= mem45(CONV_INTEGER(addr90_tmp)); end if; if (ce91 = '1') then q91 <= mem45(CONV_INTEGER(addr91_tmp)); end if; if (ce92 = '1') then q92 <= mem46(CONV_INTEGER(addr92_tmp)); end if; if (ce93 = '1') then q93 <= mem46(CONV_INTEGER(addr93_tmp)); end if; if (ce94 = '1') then q94 <= mem47(CONV_INTEGER(addr94_tmp)); end if; if (ce95 = '1') then q95 <= mem47(CONV_INTEGER(addr95_tmp)); end if; if (ce96 = '1') then q96 <= mem48(CONV_INTEGER(addr96_tmp)); end if; if (ce97 = '1') then q97 <= mem48(CONV_INTEGER(addr97_tmp)); end if; if (ce98 = '1') then q98 <= mem49(CONV_INTEGER(addr98_tmp)); end if; if (ce99 = '1') then q99 <= mem49(CONV_INTEGER(addr99_tmp)); end if; if (ce100 = '1') then q100 <= mem50(CONV_INTEGER(addr100_tmp)); end if; if (ce101 = '1') then q101 <= mem50(CONV_INTEGER(addr101_tmp)); end if; if (ce102 = '1') then q102 <= mem51(CONV_INTEGER(addr102_tmp)); end if; if (ce103 = '1') then q103 <= mem51(CONV_INTEGER(addr103_tmp)); end if; if (ce104 = '1') then q104 <= mem52(CONV_INTEGER(addr104_tmp)); end if; if (ce105 = '1') then q105 <= mem52(CONV_INTEGER(addr105_tmp)); end if; if (ce106 = '1') then q106 <= mem53(CONV_INTEGER(addr106_tmp)); end if; if (ce107 = '1') then q107 <= mem53(CONV_INTEGER(addr107_tmp)); end if; if (ce108 = '1') then q108 <= mem54(CONV_INTEGER(addr108_tmp)); end if; if (ce109 = '1') then q109 <= mem54(CONV_INTEGER(addr109_tmp)); end if; if (ce110 = '1') then q110 <= mem55(CONV_INTEGER(addr110_tmp)); end if; if (ce111 = '1') then q111 <= mem55(CONV_INTEGER(addr111_tmp)); end if; if (ce112 = '1') then q112 <= mem56(CONV_INTEGER(addr112_tmp)); end if; if (ce113 = '1') then q113 <= mem56(CONV_INTEGER(addr113_tmp)); end if; if (ce114 = '1') then q114 <= mem57(CONV_INTEGER(addr114_tmp)); end if; if (ce115 = '1') then q115 <= mem57(CONV_INTEGER(addr115_tmp)); end if; if (ce116 = '1') then q116 <= mem58(CONV_INTEGER(addr116_tmp)); end if; if (ce117 = '1') then q117 <= mem58(CONV_INTEGER(addr117_tmp)); end if; if (ce118 = '1') then q118 <= mem59(CONV_INTEGER(addr118_tmp)); end if; if (ce119 = '1') then q119 <= mem59(CONV_INTEGER(addr119_tmp)); end if; if (ce120 = '1') then q120 <= mem60(CONV_INTEGER(addr120_tmp)); end if; if (ce121 = '1') then q121 <= mem60(CONV_INTEGER(addr121_tmp)); end if; if (ce122 = '1') then q122 <= mem61(CONV_INTEGER(addr122_tmp)); end if; if (ce123 = '1') then q123 <= mem61(CONV_INTEGER(addr123_tmp)); end if; if (ce124 = '1') then q124 <= mem62(CONV_INTEGER(addr124_tmp)); end if; if (ce125 = '1') then q125 <= mem62(CONV_INTEGER(addr125_tmp)); end if; if (ce126 = '1') then q126 <= mem63(CONV_INTEGER(addr126_tmp)); end if; if (ce127 = '1') then q127 <= mem63(CONV_INTEGER(addr127_tmp)); end if; if (ce128 = '1') then q128 <= mem64(CONV_INTEGER(addr128_tmp)); end if; if (ce129 = '1') then q129 <= mem64(CONV_INTEGER(addr129_tmp)); end if; if (ce130 = '1') then q130 <= mem65(CONV_INTEGER(addr130_tmp)); end if; if (ce131 = '1') then q131 <= mem65(CONV_INTEGER(addr131_tmp)); end if; if (ce132 = '1') then q132 <= mem66(CONV_INTEGER(addr132_tmp)); end if; if (ce133 = '1') then q133 <= mem66(CONV_INTEGER(addr133_tmp)); end if; if (ce134 = '1') then q134 <= mem67(CONV_INTEGER(addr134_tmp)); end if; if (ce135 = '1') then q135 <= mem67(CONV_INTEGER(addr135_tmp)); end if; if (ce136 = '1') then q136 <= mem68(CONV_INTEGER(addr136_tmp)); end if; if (ce137 = '1') then q137 <= mem68(CONV_INTEGER(addr137_tmp)); end if; if (ce138 = '1') then q138 <= mem69(CONV_INTEGER(addr138_tmp)); end if; if (ce139 = '1') then q139 <= mem69(CONV_INTEGER(addr139_tmp)); end if; if (ce140 = '1') then q140 <= mem70(CONV_INTEGER(addr140_tmp)); end if; if (ce141 = '1') then q141 <= mem70(CONV_INTEGER(addr141_tmp)); end if; if (ce142 = '1') then q142 <= mem71(CONV_INTEGER(addr142_tmp)); end if; if (ce143 = '1') then q143 <= mem71(CONV_INTEGER(addr143_tmp)); end if; if (ce144 = '1') then q144 <= mem72(CONV_INTEGER(addr144_tmp)); end if; if (ce145 = '1') then q145 <= mem72(CONV_INTEGER(addr145_tmp)); end if; if (ce146 = '1') then q146 <= mem73(CONV_INTEGER(addr146_tmp)); end if; if (ce147 = '1') then q147 <= mem73(CONV_INTEGER(addr147_tmp)); end if; if (ce148 = '1') then q148 <= mem74(CONV_INTEGER(addr148_tmp)); end if; if (ce149 = '1') then q149 <= mem74(CONV_INTEGER(addr149_tmp)); end if; if (ce150 = '1') then q150 <= mem75(CONV_INTEGER(addr150_tmp)); end if; if (ce151 = '1') then q151 <= mem75(CONV_INTEGER(addr151_tmp)); end if; if (ce152 = '1') then q152 <= mem76(CONV_INTEGER(addr152_tmp)); end if; if (ce153 = '1') then q153 <= mem76(CONV_INTEGER(addr153_tmp)); end if; if (ce154 = '1') then q154 <= mem77(CONV_INTEGER(addr154_tmp)); end if; if (ce155 = '1') then q155 <= mem77(CONV_INTEGER(addr155_tmp)); end if; if (ce156 = '1') then q156 <= mem78(CONV_INTEGER(addr156_tmp)); end if; if (ce157 = '1') then q157 <= mem78(CONV_INTEGER(addr157_tmp)); end if; if (ce158 = '1') then q158 <= mem79(CONV_INTEGER(addr158_tmp)); end if; if (ce159 = '1') then q159 <= mem79(CONV_INTEGER(addr159_tmp)); end if; if (ce160 = '1') then q160 <= mem80(CONV_INTEGER(addr160_tmp)); end if; if (ce161 = '1') then q161 <= mem80(CONV_INTEGER(addr161_tmp)); end if; if (ce162 = '1') then q162 <= mem81(CONV_INTEGER(addr162_tmp)); end if; if (ce163 = '1') then q163 <= mem81(CONV_INTEGER(addr163_tmp)); end if; if (ce164 = '1') then q164 <= mem82(CONV_INTEGER(addr164_tmp)); end if; if (ce165 = '1') then q165 <= mem82(CONV_INTEGER(addr165_tmp)); end if; if (ce166 = '1') then q166 <= mem83(CONV_INTEGER(addr166_tmp)); end if; if (ce167 = '1') then q167 <= mem83(CONV_INTEGER(addr167_tmp)); end if; if (ce168 = '1') then q168 <= mem84(CONV_INTEGER(addr168_tmp)); end if; if (ce169 = '1') then q169 <= mem84(CONV_INTEGER(addr169_tmp)); end if; if (ce170 = '1') then q170 <= mem85(CONV_INTEGER(addr170_tmp)); end if; if (ce171 = '1') then q171 <= mem85(CONV_INTEGER(addr171_tmp)); end if; if (ce172 = '1') then q172 <= mem86(CONV_INTEGER(addr172_tmp)); end if; if (ce173 = '1') then q173 <= mem86(CONV_INTEGER(addr173_tmp)); end if; if (ce174 = '1') then q174 <= mem87(CONV_INTEGER(addr174_tmp)); end if; if (ce175 = '1') then q175 <= mem87(CONV_INTEGER(addr175_tmp)); end if; if (ce176 = '1') then q176 <= mem88(CONV_INTEGER(addr176_tmp)); end if; if (ce177 = '1') then q177 <= mem88(CONV_INTEGER(addr177_tmp)); end if; if (ce178 = '1') then q178 <= mem89(CONV_INTEGER(addr178_tmp)); end if; if (ce179 = '1') then q179 <= mem89(CONV_INTEGER(addr179_tmp)); end if; if (ce180 = '1') then q180 <= mem90(CONV_INTEGER(addr180_tmp)); end if; if (ce181 = '1') then q181 <= mem90(CONV_INTEGER(addr181_tmp)); end if; if (ce182 = '1') then q182 <= mem91(CONV_INTEGER(addr182_tmp)); end if; if (ce183 = '1') then q183 <= mem91(CONV_INTEGER(addr183_tmp)); end if; if (ce184 = '1') then q184 <= mem92(CONV_INTEGER(addr184_tmp)); end if; if (ce185 = '1') then q185 <= mem92(CONV_INTEGER(addr185_tmp)); end if; if (ce186 = '1') then q186 <= mem93(CONV_INTEGER(addr186_tmp)); end if; if (ce187 = '1') then q187 <= mem93(CONV_INTEGER(addr187_tmp)); end if; if (ce188 = '1') then q188 <= mem94(CONV_INTEGER(addr188_tmp)); end if; if (ce189 = '1') then q189 <= mem94(CONV_INTEGER(addr189_tmp)); end if; if (ce190 = '1') then q190 <= mem95(CONV_INTEGER(addr190_tmp)); end if; if (ce191 = '1') then q191 <= mem95(CONV_INTEGER(addr191_tmp)); end if; if (ce192 = '1') then q192 <= mem96(CONV_INTEGER(addr192_tmp)); end if; if (ce193 = '1') then q193 <= mem96(CONV_INTEGER(addr193_tmp)); end if; if (ce194 = '1') then q194 <= mem97(CONV_INTEGER(addr194_tmp)); end if; if (ce195 = '1') then q195 <= mem97(CONV_INTEGER(addr195_tmp)); end if; if (ce196 = '1') then q196 <= mem98(CONV_INTEGER(addr196_tmp)); end if; if (ce197 = '1') then q197 <= mem98(CONV_INTEGER(addr197_tmp)); end if; if (ce198 = '1') then q198 <= mem99(CONV_INTEGER(addr198_tmp)); end if; if (ce199 = '1') then q199 <= mem99(CONV_INTEGER(addr199_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity aestest_sboxes is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 256; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce2 : IN STD_LOGIC; q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address3 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce3 : IN STD_LOGIC; q3 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address4 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce4 : IN STD_LOGIC; q4 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address5 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce5 : IN STD_LOGIC; q5 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address6 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce6 : IN STD_LOGIC; q6 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address7 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce7 : IN STD_LOGIC; q7 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address8 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce8 : IN STD_LOGIC; q8 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address9 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce9 : IN STD_LOGIC; q9 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address10 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce10 : IN STD_LOGIC; q10 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address11 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce11 : IN STD_LOGIC; q11 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address12 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce12 : IN STD_LOGIC; q12 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address13 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce13 : IN STD_LOGIC; q13 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address14 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce14 : IN STD_LOGIC; q14 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address15 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce15 : IN STD_LOGIC; q15 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address16 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce16 : IN STD_LOGIC; q16 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address17 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce17 : IN STD_LOGIC; q17 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address18 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce18 : IN STD_LOGIC; q18 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address19 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce19 : IN STD_LOGIC; q19 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address20 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce20 : IN STD_LOGIC; q20 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address21 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce21 : IN STD_LOGIC; q21 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address22 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce22 : IN STD_LOGIC; q22 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address23 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce23 : IN STD_LOGIC; q23 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address24 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce24 : IN STD_LOGIC; q24 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address25 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce25 : IN STD_LOGIC; q25 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address26 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce26 : IN STD_LOGIC; q26 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address27 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce27 : IN STD_LOGIC; q27 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address28 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce28 : IN STD_LOGIC; q28 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address29 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce29 : IN STD_LOGIC; q29 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address30 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce30 : IN STD_LOGIC; q30 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address31 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce31 : IN STD_LOGIC; q31 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address32 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce32 : IN STD_LOGIC; q32 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address33 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce33 : IN STD_LOGIC; q33 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address34 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce34 : IN STD_LOGIC; q34 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address35 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce35 : IN STD_LOGIC; q35 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address36 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce36 : IN STD_LOGIC; q36 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address37 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce37 : IN STD_LOGIC; q37 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address38 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce38 : IN STD_LOGIC; q38 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address39 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce39 : IN STD_LOGIC; q39 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address40 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce40 : IN STD_LOGIC; q40 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address41 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce41 : IN STD_LOGIC; q41 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address42 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce42 : IN STD_LOGIC; q42 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address43 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce43 : IN STD_LOGIC; q43 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address44 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce44 : IN STD_LOGIC; q44 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address45 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce45 : IN STD_LOGIC; q45 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address46 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce46 : IN STD_LOGIC; q46 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address47 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce47 : IN STD_LOGIC; q47 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address48 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce48 : IN STD_LOGIC; q48 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address49 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce49 : IN STD_LOGIC; q49 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address50 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce50 : IN STD_LOGIC; q50 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address51 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce51 : IN STD_LOGIC; q51 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address52 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce52 : IN STD_LOGIC; q52 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address53 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce53 : IN STD_LOGIC; q53 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address54 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce54 : IN STD_LOGIC; q54 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address55 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce55 : IN STD_LOGIC; q55 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address56 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce56 : IN STD_LOGIC; q56 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address57 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce57 : IN STD_LOGIC; q57 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address58 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce58 : IN STD_LOGIC; q58 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address59 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce59 : IN STD_LOGIC; q59 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address60 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce60 : IN STD_LOGIC; q60 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address61 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce61 : IN STD_LOGIC; q61 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address62 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce62 : IN STD_LOGIC; q62 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address63 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce63 : IN STD_LOGIC; q63 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address64 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce64 : IN STD_LOGIC; q64 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address65 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce65 : IN STD_LOGIC; q65 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address66 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce66 : IN STD_LOGIC; q66 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address67 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce67 : IN STD_LOGIC; q67 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address68 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce68 : IN STD_LOGIC; q68 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address69 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce69 : IN STD_LOGIC; q69 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address70 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce70 : IN STD_LOGIC; q70 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address71 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce71 : IN STD_LOGIC; q71 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address72 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce72 : IN STD_LOGIC; q72 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address73 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce73 : IN STD_LOGIC; q73 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address74 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce74 : IN STD_LOGIC; q74 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address75 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce75 : IN STD_LOGIC; q75 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address76 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce76 : IN STD_LOGIC; q76 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address77 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce77 : IN STD_LOGIC; q77 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address78 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce78 : IN STD_LOGIC; q78 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address79 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce79 : IN STD_LOGIC; q79 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address80 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce80 : IN STD_LOGIC; q80 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address81 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce81 : IN STD_LOGIC; q81 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address82 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce82 : IN STD_LOGIC; q82 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address83 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce83 : IN STD_LOGIC; q83 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address84 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce84 : IN STD_LOGIC; q84 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address85 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce85 : IN STD_LOGIC; q85 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address86 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce86 : IN STD_LOGIC; q86 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address87 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce87 : IN STD_LOGIC; q87 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address88 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce88 : IN STD_LOGIC; q88 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address89 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce89 : IN STD_LOGIC; q89 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address90 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce90 : IN STD_LOGIC; q90 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address91 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce91 : IN STD_LOGIC; q91 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address92 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce92 : IN STD_LOGIC; q92 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address93 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce93 : IN STD_LOGIC; q93 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address94 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce94 : IN STD_LOGIC; q94 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address95 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce95 : IN STD_LOGIC; q95 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address96 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce96 : IN STD_LOGIC; q96 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address97 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce97 : IN STD_LOGIC; q97 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address98 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce98 : IN STD_LOGIC; q98 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address99 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce99 : IN STD_LOGIC; q99 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address100 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce100 : IN STD_LOGIC; q100 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address101 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce101 : IN STD_LOGIC; q101 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address102 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce102 : IN STD_LOGIC; q102 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address103 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce103 : IN STD_LOGIC; q103 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address104 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce104 : IN STD_LOGIC; q104 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address105 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce105 : IN STD_LOGIC; q105 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address106 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce106 : IN STD_LOGIC; q106 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address107 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce107 : IN STD_LOGIC; q107 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address108 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce108 : IN STD_LOGIC; q108 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address109 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce109 : IN STD_LOGIC; q109 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address110 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce110 : IN STD_LOGIC; q110 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address111 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce111 : IN STD_LOGIC; q111 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address112 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce112 : IN STD_LOGIC; q112 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address113 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce113 : IN STD_LOGIC; q113 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address114 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce114 : IN STD_LOGIC; q114 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address115 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce115 : IN STD_LOGIC; q115 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address116 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce116 : IN STD_LOGIC; q116 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address117 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce117 : IN STD_LOGIC; q117 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address118 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce118 : IN STD_LOGIC; q118 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address119 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce119 : IN STD_LOGIC; q119 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address120 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce120 : IN STD_LOGIC; q120 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address121 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce121 : IN STD_LOGIC; q121 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address122 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce122 : IN STD_LOGIC; q122 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address123 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce123 : IN STD_LOGIC; q123 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address124 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce124 : IN STD_LOGIC; q124 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address125 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce125 : IN STD_LOGIC; q125 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address126 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce126 : IN STD_LOGIC; q126 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address127 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce127 : IN STD_LOGIC; q127 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address128 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce128 : IN STD_LOGIC; q128 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address129 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce129 : IN STD_LOGIC; q129 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address130 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce130 : IN STD_LOGIC; q130 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address131 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce131 : IN STD_LOGIC; q131 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address132 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce132 : IN STD_LOGIC; q132 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address133 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce133 : IN STD_LOGIC; q133 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address134 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce134 : IN STD_LOGIC; q134 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address135 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce135 : IN STD_LOGIC; q135 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address136 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce136 : IN STD_LOGIC; q136 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address137 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce137 : IN STD_LOGIC; q137 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address138 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce138 : IN STD_LOGIC; q138 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address139 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce139 : IN STD_LOGIC; q139 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address140 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce140 : IN STD_LOGIC; q140 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address141 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce141 : IN STD_LOGIC; q141 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address142 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce142 : IN STD_LOGIC; q142 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address143 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce143 : IN STD_LOGIC; q143 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address144 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce144 : IN STD_LOGIC; q144 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address145 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce145 : IN STD_LOGIC; q145 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address146 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce146 : IN STD_LOGIC; q146 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address147 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce147 : IN STD_LOGIC; q147 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address148 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce148 : IN STD_LOGIC; q148 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address149 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce149 : IN STD_LOGIC; q149 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address150 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce150 : IN STD_LOGIC; q150 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address151 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce151 : IN STD_LOGIC; q151 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address152 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce152 : IN STD_LOGIC; q152 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address153 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce153 : IN STD_LOGIC; q153 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address154 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce154 : IN STD_LOGIC; q154 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address155 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce155 : IN STD_LOGIC; q155 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address156 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce156 : IN STD_LOGIC; q156 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address157 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce157 : IN STD_LOGIC; q157 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address158 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce158 : IN STD_LOGIC; q158 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address159 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce159 : IN STD_LOGIC; q159 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address160 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce160 : IN STD_LOGIC; q160 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address161 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce161 : IN STD_LOGIC; q161 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address162 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce162 : IN STD_LOGIC; q162 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address163 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce163 : IN STD_LOGIC; q163 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address164 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce164 : IN STD_LOGIC; q164 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address165 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce165 : IN STD_LOGIC; q165 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address166 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce166 : IN STD_LOGIC; q166 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address167 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce167 : IN STD_LOGIC; q167 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address168 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce168 : IN STD_LOGIC; q168 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address169 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce169 : IN STD_LOGIC; q169 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address170 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce170 : IN STD_LOGIC; q170 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address171 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce171 : IN STD_LOGIC; q171 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address172 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce172 : IN STD_LOGIC; q172 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address173 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce173 : IN STD_LOGIC; q173 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address174 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce174 : IN STD_LOGIC; q174 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address175 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce175 : IN STD_LOGIC; q175 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address176 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce176 : IN STD_LOGIC; q176 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address177 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce177 : IN STD_LOGIC; q177 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address178 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce178 : IN STD_LOGIC; q178 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address179 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce179 : IN STD_LOGIC; q179 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address180 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce180 : IN STD_LOGIC; q180 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address181 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce181 : IN STD_LOGIC; q181 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address182 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce182 : IN STD_LOGIC; q182 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address183 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce183 : IN STD_LOGIC; q183 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address184 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce184 : IN STD_LOGIC; q184 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address185 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce185 : IN STD_LOGIC; q185 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address186 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce186 : IN STD_LOGIC; q186 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address187 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce187 : IN STD_LOGIC; q187 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address188 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce188 : IN STD_LOGIC; q188 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address189 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce189 : IN STD_LOGIC; q189 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address190 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce190 : IN STD_LOGIC; q190 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address191 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce191 : IN STD_LOGIC; q191 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address192 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce192 : IN STD_LOGIC; q192 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address193 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce193 : IN STD_LOGIC; q193 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address194 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce194 : IN STD_LOGIC; q194 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address195 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce195 : IN STD_LOGIC; q195 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address196 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce196 : IN STD_LOGIC; q196 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address197 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce197 : IN STD_LOGIC; q197 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address198 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce198 : IN STD_LOGIC; q198 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address199 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce199 : IN STD_LOGIC; q199 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of aestest_sboxes is component aestest_sboxes_rom is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR; addr2 : IN STD_LOGIC_VECTOR; ce2 : IN STD_LOGIC; q2 : OUT STD_LOGIC_VECTOR; addr3 : IN STD_LOGIC_VECTOR; ce3 : IN STD_LOGIC; q3 : OUT STD_LOGIC_VECTOR; addr4 : IN STD_LOGIC_VECTOR; ce4 : IN STD_LOGIC; q4 : OUT STD_LOGIC_VECTOR; addr5 : IN STD_LOGIC_VECTOR; ce5 : IN STD_LOGIC; q5 : OUT STD_LOGIC_VECTOR; addr6 : IN STD_LOGIC_VECTOR; ce6 : IN STD_LOGIC; q6 : OUT STD_LOGIC_VECTOR; addr7 : IN STD_LOGIC_VECTOR; ce7 : IN STD_LOGIC; q7 : OUT STD_LOGIC_VECTOR; addr8 : IN STD_LOGIC_VECTOR; ce8 : IN STD_LOGIC; q8 : OUT STD_LOGIC_VECTOR; addr9 : IN STD_LOGIC_VECTOR; ce9 : IN STD_LOGIC; q9 : OUT STD_LOGIC_VECTOR; addr10 : IN STD_LOGIC_VECTOR; ce10 : IN STD_LOGIC; q10 : OUT STD_LOGIC_VECTOR; addr11 : IN STD_LOGIC_VECTOR; ce11 : IN STD_LOGIC; q11 : OUT STD_LOGIC_VECTOR; addr12 : IN STD_LOGIC_VECTOR; ce12 : IN STD_LOGIC; q12 : OUT STD_LOGIC_VECTOR; addr13 : IN STD_LOGIC_VECTOR; ce13 : IN STD_LOGIC; q13 : OUT STD_LOGIC_VECTOR; addr14 : IN STD_LOGIC_VECTOR; ce14 : IN STD_LOGIC; q14 : OUT STD_LOGIC_VECTOR; addr15 : IN STD_LOGIC_VECTOR; ce15 : IN STD_LOGIC; q15 : OUT STD_LOGIC_VECTOR; addr16 : IN STD_LOGIC_VECTOR; ce16 : IN STD_LOGIC; q16 : OUT STD_LOGIC_VECTOR; addr17 : IN STD_LOGIC_VECTOR; ce17 : IN STD_LOGIC; q17 : OUT STD_LOGIC_VECTOR; addr18 : IN STD_LOGIC_VECTOR; ce18 : IN STD_LOGIC; q18 : OUT STD_LOGIC_VECTOR; addr19 : IN STD_LOGIC_VECTOR; ce19 : IN STD_LOGIC; q19 : OUT STD_LOGIC_VECTOR; addr20 : IN STD_LOGIC_VECTOR; ce20 : IN STD_LOGIC; q20 : OUT STD_LOGIC_VECTOR; addr21 : IN STD_LOGIC_VECTOR; ce21 : IN STD_LOGIC; q21 : OUT STD_LOGIC_VECTOR; addr22 : IN STD_LOGIC_VECTOR; ce22 : IN STD_LOGIC; q22 : OUT STD_LOGIC_VECTOR; addr23 : IN STD_LOGIC_VECTOR; ce23 : IN STD_LOGIC; q23 : OUT STD_LOGIC_VECTOR; addr24 : IN STD_LOGIC_VECTOR; ce24 : IN STD_LOGIC; q24 : OUT STD_LOGIC_VECTOR; addr25 : IN STD_LOGIC_VECTOR; ce25 : IN STD_LOGIC; q25 : OUT STD_LOGIC_VECTOR; addr26 : IN STD_LOGIC_VECTOR; ce26 : IN STD_LOGIC; q26 : OUT STD_LOGIC_VECTOR; addr27 : IN STD_LOGIC_VECTOR; ce27 : IN STD_LOGIC; q27 : OUT STD_LOGIC_VECTOR; addr28 : IN STD_LOGIC_VECTOR; ce28 : IN STD_LOGIC; q28 : OUT STD_LOGIC_VECTOR; addr29 : IN STD_LOGIC_VECTOR; ce29 : IN STD_LOGIC; q29 : OUT STD_LOGIC_VECTOR; addr30 : IN STD_LOGIC_VECTOR; ce30 : IN STD_LOGIC; q30 : OUT STD_LOGIC_VECTOR; addr31 : IN STD_LOGIC_VECTOR; ce31 : IN STD_LOGIC; q31 : OUT STD_LOGIC_VECTOR; addr32 : IN STD_LOGIC_VECTOR; ce32 : IN STD_LOGIC; q32 : OUT STD_LOGIC_VECTOR; addr33 : IN STD_LOGIC_VECTOR; ce33 : IN STD_LOGIC; q33 : OUT STD_LOGIC_VECTOR; addr34 : IN STD_LOGIC_VECTOR; ce34 : IN STD_LOGIC; q34 : OUT STD_LOGIC_VECTOR; addr35 : IN STD_LOGIC_VECTOR; ce35 : IN STD_LOGIC; q35 : OUT STD_LOGIC_VECTOR; addr36 : IN STD_LOGIC_VECTOR; ce36 : IN STD_LOGIC; q36 : OUT STD_LOGIC_VECTOR; addr37 : IN STD_LOGIC_VECTOR; ce37 : IN STD_LOGIC; q37 : OUT STD_LOGIC_VECTOR; addr38 : IN STD_LOGIC_VECTOR; ce38 : IN STD_LOGIC; q38 : OUT STD_LOGIC_VECTOR; addr39 : IN STD_LOGIC_VECTOR; ce39 : IN STD_LOGIC; q39 : OUT STD_LOGIC_VECTOR; addr40 : IN STD_LOGIC_VECTOR; ce40 : IN STD_LOGIC; q40 : OUT STD_LOGIC_VECTOR; addr41 : IN STD_LOGIC_VECTOR; ce41 : IN STD_LOGIC; q41 : OUT STD_LOGIC_VECTOR; addr42 : IN STD_LOGIC_VECTOR; ce42 : IN STD_LOGIC; q42 : OUT STD_LOGIC_VECTOR; addr43 : IN STD_LOGIC_VECTOR; ce43 : IN STD_LOGIC; q43 : OUT STD_LOGIC_VECTOR; addr44 : IN STD_LOGIC_VECTOR; ce44 : IN STD_LOGIC; q44 : OUT STD_LOGIC_VECTOR; addr45 : IN STD_LOGIC_VECTOR; ce45 : IN STD_LOGIC; q45 : OUT STD_LOGIC_VECTOR; addr46 : IN STD_LOGIC_VECTOR; ce46 : IN STD_LOGIC; q46 : OUT STD_LOGIC_VECTOR; addr47 : IN STD_LOGIC_VECTOR; ce47 : IN STD_LOGIC; q47 : OUT STD_LOGIC_VECTOR; addr48 : IN STD_LOGIC_VECTOR; ce48 : IN STD_LOGIC; q48 : OUT STD_LOGIC_VECTOR; addr49 : IN STD_LOGIC_VECTOR; ce49 : IN STD_LOGIC; q49 : OUT STD_LOGIC_VECTOR; addr50 : IN STD_LOGIC_VECTOR; ce50 : IN STD_LOGIC; q50 : OUT STD_LOGIC_VECTOR; addr51 : IN STD_LOGIC_VECTOR; ce51 : IN STD_LOGIC; q51 : OUT STD_LOGIC_VECTOR; addr52 : IN STD_LOGIC_VECTOR; ce52 : IN STD_LOGIC; q52 : OUT STD_LOGIC_VECTOR; addr53 : IN STD_LOGIC_VECTOR; ce53 : IN STD_LOGIC; q53 : OUT STD_LOGIC_VECTOR; addr54 : IN STD_LOGIC_VECTOR; ce54 : IN STD_LOGIC; q54 : OUT STD_LOGIC_VECTOR; addr55 : IN STD_LOGIC_VECTOR; ce55 : IN STD_LOGIC; q55 : OUT STD_LOGIC_VECTOR; addr56 : IN STD_LOGIC_VECTOR; ce56 : IN STD_LOGIC; q56 : OUT STD_LOGIC_VECTOR; addr57 : IN STD_LOGIC_VECTOR; ce57 : IN STD_LOGIC; q57 : OUT STD_LOGIC_VECTOR; addr58 : IN STD_LOGIC_VECTOR; ce58 : IN STD_LOGIC; q58 : OUT STD_LOGIC_VECTOR; addr59 : IN STD_LOGIC_VECTOR; ce59 : IN STD_LOGIC; q59 : OUT STD_LOGIC_VECTOR; addr60 : IN STD_LOGIC_VECTOR; ce60 : IN STD_LOGIC; q60 : OUT STD_LOGIC_VECTOR; addr61 : IN STD_LOGIC_VECTOR; ce61 : IN STD_LOGIC; q61 : OUT STD_LOGIC_VECTOR; addr62 : IN STD_LOGIC_VECTOR; ce62 : IN STD_LOGIC; q62 : OUT STD_LOGIC_VECTOR; addr63 : IN STD_LOGIC_VECTOR; ce63 : IN STD_LOGIC; q63 : OUT STD_LOGIC_VECTOR; addr64 : IN STD_LOGIC_VECTOR; ce64 : IN STD_LOGIC; q64 : OUT STD_LOGIC_VECTOR; addr65 : IN STD_LOGIC_VECTOR; ce65 : IN STD_LOGIC; q65 : OUT STD_LOGIC_VECTOR; addr66 : IN STD_LOGIC_VECTOR; ce66 : IN STD_LOGIC; q66 : OUT STD_LOGIC_VECTOR; addr67 : IN STD_LOGIC_VECTOR; ce67 : IN STD_LOGIC; q67 : OUT STD_LOGIC_VECTOR; addr68 : IN STD_LOGIC_VECTOR; ce68 : IN STD_LOGIC; q68 : OUT STD_LOGIC_VECTOR; addr69 : IN STD_LOGIC_VECTOR; ce69 : IN STD_LOGIC; q69 : OUT STD_LOGIC_VECTOR; addr70 : IN STD_LOGIC_VECTOR; ce70 : IN STD_LOGIC; q70 : OUT STD_LOGIC_VECTOR; addr71 : IN STD_LOGIC_VECTOR; ce71 : IN STD_LOGIC; q71 : OUT STD_LOGIC_VECTOR; addr72 : IN STD_LOGIC_VECTOR; ce72 : IN STD_LOGIC; q72 : OUT STD_LOGIC_VECTOR; addr73 : IN STD_LOGIC_VECTOR; ce73 : IN STD_LOGIC; q73 : OUT STD_LOGIC_VECTOR; addr74 : IN STD_LOGIC_VECTOR; ce74 : IN STD_LOGIC; q74 : OUT STD_LOGIC_VECTOR; addr75 : IN STD_LOGIC_VECTOR; ce75 : IN STD_LOGIC; q75 : OUT STD_LOGIC_VECTOR; addr76 : IN STD_LOGIC_VECTOR; ce76 : IN STD_LOGIC; q76 : OUT STD_LOGIC_VECTOR; addr77 : IN STD_LOGIC_VECTOR; ce77 : IN STD_LOGIC; q77 : OUT STD_LOGIC_VECTOR; addr78 : IN STD_LOGIC_VECTOR; ce78 : IN STD_LOGIC; q78 : OUT STD_LOGIC_VECTOR; addr79 : IN STD_LOGIC_VECTOR; ce79 : IN STD_LOGIC; q79 : OUT STD_LOGIC_VECTOR; addr80 : IN STD_LOGIC_VECTOR; ce80 : IN STD_LOGIC; q80 : OUT STD_LOGIC_VECTOR; addr81 : IN STD_LOGIC_VECTOR; ce81 : IN STD_LOGIC; q81 : OUT STD_LOGIC_VECTOR; addr82 : IN STD_LOGIC_VECTOR; ce82 : IN STD_LOGIC; q82 : OUT STD_LOGIC_VECTOR; addr83 : IN STD_LOGIC_VECTOR; ce83 : IN STD_LOGIC; q83 : OUT STD_LOGIC_VECTOR; addr84 : IN STD_LOGIC_VECTOR; ce84 : IN STD_LOGIC; q84 : OUT STD_LOGIC_VECTOR; addr85 : IN STD_LOGIC_VECTOR; ce85 : IN STD_LOGIC; q85 : OUT STD_LOGIC_VECTOR; addr86 : IN STD_LOGIC_VECTOR; ce86 : IN STD_LOGIC; q86 : OUT STD_LOGIC_VECTOR; addr87 : IN STD_LOGIC_VECTOR; ce87 : IN STD_LOGIC; q87 : OUT STD_LOGIC_VECTOR; addr88 : IN STD_LOGIC_VECTOR; ce88 : IN STD_LOGIC; q88 : OUT STD_LOGIC_VECTOR; addr89 : IN STD_LOGIC_VECTOR; ce89 : IN STD_LOGIC; q89 : OUT STD_LOGIC_VECTOR; addr90 : IN STD_LOGIC_VECTOR; ce90 : IN STD_LOGIC; q90 : OUT STD_LOGIC_VECTOR; addr91 : IN STD_LOGIC_VECTOR; ce91 : IN STD_LOGIC; q91 : OUT STD_LOGIC_VECTOR; addr92 : IN STD_LOGIC_VECTOR; ce92 : IN STD_LOGIC; q92 : OUT STD_LOGIC_VECTOR; addr93 : IN STD_LOGIC_VECTOR; ce93 : IN STD_LOGIC; q93 : OUT STD_LOGIC_VECTOR; addr94 : IN STD_LOGIC_VECTOR; ce94 : IN STD_LOGIC; q94 : OUT STD_LOGIC_VECTOR; addr95 : IN STD_LOGIC_VECTOR; ce95 : IN STD_LOGIC; q95 : OUT STD_LOGIC_VECTOR; addr96 : IN STD_LOGIC_VECTOR; ce96 : IN STD_LOGIC; q96 : OUT STD_LOGIC_VECTOR; addr97 : IN STD_LOGIC_VECTOR; ce97 : IN STD_LOGIC; q97 : OUT STD_LOGIC_VECTOR; addr98 : IN STD_LOGIC_VECTOR; ce98 : IN STD_LOGIC; q98 : OUT STD_LOGIC_VECTOR; addr99 : IN STD_LOGIC_VECTOR; ce99 : IN STD_LOGIC; q99 : OUT STD_LOGIC_VECTOR; addr100 : IN STD_LOGIC_VECTOR; ce100 : IN STD_LOGIC; q100 : OUT STD_LOGIC_VECTOR; addr101 : IN STD_LOGIC_VECTOR; ce101 : IN STD_LOGIC; q101 : OUT STD_LOGIC_VECTOR; addr102 : IN STD_LOGIC_VECTOR; ce102 : IN STD_LOGIC; q102 : OUT STD_LOGIC_VECTOR; addr103 : IN STD_LOGIC_VECTOR; ce103 : IN STD_LOGIC; q103 : OUT STD_LOGIC_VECTOR; addr104 : IN STD_LOGIC_VECTOR; ce104 : IN STD_LOGIC; q104 : OUT STD_LOGIC_VECTOR; addr105 : IN STD_LOGIC_VECTOR; ce105 : IN STD_LOGIC; q105 : OUT STD_LOGIC_VECTOR; addr106 : IN STD_LOGIC_VECTOR; ce106 : IN STD_LOGIC; q106 : OUT STD_LOGIC_VECTOR; addr107 : IN STD_LOGIC_VECTOR; ce107 : IN STD_LOGIC; q107 : OUT STD_LOGIC_VECTOR; addr108 : IN STD_LOGIC_VECTOR; ce108 : IN STD_LOGIC; q108 : OUT STD_LOGIC_VECTOR; addr109 : IN STD_LOGIC_VECTOR; ce109 : IN STD_LOGIC; q109 : OUT STD_LOGIC_VECTOR; addr110 : IN STD_LOGIC_VECTOR; ce110 : IN STD_LOGIC; q110 : OUT STD_LOGIC_VECTOR; addr111 : IN STD_LOGIC_VECTOR; ce111 : IN STD_LOGIC; q111 : OUT STD_LOGIC_VECTOR; addr112 : IN STD_LOGIC_VECTOR; ce112 : IN STD_LOGIC; q112 : OUT STD_LOGIC_VECTOR; addr113 : IN STD_LOGIC_VECTOR; ce113 : IN STD_LOGIC; q113 : OUT STD_LOGIC_VECTOR; addr114 : IN STD_LOGIC_VECTOR; ce114 : IN STD_LOGIC; q114 : OUT STD_LOGIC_VECTOR; addr115 : IN STD_LOGIC_VECTOR; ce115 : IN STD_LOGIC; q115 : OUT STD_LOGIC_VECTOR; addr116 : IN STD_LOGIC_VECTOR; ce116 : IN STD_LOGIC; q116 : OUT STD_LOGIC_VECTOR; addr117 : IN STD_LOGIC_VECTOR; ce117 : IN STD_LOGIC; q117 : OUT STD_LOGIC_VECTOR; addr118 : IN STD_LOGIC_VECTOR; ce118 : IN STD_LOGIC; q118 : OUT STD_LOGIC_VECTOR; addr119 : IN STD_LOGIC_VECTOR; ce119 : IN STD_LOGIC; q119 : OUT STD_LOGIC_VECTOR; addr120 : IN STD_LOGIC_VECTOR; ce120 : IN STD_LOGIC; q120 : OUT STD_LOGIC_VECTOR; addr121 : IN STD_LOGIC_VECTOR; ce121 : IN STD_LOGIC; q121 : OUT STD_LOGIC_VECTOR; addr122 : IN STD_LOGIC_VECTOR; ce122 : IN STD_LOGIC; q122 : OUT STD_LOGIC_VECTOR; addr123 : IN STD_LOGIC_VECTOR; ce123 : IN STD_LOGIC; q123 : OUT STD_LOGIC_VECTOR; addr124 : IN STD_LOGIC_VECTOR; ce124 : IN STD_LOGIC; q124 : OUT STD_LOGIC_VECTOR; addr125 : IN STD_LOGIC_VECTOR; ce125 : IN STD_LOGIC; q125 : OUT STD_LOGIC_VECTOR; addr126 : IN STD_LOGIC_VECTOR; ce126 : IN STD_LOGIC; q126 : OUT STD_LOGIC_VECTOR; addr127 : IN STD_LOGIC_VECTOR; ce127 : IN STD_LOGIC; q127 : OUT STD_LOGIC_VECTOR; addr128 : IN STD_LOGIC_VECTOR; ce128 : IN STD_LOGIC; q128 : OUT STD_LOGIC_VECTOR; addr129 : IN STD_LOGIC_VECTOR; ce129 : IN STD_LOGIC; q129 : OUT STD_LOGIC_VECTOR; addr130 : IN STD_LOGIC_VECTOR; ce130 : IN STD_LOGIC; q130 : OUT STD_LOGIC_VECTOR; addr131 : IN STD_LOGIC_VECTOR; ce131 : IN STD_LOGIC; q131 : OUT STD_LOGIC_VECTOR; addr132 : IN STD_LOGIC_VECTOR; ce132 : IN STD_LOGIC; q132 : OUT STD_LOGIC_VECTOR; addr133 : IN STD_LOGIC_VECTOR; ce133 : IN STD_LOGIC; q133 : OUT STD_LOGIC_VECTOR; addr134 : IN STD_LOGIC_VECTOR; ce134 : IN STD_LOGIC; q134 : OUT STD_LOGIC_VECTOR; addr135 : IN STD_LOGIC_VECTOR; ce135 : IN STD_LOGIC; q135 : OUT STD_LOGIC_VECTOR; addr136 : IN STD_LOGIC_VECTOR; ce136 : IN STD_LOGIC; q136 : OUT STD_LOGIC_VECTOR; addr137 : IN STD_LOGIC_VECTOR; ce137 : IN STD_LOGIC; q137 : OUT STD_LOGIC_VECTOR; addr138 : IN STD_LOGIC_VECTOR; ce138 : IN STD_LOGIC; q138 : OUT STD_LOGIC_VECTOR; addr139 : IN STD_LOGIC_VECTOR; ce139 : IN STD_LOGIC; q139 : OUT STD_LOGIC_VECTOR; addr140 : IN STD_LOGIC_VECTOR; ce140 : IN STD_LOGIC; q140 : OUT STD_LOGIC_VECTOR; addr141 : IN STD_LOGIC_VECTOR; ce141 : IN STD_LOGIC; q141 : OUT STD_LOGIC_VECTOR; addr142 : IN STD_LOGIC_VECTOR; ce142 : IN STD_LOGIC; q142 : OUT STD_LOGIC_VECTOR; addr143 : IN STD_LOGIC_VECTOR; ce143 : IN STD_LOGIC; q143 : OUT STD_LOGIC_VECTOR; addr144 : IN STD_LOGIC_VECTOR; ce144 : IN STD_LOGIC; q144 : OUT STD_LOGIC_VECTOR; addr145 : IN STD_LOGIC_VECTOR; ce145 : IN STD_LOGIC; q145 : OUT STD_LOGIC_VECTOR; addr146 : IN STD_LOGIC_VECTOR; ce146 : IN STD_LOGIC; q146 : OUT STD_LOGIC_VECTOR; addr147 : IN STD_LOGIC_VECTOR; ce147 : IN STD_LOGIC; q147 : OUT STD_LOGIC_VECTOR; addr148 : IN STD_LOGIC_VECTOR; ce148 : IN STD_LOGIC; q148 : OUT STD_LOGIC_VECTOR; addr149 : IN STD_LOGIC_VECTOR; ce149 : IN STD_LOGIC; q149 : OUT STD_LOGIC_VECTOR; addr150 : IN STD_LOGIC_VECTOR; ce150 : IN STD_LOGIC; q150 : OUT STD_LOGIC_VECTOR; addr151 : IN STD_LOGIC_VECTOR; ce151 : IN STD_LOGIC; q151 : OUT STD_LOGIC_VECTOR; addr152 : IN STD_LOGIC_VECTOR; ce152 : IN STD_LOGIC; q152 : OUT STD_LOGIC_VECTOR; addr153 : IN STD_LOGIC_VECTOR; ce153 : IN STD_LOGIC; q153 : OUT STD_LOGIC_VECTOR; addr154 : IN STD_LOGIC_VECTOR; ce154 : IN STD_LOGIC; q154 : OUT STD_LOGIC_VECTOR; addr155 : IN STD_LOGIC_VECTOR; ce155 : IN STD_LOGIC; q155 : OUT STD_LOGIC_VECTOR; addr156 : IN STD_LOGIC_VECTOR; ce156 : IN STD_LOGIC; q156 : OUT STD_LOGIC_VECTOR; addr157 : IN STD_LOGIC_VECTOR; ce157 : IN STD_LOGIC; q157 : OUT STD_LOGIC_VECTOR; addr158 : IN STD_LOGIC_VECTOR; ce158 : IN STD_LOGIC; q158 : OUT STD_LOGIC_VECTOR; addr159 : IN STD_LOGIC_VECTOR; ce159 : IN STD_LOGIC; q159 : OUT STD_LOGIC_VECTOR; addr160 : IN STD_LOGIC_VECTOR; ce160 : IN STD_LOGIC; q160 : OUT STD_LOGIC_VECTOR; addr161 : IN STD_LOGIC_VECTOR; ce161 : IN STD_LOGIC; q161 : OUT STD_LOGIC_VECTOR; addr162 : IN STD_LOGIC_VECTOR; ce162 : IN STD_LOGIC; q162 : OUT STD_LOGIC_VECTOR; addr163 : IN STD_LOGIC_VECTOR; ce163 : IN STD_LOGIC; q163 : OUT STD_LOGIC_VECTOR; addr164 : IN STD_LOGIC_VECTOR; ce164 : IN STD_LOGIC; q164 : OUT STD_LOGIC_VECTOR; addr165 : IN STD_LOGIC_VECTOR; ce165 : IN STD_LOGIC; q165 : OUT STD_LOGIC_VECTOR; addr166 : IN STD_LOGIC_VECTOR; ce166 : IN STD_LOGIC; q166 : OUT STD_LOGIC_VECTOR; addr167 : IN STD_LOGIC_VECTOR; ce167 : IN STD_LOGIC; q167 : OUT STD_LOGIC_VECTOR; addr168 : IN STD_LOGIC_VECTOR; ce168 : IN STD_LOGIC; q168 : OUT STD_LOGIC_VECTOR; addr169 : IN STD_LOGIC_VECTOR; ce169 : IN STD_LOGIC; q169 : OUT STD_LOGIC_VECTOR; addr170 : IN STD_LOGIC_VECTOR; ce170 : IN STD_LOGIC; q170 : OUT STD_LOGIC_VECTOR; addr171 : IN STD_LOGIC_VECTOR; ce171 : IN STD_LOGIC; q171 : OUT STD_LOGIC_VECTOR; addr172 : IN STD_LOGIC_VECTOR; ce172 : IN STD_LOGIC; q172 : OUT STD_LOGIC_VECTOR; addr173 : IN STD_LOGIC_VECTOR; ce173 : IN STD_LOGIC; q173 : OUT STD_LOGIC_VECTOR; addr174 : IN STD_LOGIC_VECTOR; ce174 : IN STD_LOGIC; q174 : OUT STD_LOGIC_VECTOR; addr175 : IN STD_LOGIC_VECTOR; ce175 : IN STD_LOGIC; q175 : OUT STD_LOGIC_VECTOR; addr176 : IN STD_LOGIC_VECTOR; ce176 : IN STD_LOGIC; q176 : OUT STD_LOGIC_VECTOR; addr177 : IN STD_LOGIC_VECTOR; ce177 : IN STD_LOGIC; q177 : OUT STD_LOGIC_VECTOR; addr178 : IN STD_LOGIC_VECTOR; ce178 : IN STD_LOGIC; q178 : OUT STD_LOGIC_VECTOR; addr179 : IN STD_LOGIC_VECTOR; ce179 : IN STD_LOGIC; q179 : OUT STD_LOGIC_VECTOR; addr180 : IN STD_LOGIC_VECTOR; ce180 : IN STD_LOGIC; q180 : OUT STD_LOGIC_VECTOR; addr181 : IN STD_LOGIC_VECTOR; ce181 : IN STD_LOGIC; q181 : OUT STD_LOGIC_VECTOR; addr182 : IN STD_LOGIC_VECTOR; ce182 : IN STD_LOGIC; q182 : OUT STD_LOGIC_VECTOR; addr183 : IN STD_LOGIC_VECTOR; ce183 : IN STD_LOGIC; q183 : OUT STD_LOGIC_VECTOR; addr184 : IN STD_LOGIC_VECTOR; ce184 : IN STD_LOGIC; q184 : OUT STD_LOGIC_VECTOR; addr185 : IN STD_LOGIC_VECTOR; ce185 : IN STD_LOGIC; q185 : OUT STD_LOGIC_VECTOR; addr186 : IN STD_LOGIC_VECTOR; ce186 : IN STD_LOGIC; q186 : OUT STD_LOGIC_VECTOR; addr187 : IN STD_LOGIC_VECTOR; ce187 : IN STD_LOGIC; q187 : OUT STD_LOGIC_VECTOR; addr188 : IN STD_LOGIC_VECTOR; ce188 : IN STD_LOGIC; q188 : OUT STD_LOGIC_VECTOR; addr189 : IN STD_LOGIC_VECTOR; ce189 : IN STD_LOGIC; q189 : OUT STD_LOGIC_VECTOR; addr190 : IN STD_LOGIC_VECTOR; ce190 : IN STD_LOGIC; q190 : OUT STD_LOGIC_VECTOR; addr191 : IN STD_LOGIC_VECTOR; ce191 : IN STD_LOGIC; q191 : OUT STD_LOGIC_VECTOR; addr192 : IN STD_LOGIC_VECTOR; ce192 : IN STD_LOGIC; q192 : OUT STD_LOGIC_VECTOR; addr193 : IN STD_LOGIC_VECTOR; ce193 : IN STD_LOGIC; q193 : OUT STD_LOGIC_VECTOR; addr194 : IN STD_LOGIC_VECTOR; ce194 : IN STD_LOGIC; q194 : OUT STD_LOGIC_VECTOR; addr195 : IN STD_LOGIC_VECTOR; ce195 : IN STD_LOGIC; q195 : OUT STD_LOGIC_VECTOR; addr196 : IN STD_LOGIC_VECTOR; ce196 : IN STD_LOGIC; q196 : OUT STD_LOGIC_VECTOR; addr197 : IN STD_LOGIC_VECTOR; ce197 : IN STD_LOGIC; q197 : OUT STD_LOGIC_VECTOR; addr198 : IN STD_LOGIC_VECTOR; ce198 : IN STD_LOGIC; q198 : OUT STD_LOGIC_VECTOR; addr199 : IN STD_LOGIC_VECTOR; ce199 : IN STD_LOGIC; q199 : OUT STD_LOGIC_VECTOR); end component; begin aestest_sboxes_rom_U : component aestest_sboxes_rom port map ( clk => clk, addr0 => address0, ce0 => ce0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1, addr2 => address2, ce2 => ce2, q2 => q2, addr3 => address3, ce3 => ce3, q3 => q3, addr4 => address4, ce4 => ce4, q4 => q4, addr5 => address5, ce5 => ce5, q5 => q5, addr6 => address6, ce6 => ce6, q6 => q6, addr7 => address7, ce7 => ce7, q7 => q7, addr8 => address8, ce8 => ce8, q8 => q8, addr9 => address9, ce9 => ce9, q9 => q9, addr10 => address10, ce10 => ce10, q10 => q10, addr11 => address11, ce11 => ce11, q11 => q11, addr12 => address12, ce12 => ce12, q12 => q12, addr13 => address13, ce13 => ce13, q13 => q13, addr14 => address14, ce14 => ce14, q14 => q14, addr15 => address15, ce15 => ce15, q15 => q15, addr16 => address16, ce16 => ce16, q16 => q16, addr17 => address17, ce17 => ce17, q17 => q17, addr18 => address18, ce18 => ce18, q18 => q18, addr19 => address19, ce19 => ce19, q19 => q19, addr20 => address20, ce20 => ce20, q20 => q20, addr21 => address21, ce21 => ce21, q21 => q21, addr22 => address22, ce22 => ce22, q22 => q22, addr23 => address23, ce23 => ce23, q23 => q23, addr24 => address24, ce24 => ce24, q24 => q24, addr25 => address25, ce25 => ce25, q25 => q25, addr26 => address26, ce26 => ce26, q26 => q26, addr27 => address27, ce27 => ce27, q27 => q27, addr28 => address28, ce28 => ce28, q28 => q28, addr29 => address29, ce29 => ce29, q29 => q29, addr30 => address30, ce30 => ce30, q30 => q30, addr31 => address31, ce31 => ce31, q31 => q31, addr32 => address32, ce32 => ce32, q32 => q32, addr33 => address33, ce33 => ce33, q33 => q33, addr34 => address34, ce34 => ce34, q34 => q34, addr35 => address35, ce35 => ce35, q35 => q35, addr36 => address36, ce36 => ce36, q36 => q36, addr37 => address37, ce37 => ce37, q37 => q37, addr38 => address38, ce38 => ce38, q38 => q38, addr39 => address39, ce39 => ce39, q39 => q39, addr40 => address40, ce40 => ce40, q40 => q40, addr41 => address41, ce41 => ce41, q41 => q41, addr42 => address42, ce42 => ce42, q42 => q42, addr43 => address43, ce43 => ce43, q43 => q43, addr44 => address44, ce44 => ce44, q44 => q44, addr45 => address45, ce45 => ce45, q45 => q45, addr46 => address46, ce46 => ce46, q46 => q46, addr47 => address47, ce47 => ce47, q47 => q47, addr48 => address48, ce48 => ce48, q48 => q48, addr49 => address49, ce49 => ce49, q49 => q49, addr50 => address50, ce50 => ce50, q50 => q50, addr51 => address51, ce51 => ce51, q51 => q51, addr52 => address52, ce52 => ce52, q52 => q52, addr53 => address53, ce53 => ce53, q53 => q53, addr54 => address54, ce54 => ce54, q54 => q54, addr55 => address55, ce55 => ce55, q55 => q55, addr56 => address56, ce56 => ce56, q56 => q56, addr57 => address57, ce57 => ce57, q57 => q57, addr58 => address58, ce58 => ce58, q58 => q58, addr59 => address59, ce59 => ce59, q59 => q59, addr60 => address60, ce60 => ce60, q60 => q60, addr61 => address61, ce61 => ce61, q61 => q61, addr62 => address62, ce62 => ce62, q62 => q62, addr63 => address63, ce63 => ce63, q63 => q63, addr64 => address64, ce64 => ce64, q64 => q64, addr65 => address65, ce65 => ce65, q65 => q65, addr66 => address66, ce66 => ce66, q66 => q66, addr67 => address67, ce67 => ce67, q67 => q67, addr68 => address68, ce68 => ce68, q68 => q68, addr69 => address69, ce69 => ce69, q69 => q69, addr70 => address70, ce70 => ce70, q70 => q70, addr71 => address71, ce71 => ce71, q71 => q71, addr72 => address72, ce72 => ce72, q72 => q72, addr73 => address73, ce73 => ce73, q73 => q73, addr74 => address74, ce74 => ce74, q74 => q74, addr75 => address75, ce75 => ce75, q75 => q75, addr76 => address76, ce76 => ce76, q76 => q76, addr77 => address77, ce77 => ce77, q77 => q77, addr78 => address78, ce78 => ce78, q78 => q78, addr79 => address79, ce79 => ce79, q79 => q79, addr80 => address80, ce80 => ce80, q80 => q80, addr81 => address81, ce81 => ce81, q81 => q81, addr82 => address82, ce82 => ce82, q82 => q82, addr83 => address83, ce83 => ce83, q83 => q83, addr84 => address84, ce84 => ce84, q84 => q84, addr85 => address85, ce85 => ce85, q85 => q85, addr86 => address86, ce86 => ce86, q86 => q86, addr87 => address87, ce87 => ce87, q87 => q87, addr88 => address88, ce88 => ce88, q88 => q88, addr89 => address89, ce89 => ce89, q89 => q89, addr90 => address90, ce90 => ce90, q90 => q90, addr91 => address91, ce91 => ce91, q91 => q91, addr92 => address92, ce92 => ce92, q92 => q92, addr93 => address93, ce93 => ce93, q93 => q93, addr94 => address94, ce94 => ce94, q94 => q94, addr95 => address95, ce95 => ce95, q95 => q95, addr96 => address96, ce96 => ce96, q96 => q96, addr97 => address97, ce97 => ce97, q97 => q97, addr98 => address98, ce98 => ce98, q98 => q98, addr99 => address99, ce99 => ce99, q99 => q99, addr100 => address100, ce100 => ce100, q100 => q100, addr101 => address101, ce101 => ce101, q101 => q101, addr102 => address102, ce102 => ce102, q102 => q102, addr103 => address103, ce103 => ce103, q103 => q103, addr104 => address104, ce104 => ce104, q104 => q104, addr105 => address105, ce105 => ce105, q105 => q105, addr106 => address106, ce106 => ce106, q106 => q106, addr107 => address107, ce107 => ce107, q107 => q107, addr108 => address108, ce108 => ce108, q108 => q108, addr109 => address109, ce109 => ce109, q109 => q109, addr110 => address110, ce110 => ce110, q110 => q110, addr111 => address111, ce111 => ce111, q111 => q111, addr112 => address112, ce112 => ce112, q112 => q112, addr113 => address113, ce113 => ce113, q113 => q113, addr114 => address114, ce114 => ce114, q114 => q114, addr115 => address115, ce115 => ce115, q115 => q115, addr116 => address116, ce116 => ce116, q116 => q116, addr117 => address117, ce117 => ce117, q117 => q117, addr118 => address118, ce118 => ce118, q118 => q118, addr119 => address119, ce119 => ce119, q119 => q119, addr120 => address120, ce120 => ce120, q120 => q120, addr121 => address121, ce121 => ce121, q121 => q121, addr122 => address122, ce122 => ce122, q122 => q122, addr123 => address123, ce123 => ce123, q123 => q123, addr124 => address124, ce124 => ce124, q124 => q124, addr125 => address125, ce125 => ce125, q125 => q125, addr126 => address126, ce126 => ce126, q126 => q126, addr127 => address127, ce127 => ce127, q127 => q127, addr128 => address128, ce128 => ce128, q128 => q128, addr129 => address129, ce129 => ce129, q129 => q129, addr130 => address130, ce130 => ce130, q130 => q130, addr131 => address131, ce131 => ce131, q131 => q131, addr132 => address132, ce132 => ce132, q132 => q132, addr133 => address133, ce133 => ce133, q133 => q133, addr134 => address134, ce134 => ce134, q134 => q134, addr135 => address135, ce135 => ce135, q135 => q135, addr136 => address136, ce136 => ce136, q136 => q136, addr137 => address137, ce137 => ce137, q137 => q137, addr138 => address138, ce138 => ce138, q138 => q138, addr139 => address139, ce139 => ce139, q139 => q139, addr140 => address140, ce140 => ce140, q140 => q140, addr141 => address141, ce141 => ce141, q141 => q141, addr142 => address142, ce142 => ce142, q142 => q142, addr143 => address143, ce143 => ce143, q143 => q143, addr144 => address144, ce144 => ce144, q144 => q144, addr145 => address145, ce145 => ce145, q145 => q145, addr146 => address146, ce146 => ce146, q146 => q146, addr147 => address147, ce147 => ce147, q147 => q147, addr148 => address148, ce148 => ce148, q148 => q148, addr149 => address149, ce149 => ce149, q149 => q149, addr150 => address150, ce150 => ce150, q150 => q150, addr151 => address151, ce151 => ce151, q151 => q151, addr152 => address152, ce152 => ce152, q152 => q152, addr153 => address153, ce153 => ce153, q153 => q153, addr154 => address154, ce154 => ce154, q154 => q154, addr155 => address155, ce155 => ce155, q155 => q155, addr156 => address156, ce156 => ce156, q156 => q156, addr157 => address157, ce157 => ce157, q157 => q157, addr158 => address158, ce158 => ce158, q158 => q158, addr159 => address159, ce159 => ce159, q159 => q159, addr160 => address160, ce160 => ce160, q160 => q160, addr161 => address161, ce161 => ce161, q161 => q161, addr162 => address162, ce162 => ce162, q162 => q162, addr163 => address163, ce163 => ce163, q163 => q163, addr164 => address164, ce164 => ce164, q164 => q164, addr165 => address165, ce165 => ce165, q165 => q165, addr166 => address166, ce166 => ce166, q166 => q166, addr167 => address167, ce167 => ce167, q167 => q167, addr168 => address168, ce168 => ce168, q168 => q168, addr169 => address169, ce169 => ce169, q169 => q169, addr170 => address170, ce170 => ce170, q170 => q170, addr171 => address171, ce171 => ce171, q171 => q171, addr172 => address172, ce172 => ce172, q172 => q172, addr173 => address173, ce173 => ce173, q173 => q173, addr174 => address174, ce174 => ce174, q174 => q174, addr175 => address175, ce175 => ce175, q175 => q175, addr176 => address176, ce176 => ce176, q176 => q176, addr177 => address177, ce177 => ce177, q177 => q177, addr178 => address178, ce178 => ce178, q178 => q178, addr179 => address179, ce179 => ce179, q179 => q179, addr180 => address180, ce180 => ce180, q180 => q180, addr181 => address181, ce181 => ce181, q181 => q181, addr182 => address182, ce182 => ce182, q182 => q182, addr183 => address183, ce183 => ce183, q183 => q183, addr184 => address184, ce184 => ce184, q184 => q184, addr185 => address185, ce185 => ce185, q185 => q185, addr186 => address186, ce186 => ce186, q186 => q186, addr187 => address187, ce187 => ce187, q187 => q187, addr188 => address188, ce188 => ce188, q188 => q188, addr189 => address189, ce189 => ce189, q189 => q189, addr190 => address190, ce190 => ce190, q190 => q190, addr191 => address191, ce191 => ce191, q191 => q191, addr192 => address192, ce192 => ce192, q192 => q192, addr193 => address193, ce193 => ce193, q193 => q193, addr194 => address194, ce194 => ce194, q194 => q194, addr195 => address195, ce195 => ce195, q195 => q195, addr196 => address196, ce196 => ce196, q196 => q196, addr197 => address197, ce197 => ce197, q197 => q197, addr198 => address198, ce198 => ce198, q198 => q198, addr199 => address199, ce199 => ce199, q199 => q199); end architecture;

-------------------------------------------------------------------------------- -- Company: CPE233 -- Engineer: Jacob Hladky -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY rat_sim_tb IS END rat_sim_tb; ARCHITECTURE behavior OF rat_sim_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT rat_wrapper PORT( leds, seg : OUT std_logic_vector(7 downto 0); sel : OUT std_logic_vector(3 downto 0); tx : OUT std_logic; switches : IN std_logic_vector(7 downto 0); rst, clk : IN std_logic; int, rx : IN std_logic); END COMPONENT; --Inputs signal switches : std_logic_vector(7 downto 0) := (others => '0'); signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal int : std_logic := '0'; signal rx : std_logic := '0'; --Outputs signal leds : std_logic_vector(7 downto 0); signal seg : std_logic_vector(7 downto 0); signal sel : std_logic_vector(3 downto 0); signal tx : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: RAT_wrapper PORT MAP ( leds => leds, switches => switches, seg => seg, rx => rx, tx => tx, sel => sel, int => int, rst => rst, clk => clk); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 20 ns rst <= '1'; wait for 20 ns; rst <= '0'; wait for 50 ns; -- let the loop start for i in 0 to 19 loop switches <= x"FF"; -- send the first data int <= '1'; wait for 20 ns; int <= '0'; wait for 120 ns; -- wait for it to be processed switches <= x"aa"; -- send the first data int <= '1'; wait for 20 ns; int <= '0'; wait for 120 ns; -- wait for it to be processed end loop; -- wait for clk_period*5; -- switches <= x"aa"; -- int <= '1'; -- wait for clk_period*12; -- switches <= x"00"; -- wait for clk_period*10; -- switches <= x"FC"; wait; end process; END;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.myTypes.all; entity cw_mem is generic ( MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size OP_CODE_SIZE : integer := 6; -- Op Code Size CW_SIZE : integer := 13); -- Control Word Size port ( OPCODE_IN : in std_logic_vector(5 downto 0); -- Instruction Register CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0) ); end cw_mem; architecture bhe of cw_mem is -- signal OPC : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory type mem_array is array (integer range 0 to 63) of std_logic_vector(12 downto 0); signal cw_mem : mem_array := ( "0000000010001", -- (0X00) R type "0000000010001", -- (0X01) F type "1011000000000", -- (0X02) J "1011011110001", -- (0X03) JAL "1101000000000", -- (0X04) BEQZ "1101100000000", -- (0X05) BNEZ "0000000000000", -- (0X06) BFPT "0000000000000", -- (0X07) BFPT "0001001100001", -- (0X08) ADDI "0000001100001", -- (0X09) ADDUI "0001001100001", -- (0X0A) SUBI "0000001100001", -- (0X0B) SUBUI "0000001100001", -- (0X0C) ANDI "0000001100001", -- (0X0D) ORI "0000001100001", -- (0X0E) XORI "0000000000000", -- (0X0F) LHI -- NOT IMPLEMENTED "0000000000000", -- (0X10) RFE -- NOT IMPLEMENTED "0000000000000", -- (0X11) TRAP -- NOT IMPLEMENTED "0100000000000", -- (0X12) JR "0100011100001", -- (0X13) JALR "0000001100001", -- (0X14) SLLI "0000000000000", -- (0X15) NOP "0000001100001", -- (0X16) SRLI "0000001100001", -- (0X17) SRAI "0000001100001", -- (0X18) SEQI "0000001100001", -- (0X19) SNEI "0000001100001", -- (0X1A) SLTI "0000001100001", -- (0X1B) SGTI "0000001100001", -- (0X1C) SLEI "0000001100001", -- (0X1D) SGEI "0000000000000", -- (0X1E) "0000000000000", -- (0X1F) "0000000000000", -- (0X20) LB -- NOT IMPLEMENTED "0000000000000", -- (0X21) LH -- NOT IMPLEMENTED "0000000000000", -- (0X22) "0000001101011", -- (0X23) LW "0000000000000", -- (0X24) LBU -- NOT IMPLEMENTED "0000000000000", -- (0X25) LHU -- NOT IMPLEMENTED "0000000000000", -- (0X26) LF -- NOT IMPLEMENTED "0000000000000", -- (0X27) LD -- NOT IMPLEMENTED "0000000000000", -- (0X28) SB -- NOT IMPLEMENTED "0000000000000", -- (0X29) SH -- NOT IMPLEMENTED "0000000000000", -- (0X2A) "0000001101100", -- (0X2B) SW "0000000000000", -- (0X2C) "0000000000000", -- (0X2D) "0000000000000", -- (0X2E) SF -- NOT IMPLEMENTED "0000000000000", -- (0X2F) SD -- NOT IMPLEMENTED "0000000000000", -- (0X30) "0000000000000", -- (0X31) "0000000000000", -- (0X32) "0000000000000", -- (0X33) "0000000000000", -- (0X34) "0000000000000", -- (0X35) "0000000000000", -- (0X36) "0000000000000", -- (0X37) "0000000000000", -- (0X38) ITLB -- NOT IMPLEMENTED "0000000000000", -- (0X39) "0000001100001", -- (0X3A) SLTUI "0000001100001", -- (0X3B) SGTUI "0000001100001", -- (0X3C) SLEUI "0000001100001", -- (0X3D) SGEUI "0000000000000", -- (0X3E) "0000000000000" -- (0X3F) ); begin -- CW_OUT <= cw_mem(to_integer(unsigned(OPCODE_IN))); -- CW_OUT <= cw_mem(0) when OPCODE_IN = "0X00" else -- cw_mem(1) when OPCODE_IN = "0X01" else -- NULL; process (OPCODE_IN) begin case to_integer(unsigned(OPCODE_IN)) is when 0 => CW_OUT <= "0000000010001"; when 1 => CW_OUT <= "0000000010001"; when 2 => CW_OUT <= "1011000000000"; when 3 => CW_OUT <= "1011011110001"; when 4 => CW_OUT <= "1101000000000"; when 5 => CW_OUT <= "1101100000000"; when 6 => CW_OUT <= "0000000000000"; when 7 => CW_OUT <= "0000000000000"; when 8 => CW_OUT <= "0001001100001"; when 9 => CW_OUT <= "0000001100001"; when 10 => CW_OUT <="0001001100001"; when 11 => CW_OUT <="0000001100001"; when 12 => CW_OUT <="0000001100001"; when 13 => CW_OUT <="0000001100001"; when 14 => CW_OUT <="0000001100001"; when 15 => CW_OUT <="0000000000000"; when 16 => CW_OUT <="0000000000000"; when 17 => CW_OUT <="0000000000000"; when 18 => CW_OUT <="0100000000000"; when 19 => CW_OUT <="0100011100001"; when 20 => CW_OUT <="0000001100001"; when 21 => CW_OUT <="0000000000000"; when 22 => CW_OUT <="0000001100001"; when 23 => CW_OUT <="0000001100001"; when 24 => CW_OUT <="0000001100001"; when 25 => CW_OUT <="0000001100001"; when 26 => CW_OUT <="0000001100001"; when 27 => CW_OUT <="0000001100001"; when 28 => CW_OUT <="0000001100001"; when 29 => CW_OUT <="0000001100001"; when 30 => CW_OUT <="0000000000000"; when 31 => CW_OUT <="0000000000000"; when 32 => CW_OUT <="0000000000000"; when 33 => CW_OUT <="0000000000000"; when 34 => CW_OUT <="0000000000000"; when 35 => CW_OUT <="0000001101011"; when 36 => CW_OUT <="0000000000000"; when 37 => CW_OUT <="0000000000000"; when 38 => CW_OUT <="0000000000000"; when 39 => CW_OUT <="0000000000000"; when 40 => CW_OUT <="0000000000000"; when 41 => CW_OUT <="0000000000000"; when 42 => CW_OUT <="0000000000000"; when 43 => CW_OUT <="0000001101100"; when 44 => CW_OUT <="0000000000000"; when 45 => CW_OUT <="0000000000000"; when 46 => CW_OUT <="0000000000000"; when 47 => CW_OUT <="0000000000000"; when 48 => CW_OUT <="0000000000000"; when 49 => CW_OUT <="0000000000000"; when 50 => CW_OUT <="0000000000000"; when 51 => CW_OUT <="0000000000000"; when 52 => CW_OUT <="0000000000000"; when 53 => CW_OUT <="0000000000000"; when 54 => CW_OUT <="0000000000000"; when 55 => CW_OUT <="0000000000000"; when 56 => CW_OUT <="0000000000000"; when 57 => CW_OUT <="0000000000000"; when 58 => CW_OUT <="0000001100001"; when 59 => CW_OUT <="0000001100001"; when 60 => CW_OUT <="0000001100001"; when 61 => CW_OUT <="0000001100001"; when 62 => CW_OUT <="0000000000000"; when 63 => CW_OUT <="0000000000000"; when others => NULL; end case; end process; end bhe;

-- -- File Name: AlertLogPkg.vhd -- Design Unit Name: AlertLogPkg -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: [email protected] -- Contributor(s): -- Jim Lewis [email protected] -- -- -- Description: -- Alert handling and log filtering (verbosity control) -- Alert handling provides a method to count failures, errors, and warnings -- To accumlate counts, a data structure is created in a shared variable -- It is of type AlertLogStructPType which is defined in AlertLogBasePkg -- Log filtering provides verbosity control for logs (display or do not display) -- AlertLogPkg provides a simplified interface to the shared variable -- -- -- Developed for: -- SynthWorks Design Inc. -- VHDL Training Classes -- 11898 SW 128th Ave. Tigard, Or 97223 -- http://www.SynthWorks.com -- -- Revision History: -- Date Version Description -- 01/2015: 2015.01 Initial revision -- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail, -- ReportNonZeroAlerts, ReadLogEnables -- 05/2015 2015.06 Added IncAlertCount, AffirmIf -- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs -- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel) -- Created LocalInitialize -- -- Copyright (c) 2015 - 2016 by SynthWorks Design Inc. All rights reserved. -- -- Verbatim copies of this source file may be used and -- distributed without restriction. -- -- This source file is free software; you can redistribute it -- and/or modify it under the terms of the ARTISTIC License -- as published by The Perl Foundation; either version 2.0 of -- the License, or (at your option) any later version. -- -- This source is distributed in the hope that it will be -- useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- PURPOSE. See the Artistic License for details. -- -- You should have received a copy of the license with this source. -- If not download it from, -- http://www.perlfoundation.org/artistic_license_2_0 -- use std.textio.all ; use work.OsvvmGlobalPkg.all ; use work.TranscriptPkg.all ; use work.TextUtilPkg.all ; library IEEE ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; package AlertLogPkg is subtype AlertLogIDType is integer ; type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER subtype AlertIndexType is AlertType range FAILURE to WARNING ; type AlertCountType is array (AlertIndexType) of integer ; type AlertEnableType is array(AlertIndexType) of boolean ; type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType subtype LogIndexType is LogType range DEBUG to PASSED ; type LogEnableType is array (LogIndexType) of boolean ; constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0. constant ALERTLOG_DEFAULT_ID : AlertLogIDType := 1 ; constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant OSVVM_ALERTLOG_ID : AlertLogIDType := 2 ; constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ; -- NUM_PREDEFINED_AL_IDS intended to be local, but depends on others -- constant NUM_PREDEFINED_AL_IDS : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID - ALERTLOG_BASE_ID ; -- Not including base constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ; constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ; ------------------------------------------------------------ -- Alert always goes to the transcript file procedure Alert( AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; procedure Alert( Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount( -- A silent form of alert AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) ; procedure IncAlertCount( Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Similar to assert, except condition is positive procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- Direct replacement for assert procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- overloading for common functionality procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Simple Diff for file comparisons procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR ) ; procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) ; ------------------------------------------------------------ procedure SetAlertLogJustify ; procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ClearAlerts ; function "ABS" (L : AlertCountType) return AlertCountType ; function "+" (L, R : AlertCountType) return AlertCountType ; function "-" (L, R : AlertCountType) return AlertCountType ; function "-" (R : AlertCountType) return AlertCountType ; impure function SumAlertCount(AlertCount: AlertCountType) return integer ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount return integer ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ; ------------------------------------------------------------ -- log filtering for verbosity control, optionally has a separate file parameter procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ; ------------------------------------------------------------ -- Accessor Methods procedure SetAlertLogName(Name : string ) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ; procedure DeallocateAlertLogStruct ; procedure InitializeAlertLogStruct ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; ------------------------------------------------------------ -- Accessor Methods procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCheckCount ; impure function GetAffirmCheckCount return natural ; --?? procedure IncAffirmPassCount ; --?? impure function GetAffirmPassCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; procedure SetAlertStopCount(Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; impure function GetAlertStopCount(Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; impure function GetAlertEnable(Level : AlertType) return boolean ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; impure function GetLogEnable(Level : LogType) return boolean ; impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; -- same as GetLogEnable impure function IsLoggingEnabled(Level : LogType) return boolean ; procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; -- File Reading Utilities function IsLogEnableType (Name : String) return boolean ; procedure ReadLogEnables (file AlertLogInitFile : text) ; procedure ReadLogEnables (FileName : string) ; -- String Helper Functions -- This should be in a more general string package function PathTail (A : string) return string ; end AlertLogPkg ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// use work.NamePkg.all ; package body AlertLogPkg is -- instead of justify(to_upper(to_string())), just look up the upper case, left justified values type AlertNameType is array(AlertType) of string(1 to 7) ; constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER " type LogNameType is array(LogType) of string(1 to 7) ; constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER " type AlertLogStructPType is protected ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ; procedure SetJustify ; procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ; procedure ClearAlerts ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; ------------------------------------------------------------ -- FILE IO Controls -- procedure SetTranscriptEnable (A : boolean := TRUE) ; -- impure function IsTranscriptEnabled return boolean ; -- procedure MirrorTranscript (A : boolean := TRUE) ; -- impure function IsTranscriptMirrored return boolean ; ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) ; procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) ; procedure Deallocate ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCheckCount ; impure function GetAffirmCheckCount return natural ; --?? procedure IncAffirmPassCount ; --?? impure function GetAffirmPassCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; procedure ReportLogEnables ; ------------------------------------------------------------ -- Reporting Accessor procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; end protected AlertLogStructPType ; --- /////////////////////////////////////////////////////////////////////////// type AlertLogStructPType is protected body variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on variable AffirmCheckCountVar : natural := 0 ; --?? variable AffirmPassedCountVar : natural := 0 ; ------------------------------------------------------------ type AlertLogRecType is record ------------------------------------------------------------ Name : Line ; ParentID : AlertLogIDType ; AlertCount : AlertCountType ; AlertStopCount : AlertCountType ; AlertEnabled : AlertEnableType ; LogEnabled : LogEnableType ; end record AlertLogRecType ; ------------------------------------------------------------ -- Basis for AlertLog Data Structure variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ; --xx variable NumPredefinedAlIDsVar : AlertLogIDType := 0 ; -- defined by initialize type AlertLogRecPtrType is access AlertLogRecType ; type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ; type AlertLogArrayPtrType is access AlertLogArrayType ; variable AlertLogPtr : AlertLogArrayPtrType ; ------------------------------------------------------------ -- Report formatting settings, with defaults variable FailOnWarningVar : boolean := TRUE ; variable FailOnDisabledErrorsVar : boolean := TRUE ; variable ReportHierarchyVar : boolean := TRUE ; variable FoundReportHierVar : boolean := FALSE ; variable FoundAlertHierVar : boolean := FALSE ; variable WriteAlertLevelVar : boolean := TRUE ; variable WriteAlertNameVar : boolean := TRUE ; variable WriteAlertTimeVar : boolean := TRUE ; variable WriteLogLevelVar : boolean := TRUE ; variable WriteLogNameVar : boolean := TRUE ; variable WriteLogTimeVar : boolean := TRUE ; variable AlertPrefixVar : NamePType ; variable LogPrefixVar : NamePType ; variable ReportPrefixVar : NamePType ; variable DoneNameVar : NamePType ; variable PassNameVar : NamePType ; variable FailNameVar : NamePType ; variable AlertLogJustifyAmountVar : integer := 0 ; variable ReportJustifyAmountVar : integer := 0 ; ------------------------------------------------------------ -- PT Local impure function LeftJustify(A : String; Amount : integer) return string is ------------------------------------------------------------ constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ; begin if A'length >= Amount then return A ; else return A & Spaces(1 to Amount - A'length) ; end if ; end function LeftJustify ; ------------------------------------------------------------ -- PT Local procedure IncrementAlertCount( ------------------------------------------------------------ constant AlertLogID : in AlertLogIDType ; constant Level : in AlertType ; variable StopDueToCount : inout boolean ) is begin -- Always Count at this level AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + 1 ; -- Only do remaining actions if enabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- Exceeded Stop Count at this level? if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then StopDueToCount := TRUE ; end if ; -- Propagate counts to parent(s) -- Ascend Hierarchy if AlertLogID /= ALERTLOG_BASE_ID then IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount) ; end if ; end if ; end procedure IncrementAlertCount ; ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then -- Do not write or count when GlobalAlertEnabledVar is disabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- do not write when disabled write(buf, AlertPrefix) ; if WriteAlertLevelVar then -- write(buf, " " & to_string(Level) ) ; write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup end if ; --xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteAlertNameVar then -- print hierarchy names even when silent if FoundAlertHierVar and WriteAlertNameVar then -- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ; write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteAlertTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end if ; -- Always Count IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; --xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop(1) ; end if ; end if ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; --xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop ; end if ; end if ; end procedure IncAlertCount ; ------------------------------------------------------------ -- PT Local impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is ------------------------------------------------------------ variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then LowerLevelValues := CalcJustify(i, AlertLogPtr(i).Name'length, IndentAmount + 2) ; ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ; ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ; end if ; end loop ; return ResultValues ; end function CalcJustify ; ------------------------------------------------------------ procedure SetJustify is ------------------------------------------------------------ variable ResultValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues := CalcJustify(ALERTLOG_BASE_ID, 0, 0) ; AlertLogJustifyAmountVar := ResultValues(1) ; ReportJustifyAmountVar := ResultValues(2) ; end procedure SetJustify ; ------------------------------------------------------------ -- PT Local impure function GetEnabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return AlertLogPtr(AlertLogID).AlertCount ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ -- PT Local impure function GetDisabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if not AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if not AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and not AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Count := Count + GetDisabledAlertCount(AlertLogPtr(i).AlertCount, AlertLogPtr(i).AlertEnabled) ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin Count := GetDisabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then Count := Count + GetDisabledAlertCount(i) ; end if ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ -- PT Local procedure PrintTopAlerts ( ------------------------------------------------------------ NumErrors : integer ; AlertCount : AlertCountType ; Name : string ; NumDisabledErrors : integer ) is constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ; constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ; constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ; constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ; variable buf : line ; begin if NumErrors = 0 then if NumDisabledErrors = 0 then -- Passed write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; else -- Failed Due to Disabled Errors write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; write(buf, " Failed Due to Disabled Error(s) = " & to_string(NumDisabledErrors)) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; else -- Failed write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ; write(buf, " Total Error(s) = " & to_string(NumErrors) ) ; write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ; write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ; if AffirmCheckCountVar > 0 then --?? write(buf, " Affirmations Passed: " & to_string(AffirmPassedCountVar)) ; --?? write(buf, " Checked: " & to_string(AffirmCheckCountVar)) ; write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; Write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; end procedure PrintTopAlerts ; ------------------------------------------------------------ -- PT Local procedure PrintChild( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ; ReportAll : boolean ) is variable buf : line ; begin for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then if ReportAll or SumAlertCount(AlertLogPtr(i).AlertCount) > 0 then Write(buf, Prefix & " " & LeftJustify(AlertLogPtr(i).Name.all, ReportJustifyAmountVar - IndentAmount)) ; write(buf, " Failures: " & to_string(AlertLogPtr(i).AlertCount(FAILURE) ) ) ; write(buf, " Errors: " & to_string(AlertLogPtr(i).AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertLogPtr(i).AlertCount(WARNING) ) ) ; WriteLine(buf) ; end if ; PrintChild( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2, ReportAll => ReportAll ) ; end if ; end loop ; end procedure PrintChild ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE) is ------------------------------------------------------------ variable NumErrors : integer ; variable NumDisabledErrors : integer ; constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; NumErrors := SumAlertCount( ExternalErrors + GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ) ; if FailOnDisabledErrorsVar then NumDisabledErrors := SumAlertCount( GetDisabledAlertCount(AlertLogID) ) ; else NumDisabledErrors := 0 ; end if ; if IsOsvvmStringSet(Name) then PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => Name, NumDisabledErrors => NumDisabledErrors ) ; else PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => AlertLogPtr(AlertLogID).Name.all, NumDisabledErrors => NumDisabledErrors ) ; end if ; --Print Hierarchy when enabled and error or disabled error if (FoundReportHierVar and ReportHierarchyVar) and (NumErrors /= 0 or NumDisabledErrors /=0) then PrintChild( AlertLogID => AlertLogID, Prefix => ReportPrefix & " ", IndentAmount => 2, ReportAll => ReportAll ) ; end if ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin PrintTopAlerts ( NumErrors => SumAlertCount(AlertCount), AlertCount => AlertCount, Name => Name, NumDisabledErrors => 0 ) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AffirmCheckCountVar := 0 ; --?? AffirmPassedCountVar := 0 ; AlertLogPtr(ALERTLOG_BASE_ID).AlertCount := (0, 0, 0) ; AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop AlertLogPtr(i).AlertCount := (0, 0, 0) ; AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end loop ; end procedure ClearAlerts ; ------------------------------------------------------------ -- PT Local procedure LocalLog ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType ) is variable buf : line ; constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; begin write(buf, LogPrefix) ; if WriteLogLevelVar then write(buf, " " & LOG_NAME(Level) ) ; end if ; --xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteLogNameVar then -- print hierarchy names even when silent if FoundAlertHierVar and WriteLogNameVar then -- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ; write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteLogTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end procedure LocalLog ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin if Level = ALWAYS or Enable then LocalLog(AlertLogID, Message, Level) ; elsif AlertLogPtr(AlertLogID).LogEnabled(Level) then LocalLog(AlertLogID, Message, Level) ; end if ; end procedure log ; ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ; AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).Name.all ; end function GetAlertLogName ; ------------------------------------------------------------ -- PT Local procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is ------------------------------------------------------------ variable AlertEnabled : AlertEnableType ; variable AlertStopCount : AlertCountType ; variable LogEnabled : LogEnableType ; begin if AlertLogID = ALERTLOG_BASE_ID then AlertEnabled := (TRUE, TRUE, TRUE) ; LogEnabled := (others => FALSE) ; AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; else if ParentID < ALERTLOG_BASE_ID then AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ; LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ; else AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ; LogEnabled := AlertLogPtr(ParentID).LogEnabled ; end if ; AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end if ; AlertLogPtr(AlertLogID) := new AlertLogRecType ; AlertLogPtr(AlertLogID).Name := new string'(NAME) ; AlertLogPtr(AlertLogID).ParentID := ParentID ; AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ; AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ; AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ; AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ; -- AlertLogPtr(AlertLogID) := new AlertLogRecType'( -- Name => new string'(NAME), -- ParentID => ParentID, -- AlertCount => (0, 0, 0), -- AlertEnabled => AlertEnabled, -- AlertStopCount => AlertStopCount, -- LogEnabled => LogEnabled -- ) ; end procedure NewAlertLogRec ; ------------------------------------------------------------ -- PT Local -- Construct initial data structure procedure LocalInitialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin if NumAllocatedAlertLogIDsVar /= 0 then Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ; return ; end if ; -- Initialize Pointer AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; -- Create BASE AlertLogID (if it differs from DEFAULT if ALERTLOG_BASE_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ; end if ; -- Create DEFAULT AlertLogID NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := ALERT_DEFAULT_ID ; -- Create OSVVM AlertLogID (if it differs from DEFAULT if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; end procedure LocalInitialize ; ------------------------------------------------------------ -- Construct initial data structure procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin LocalInitialize(NewNumAlertLogIDs) ; end procedure Initialize ; ------------------------------------------------------------ -- PT Local -- Constructs initial data structure using constant below impure function LocalInitialize return boolean is ------------------------------------------------------------ begin LocalInitialize(MIN_NUM_AL_IDS) ; return TRUE ; end function LocalInitialize ; constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ; ------------------------------------------------------------ procedure Deallocate is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Deallocate(AlertLogPtr(i).Name) ; Deallocate(AlertLogPtr(i)) ; end loop ; deallocate(AlertLogPtr) ; -- Free up space used by protected types within AlertLogPkg AlertPrefixVar.Deallocate ; LogPrefixVar.Deallocate ; ReportPrefixVar.Deallocate ; DoneNameVar.Deallocate ; PassNameVar.Deallocate ; FailNameVar.Deallocate ; -- Restore variables to their initial state NumAlertLogIDsVar := 0 ; NumAllocatedAlertLogIDsVar := 0 ; GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on AffirmCheckCountVar := 0 ; --?? AffirmPassedCountVar := 0 ; FailOnWarningVar := TRUE ; FailOnDisabledErrorsVar := TRUE ; ReportHierarchyVar := TRUE ; FoundReportHierVar := FALSE ; FoundAlertHierVar := FALSE ; WriteAlertLevelVar := TRUE ; WriteAlertNameVar := TRUE ; WriteAlertTimeVar := TRUE ; WriteLogLevelVar := TRUE ; WriteLogNameVar := TRUE ; WriteLogTimeVar := TRUE ; end procedure Deallocate ; ------------------------------------------------------------ -- PT Local. procedure GrowAlertStructure (NewNumAlertLogIDs : integer) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NumAllocatedAlertLogIDsVar = 0 then Initialize (NewNumAlertLogIDs) ; -- Construct initial structure else oldAlertLogPtr := AlertLogPtr ; AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ; AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ; deallocate(oldAlertLogPtr) ; end if ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; end procedure GrowAlertStructure ; ------------------------------------------------------------ -- Sets a AlertLogPtr to a particular size -- Use for small bins to save space or large bins to -- suppress the resize and copy as a CovBin autosizes. procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NewNumAlertLogIDs) ; end if; end procedure SetNumAlertLogIDs ; ------------------------------------------------------------ -- PT Local impure function GetNextAlertLogID return AlertLogIDType is ------------------------------------------------------------ variable NewNumAlertLogIDs : AlertLogIDType ; begin NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ; if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ; end if ; NumAlertLogIDsVar := NewNumAlertLogIDs ; return NumAlertLogIDsVar ; end function GetNextAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop if Name = AlertLogPtr(i).Name.all then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ variable CurParentID : AlertLogIDType ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop CurParentID := AlertLogPtr(i).ParentID ; if Name = AlertLogPtr(i).Name.all and (CurParentID = ParentID or CurParentID = ALERTLOG_ID_NOT_ASSIGNED or ParentID = ALERTLOG_ID_NOT_ASSIGNED) then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is ------------------------------------------------------------ variable ResultID : AlertLogIDType ; begin ResultID := FindAlertLogID(Name, ParentID) ; if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set ParentID if AlertLogPtr(ResultID).ParentID = ALERTLOG_ID_NOT_ASSIGNED then AlertLogPtr(ResultID).ParentID := ParentID ; -- else -- do not update as ParentIDs are either same or input ParentID = ALERTLOG_ID_NOT_ASSIGNED end if ; else ResultID := GetNextAlertLogID ; NewAlertLogRec(ResultID, Name, ParentID) ; FoundAlertHierVar := TRUE ; if CreateHierarchy then FoundReportHierVar := TRUE ; end if ; end if ; return ResultID ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).ParentID ; end function GetAlertLogParentID ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin GlobalAlertEnabledVar := A ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return GlobalAlertEnabledVar ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCheckCount is ------------------------------------------------------------ begin if GlobalAlertEnabledVar then AffirmCheckCountVar := AffirmCheckCountVar + 1 ; end if ; end procedure IncAffirmCheckCount ; ------------------------------------------------------------ impure function GetAffirmCheckCount return natural is ------------------------------------------------------------ begin return AffirmCheckCountVar ; end function GetAffirmCheckCount ; --?? ------------------------------------------------------------ --?? procedure IncAffirmPassCount is --?? ------------------------------------------------------------ --?? begin --?? if GlobalAlertEnabledVar then --?? AffirmCheckCountVar := AffirmCheckCountVar + 1 ; --?? AffirmPassedCountVar := AffirmPassedCountVar + 1 ; --?? end if ; --?? end procedure IncAffirmPassCount ; --?? --?? ------------------------------------------------------------ --?? impure function GetAffirmPassCount return natural is --?? ------------------------------------------------------------ --?? begin --?? return AffirmPassedCountVar ; --?? end function GetAffirmPassCount ; ------------------------------------------------------------ -- PT LOCAL procedure SetOneStopCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer ) is begin if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ; else AlertLogPtr(AlertLogID).AlertStopCount(Level) := AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ; end if ; end procedure SetOneStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin SetOneStopCount(AlertLogID, Level, Count) ; if AlertLogID /= ALERTLOG_BASE_ID then SetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ; end if ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertStopCount(Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).AlertEnabled(Level) := Enable ; end loop ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetAlertEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertEnabled(Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).LogEnabled(Level) := Enable ; end loop ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetLogEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin if Level = ALWAYS then return TRUE ; else return AlertLogPtr(AlertLogID).LogEnabled(Level) ; end if ; end function GetLogEnable ; ------------------------------------------------------------ -- PT Local procedure PrintLogLevels( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ) is variable buf : line ; begin write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ; for i in LogIndexType loop if AlertLogPtr(AlertLogID).LogEnabled(i) then -- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ; write(buf, " " & to_string(i)) ; end if ; end loop ; WriteLine(buf) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then PrintLogLevels( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2 ) ; end if ; end loop ; end procedure PrintLogLevels ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ; end procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if FailOnWarning /= OPT_INIT_PARM_DETECT then FailOnWarningVar := IsEnabled(FailOnWarning) ; end if ; if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ; end if ; if ReportHierarchy /= OPT_INIT_PARM_DETECT then ReportHierarchyVar := IsEnabled(ReportHierarchy) ; end if ; if WriteAlertLevel /= OPT_INIT_PARM_DETECT then WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ; end if ; if WriteAlertName /= OPT_INIT_PARM_DETECT then WriteAlertNameVar := IsEnabled(WriteAlertName) ; end if ; if WriteAlertTime /= OPT_INIT_PARM_DETECT then WriteAlertTimeVar := IsEnabled(WriteAlertTime) ; end if ; if WriteLogLevel /= OPT_INIT_PARM_DETECT then WriteLogLevelVar := IsEnabled(WriteLogLevel) ; end if ; if WriteLogName /= OPT_INIT_PARM_DETECT then WriteLogNameVar := IsEnabled(WriteLogName) ; end if ; if WriteLogTime /= OPT_INIT_PARM_DETECT then WriteLogTimeVar := IsEnabled(WriteLogTime) ; end if ; if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then AlertPrefixVar.Set(AlertPrefix) ; end if ; if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then LogPrefixVar.Set(LogPrefix) ; end if ; if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then ReportPrefixVar.Set(ReportPrefix) ; end if ; if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then DoneNameVar.Set(DoneName) ; end if ; if PassName /= OSVVM_STRING_INIT_PARM_DETECT then PassNameVar.Set(PassName) ; end if ; if FailName /= OSVVM_STRING_INIT_PARM_DETECT then FailNameVar.Set(FailName) ; end if ; end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ variable buf : line ; begin -- Boolean Values swrite(buf, "ReportAlertLogOptions" & LF ) ; swrite(buf, "---------------------" & LF ) ; swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ; swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ; swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ; swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ; swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ; swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ; swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ; swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ; swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ; -- String swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ; swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ; swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ; swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ; swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ; swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ; writeline(buf) ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnWarningVar) ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(ReportHierarchyVar) ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return FoundReportHierVar ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return FoundAlertHierVar ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertLevelVar) ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertNameVar) ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertTimeVar) ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogLevelVar) ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogNameVar) ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogTimeVar) ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return ResolveOsvvmPassName(PassNameVar.GetOpt) ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return ResolveOsvvmFailName(FailNameVar.GetOpt) ; end function GetAlertLogFailName ; end protected body AlertLogStructPType ; shared variable AlertLogStruct : AlertLogStructPType ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------ procedure Alert( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is begin AlertLogStruct.Alert(AlertLogID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure Alert( Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) is begin AlertLogStruct.IncAlertCount(AlertLogID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure IncAlertCount( Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIf( AlertLogID, condition, Message, Level) ; end procedure AlertIf ; ------------------------------------------------------------ procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ -- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ -- deprecated impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin return AlertIf( AlertLogID, condition, Message, Level) ; end function AlertIf ; ------------------------------------------------------------ impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfNot( AlertLogID, condition, Message, Level) ; end procedure AlertIfNot ; ------------------------------------------------------------ procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ -- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; ------------------------------------------------------------ -- deprecated impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin return AlertIfNot( AlertLogID, condition, Message, Level) ; end function AlertIfNot ; ------------------------------------------------------------ impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; -- With AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; -- Without AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; -- With AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; -- Without AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is -- Open files and call AlertIfDiff[text, ...] ------------------------------------------------------------ file FileID1, FileID2 : text ; variable status1, status2 : file_open_status ; begin file_open(status1, FileID1, Name1, READ_MODE) ; file_open(status2, FileID2, Name2, READ_MODE) ; if status1 = OPEN_OK and status2 = OPEN_OK then AlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level) ; else if status1 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ; end if ; if status2 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ; end if ; end if; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is -- Simple diff. ------------------------------------------------------------ variable Buf1, Buf2 : line ; variable File1Done, File2Done : boolean ; variable LineCount : integer := 0 ; begin ReadLoop : loop File1Done := EndFile(File1) ; File2Done := EndFile(File2) ; exit ReadLoop when File1Done or File2Done ; ReadLine(File1, Buf1) ; ReadLine(File2, Buf2) ; LineCount := LineCount + 1 ; if Buf1.all /= Buf2.all then AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ; exit ReadLoop ; end if ; end loop ReadLoop ; if File1Done /= File2Done then if not File1Done then AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ; end if ; if not File2Done then AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ; end if ; end if; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AffirmIf( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR ) is begin AlertLogStruct.IncAffirmCheckCount ; -- increment check count if condition then -- passed AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log -- AlertLogStruct.IncAffirmPassCount ; -- increment pass & check count else AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure end if ; end procedure AffirmIf ; ------------------------------------------------------------ procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ; end procedure AffirmIf; ------------------------------------------------------------ procedure SetAlertLogJustify is ------------------------------------------------------------ begin AlertLogStruct.SetJustify ; end procedure SetAlertLogJustify ; ------------------------------------------------------------ procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertCount) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ; end procedure ReportNonZeroAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AlertLogStruct.ClearAlerts ; end procedure ClearAlerts ; ------------------------------------------------------------ function "ABS" (L : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := ABS( L(FAILURE) ) ; Result(ERROR) := ABS( L(ERROR) ) ; Result(WARNING) := ABS( L(WARNING) ); return Result ; end function "ABS" ; ------------------------------------------------------------ function "+" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) + R(FAILURE) ; Result(ERROR) := L(ERROR) + R(ERROR) ; Result(WARNING) := L(WARNING) + R(WARNING) ; return Result ; end function "+" ; ------------------------------------------------------------ function "-" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) - R(FAILURE) ; Result(ERROR) := L(ERROR) - R(ERROR) ; Result(WARNING) := L(WARNING) - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ function "-" (R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := - R(FAILURE) ; Result(ERROR) := - R(ERROR) ; Result(WARNING) := - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ impure function SumAlertCount(AlertCount: AlertCountType) return integer is ------------------------------------------------------------ begin -- Using ABS ensures correct expected error handling. return abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ; end function SumAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertCount(AlertLogID) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetEnabledAlertCount(AlertLogID) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount(AlertLogID) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is ------------------------------------------------------------ begin AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertLogName(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogName(AlertLogID) ; end GetAlertLogName ; ------------------------------------------------------------ procedure DeallocateAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Deallocate ; end procedure DeallocateAlertLogStruct ; ------------------------------------------------------------ procedure InitializeAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Initialize ; end procedure InitializeAlertLogStruct ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name, ParentID) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogParentID(AlertLogID) ; end function GetAlertLogParentID ; ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ -- Set using constant. Set before code runs. impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; return A ; end function SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetGlobalAlertEnable ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCheckCount is ------------------------------------------------------------ begin AlertLogStruct.IncAffirmCheckCount ; end procedure IncAffirmCheckCount ; ------------------------------------------------------------ impure function GetAffirmCheckCount return natural is ------------------------------------------------------------ begin return AlertLogStruct.GetAffirmCheckCount ; end function GetAffirmCheckCount ; --?? ------------------------------------------------------------ --?? procedure IncAffirmPassCount is --?? ------------------------------------------------------------ --?? begin --?? AlertLogStruct.IncAffirmPassCount ; --?? end procedure IncAffirmPassCount ; --?? --?? ------------------------------------------------------------ --?? impure function GetAffirmPassCount return natural is --?? ------------------------------------------------------------ --?? begin --?? return AlertLogStruct.GetAffirmPassCount ; --?? end function GetAffirmPassCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(Level, Enable) ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(AlertLogID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(Level, Enable) ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(AlertLogID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(AlertLogID, Level) ; end function IsLoggingEnabled ; ------------------------------------------------------------ impure function IsLoggingEnabled(Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ; end function IsLoggingEnabled ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin AlertLogStruct.ReportLogEnables ; end ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin AlertLogStruct.SetAlertLogOptions ( FailOnWarning => FailOnWarning , FailOnDisabledErrors => FailOnDisabledErrors, ReportHierarchy => ReportHierarchy , WriteAlertLevel => WriteAlertLevel , WriteAlertName => WriteAlertName , WriteAlertTime => WriteAlertTime , WriteLogLevel => WriteLogLevel , WriteLogName => WriteLogName , WriteLogTime => WriteLogTime , AlertPrefix => AlertPrefix , LogPrefix => LogPrefix , ReportPrefix => ReportPrefix , DoneName => DoneName , PassName => PassName , FailName => FailName ); end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ begin AlertLogStruct.ReportAlertLogOptions ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnWarning ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnDisabledErrors ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportHierarchy ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundReportHier ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundAlertHier ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertLevel ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertName ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertTime ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogLevel ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogName ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogTime ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogAlertPrefix ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogLogPrefix ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportPrefix ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogDoneName ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogPassName ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailName ; end function GetAlertLogFailName ; ------------------------------------------------------------ function IsLogEnableType (Name : String) return boolean is ------------------------------------------------------------ -- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER begin if Name = "PASSED" then return TRUE ; elsif Name = "DEBUG" then return TRUE ; elsif Name = "FINAL" then return TRUE ; elsif Name = "INFO" then return TRUE ; end if ; return FALSE ; end function IsLogEnableType ; ------------------------------------------------------------ procedure ReadLogEnables (file AlertLogInitFile : text) is -- Preferred Read format -- Line 1: instance1_name log_enable log_enable log_enable -- Line 2: instance2_name log_enable log_enable log_enable -- when reading multiple log_enables on a line, they must be separated by a space -- --- Also supports alternate format from Lyle/.... -- Line 1: instance1_name -- Line 2: log enable -- Line 3: instance2_name -- Line 4: log enable -- ------------------------------------------------------------ type ReadStateType is (GET_ID, GET_ENABLE) ; variable ReadState : ReadStateType := GET_ID ; variable buf : line ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; variable Name : string(1 to 80) ; variable NameLen : integer ; variable AlertLogID : AlertLogIDType ; variable ReadAnEnable : boolean ; variable LogLevel : LogType ; begin ReadState := GET_ID ; ReadLineLoop : while not EndFile(AlertLogInitFile) loop ReadLine(AlertLogInitFile, buf) ; if ReadAnEnable then -- Read one or more enable values, next line read AlertLog name -- Note that any newline with ReadAnEnable TRUE will result in -- searching for another AlertLogID name - this includes multi-line comments. ReadState := GET_ID ; end if ; ReadNameLoop : loop EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next ReadLineLoop when Empty ; case ReadState is when GET_ID => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ; ReadState := GET_ENABLE ; ReadAnEnable := FALSE ; when GET_ENABLE => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; ReadAnEnable := TRUE ; if not IsLogEnableType(Name(1 to NameLen)) then Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ; exit ReadNameLoop ; end if ; LogLevel := LogType'value(Name(1 to NameLen)) ; SetLogEnable(AlertLogID, LogLevel, TRUE) ; end case ; end loop ReadNameLoop ; end loop ReadLineLoop ; end procedure ReadLogEnables ; ------------------------------------------------------------ procedure ReadLogEnables (FileName : string) is ------------------------------------------------------------ file AlertLogInitFile : text open READ_MODE is FileName ; begin ReadLogEnables(AlertLogInitFile) ; end procedure ReadLogEnables ; ------------------------------------------------------------ function PathTail (A : string) return string is ------------------------------------------------------------ alias aA : string(1 to A'length) is A ; begin for i in aA'length - 1 downto 1 loop if aA(i) = ':' then return aA(i+1 to aA'length-1) ; end if ; end loop ; return aA ; end function PathTail ; end package body AlertLogPkg ;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: inpad -- File: inpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: input pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity inpad is generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v; filter : integer := 0; strength : integer := 0); port (pad : in std_ulogic; o : out std_ulogic); end; architecture rtl of inpad is begin gen0 : if has_pads(tech) = 0 generate o <= transport to_X01(pad) -- pragma translate_off after 1 ns -- pragma translate_on ; end generate; xcv : if (is_unisim(tech) = 1) generate x0 : unisim_inpad generic map (level, voltage) port map (pad, o); end generate; axc : if (tech = axcel) or (tech = axdsp) generate x0 : axcel_inpad generic map (level, voltage) port map (pad, o); end generate; pa3 : if (tech = proasic) or (tech = apa3) generate x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o); end generate; pa3e : if (tech = apa3e) generate x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o); end generate; igl2 : if (tech = igloo2) generate x0 : igloo2_inpad port map (pad, o); end generate; pa3l : if (tech = apa3l) generate x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o); end generate; fus : if (tech = actfus) generate x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o); end generate; atc : if (tech = atc18s) generate x0 : atc18_inpad generic map (level, voltage) port map (pad, o); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o); end generate; um : if (tech = umc) generate x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; saed : if (tech = saed32) generate x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o); end generate; rhs : if (tech = rhs65) generate x0 : rhs65_inpad generic map (level, voltage, filter) port map (pad, o); end generate; dar : if (tech = dare) generate x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_inpad generic map(level, voltage) port map(pad, o); end generate; ihprh : if (tech = ihp25rh) generate x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o); end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o); end generate; ut13 : if (tech = ut130) generate x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; pereg : if (tech = peregrine) generate x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o); end generate; eas : if (tech = easic90) generate x0 : nextreme_inpad generic map (level, voltage) port map (pad, o); end generate; n2x : if (tech = easic45) generate x0 : n2x_inpad generic map (level, voltage) port map (pad, o); end generate; ut90nhbd : if (tech = ut90) generate x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity inpadv is generic (tech : integer := 0; level : integer := 0; voltage : integer := 0; width : integer := 1; filter : integer := 0; strength : integer := 0); port ( pad : in std_logic_vector(width-1 downto 0); o : out std_logic_vector(width-1 downto 0)); end; architecture rtl of inpadv is begin v : for i in width-1 downto 0 generate x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i)); end generate; end;

---------------------------------------------------------------------------------- -- Engineer: Longofono -- -- Create Date: 02/04/2018 02:45:16 PM -- Module Name: load_store - Behavioral -- Description: Handles loading, storing, and signalling between core, control, and MMU -- -- Additional Comments: -- If storing, addr will be the MMU destination address and data will be the data to be written there -- If loading, addr will be the MMU source address and data will be an encoding of the number of bytes to load -- Encoding is as follows: -- One byte (LB, LBU) -> 0x0 -- Two bytes (LH, LHU) -> 0x1 -- Four bytes (LW, LWU) -> 0x2 -- Eight bytes (LD) -> 0x3 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library config; use work.config.all; -- If loading, we need to know: -- Memory address to load from (register file holds base, instruction holds offset -- Register address to load to -- If storing, we need to know: -- Register address to store from -- Memory address to store to (register file holds base, instruction holds offset entity load_store is Port( instr: in instr_t; -- Current instruction type imm12: in std_logic_vector(11 downto 0); -- offset value rs1: in reg_t; -- rs1 for S-type and I-type rs2: in reg_t; -- rs2 for S-type addr: out doubleword; -- Destination address data: out doubleword -- Data to be stored ); end load_store; architecture Behavioral of load_store is -- Latch for modifying data and address piecewise signal s_data: doubleword; signal s_addr: doubleword; begin process(instr) begin -- Encoding for load data is as follows: -- One byte (LB, LBU) -> 0x0 -- Two bytes (LH, LHU) -> 0x1 -- Four bytes (LW, LWU) -> 0x2 -- Eight bytes (LD) -> 0x3 case instr is when instr_LB => -- Load byte s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (others => '0'); when instr_LBU => -- Load byte, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (others => '0'); when instr_LD => -- Load doubleword s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 downto 0 => '1', others => '0'); when instr_LH => -- Load half word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (0 => '1', others => '0'); when instr_LHU => -- Load half word, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (0 => '1', others => '0'); when instr_LW => -- Load word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 => '1', others => '0'); when instr_LWU => -- Load word, unsigned s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= (1 => '1', others => '0'); when instr_SB => -- Store byte s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 8) <= (others => '0'); s_data(7 downto 0) <= rs2(7 downto 0); when instr_SD => -- Store doubleword s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data <= rs2; when instr_SH => -- Store half word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 16) <= (others => '0'); s_data(15 downto 0) <= rs2(15 downto 0); when instr_SW => -- Store word s_addr <= std_logic_vector(signed(rs1) + signed(imm12)); s_data(63 downto 32) <= (others => '0'); s_data(31 downto 0) <= rs2(31 downto 0); when others => s_addr <= (others => '0'); s_data <= (others => '0'); end case; data <= s_data; addr <= s_addr; end process; end Behavioral;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.plasoc_gpio_pack.all; entity koc_lock is generic ( axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width. axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width. axi_control_offset : integer := 0; --! Defines the offset for the Control register. control_default : integer := 1 ); port ( aclk : in std_logic; --! Clock. Tested with 50 MHz. aresetn : in std_logic; -- Slave AXI4-Lite Write interface. axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal. axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal. axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal. axi_awready : out std_logic; --! AXI4-Lite Address Write signal. axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal. axi_wready : out std_logic; --! AXI4-Lite Write Data signal. axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal. axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal. axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal. axi_bready : in std_logic; --! AXI4-Lite Write Response signal. axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal. -- Slave AXI4-Lite Read interface. axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal. axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal. axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal. axi_arready : out std_logic; --! AXI4-Lite Address Read signal. axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal. axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal. axi_rready : in std_logic; --! AXI4-Lite Read Data signal. axi_rresp : out std_logic_vector(1 downto 0) ); end koc_lock; architecture Behavioral of koc_lock is component koc_lock_axi4_write_cntrl is generic ( axi_address_width : integer := 16; axi_data_width : integer := 32; reg_control_offset : std_logic_vector := X"0000"; reg_control_default : std_logic_vector := X"00000001" ); port ( aclk : in std_logic; aresetn : in std_logic; axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); axi_awprot : in std_logic_vector(2 downto 0); axi_awvalid : in std_logic; axi_awready : out std_logic; axi_wvalid : in std_logic; axi_wready : out std_logic; axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); axi_bvalid : out std_logic; axi_bready : in std_logic; axi_bresp : out std_logic_vector(1 downto 0); reg_control : out std_logic_vector(axi_data_width-1 downto 0) ); end component; component koc_lock_axi4_read_cntrl is generic ( axi_address_width : integer := 16; axi_data_width : integer := 32; reg_control_offset : std_logic_vector := X"0000" ); port ( aclk : in std_logic; aresetn : in std_logic; axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal. axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal. axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal. axi_arready : out std_logic; --! AXI4-Lite Address Read signal. axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal. axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal. axi_rready : in std_logic; --! AXI4-Lite Read Data signal. axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal. reg_control : in std_logic_vector(axi_data_width-1 downto 0) ); end component; constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width)); constant control_default_slv : std_logic_vector := std_logic_vector(to_unsigned(control_default,axi_data_width)); signal reg_control : std_logic_vector(axi_data_width-1 downto 0); begin koc_lock_axi4_write_cntrl_inst : koc_lock_axi4_write_cntrl generic map ( axi_address_width => axi_address_width, axi_data_width => axi_data_width, reg_control_offset => axi_control_offset_slv, reg_control_default => control_default_slv) port map ( aclk => aclk, aresetn => aresetn, axi_awaddr => axi_awaddr, axi_awprot => axi_awprot, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_wvalid => axi_wvalid, axi_wready => axi_wready, axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bresp => axi_bresp, reg_control => reg_control); koc_lock_axi4_read_cntrl_inst : koc_lock_axi4_read_cntrl generic map ( axi_address_width => axi_address_width, axi_data_width => axi_data_width, reg_control_offset => axi_control_offset_slv) port map ( aclk => aclk, aresetn => aresetn, axi_araddr => axi_araddr, axi_arprot => axi_arprot, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_rdata => axi_rdata, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rresp => axi_rresp, reg_control => reg_control); end Behavioral;

-------------------------------------------------------------------------------- --Author: Jay Aurabind --Email : [email protected] -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity synchro is Port ( x1 : in STD_LOGIC; x2 : in STD_LOGIC; x3 : in STD_LOGIC; y1 : in STD_LOGIC; y2 : in STD_LOGIC; y3 : in STD_LOGIC; vcomp, rst : in STD_LOGIC; phase : inout STD_LOGIC; freq : inout STD_LOGIC; voltage : inout STD_LOGIC; inst : out STD_LOGIC; clock : in std_logic); end synchro; architecture Behavioral of synchro is COMPONENT pulse_counter PORT( Pulse_I : IN std_logic; CLK_I : IN std_logic; DAT_O : OUT std_logic_vector(63 downto 0); ERR_O : OUT std_logic ); END COMPONENT; signal error_x, error_y, freq_temp,posedge_x, posedge_y : std_logic; signal x1_store, y1_store : std_logic; signal countx,county : std_logic_vector(63 downto 0) :=(others => '0'); begin --architecture begins Inst_pulse_counter_X1: pulse_counter PORT MAP( DAT_O => countx, ERR_O => error_x, Pulse_I => x1, CLK_I => clock ); Inst_pulse_counter_Y1: pulse_counter PORT MAP( DAT_O => county, ERR_O => error_y, Pulse_I => y1, CLK_I => clock ); --phase seq process(x1,x2,x3, y1,y2,y3) variable xph, yph : std_logic_vector(1 downto 0) := "00"; begin if x1'event and x1='1' then xph := x2 & x3; end if; if y1'event and y1='1' then yph := y2 & y3; end if; if xph=yph then phase <= '1'; else phase <= '0'; end if; end process; --comparasion-- process(countx,county,rst) variable temp_var, temp : std_logic_vector(63 downto 0); begin if rst = '1' then freq_temp <= '0'; else --flag1 comes from a component instantiation statement at the top temp_var := (countx - county); temp := "000000" & countx(63 downto 6); if (temp_var <= temp) then freq_temp <= '1'; else freq_temp <='0'; end if; end if; end process; freq <= freq_temp and (not error_x) and (not error_y); --rdy is high when division is completed --voltage-- voltage <= vcomp; --instant inphase-- process(clock) --process to store x1 and y1 begin if clock'event and clock ='1' then if rst = '1' then x1_store <= '0'; y1_store <= '0'; else x1_store <= x1; y1_store <= y1; end if; end if; end process; --process to create a pulse at positive edge of both x1 and y1 process(x1_store, x1, y1_store, y1) begin posedge_x <= x1 and (not x1_store); posedge_y <= y1 and (not y1_store); end process; process(phase,freq,voltage,posedge_x, posedge_y,error_x,error_y) begin inst <= posedge_x and posedge_y and phase and freq and voltage; end process; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity idreadback is Generic ( id : std_logic_vector(31 downto 0); mc : std_logic_vector(31 downto 0)); Port ( readid : in std_logic; readmc : in std_logic; obus : out std_logic_vector(31 downto 0)); end idreadback; architecture Behavioral of idreadback is begin areadidprocess: process (readid, readmc) begin if readid = '1' and readmc = '0' then obus <= id; elsif readmc = '1' and readid = '0' then obus <= mc; else obus <= (others => 'Z'); end if; end process areadidprocess; end Behavioral;

-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY async_fifo_align_64in_out IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; valid : OUT STD_LOGIC ); END async_fifo_align_64in_out; ARCHITECTURE async_fifo_align_64in_out_arch OF async_fifo_align_64in_out IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(8 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF async_fifo_align_64in_out_arch : ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF async_fifo_align_64in_out_arch: ARCHITECTURE IS "async_fifo_align_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=510,C_PROG_FULL_THRESH_NEGATE_VAL=509,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 9, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "virtex7", C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 1, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 510, C_PROG_FULL_THRESH_NEGATE_VAL => 509, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 9, C_RD_DEPTH => 512, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 9, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 9, C_WR_DEPTH => 512, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 9, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => rst, srst => '0', wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, valid => valid, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END async_fifo_align_64in_out_arch;

package pkg is type integer_vector is array (natural range <>) of integer; type integer_vector_ptr is access integer_vector; procedure get(variable vec : in integer_vector_ptr; sum : inout integer); end package; package body pkg is procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is begin sum := 0; for i in vec.all'range loop sum := sum + vec.all(i); end loop; end procedure; end package body; ------------------------------------------------------------------------------- entity issue152 is end entity; use work.pkg.all; architecture test of issue152 is begin process is variable sum : integer; variable vec : integer_vector_ptr; begin vec := new integer_vector'(1, 2, 3, 4, 5); get(vec, sum); assert sum = 15; wait; end process; end architecture;

-- Clock generator constant CFG_CLKTECH : integer := CFG_CLK_TECH; constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;

architecture rtl of fifo is begin connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow ); connect_ports( port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow ); connect_ports ( port_1 => data , port_2 => enable, port_3 => overflow , port_4 => underflow ); process begin connect_ports( port_1 => data, port_2=> enable, port_3 => overflow, port_4 => underflow ); end process; end architecture;

-- -- This file is part of the lafw16 project. -- -- Copyright (C) 2014-2015 Gregor Anich -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_clockmux is end test_clockmux; architecture behavior of test_clockmux is -- Component Declaration for the Unit Under Test (UUT) component clockmux port( clk_ctl : in std_logic; clk_sel : in std_logic_vector(1 downto 0); clk_in : in std_logic_vector(3 downto 0); clk_out : out std_logic ); end component; --Inputs signal clk_ctl : std_logic := '0'; signal clk_sel : unsigned(1 downto 0) := (others => '0'); signal clk_in : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal clk_out : std_logic; -- Clock period definitions constant clk_ctl_period : time := 10 ns; constant clk_in_0_period : time := 3 ns; constant clk_in_1_period : time := 17 ns; constant clk_in_2_period : time := 37 ns; constant clk_in_3_period : time := 113 ns; begin -- Instantiate the Unit Under Test (UUT) uut: clockmux port map ( clk_ctl => clk_ctl, clk_sel => std_logic_vector(clk_sel), clk_in => clk_in, clk_out => clk_out ); -- Clock process definitions clk_ctl_process :process begin clk_ctl <= '0'; wait for clk_ctl_period/2; clk_ctl <= '1'; wait for clk_ctl_period/2; end process; clk_in_0_process :process begin clk_in(0) <= '0'; wait for clk_in_0_period/2; clk_in(0) <= '1'; wait for clk_in_0_period/2; end process; clk_in_1_process :process begin clk_in(1) <= '0'; wait for clk_in_1_period/2; clk_in(1) <= '1'; wait for clk_in_1_period/2; end process; clk_in_2_process :process begin clk_in(2) <= '0'; wait for clk_in_2_period/2; clk_in(2) <= '1'; wait for clk_in_2_period/2; end process; clk_in_3_process :process begin clk_in(3) <= '0'; wait for clk_in_3_period/2; clk_in(3) <= '1'; wait for clk_in_3_period/2; end process; -- Stimulus process stim_proc: process begin clk_sel <= to_unsigned(0, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(1, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(2, clk_sel'length); wait for 1 us; clk_sel <= to_unsigned(3, clk_sel'length); wait for 1 us; wait; end process; end;

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_07_01 is end entity ch_07_01; ---------------------------------------------------------------- architecture test of ch_07_01 is begin process_07_2_a : process is type t1 is (t1_1, t1_2); type t2 is (t2_1, t2_2); type t3 is (t3_1, t3_2); type t4 is (t4_1, t4_2); constant v4 : t4 := t4_1; constant val1 : t1 := t1_1; constant val2 : t2 := t2_1; variable var3 : t3 := t3_1; constant val4 : t4 := t4_1; -- code from book: procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is begin -- . . . end procedure p; -- end of code from book begin -- code from book: p ( val1, val2, var3, val4 ); p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 ); p ( val1, val2, f4 => open, f3 => var3 ); p ( val1, val2, var3 ); -- end of code from book wait; end process process_07_2_a; end architecture test;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PuPIP0VhRYOvmy3YQKBtmK2n6y8D0dWiKhfOFbgKPAexbIleKocvnRl8Y184WIBVZmvl7McO6xqh oSNkJUw1rw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bmWXy3fu5Cr8p9ffB3MhQuVIAxp3JSY9+rqQTwkcvIRwgJOQ1p+ZmYgQfTBIrKURt1Xa0KLubUnA 4EPlmILaIIwaoYgJK3KOShUZWEZt28lTZjreYRdC2SYMsT1E5Uia0fI/FUmtjfEQWKDVmgyTGBsb /k/6l6ocSG4L6fNbp1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_timer:2.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_timer_v2_0; USE axi_timer_v2_0.axi_timer; ENTITY system_axi_timer_0_0 IS PORT ( capturetrig0 : IN STD_LOGIC; capturetrig1 : IN STD_LOGIC; generateout0 : OUT STD_LOGIC; generateout1 : OUT STD_LOGIC; pwm0 : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; freeze : IN STD_LOGIC; s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC ); END system_axi_timer_0_0; ARCHITECTURE system_axi_timer_0_0_arch OF system_axi_timer_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_timer_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_timer IS GENERIC ( C_FAMILY : STRING; C_COUNT_WIDTH : INTEGER; C_ONE_TIMER_ONLY : INTEGER; C_TRIG0_ASSERT : STD_LOGIC; C_TRIG1_ASSERT : STD_LOGIC; C_GEN0_ASSERT : STD_LOGIC; C_GEN1_ASSERT : STD_LOGIC; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER ); PORT ( capturetrig0 : IN STD_LOGIC; capturetrig1 : IN STD_LOGIC; generateout0 : OUT STD_LOGIC; generateout1 : OUT STD_LOGIC; pwm0 : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; freeze : IN STD_LOGIC; s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC ); END COMPONENT axi_timer; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; BEGIN U0 : axi_timer GENERIC MAP ( C_FAMILY => "zynq", C_COUNT_WIDTH => 32, C_ONE_TIMER_ONLY => 0, C_TRIG0_ASSERT => '1', C_TRIG1_ASSERT => '1', C_GEN0_ASSERT => '1', C_GEN1_ASSERT => '1', C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ADDR_WIDTH => 5 ) PORT MAP ( capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, generateout0 => generateout0, generateout1 => generateout1, pwm0 => pwm0, interrupt => interrupt, freeze => freeze, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); END system_axi_timer_0_0_arch;

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity convolve_kernel is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_EN_A : OUT STD_LOGIC; bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufw_Clk_A : OUT STD_LOGIC; bufw_Rst_A : OUT STD_LOGIC; bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_EN_A : OUT STD_LOGIC; bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufi_Clk_A : OUT STD_LOGIC; bufi_Rst_A : OUT STD_LOGIC; bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_EN_A : OUT STD_LOGIC; bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufo_Clk_A : OUT STD_LOGIC; bufo_Rst_A : OUT STD_LOGIC ); end; architecture behav of convolve_kernel is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=38509,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=1433,HLS_SYN_LUT=1252}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000100000"; constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000001000000"; constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000010000000"; constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000100000000"; constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000001000000000"; constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000010000000000"; constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000100000000000"; constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000001000000000000"; constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000010000000000000"; constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000100000000000000"; constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000001000000000000000"; constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000010000000000000000"; constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000100000000000000000"; constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (29 downto 0) := "000000000001000000000000000000"; constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (29 downto 0) := "000000000010000000000000000000"; constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (29 downto 0) := "000000000100000000000000000000"; constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (29 downto 0) := "000000001000000000000000000000"; constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (29 downto 0) := "000000010000000000000000000000"; constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (29 downto 0) := "000000100000000000000000000000"; constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (29 downto 0) := "000001000000000000000000000000"; constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (29 downto 0) := "000010000000000000000000000000"; constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (29 downto 0) := "000100000000000000000000000000"; constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (29 downto 0) := "001000000000000000000000000000"; constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (29 downto 0) := "010000000000000000000000000000"; constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (29 downto 0) := "100000000000000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101"; constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_CS_fsm : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal to_b_V_fu_201_p2 : STD_LOGIC_VECTOR (1 downto 0); signal to_b_V_reg_479 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal tmp_16_cast_fu_229_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_cast_reg_484 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_fu_195_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ti_b_V_fu_239_p2 : STD_LOGIC_VECTOR (1 downto 0); signal ti_b_V_reg_493 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none"; signal tmp_4_fu_249_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_4_reg_498 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_2_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_266_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_reg_504 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_11_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_11_reg_509 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none"; signal tmp_21_cast_fu_292_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_21_cast_reg_514 : STD_LOGIC_VECTOR (6 downto 0); signal row_b_V_fu_301_p2 : STD_LOGIC_VECTOR (1 downto 0); signal row_b_V_reg_522 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none"; signal tmp_17_fu_311_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_17_reg_527 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_5_fu_295_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_321_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_19_reg_533 : STD_LOGIC_VECTOR (5 downto 0); signal ap_CS_fsm_state6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none"; signal tmp_7_cast_fu_326_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_7_cast_reg_538 : STD_LOGIC_VECTOR (2 downto 0); signal col_b_V_fu_336_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_b_V_reg_546 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none"; signal bufo_addr_reg_551 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_8_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_cast_fu_356_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_cast_reg_556 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none"; signal i_V_fu_366_p2 : STD_LOGIC_VECTOR (2 downto 0); signal i_V_reg_569 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none"; signal tmp_22_fu_381_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_22_reg_574 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_3_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_385_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_23_reg_579 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_9_fu_389_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_9_reg_584 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_24_fu_401_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_24_reg_589 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none"; signal tmp_25_fu_409_p2 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_25_reg_594 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_26_fu_414_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_26_reg_599 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_27_fu_428_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_27_reg_604 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none"; signal j_V_fu_440_p2 : STD_LOGIC_VECTOR (2 downto 0); signal j_V_reg_612 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none"; signal tmp_28_fu_450_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_28_reg_617 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_10_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_fu_455_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_12_reg_622 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_29_fu_463_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_reg_627 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none"; signal ap_CS_fsm_state15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none"; signal bufw_load_reg_642 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none"; signal bufi_load_reg_647 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_191_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_reg_652 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none"; signal grp_fu_186_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none"; signal p_s_reg_95 : STD_LOGIC_VECTOR (1 downto 0); signal p_1_reg_106 : STD_LOGIC_VECTOR (1 downto 0); signal p_2_reg_117 : STD_LOGIC_VECTOR (1 downto 0); signal p_3_reg_129 : STD_LOGIC_VECTOR (1 downto 0); signal p_4_reg_141 : STD_LOGIC_VECTOR (2 downto 0); signal temp1_reg_152 : STD_LOGIC_VECTOR (31 downto 0); signal p_5_reg_162 : STD_LOGIC_VECTOR (2 downto 0); signal temp_1_reg_173 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_25_cast_fu_351_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_32_cast_fu_468_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_33_cast_fu_472_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none"; signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none"; signal ap_CS_fsm_state17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none"; signal tmp_s_fu_211_p3 : STD_LOGIC_VECTOR (3 downto 0); signal p_shl_cast_fu_219_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_cast_fu_207_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_fu_223_p2 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_4_cast_fu_245_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_15_fu_254_p3 : STD_LOGIC_VECTOR (4 downto 0); signal p_shl1_cast_fu_262_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_7_fu_275_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_cast_fu_272_p1 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl2_fu_282_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_cast8_fu_307_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_18_fu_316_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_cast7_fu_342_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_20_fu_346_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_6_fu_372_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_21_fu_376_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl5_cast_fu_394_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_9_cast_cast_fu_406_p1 : STD_LOGIC_VECTOR (6 downto 0); signal p_shl4_cast_fu_421_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_cast_fu_418_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_11_cast_fu_446_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_12_cast_cast_fu_460_p1 : STD_LOGIC_VECTOR (8 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (29 downto 0); component convolve_kernel_fbkb IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component convolve_kernel_fcud IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin convolve_kernel_fbkb_U0 : component convolve_kernel_fbkb generic map ( ID => 1, NUM_STAGE => 9, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => temp_1_reg_173, din1 => tmp_13_reg_652, ce => ap_const_logic_1, dout => grp_fu_186_p2); convolve_kernel_fcud_U1 : component convolve_kernel_fcud generic map ( ID => 1, NUM_STAGE => 5, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => bufw_load_reg_642, din1 => bufi_load_reg_647, ce => ap_const_logic_1, dout => grp_fu_191_p2); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; p_1_reg_106_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then p_1_reg_106 <= ti_b_V_reg_493; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then p_1_reg_106 <= ap_const_lv2_0; end if; end if; end process; p_2_reg_117_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then p_2_reg_117 <= row_b_V_reg_522; elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then p_2_reg_117 <= ap_const_lv2_0; end if; end if; end process; p_3_reg_129_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then p_3_reg_129 <= col_b_V_reg_546; elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then p_3_reg_129 <= ap_const_lv2_0; end if; end if; end process; p_4_reg_141_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then p_4_reg_141 <= i_V_reg_569; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then p_4_reg_141 <= ap_const_lv3_0; end if; end if; end process; p_5_reg_162_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then p_5_reg_162 <= j_V_reg_612; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then p_5_reg_162 <= ap_const_lv3_0; end if; end if; end process; p_s_reg_95_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then p_s_reg_95 <= to_b_V_reg_479; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then p_s_reg_95 <= ap_const_lv2_0; end if; end if; end process; temp1_reg_152_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then temp1_reg_152 <= temp_1_reg_173; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then temp1_reg_152 <= bufo_Dout_A; end if; end if; end process; temp_1_reg_173_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then temp_1_reg_173 <= grp_fu_186_p2; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then temp_1_reg_173 <= temp1_reg_152; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state16)) then bufi_load_reg_647 <= bufi_Dout_A; bufw_load_reg_642 <= bufw_Dout_A; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_0 = tmp_8_fu_330_p2))) then bufo_addr_reg_551 <= tmp_25_cast_fu_351_p1(5 - 1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state7)) then col_b_V_reg_546 <= col_b_V_fu_336_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state10)) then i_V_reg_569 <= i_V_fu_366_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state13)) then j_V_reg_612 <= j_V_fu_440_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state5)) then row_b_V_reg_522 <= row_b_V_fu_301_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state3)) then ti_b_V_reg_493 <= ti_b_V_fu_239_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state4)) then tmp_11_reg_509 <= tmp_11_fu_286_p2; tmp_21_cast_reg_514 <= tmp_21_cast_fu_292_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = tmp_10_fu_434_p2))) then tmp_12_reg_622 <= tmp_12_fu_455_p2; tmp_28_reg_617 <= tmp_28_fu_450_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state21)) then tmp_13_reg_652 <= grp_fu_191_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then tmp_16_cast_reg_484 <= tmp_16_cast_fu_229_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_2_fu_233_p2))) then tmp_16_reg_504 <= tmp_16_fu_266_p2; tmp_4_reg_498 <= tmp_4_fu_249_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_5_fu_295_p2))) then tmp_17_reg_527 <= tmp_17_fu_311_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state6)) then tmp_19_reg_533 <= tmp_19_fu_321_p2; tmp_7_cast_reg_538(1 downto 0) <= tmp_7_cast_fu_326_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (ap_const_lv1_0 = tmp_3_fu_360_p2))) then tmp_22_reg_574 <= tmp_22_fu_381_p1; tmp_23_reg_579 <= tmp_23_fu_385_p1; tmp_9_reg_584 <= tmp_9_fu_389_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state11)) then tmp_24_reg_589 <= tmp_24_fu_401_p2; tmp_25_reg_594 <= tmp_25_fu_409_p2; tmp_26_reg_599 <= tmp_26_fu_414_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state12)) then tmp_27_reg_604 <= tmp_27_fu_428_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state14)) then tmp_29_reg_627 <= tmp_29_fu_463_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state9)) then tmp_cast_reg_556(1 downto 0) <= tmp_cast_fu_356_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state2)) then to_b_V_reg_479 <= to_b_V_fu_201_p2; end if; end if; end process; tmp_7_cast_reg_538(2) <= '0'; tmp_cast_reg_556(2) <= '0'; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_195_p2, ap_CS_fsm_state3, tmp_2_fu_233_p2, ap_CS_fsm_state5, tmp_5_fu_295_p2, ap_CS_fsm_state7, tmp_8_fu_330_p2, ap_CS_fsm_state10, tmp_3_fu_360_p2, ap_CS_fsm_state13, tmp_10_fu_434_p2) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state3; end if; when ap_ST_fsm_state3 => if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state4; end if; when ap_ST_fsm_state4 => ap_NS_fsm <= ap_ST_fsm_state5; when ap_ST_fsm_state5 => if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state3; else ap_NS_fsm <= ap_ST_fsm_state6; end if; when ap_ST_fsm_state6 => ap_NS_fsm <= ap_ST_fsm_state7; when ap_ST_fsm_state7 => if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state5; else ap_NS_fsm <= ap_ST_fsm_state8; end if; when ap_ST_fsm_state8 => ap_NS_fsm <= ap_ST_fsm_state9; when ap_ST_fsm_state9 => ap_NS_fsm <= ap_ST_fsm_state10; when ap_ST_fsm_state10 => if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state7; else ap_NS_fsm <= ap_ST_fsm_state11; end if; when ap_ST_fsm_state11 => ap_NS_fsm <= ap_ST_fsm_state12; when ap_ST_fsm_state12 => ap_NS_fsm <= ap_ST_fsm_state13; when ap_ST_fsm_state13 => if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state10; else ap_NS_fsm <= ap_ST_fsm_state14; end if; when ap_ST_fsm_state14 => ap_NS_fsm <= ap_ST_fsm_state15; when ap_ST_fsm_state15 => ap_NS_fsm <= ap_ST_fsm_state16; when ap_ST_fsm_state16 => ap_NS_fsm <= ap_ST_fsm_state17; when ap_ST_fsm_state17 => ap_NS_fsm <= ap_ST_fsm_state18; when ap_ST_fsm_state18 => ap_NS_fsm <= ap_ST_fsm_state19; when ap_ST_fsm_state19 => ap_NS_fsm <= ap_ST_fsm_state20; when ap_ST_fsm_state20 => ap_NS_fsm <= ap_ST_fsm_state21; when ap_ST_fsm_state21 => ap_NS_fsm <= ap_ST_fsm_state22; when ap_ST_fsm_state22 => ap_NS_fsm <= ap_ST_fsm_state23; when ap_ST_fsm_state23 => ap_NS_fsm <= ap_ST_fsm_state24; when ap_ST_fsm_state24 => ap_NS_fsm <= ap_ST_fsm_state25; when ap_ST_fsm_state25 => ap_NS_fsm <= ap_ST_fsm_state26; when ap_ST_fsm_state26 => ap_NS_fsm <= ap_ST_fsm_state27; when ap_ST_fsm_state27 => ap_NS_fsm <= ap_ST_fsm_state28; when ap_ST_fsm_state28 => ap_NS_fsm <= ap_ST_fsm_state29; when ap_ST_fsm_state29 => ap_NS_fsm <= ap_ST_fsm_state30; when ap_ST_fsm_state30 => ap_NS_fsm <= ap_ST_fsm_state13; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state10 <= ap_CS_fsm(9); ap_CS_fsm_state11 <= ap_CS_fsm(10); ap_CS_fsm_state12 <= ap_CS_fsm(11); ap_CS_fsm_state13 <= ap_CS_fsm(12); ap_CS_fsm_state14 <= ap_CS_fsm(13); ap_CS_fsm_state15 <= ap_CS_fsm(14); ap_CS_fsm_state16 <= ap_CS_fsm(15); ap_CS_fsm_state17 <= ap_CS_fsm(16); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state21 <= ap_CS_fsm(20); ap_CS_fsm_state22 <= ap_CS_fsm(21); ap_CS_fsm_state3 <= ap_CS_fsm(2); ap_CS_fsm_state30 <= ap_CS_fsm(29); ap_CS_fsm_state4 <= ap_CS_fsm(3); ap_CS_fsm_state5 <= ap_CS_fsm(4); ap_CS_fsm_state6 <= ap_CS_fsm(5); ap_CS_fsm_state7 <= ap_CS_fsm(6); ap_CS_fsm_state8 <= ap_CS_fsm(7); ap_CS_fsm_state9 <= ap_CS_fsm(8); ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; bufi_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_33_cast_fu_472_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufi_Clk_A <= ap_clk; bufi_Din_A <= ap_const_lv32_0; bufi_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufi_EN_A <= ap_const_logic_1; else bufi_EN_A <= ap_const_logic_0; end if; end process; bufi_Rst_A <= ap_rst; bufi_WEN_A <= ap_const_lv4_0; bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_551),32)); bufo_Clk_A <= ap_clk; bufo_Din_A <= temp_1_reg_173; bufo_EN_A_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state8) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state8))) then bufo_EN_A <= ap_const_logic_1; else bufo_EN_A <= ap_const_logic_0; end if; end process; bufo_Rst_A <= ap_rst; bufo_WEN_A_assign_proc : process(ap_CS_fsm_state13, tmp_10_fu_434_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then bufo_WEN_A <= ap_const_lv4_F; else bufo_WEN_A <= ap_const_lv4_0; end if; end process; bufw_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_32_cast_fu_468_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufw_Clk_A <= ap_clk; bufw_Din_A <= ap_const_lv32_0; bufw_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufw_EN_A <= ap_const_logic_1; else bufw_EN_A <= ap_const_logic_0; end if; end process; bufw_Rst_A <= ap_rst; bufw_WEN_A <= ap_const_lv4_0; col_b_V_fu_336_p2 <= std_logic_vector(unsigned(p_3_reg_129) + unsigned(ap_const_lv2_1)); i_V_fu_366_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(ap_const_lv3_1)); j_V_fu_440_p2 <= std_logic_vector(unsigned(p_5_reg_162) + unsigned(ap_const_lv3_1)); p_shl1_cast_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_254_p3),6)); p_shl2_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_7_fu_275_p3),32)); p_shl4_cast_fu_421_p3 <= (tmp_26_reg_599 & ap_const_lv3_0); p_shl5_cast_fu_394_p3 <= (tmp_23_reg_579 & ap_const_lv2_0); p_shl_cast_fu_219_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_211_p3),5)); row_b_V_fu_301_p2 <= std_logic_vector(unsigned(p_2_reg_117) + unsigned(ap_const_lv2_1)); ti_b_V_fu_239_p2 <= std_logic_vector(unsigned(p_1_reg_106) + unsigned(ap_const_lv2_1)); tmp_10_fu_434_p2 <= "1" when (p_5_reg_162 = ap_const_lv3_5) else "0"; tmp_11_cast_fu_446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_5_reg_162),9)); tmp_11_fu_286_p2 <= std_logic_vector(signed(tmp_17_cast_fu_272_p1) + signed(p_shl2_fu_282_p1)); tmp_12_cast_cast_fu_460_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_reg_622),9)); tmp_12_fu_455_p2 <= std_logic_vector(unsigned(tmp_cast_reg_556) + unsigned(p_5_reg_162)); tmp_15_fu_254_p3 <= (p_1_reg_106 & ap_const_lv3_0); tmp_16_cast_fu_229_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_1_fu_223_p2),6)); tmp_16_fu_266_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_262_p1) - unsigned(tmp_4_cast_fu_245_p1)); tmp_17_cast_fu_272_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_4_reg_498),32)); tmp_17_fu_311_p2 <= std_logic_vector(unsigned(tmp_7_cast8_fu_307_p1) + unsigned(tmp_16_cast_reg_484)); tmp_18_fu_316_p2 <= std_logic_vector(shift_left(unsigned(tmp_17_reg_527),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0))))); tmp_19_fu_321_p2 <= std_logic_vector(unsigned(tmp_18_fu_316_p2) - unsigned(tmp_17_reg_527)); tmp_1_cast_fu_207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_s_reg_95),5)); tmp_1_fu_223_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_219_p1) - unsigned(tmp_1_cast_fu_207_p1)); tmp_20_fu_346_p2 <= std_logic_vector(unsigned(tmp_19_reg_533) + unsigned(tmp_cast7_fu_342_p1)); tmp_21_cast_fu_292_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_reg_504),7)); tmp_21_fu_376_p2 <= std_logic_vector(unsigned(tmp_6_fu_372_p1) + unsigned(tmp_11_reg_509)); tmp_22_fu_381_p1 <= tmp_21_fu_376_p2(9 - 1 downto 0); tmp_23_fu_385_p1 <= tmp_21_fu_376_p2(7 - 1 downto 0); tmp_24_fu_401_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_394_p3) + unsigned(tmp_22_reg_574)); tmp_25_cast_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_20_fu_346_p2),32)); tmp_25_fu_409_p2 <= std_logic_vector(unsigned(tmp_9_cast_cast_fu_406_p1) + unsigned(tmp_21_cast_reg_514)); tmp_26_fu_414_p1 <= tmp_25_fu_409_p2(6 - 1 downto 0); tmp_27_fu_428_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_421_p3) - unsigned(tmp_29_cast_fu_418_p1)); tmp_28_fu_450_p2 <= std_logic_vector(unsigned(tmp_24_reg_589) + unsigned(tmp_11_cast_fu_446_p1)); tmp_29_cast_fu_418_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_25_reg_594),9)); tmp_29_fu_463_p2 <= std_logic_vector(unsigned(tmp_27_reg_604) + unsigned(tmp_12_cast_cast_fu_460_p1)); tmp_2_fu_233_p2 <= "1" when (p_1_reg_106 = ap_const_lv2_3) else "0"; tmp_32_cast_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_28_reg_617),32)); tmp_33_cast_fu_472_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_627),32)); tmp_3_fu_360_p2 <= "1" when (p_4_reg_141 = ap_const_lv3_5) else "0"; tmp_4_cast_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_1_reg_106),6)); tmp_4_fu_249_p2 <= std_logic_vector(signed(tmp_16_cast_reg_484) + signed(tmp_4_cast_fu_245_p1)); tmp_5_fu_295_p2 <= "1" when (p_2_reg_117 = ap_const_lv2_3) else "0"; tmp_6_fu_372_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_4_reg_141),32)); tmp_7_cast8_fu_307_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),6)); tmp_7_cast_fu_326_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),3)); tmp_7_fu_275_p3 <= (tmp_4_reg_498 & ap_const_lv2_0); tmp_8_fu_330_p2 <= "1" when (p_3_reg_129 = ap_const_lv2_3) else "0"; tmp_9_cast_cast_fu_406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_584),7)); tmp_9_fu_389_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(tmp_7_cast_reg_538)); tmp_cast7_fu_342_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),6)); tmp_cast_fu_356_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),3)); tmp_fu_195_p2 <= "1" when (p_s_reg_95 = ap_const_lv2_3) else "0"; tmp_s_fu_211_p3 <= (p_s_reg_95 & ap_const_lv2_0); to_b_V_fu_201_p2 <= std_logic_vector(unsigned(p_s_reg_95) + unsigned(ap_const_lv2_1)); end behav;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is Port ( button : in std_logic; LED : out std_logic); end test; architecture Behavioral of test is begin LED <= button; end Behavioral;

lpm_divide0_inst : lpm_divide0 PORT MAP ( denom => denom_sig, numer => numer_sig, quotient => quotient_sig, remain => remain_sig );

library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu is generic( W : natural := 4 ); port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A i_data_b : in std_logic_vector(W-1 downto 0); -- input data B i_data_carry : in std_logic; -- carry in or borrow in i_ctrl : in std_logic_vector(3 downto 0); -- control signals o_data_c : out std_logic_vector(W-1 downto 0); -- output data C o_data_carry : out std_logic; -- carry out or borrow out o_data_comp : out std_logic_vector(1 downto 0) -- output comparison ); end alu; architecture behavioral of alu is begin comb_memless_process: process ( i_data_a, i_data_b, i_data_carry, i_ctrl ) variable temp_carry: std_logic_vector(W downto 0) := ( others => '0' ); begin o_data_c <= (others => '0'); o_data_carry <= '0'; o_data_comp <= (others => '0'); case i_ctrl is when "0001" => -- ripple carry adder: {sum, cout} = a+b+cin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- sum(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- cout(k+1) = a(k).b(k) + b(k).c(k) + c(k).a(k) temp_carry(i+1) := ( i_data_a(i) and i_data_b(i) ) or ( i_data_b(i) and temp_carry(i) ) or ( temp_carry(i) and i_data_a(i) ); end loop; o_data_carry <= temp_carry(W); when "0010" => -- full subtraction: {diff, bout} = a-b-bin temp_carry(0) := i_data_carry; for i in 0 to W-1 loop -- diff(k) = a(k) xor b(k) xor c(k) o_data_c(i) <= i_data_a(i) xor i_data_b(i) xor temp_carry(i); -- bout(k+1) = !a(k).b(k) + b(k).c(k) + c(k).!a(k) temp_carry(i+1) := ( ( NOT i_data_a(i) ) AND i_data_b(i) ) OR ( i_data_b(i) AND temp_carry(i) ) OR ( temp_carry(i) AND ( NOT i_data_a(i) ) ); end loop; o_data_carry <= temp_carry(W); when "0011" => -- comparator: comp_out = 1 if A > B if( i_data_a > i_data_b ) then o_data_comp <= "01"; else o_data_comp <= "00"; end if; when "0100" => -- comparator: comp_out = 1 if A < B if( i_data_a < i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0101" => -- comparator: comp_out = 1 if A = B if( i_data_a = i_data_b ) then o_data_comp <= "01"; else o_data_comp <= ( others => '0' ); end if; when "0110" => -- logical right shift A by B[1:0] o_data_c <= std_logic_vector( unsigned(i_data_a) srl to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when "0111" => -- logical left shift A by B o_data_c <= std_logic_vector( unsigned(i_data_a) sll to_integer( unsigned( i_data_b(1 downto 0) ) ) ); when others => -- NOP end case; end process comb_memless_process; end behavioral;

---- Controller -------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.processor_functions.all; ------------------------------------------------------------------------------------------------------------------ ENTITY controller IS PORT (clk, nrst: IN std_logic; CONTROL_bus: INOUT std_logic_vector(n-1 DOWNTO 0); state_7seg: OUT std_logic_vector(0 TO 7); -- IR IR_opcode: IN opcode; IR_load: OUT std_logic; IR_valid: OUT std_logic; -- PC PC_inc: OUT std_logic; PC_load: OUT std_logic; PC_valid: OUT std_logic; -- Memory MDR_load: OUT std_logic; MAR_load: OUT std_logic; MEM_valid: OUT std_logic; MEM_en: OUT std_logic; MEM_rw: OUT std_logic; -- ALU ALU_zero: IN std_logic; ALU_valid: OUT std_logic; ALU_slt: IN std_logic; ALU_enable: OUT std_logic; ALU_cmd: OUT std_logic_vector(3 DOWNTO 0); -- IO IODR_load: OUT STD_LOGIC; IOAR_load: OUT STD_LOGIC; IO_valid: OUT STD_LOGIC; IO_en: OUT STD_LOGIC; IO_rw: OUT STD_LOGIC; -- WAKE WAKE_signal: IN STD_LOGIC; waiting: OUT STD_LOGIC); END ENTITY controller; ------------------------------------------------------------------------------------------------------------------ ARCHITECTURE RTL OF controller IS TYPE states IS (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10); SIGNAL current_state, next_state: states; SIGNAL BRANCH_trigger: std_logic; SIGNAL state_vector: STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT bcd_to_7seg IS PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0); en: IN std_logic; output: OUT STD_LOGIC_VECTOR (0 TO 7)); END COMPONENT; BEGIN -- Converte o estado atual para um std_logic_vector com sua posicao na lista state_vector <= std_logic_vector(to_unsigned(states'pos(current_state), 4)); -- Gera a visualizacao 7seg state7seg: bcd_to_7seg PORT MAP(state_vector, seg_en, state_7seg); -- Indicador de se o branch deve ser aceito BRANCH_trigger <= '1' WHEN ((IR_opcode = BZERO AND ALU_zero = '1') OR (IR_opcode = BLESS AND ALU_slt = '1') OR (IR_opcode = BGREATER AND ALU_zero = '0' AND ALU_slt = '0')) ELSE '0'; -- Esta em waiting? waiting <= '1' WHEN current_state = s10 ELSE '0'; -- Processo que gerencia a transicao do current_state para o next_state -- e a configuracao de reset state_sequence: PROCESS (clk, nrst) BEGIN IF nrst = '0' THEN -- reset assincrono current_state <= s0; ELSE IF rising_edge(clk) THEN -- mudanca de estado eh sincrona current_state <= next_state; END IF; END IF; END PROCESS state_sequence; -- espera a mudanca de estado ou opcode -- processo que de fato mudam os sinais de controle conforme a transicao state_machine: PROCESS ( current_state, IR_opcode ) IS BEGIN -- Reset all the control SIGNALs IR_load <= '0'; IR_valid <= '0'; PC_inc <= '0'; PC_load <= '0'; PC_valid <= '0'; MDR_load <= '0'; MAR_load <= '0'; MEM_valid <= '0'; MEM_en <= '0'; MEM_rw <= '0'; ALU_valid <= '0'; ALU_enable <= '0'; ALU_cmd <= "0000"; IODR_load <= '0'; IOAR_load <= '0'; IO_valid <= '0'; IO_en <= '0'; IO_rw <= '0'; CASE current_state IS WHEN s0 => MAR_load <= '1'; PC_valid <= '1'; PC_inc <= '1'; next_state <= s1; WHEN s1 => MEM_en <='1'; next_state <= s2; WHEN s2 => MEM_valid <= '1'; IR_load <= '1'; next_state <= s3; WHEN s3 => IR_valid <= '1'; MAR_load <= '1'; IOAR_load <= '1'; IF (IR_opcode = INC) THEN next_state <= s7; ELSIF (IR_opcode = JUMP) THEN next_state <= s9; ELSIF (IR_opcode = BZERO OR IR_opcode = BGREATER OR IR_opcode = BLESS) THEN next_state <= s8; ELSIF (IR_opcode = NOP) THEN next_state <= s0; ELSIF (IR_opcode = WAITT) THEN next_state <= s10; ELSIF (IR_opcode = STORE) THEN next_state <= s4; ELSE next_state <= s6; END IF; WHEN s4 => ALU_valid <= '1'; MDR_load <= '1'; IODR_load <= '1'; next_state <= s5; WHEN s5 => MEM_en <= '1'; MEM_rw <= '1'; IO_en <= '1'; IO_rw <= '1'; next_state <= s0; WHEN s6 => MEM_en <= '1'; IO_en <= '1'; next_state <= s7; WHEN s7 => MEM_valid <= '1'; IO_valid <= '1'; ALU_enable <= '1'; ALU_cmd <= cmdDecode(IR_opcode); next_state <= s0; WHEN s8 => IF (BRANCH_trigger = '1') THEN next_state <= s9; ELSE next_state <= s0; END IF; WHEN s9 => PC_load <= '1'; IR_valid <= '1'; next_state <= s0; WHEN s10 => IF (WAKE_signal = '0') THEN next_state <= s0; END IF; END CASE; END PROCESS state_machine; END ARCHITECTURE; ------------------------------------------------------------------------------------------------------------------

package foo is -- Declaration attribute LOCATION: COORDINATE; attribute PIN_NO: POSITIVE; -- Specification attribute PIN_NO of CIN: signal is 10; attribute PIN_NO of COUT: signal is 5; attribute LOCATION of ADDER1: label is (10,15); attribute LOCATION of others: label is (25,77); attribute CAPACITANCE of all: signal is 15 pF; attribute IMPLEMENTATION of G1: group is "74LS152"; attribute RISING_DELAY of C2Q: group is 7.2 ns; attribute FOREIGN of F: function is "implementation-dependent information"; --attribute BuiltIn of "or" [MVL, MVL return MVL]: function is TRUE; --attribute Mapping of JMP [return OpCode] :literal is "001"; end;

-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ConstRAM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2011 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ConstRAM IS PORT ( clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (35 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) ); END ConstRAM; ARCHITECTURE SYN OF constram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_b : STRING; address_reg_b : STRING; clock_enable_input_a : STRING; clock_enable_input_b : STRING; clock_enable_output_b : STRING; intended_device_family : STRING; lpm_type : STRING; numwords_a : NATURAL; numwords_b : NATURAL; operation_mode : STRING; outdata_aclr_b : STRING; outdata_reg_b : STRING; power_up_uninitialized : STRING; read_during_write_mode_mixed_ports : STRING; widthad_a : NATURAL; widthad_b : NATURAL; width_a : NATURAL; width_b : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); wren_a : IN STD_LOGIC ; address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(35 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", intended_device_family => "Cyclone IV E", lpm_type => "altsyncram", numwords_a => 1024, numwords_b => 1024, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_mixed_ports => "OLD_DATA", widthad_a => 10, widthad_b => 10, width_a => 36, width_b => 36, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, clock0 => clock, data_a => data, wren_a => wren, address_b => rdaddress, q_b => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]" -- Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]" -- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]" -- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" -- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0 -- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY CDiv IS PORT ( Cin : IN std_logic ; Cout : OUT std_logic ) ; END CDiv ; ARCHITECTURE Behavior OF CDiv IS constant TC: integer := 12; --Time Constant signal c0,c1,c2,c3: integer range 0 to 1000; signal D: std_logic := '0'; BEGIN PROCESS(Cin) BEGIN if (Cin'event and Cin='1') then c0 <= c0 + 1; if c0 = TC then c0 <= 0; c1 <= c1 + 1; elsif c1 = TC then c1 <= 0; c2 <= c2 + 1; elsif c2 = TC then c2 <= 0; c3 <= c3 + 1; elsif c3 = TC then c3 <= 0; D <= NOT D; end if; end if; Cout <= D; END PROCESS ; END Behavior ;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mc6847_ntsc is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of mc6847_ntsc is signal rom_addr : std_logic_vector(9 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(9 downto 0) <= ADDR(9 downto 0); end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); if rom_addr(9 downto 8) = "00" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"1C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"02"; when x"06" => DATA <= x"1A"; when x"07" => DATA <= x"2A"; when x"08" => DATA <= x"2A"; when x"09" => DATA <= x"1C"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"14"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"3E"; when x"18" => DATA <= x"22"; when x"19" => DATA <= x"22"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"12"; when x"25" => DATA <= x"12"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"12"; when x"28" => DATA <= x"12"; when x"29" => DATA <= x"3C"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"20"; when x"36" => DATA <= x"20"; when x"37" => DATA <= x"20"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3C"; when x"44" => DATA <= x"12"; when x"45" => DATA <= x"12"; when x"46" => DATA <= x"12"; when x"47" => DATA <= x"12"; when x"48" => DATA <= x"12"; when x"49" => DATA <= x"3C"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"20"; when x"56" => DATA <= x"38"; when x"57" => DATA <= x"20"; when x"58" => DATA <= x"20"; when x"59" => DATA <= x"3E"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"3E"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"38"; when x"67" => DATA <= x"20"; when x"68" => DATA <= x"20"; when x"69" => DATA <= x"20"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"1E"; when x"74" => DATA <= x"20"; when x"75" => DATA <= x"20"; when x"76" => DATA <= x"26"; when x"77" => DATA <= x"22"; when x"78" => DATA <= x"22"; when x"79" => DATA <= x"1E"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"3E"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"08"; when x"95" => DATA <= x"08"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"02"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"02"; when x"A6" => DATA <= x"02"; when x"A7" => DATA <= x"22"; when x"A8" => DATA <= x"22"; when x"A9" => DATA <= x"1C"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"22"; when x"B4" => DATA <= x"24"; when x"B5" => DATA <= x"28"; when x"B6" => DATA <= x"30"; when x"B7" => DATA <= x"28"; when x"B8" => DATA <= x"24"; when x"B9" => DATA <= x"22"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"20"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"20"; when x"C8" => DATA <= x"20"; when x"C9" => DATA <= x"3E"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"22"; when x"D4" => DATA <= x"36"; when x"D5" => DATA <= x"2A"; when x"D6" => DATA <= x"2A"; when x"D7" => DATA <= x"22"; when x"D8" => DATA <= x"22"; when x"D9" => DATA <= x"22"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"22"; when x"E4" => DATA <= x"32"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"26"; when x"E7" => DATA <= x"22"; when x"E8" => DATA <= x"22"; when x"E9" => DATA <= x"22"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"3E"; when x"F4" => DATA <= x"22"; when x"F5" => DATA <= x"22"; when x"F6" => DATA <= x"22"; when x"F7" => DATA <= x"22"; when x"F8" => DATA <= x"22"; when x"F9" => DATA <= x"3E"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "01" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"3C"; when x"04" => DATA <= x"22"; when x"05" => DATA <= x"22"; when x"06" => DATA <= x"3C"; when x"07" => DATA <= x"20"; when x"08" => DATA <= x"20"; when x"09" => DATA <= x"20"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"1C"; when x"14" => DATA <= x"22"; when x"15" => DATA <= x"22"; when x"16" => DATA <= x"22"; when x"17" => DATA <= x"2A"; when x"18" => DATA <= x"24"; when x"19" => DATA <= x"1A"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"3C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"22"; when x"26" => DATA <= x"3C"; when x"27" => DATA <= x"28"; when x"28" => DATA <= x"24"; when x"29" => DATA <= x"22"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"10"; when x"36" => DATA <= x"08"; when x"37" => DATA <= x"04"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"3E"; when x"44" => DATA <= x"08"; when x"45" => DATA <= x"08"; when x"46" => DATA <= x"08"; when x"47" => DATA <= x"08"; when x"48" => DATA <= x"08"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"22"; when x"54" => DATA <= x"22"; when x"55" => DATA <= x"22"; when x"56" => DATA <= x"22"; when x"57" => DATA <= x"22"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"22"; when x"64" => DATA <= x"22"; when x"65" => DATA <= x"22"; when x"66" => DATA <= x"14"; when x"67" => DATA <= x"14"; when x"68" => DATA <= x"08"; when x"69" => DATA <= x"08"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"22"; when x"74" => DATA <= x"22"; when x"75" => DATA <= x"22"; when x"76" => DATA <= x"2A"; when x"77" => DATA <= x"2A"; when x"78" => DATA <= x"36"; when x"79" => DATA <= x"22"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"22"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"14"; when x"86" => DATA <= x"08"; when x"87" => DATA <= x"14"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"22"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"22"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"14"; when x"96" => DATA <= x"08"; when x"97" => DATA <= x"08"; when x"98" => DATA <= x"08"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"3E"; when x"A4" => DATA <= x"02"; when x"A5" => DATA <= x"04"; when x"A6" => DATA <= x"08"; when x"A7" => DATA <= x"10"; when x"A8" => DATA <= x"20"; when x"A9" => DATA <= x"3E"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"38"; when x"B4" => DATA <= x"20"; when x"B5" => DATA <= x"20"; when x"B6" => DATA <= x"20"; when x"B7" => DATA <= x"20"; when x"B8" => DATA <= x"20"; when x"B9" => DATA <= x"38"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"20"; when x"C4" => DATA <= x"20"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"08"; when x"C7" => DATA <= x"04"; when x"C8" => DATA <= x"02"; when x"C9" => DATA <= x"02"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"0E"; when x"D4" => DATA <= x"02"; when x"D5" => DATA <= x"02"; when x"D6" => DATA <= x"02"; when x"D7" => DATA <= x"02"; when x"D8" => DATA <= x"02"; when x"D9" => DATA <= x"0E"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"08"; when x"E4" => DATA <= x"1C"; when x"E5" => DATA <= x"2A"; when x"E6" => DATA <= x"08"; when x"E7" => DATA <= x"08"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"08"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"00"; when x"F4" => DATA <= x"08"; when x"F5" => DATA <= x"10"; when x"F6" => DATA <= x"3E"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"08"; when x"F9" => DATA <= x"00"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "10" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"00"; when x"04" => DATA <= x"00"; when x"05" => DATA <= x"00"; when x"06" => DATA <= x"00"; when x"07" => DATA <= x"00"; when x"08" => DATA <= x"00"; when x"09" => DATA <= x"00"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"08"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"00"; when x"19" => DATA <= x"08"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"14"; when x"24" => DATA <= x"14"; when x"25" => DATA <= x"14"; when x"26" => DATA <= x"00"; when x"27" => DATA <= x"00"; when x"28" => DATA <= x"00"; when x"29" => DATA <= x"00"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"14"; when x"34" => DATA <= x"14"; when x"35" => DATA <= x"36"; when x"36" => DATA <= x"00"; when x"37" => DATA <= x"36"; when x"38" => DATA <= x"14"; when x"39" => DATA <= x"14"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"08"; when x"44" => DATA <= x"1E"; when x"45" => DATA <= x"20"; when x"46" => DATA <= x"1C"; when x"47" => DATA <= x"02"; when x"48" => DATA <= x"3C"; when x"49" => DATA <= x"08"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"32"; when x"54" => DATA <= x"32"; when x"55" => DATA <= x"04"; when x"56" => DATA <= x"08"; when x"57" => DATA <= x"10"; when x"58" => DATA <= x"26"; when x"59" => DATA <= x"26"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"10"; when x"64" => DATA <= x"28"; when x"65" => DATA <= x"28"; when x"66" => DATA <= x"10"; when x"67" => DATA <= x"2A"; when x"68" => DATA <= x"24"; when x"69" => DATA <= x"1A"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"18"; when x"74" => DATA <= x"18"; when x"75" => DATA <= x"18"; when x"76" => DATA <= x"00"; when x"77" => DATA <= x"00"; when x"78" => DATA <= x"00"; when x"79" => DATA <= x"00"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"08"; when x"84" => DATA <= x"10"; when x"85" => DATA <= x"20"; when x"86" => DATA <= x"20"; when x"87" => DATA <= x"20"; when x"88" => DATA <= x"10"; when x"89" => DATA <= x"08"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"08"; when x"94" => DATA <= x"04"; when x"95" => DATA <= x"02"; when x"96" => DATA <= x"02"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"04"; when x"99" => DATA <= x"08"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"08"; when x"A5" => DATA <= x"1C"; when x"A6" => DATA <= x"3E"; when x"A7" => DATA <= x"1C"; when x"A8" => DATA <= x"08"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"00"; when x"B4" => DATA <= x"08"; when x"B5" => DATA <= x"08"; when x"B6" => DATA <= x"3E"; when x"B7" => DATA <= x"08"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"00"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"00"; when x"C4" => DATA <= x"00"; when x"C5" => DATA <= x"00"; when x"C6" => DATA <= x"30"; when x"C7" => DATA <= x"30"; when x"C8" => DATA <= x"10"; when x"C9" => DATA <= x"20"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"00"; when x"D6" => DATA <= x"3E"; when x"D7" => DATA <= x"00"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"00"; when x"E4" => DATA <= x"00"; when x"E5" => DATA <= x"00"; when x"E6" => DATA <= x"00"; when x"E7" => DATA <= x"00"; when x"E8" => DATA <= x"30"; when x"E9" => DATA <= x"30"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"02"; when x"F4" => DATA <= x"02"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"10"; when x"F8" => DATA <= x"20"; when x"F9" => DATA <= x"20"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; if rom_addr(9 downto 8) = "11" then case rom_addr(7 downto 0) is when x"00" => DATA <= x"00"; when x"01" => DATA <= x"00"; when x"02" => DATA <= x"00"; when x"03" => DATA <= x"18"; when x"04" => DATA <= x"24"; when x"05" => DATA <= x"24"; when x"06" => DATA <= x"24"; when x"07" => DATA <= x"24"; when x"08" => DATA <= x"24"; when x"09" => DATA <= x"18"; when x"0A" => DATA <= x"00"; when x"0B" => DATA <= x"00"; when x"0C" => DATA <= x"00"; when x"0D" => DATA <= x"00"; when x"0E" => DATA <= x"00"; when x"0F" => DATA <= x"00"; when x"10" => DATA <= x"00"; when x"11" => DATA <= x"00"; when x"12" => DATA <= x"00"; when x"13" => DATA <= x"08"; when x"14" => DATA <= x"18"; when x"15" => DATA <= x"08"; when x"16" => DATA <= x"08"; when x"17" => DATA <= x"08"; when x"18" => DATA <= x"08"; when x"19" => DATA <= x"1C"; when x"1A" => DATA <= x"00"; when x"1B" => DATA <= x"00"; when x"1C" => DATA <= x"00"; when x"1D" => DATA <= x"00"; when x"1E" => DATA <= x"00"; when x"1F" => DATA <= x"00"; when x"20" => DATA <= x"00"; when x"21" => DATA <= x"00"; when x"22" => DATA <= x"00"; when x"23" => DATA <= x"1C"; when x"24" => DATA <= x"22"; when x"25" => DATA <= x"02"; when x"26" => DATA <= x"1C"; when x"27" => DATA <= x"20"; when x"28" => DATA <= x"20"; when x"29" => DATA <= x"3E"; when x"2A" => DATA <= x"00"; when x"2B" => DATA <= x"00"; when x"2C" => DATA <= x"00"; when x"2D" => DATA <= x"00"; when x"2E" => DATA <= x"00"; when x"2F" => DATA <= x"00"; when x"30" => DATA <= x"00"; when x"31" => DATA <= x"00"; when x"32" => DATA <= x"00"; when x"33" => DATA <= x"1C"; when x"34" => DATA <= x"22"; when x"35" => DATA <= x"02"; when x"36" => DATA <= x"04"; when x"37" => DATA <= x"02"; when x"38" => DATA <= x"22"; when x"39" => DATA <= x"1C"; when x"3A" => DATA <= x"00"; when x"3B" => DATA <= x"00"; when x"3C" => DATA <= x"00"; when x"3D" => DATA <= x"00"; when x"3E" => DATA <= x"00"; when x"3F" => DATA <= x"00"; when x"40" => DATA <= x"00"; when x"41" => DATA <= x"00"; when x"42" => DATA <= x"00"; when x"43" => DATA <= x"04"; when x"44" => DATA <= x"0C"; when x"45" => DATA <= x"14"; when x"46" => DATA <= x"3E"; when x"47" => DATA <= x"04"; when x"48" => DATA <= x"04"; when x"49" => DATA <= x"04"; when x"4A" => DATA <= x"00"; when x"4B" => DATA <= x"00"; when x"4C" => DATA <= x"00"; when x"4D" => DATA <= x"00"; when x"4E" => DATA <= x"00"; when x"4F" => DATA <= x"00"; when x"50" => DATA <= x"00"; when x"51" => DATA <= x"00"; when x"52" => DATA <= x"00"; when x"53" => DATA <= x"3E"; when x"54" => DATA <= x"20"; when x"55" => DATA <= x"3C"; when x"56" => DATA <= x"02"; when x"57" => DATA <= x"02"; when x"58" => DATA <= x"22"; when x"59" => DATA <= x"1C"; when x"5A" => DATA <= x"00"; when x"5B" => DATA <= x"00"; when x"5C" => DATA <= x"00"; when x"5D" => DATA <= x"00"; when x"5E" => DATA <= x"00"; when x"5F" => DATA <= x"00"; when x"60" => DATA <= x"00"; when x"61" => DATA <= x"00"; when x"62" => DATA <= x"00"; when x"63" => DATA <= x"1C"; when x"64" => DATA <= x"20"; when x"65" => DATA <= x"20"; when x"66" => DATA <= x"3C"; when x"67" => DATA <= x"22"; when x"68" => DATA <= x"22"; when x"69" => DATA <= x"1C"; when x"6A" => DATA <= x"00"; when x"6B" => DATA <= x"00"; when x"6C" => DATA <= x"00"; when x"6D" => DATA <= x"00"; when x"6E" => DATA <= x"00"; when x"6F" => DATA <= x"00"; when x"70" => DATA <= x"00"; when x"71" => DATA <= x"00"; when x"72" => DATA <= x"00"; when x"73" => DATA <= x"3E"; when x"74" => DATA <= x"02"; when x"75" => DATA <= x"04"; when x"76" => DATA <= x"08"; when x"77" => DATA <= x"10"; when x"78" => DATA <= x"20"; when x"79" => DATA <= x"20"; when x"7A" => DATA <= x"00"; when x"7B" => DATA <= x"00"; when x"7C" => DATA <= x"00"; when x"7D" => DATA <= x"00"; when x"7E" => DATA <= x"00"; when x"7F" => DATA <= x"00"; when x"80" => DATA <= x"00"; when x"81" => DATA <= x"00"; when x"82" => DATA <= x"00"; when x"83" => DATA <= x"1C"; when x"84" => DATA <= x"22"; when x"85" => DATA <= x"22"; when x"86" => DATA <= x"1C"; when x"87" => DATA <= x"22"; when x"88" => DATA <= x"22"; when x"89" => DATA <= x"1C"; when x"8A" => DATA <= x"00"; when x"8B" => DATA <= x"00"; when x"8C" => DATA <= x"00"; when x"8D" => DATA <= x"00"; when x"8E" => DATA <= x"00"; when x"8F" => DATA <= x"00"; when x"90" => DATA <= x"00"; when x"91" => DATA <= x"00"; when x"92" => DATA <= x"00"; when x"93" => DATA <= x"1C"; when x"94" => DATA <= x"22"; when x"95" => DATA <= x"22"; when x"96" => DATA <= x"1E"; when x"97" => DATA <= x"02"; when x"98" => DATA <= x"02"; when x"99" => DATA <= x"1C"; when x"9A" => DATA <= x"00"; when x"9B" => DATA <= x"00"; when x"9C" => DATA <= x"00"; when x"9D" => DATA <= x"00"; when x"9E" => DATA <= x"00"; when x"9F" => DATA <= x"00"; when x"A0" => DATA <= x"00"; when x"A1" => DATA <= x"00"; when x"A2" => DATA <= x"00"; when x"A3" => DATA <= x"00"; when x"A4" => DATA <= x"18"; when x"A5" => DATA <= x"18"; when x"A6" => DATA <= x"00"; when x"A7" => DATA <= x"18"; when x"A8" => DATA <= x"18"; when x"A9" => DATA <= x"00"; when x"AA" => DATA <= x"00"; when x"AB" => DATA <= x"00"; when x"AC" => DATA <= x"00"; when x"AD" => DATA <= x"00"; when x"AE" => DATA <= x"00"; when x"AF" => DATA <= x"00"; when x"B0" => DATA <= x"00"; when x"B1" => DATA <= x"00"; when x"B2" => DATA <= x"00"; when x"B3" => DATA <= x"18"; when x"B4" => DATA <= x"18"; when x"B5" => DATA <= x"00"; when x"B6" => DATA <= x"18"; when x"B7" => DATA <= x"18"; when x"B8" => DATA <= x"08"; when x"B9" => DATA <= x"10"; when x"BA" => DATA <= x"00"; when x"BB" => DATA <= x"00"; when x"BC" => DATA <= x"00"; when x"BD" => DATA <= x"00"; when x"BE" => DATA <= x"00"; when x"BF" => DATA <= x"00"; when x"C0" => DATA <= x"00"; when x"C1" => DATA <= x"00"; when x"C2" => DATA <= x"00"; when x"C3" => DATA <= x"04"; when x"C4" => DATA <= x"08"; when x"C5" => DATA <= x"10"; when x"C6" => DATA <= x"20"; when x"C7" => DATA <= x"10"; when x"C8" => DATA <= x"08"; when x"C9" => DATA <= x"04"; when x"CA" => DATA <= x"00"; when x"CB" => DATA <= x"00"; when x"CC" => DATA <= x"00"; when x"CD" => DATA <= x"00"; when x"CE" => DATA <= x"00"; when x"CF" => DATA <= x"00"; when x"D0" => DATA <= x"00"; when x"D1" => DATA <= x"00"; when x"D2" => DATA <= x"00"; when x"D3" => DATA <= x"00"; when x"D4" => DATA <= x"00"; when x"D5" => DATA <= x"3E"; when x"D6" => DATA <= x"00"; when x"D7" => DATA <= x"3E"; when x"D8" => DATA <= x"00"; when x"D9" => DATA <= x"00"; when x"DA" => DATA <= x"00"; when x"DB" => DATA <= x"00"; when x"DC" => DATA <= x"00"; when x"DD" => DATA <= x"00"; when x"DE" => DATA <= x"00"; when x"DF" => DATA <= x"00"; when x"E0" => DATA <= x"00"; when x"E1" => DATA <= x"00"; when x"E2" => DATA <= x"00"; when x"E3" => DATA <= x"10"; when x"E4" => DATA <= x"08"; when x"E5" => DATA <= x"04"; when x"E6" => DATA <= x"02"; when x"E7" => DATA <= x"04"; when x"E8" => DATA <= x"08"; when x"E9" => DATA <= x"10"; when x"EA" => DATA <= x"00"; when x"EB" => DATA <= x"00"; when x"EC" => DATA <= x"00"; when x"ED" => DATA <= x"00"; when x"EE" => DATA <= x"00"; when x"EF" => DATA <= x"00"; when x"F0" => DATA <= x"00"; when x"F1" => DATA <= x"00"; when x"F2" => DATA <= x"00"; when x"F3" => DATA <= x"18"; when x"F4" => DATA <= x"24"; when x"F5" => DATA <= x"04"; when x"F6" => DATA <= x"08"; when x"F7" => DATA <= x"08"; when x"F8" => DATA <= x"00"; when x"F9" => DATA <= x"08"; when x"FA" => DATA <= x"00"; when x"FB" => DATA <= x"00"; when x"FC" => DATA <= x"00"; when x"FD" => DATA <= x"00"; when x"FE" => DATA <= x"00"; when x"FF" => DATA <= x"00"; when others => DATA <= (others => '0'); end case; end if; end process; end RTL;

ARCHITECTURE RTL of ENT is begin end; ARCHITECTURE RTL of ENT is begin end; ARCHITECTURE RTL of ENT is begin end;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: config -- File: config.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: GRLIB Global configuration package. Can be overriden -- by local config packages in template designs. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.config_types.all; package config is -- AHBDW - AHB data with -- -- Valid values are 32, 64, 128 and 256 -- -- The value here sets the width of the AMBA AHB data vectors for all -- cores in the library. -- constant CFG_AHBDW : integer := 64; -- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores -- -- Valid values are 0 and 1 -- -- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package -- will read their data from the low part of the AHB data vector. -- -- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package -- will select valid data, as defined in the AMBA AHB standard, from the -- AHB data vectors based on the address input. If a core uses a function -- that does not have the address input, a failure will be asserted. -- constant CFG_AHB_ACDM : integer := 0; -- GRLIB_CONFIG_ARRAY - Array of configuration values -- -- The length of this array and the meaning of different positions is defined -- in the grlib.config_types package. constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := ( grlib_debug_level => 0, grlib_debug_mask => 0, grlib_techmap_strict_ram => 0, others => 0); end;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:06:01 10/23/2013 -- Design Name: -- Module Name: practica1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity practica1 is port ( switch: in std_logic_vector(7 downto 0); leds: out std_logic_vector(7 downto 0) ); end practica1; architecture Behavioral of practica1 is begin leds <= not(switch); end Behavioral;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: syncfifo_2p -- File: syncfifo_2p.vhd -- Author: Andrea Gianarro - Aeroflex Gaisler AB -- Description: Syncronous 2-port fifo with tech selection ----------------------------------------------------------------------------- -- Revisions: -- 2014/12/16 Pascal Trotta: support for generic fifo -- Notes: Generic fifo has the following features & limitations: -- -almost full is driven only in write clock domain; -- -almost empty is driven only in read clock domain; -- -full and empty are driven in both clock domains; -- -usedw is re-computed in each clock domain; -- -in "first word fall through" mode empty should be observed as data -- valid signal. If renable is asserted while empty='0', and at the -- next read clock rising edge empty='1', then new read data is not -- valid because fifo is empty. This does not apply in standard fifo -- mode, i.e., when empty is asserted, the last read data is valid; -- -supports only sepclk=1, i.e., asynchronous read/write clocks. -- -it works also if rclk = wclk, but synchronization stages and gray -- encoder/decoder are always instantiated, even if not necessary. ------------------------------------------------------------------------------ library ieee; library techmap; use ieee.std_logic_1164.all; use techmap.gencomp.all; use work.allmem.all; library grlib; use grlib.config.all; use grlib.config_types.all; use grlib.stdlib.all; entity syncfifo_2p is generic ( tech : integer := 0; -- target technology abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits) dbits : integer := 32; -- fifo data width sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks pfull : integer := 100; -- almost full threshold (max 2**abits - 3) pempty : integer := 10; -- almost empty threshold (min 2) fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode ); port ( rclk : in std_logic; -- read clock rrstn : in std_logic; -- read clock domain synchronous reset wrstn : in std_logic; -- write clock domain synchronous reset renable : in std_logic; -- read enable rfull : out std_logic; -- fifo full (synchronized in read clock domain) rempty : out std_logic; -- fifo empty aempty : out std_logic; -- fifo almost empty (depending on pempty threshold) rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain) dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output wclk : in std_logic; -- write clock write : in std_logic; -- write enable wfull : out std_logic; -- fifo full afull : out std_logic; -- fifo almost full (depending on pfull threshold) wempty : out std_logic; -- fifo empty (synchronized in write clock domain) wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain) datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input end; architecture rtl of syncfifo_2p is begin -- Altera fifo alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or (tech = stratix3) or (tech = stratix4) generate x0 : altera_fifo_dp generic map (tech, abits, dbits) port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk, write, wfull, wempty, wusedw, datain); end generate; -- generic FIFO implemented using syncram_2p component inf : if (tech /= altera) and (tech /= stratix1) and (tech /= stratix2) and (tech /= stratix3) and (tech /= stratix4) generate x0: generic_fifo generic map (tech, abits, dbits, sepclk, pfull, pempty, fwft) port map (rclk, rrstn, wrstn, renable, rfull, rempty, aempty, rusedw, dataout, wclk, write, wfull, afull, wempty, wusedw, datain); end generate; -- pragma translate_off nofifo : if (has_2pfifo(tech) = 0) and (has_2pram(tech) = 0) generate x : process begin assert false report "syncfifo_2p: technology " & tech_table(tech) & " not supported" severity failure; wait; end process; end generate; dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate x : process begin assert false report "syncfifo_2p: " & tost(2**abits) & "x" & tost(dbits) & " (" & tech_table(tech) & ")" severity note; wait; end process; end generate; -- pragma translate_on end;

------------------------------------------------------------------------------ ---- ---- ---- I2C Master Testbench ---- ---- ---- ---- Internal file, can't be downloaded. ---- ---- ---- ---- Description: ---- ---- I2C module test bench. Connects a Wishbone handler and an I2C ---- ---- memory to the module. Then it makes some write/read operations. ---- ---- The test cases are the same performed by the Verilog test bench by ---- ---- Richard Herveille. ---- ---- ---- ---- To Do: ---- ---- - ---- ---- ---- ---- Author: ---- ---- - Salvador E. Tropea, salvador en inti gov ar ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ---- ---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Covered by the GPL license. ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: TB(TestBench) (Entity and architecture) ---- ---- File name: tst_bench_top.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: i2c_mwb ---- ---- Dependencies: IEEE.std_logic_1164 ---- ---- IEEE.numeric_std ---- ---- c.stdio_h ---- ---- wb_handler.WishboneTB ---- ---- irq_ctrl.I2C_TB ---- ---- irq_ctrl.I2C_Master ---- ---- Target FPGA: None ---- ---- Language: VHDL ---- ---- Wishbone: None ---- ---- Synthesis tools: None ---- ---- Simulation tools: GHDL [Sokcho edition] (0.1x) ---- ---- Text editor: SETEdit 0.5.x ---- ---- ---- ------------------------------------------------------------------------------ -- -- CVS Revision History -- -- $Log: tst_bench_top.vhdl,v $ -- Revision 1.11 2006/04/17 19:44:43 salvador -- * Modified: License to GPL. -- -- Revision 1.10 2005/05/20 14:39:05 salvador -- * Modificado: Mejorado el indentado usando bakalint 0.3.7. -- -- Revision 1.9 2005/05/18 14:50:20 salvador -- * Modificado: Los encabezados de los archivos para que cumplan con nuestras -- recomendaciones. -- -- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library c; use c.stdio_h.all; library wb_handler; use wb_handler.WishboneTB.all; library Work; use Work.I2C_TB.all; use Work.I2C_Master.all; entity TB is end entity TB; architecture TestBench of TB is -- Clock=100000 KHz constant CLKPERIOD : time:=10 us; signal delay : integer:=5; signal veces : integer:=0; signal addr : std_logic_vector(8-1 downto 0); signal datai : std_logic_vector(8-1 downto 0); signal datao : std_logic_vector(8-1 downto 0); signal rd : std_logic:='0'; signal wr : std_logic:='0'; signal rde : std_logic; signal wre : std_logic; signal wb_rst : std_logic:='1'; signal wb_clk : std_logic;--:='0'; signal wb_adr : std_logic_vector(8-1 downto 0); signal adr_o3 : unsigned(2 downto 0); signal wb_dati : std_logic_vector(8-1 downto 0):=(others => 'Z'); signal wb_dato : std_logic_vector(8-1 downto 0); signal wb_we : std_logic; signal wb_stb : std_logic; signal wb_cyc : std_logic; signal wb_ack : std_logic:='0'; signal inta : std_logic; signal scl_padi : std_logic; -- i2c clock line input signal scl_pado : std_logic; -- i2c clock line output signal scl_padoen : std_logic; -- i2c clock line output enable, active low signal sda_padi : std_logic; -- i2c data line input signal sda_pado : std_logic; -- i2c data line output signal sda_padoen : std_logic; -- i2c data line output enable, active low signal scl : std_logic; -- i2c clock line signal sda : std_logic; -- i2c data line signal sdar : std_logic; -- i2c data line signal sclr : std_logic; -- i2c data line constant PREV_LO : std_logic_vector(8-1 downto 0):="00000001"; constant PREV_HI : std_logic_vector(8-1 downto 0):="00000000"; constant RD_B : std_logic:='1'; constant WR_B : std_logic:='0'; constant SADR : std_logic_vector(6 downto 0):="0010000"; --Constant FIXED_PRER : integer:=-1; constant FIXED_PRER : integer:=1; procedure DelayCk(signal wb_clk_i: in std_logic; constant TIMES : in integer) is variable count : integer; begin count:=TIMES; while count>0 loop wait until rising_edge(wb_clk_i); count:=count-1; end loop; end procedure DelayCk; procedure CheckTIP(signal addr_o : out std_logic_vector(8-1 downto 0); signal data_i : in std_logic_vector(8-1 downto 0); signal rd_o : out std_logic; signal rde_i : in std_logic; constant ACKV : in boolean:=true) is begin WBRead(addr_o,I2C_SR,rd_o,rde_i); while data_i(1)='1' loop WBRead(addr_o,I2C_SR,rd_o,rde_i); end loop; if ACKV then assert data_i(7)='0' report "Expected ACK, received NACK" severity failure; else assert data_i(7)='1' report "Expected NACK, received ACK" severity failure; end if; end procedure CheckTIP; begin -- Clock clock_generator: process begin wb_clk <= '0'; wait for CLKPERIOD/2; wb_clk <= '1'; wait for CLKPERIOD/2; veces <= veces+1; if veces=1500 then assert false report "Fin de la simulación" severity failure; end if; end process clock_generator; -- Reset pulse p_reset: process begin wb_rst <= '1'; wait until rising_edge(wb_clk); wb_rst <= '0' after 500 ns; wait; end process p_reset; -- Wishbone master simulator wb_master: WBHandler port map( addr_i => addr, data_i => datai, data_o => datao, rd_i => rd, wr_i => wr, rde_o => rde, wre_o => wre, wb_rst_i => wb_rst, wb_clk_i => wb_clk, wb_ack_i => wb_ack, wb_adr_o => wb_adr, wb_dat_i => wb_dati, wb_dat_o => wb_dato, wb_we_o => wb_we, wb_stb_o => wb_stb, wb_cyc_o => wb_cyc); -- I2C module (Wishbone slave, I2C master) adr_o3 <= unsigned(wb_adr(2 downto 0)); wb_i2c: I2C_MasterTop generic map(DEBUG => false, FULL_SYNC => false, FIXED_PRER => FIXED_PRER) port map(-- Wishbone signals wb_clk_i => wb_clk, wb_rst_i => wb_rst, wb_adr_i => adr_o3, wb_dat_i => wb_dato, wb_dat_o => wb_dati, wb_we_i => wb_we, wb_stb_i => wb_stb, wb_cyc_i => wb_cyc, wb_ack_o => wb_ack, wb_inta_o => inta, -- i2c lines scl_pad_i => scl_padi, scl_pad_o => scl_pado, scl_padoen_o => scl_padoen, sda_pad_i => sda_padi, sda_pad_o => sda_pado, sda_padoen_o => sda_padoen); -- SCL/SDA pads scl <= 'Z' when scl_padoen='1' else scl_pado;-- after 600 ns; scl_padi <= sclr; scl <= 'H'; -- Pull-up sda <= 'Z' when sda_padoen='1' else sda_pado;-- after 600 ns; sda_padi <= sdar; sda <= 'H'; -- Pull-up -- SCL/SDA values converted to X/0/1/Z -- The I2C module can't handle 'H' sdar <= to_x01z(sda); sclr <= to_x01z(scl); -- I2C memory (I2C slave) i2c_mem: I2C_Memory generic map( I2C_ADR => SADR, DEBUG => false) port map( scl_x_i => scl, sda_x_io => sda, rst_i => wb_rst); sequence: process begin wait until wb_rst='0'; if FIXED_PRER=-1 then -- load prescaler lo-byte DelayCk(wb_clk,1); WBWrite(addr,I2C_PRER_LO,datai,PREV_LO,wr,wre); -- load prescaler hi-byte WBWrite(addr,I2C_PRER_HI,datai,PREV_HI,wr,wre); assert false report "Programmed registers" severity note; -- verify WBRead(addr,I2C_PRER_LO,rd,rde); if not(datao=PREV_LO) then printf("Prescaler lo: %s\n",datao); assert false report "Wrong prescaler lo readback" severity failure; end if; WBRead(addr,I2C_PRER_HI,rd,rde); assert datao=PREV_HI report "Wrong prescaler hi readback" severity failure; else assert false report "Using fixed pre-scaler" severity note; end if; -- enable core WBWrite(addr,I2C_CTR,datai,"10000000",wr,wre); -- 0x80 assert false report "Core Enabled" severity note; -- present slave address, set write-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate Start" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 01" severity note; CheckTIP(addr,datao,rd,rde); -- send memory contents -- present data WBWrite(addr,I2C_TXR,datai,"10100101",wr,wre); -- 0xA5 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write data 0xA5" severity note; CheckTIP(addr,datao,rd,rde); -- send memory contents for next memory address (auto_inc) -- present data WBWrite(addr,I2C_TXR,datai,"01011010",wr,wre); -- 0x5A -- set command (stop, write) WBWrite(addr,I2C_CR,datai,"01010000",wr,wre); -- 0x50 assert false report "Write next data 0x5A, generate 'stop'" severity note; CheckTIP(addr,datao,rd,rde); DelayCk(wb_clk,30); -- present slave address, set write-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate Start" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00000001",wr,wre); -- 0x01 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 01" severity note; CheckTIP(addr,datao,rd,rde); -- present slave address, set read-bit WBWrite(addr,I2C_TXR,datai,SADR & RD_B,wr,wre); -- 0x21 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate 'Repeated Start' (RD)" severity note; CheckTIP(addr,datao,rd,rde); -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); if unsigned(datao)=16#A5# then assert false report "Received ok" severity note; else printf("Wrong value: %s\n",datao); assert false report "Wrong value received" severity failure; end if; -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); if unsigned(datao)=16#5A# then assert false report "Received ok" severity note; else printf("Wrong value: %s\n",datao); assert false report "Wrong value received" severity failure; end if; -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); printf("Received 0x%X from 3rd read address\n",to_integer(unsigned(datao))); -- read data from slave -- set command (read, ack_read) WBWrite(addr,I2C_CR,datai,"00100000",wr,wre); -- 0x20 assert false report "Sending read + ack" severity note; CheckTIP(addr,datao,rd,rde); -- check data just received WBRead(addr,I2C_RXR,rd,rde); printf("Received 0x%X from 4th read address\n",to_integer(unsigned(datao))); -- present slave address, set read-bit WBWrite(addr,I2C_TXR,datai,SADR & WR_B,wr,wre); -- 0x20 -- set command (start, write) WBWrite(addr,I2C_CR,datai,"10010000",wr,wre); -- 0x90 assert false report "Generate 'Repeated Start' (RD)" severity note; CheckTIP(addr,datao,rd,rde); -- send memory address -- present slave's memory address WBWrite(addr,I2C_TXR,datai,"00010000",wr,wre); -- 0x10 -- set command (write) WBWrite(addr,I2C_CR,datai,"00010000",wr,wre); -- 0x10 assert false report "Write slave memory address 0x10" severity note; CheckTIP(addr,datao,rd,rde,false); assert false report "OK, NACK received" severity note; -- set command (stop) WBWrite(addr,I2C_CR,datai,"01000000",wr,wre); -- 0x40 assert false report "Sending stop" severity note; wait; end process sequence; end architecture TestBench; -- of entity TB

--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 --Date : Thu Mar 10 15:45:23 2016 --Host : minmi running 64-bit elementary OS Freya --Command : generate_target system_wrapper.bd --Design : system_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC; sw0 : in STD_LOGIC; sw1 : in STD_LOGIC; sw2 : in STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ); hdmi_out_en : out STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; sw0 : in STD_LOGIC; sw1 : in STD_LOGIC; sw2 : in STD_LOGIC ); end component system; begin system_i: component system port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, hdmi_cec => hdmi_cec, hdmi_hpd => hdmi_hpd, hdmi_out_en => hdmi_out_en, sw0 => sw0, sw1 => sw1, sw2 => sw2, tmds(3 downto 0) => tmds(3 downto 0), tmdsb(3 downto 0) => tmdsb(3 downto 0) ); end STRUCTURE;

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity I2C_ADN2816 is port (clk_i : in std_logic; sub_i2c_i: in std_logic; reset_n_i : in std_logic; sda_o : out std_logic; sda_dir_o : out std_logic; sclen_o: out std_logic); end I2C_ADN2816; architecture rtl of I2C_ADN2816 is type t_state is (waiting, send_START, send_A7, send_A6, send_A5, send_A4, send_A3, send_A2, send_A1, send_RW, read_A_ACK, send_SA7, send_SA6, send_SA5, send_SA4, send_SA3, send_SA2, send_SA1, send_SA0, read_SA_ACK, send_D7, send_D6, send_D5, send_D4, send_D3, send_D2, send_D1, send_D0, read_D_ACK, send_ACK, send_STOPCLK, send_PAUS1, send_PAUS2, send_PAUS3, send_PAUS4, send_PAUS5, send_PAUS6, send_PAUS7, send_STOP); signal s_state : t_state; signal s_count : std_logic; begin p_i2cmaster: process (clk_i, reset_n_i) begin -- process p_serin if (reset_n_i = '0') then -- asynchronous reset (active low) sda_dir_o <= '1'; sda_o <= '1'; sclen_o <= '0'; s_count <= '0'; s_state <= waiting; elsif rising_edge(clk_i) then -- rising clock edge case s_state is when send_START => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_A7 ; ------------------------------------------------------------------------- when send_A7 => sclen_o <= '1'; sda_o <= '1'; s_state <= send_A6; ------------------------------------------------------------------------- when send_A6 => sda_o <= s_count; --sda_o <= '1'; old PCB version s_state <= send_A5; ------------------------------------------------------------------------- when send_A5 => sda_o <= '0'; s_state <= send_A4; ------------------------------------------------------------------------- when send_A4 => sda_o <= '0'; s_state <= send_A3; ------------------------------------------------------------------------- when send_A3 => sda_o <= '0'; s_state <= send_A2; ------------------------------------------------------------------------- when send_A2 => sda_o <= '0'; s_state <= send_A1; ------------------------------------------------------------------------- when send_A1 => sda_o <= '0'; s_state <= send_RW; ----------------------------------------------------------------------- when send_RW => sda_o <= '0'; s_state <= read_A_ACK; ------------------------------------------------------------------------- when read_A_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_SA7; ------------------------------------------------------------------------- when send_SA7 => sda_dir_o <= '1'; sda_o <= '0'; s_state <= send_SA6; ------------------------------------------------------------------------- when send_SA6 => sda_o <= '0'; s_state <= send_SA5; ------------------------------------------------------------------------- when send_SA5 => sda_o <= '0'; s_state <= send_SA4; ------------------------------------------------------------------------- when send_SA4 => sda_o <= '0'; s_state <= send_SA3; ------------------------------------------------------------------------- when send_SA3 => sda_o <= '1'; s_state <= send_SA2; ------------------------------------------------------------------------- when send_SA2 => sda_o <= '0'; s_state <= send_SA1; ------------------------------------------------------------------------- when send_SA1 => sda_o <= '0'; s_state <= send_SA0; ----------------------------------------------------------------------- when send_SA0 => sda_o <= '0'; s_state <= read_SA_ACK; ------------------------------------------------------------------------- when read_SA_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_D7; ------------------------------------------------------------------------- when send_D7 => sda_dir_o <= '1'; sda_o <= '1'; s_state <= send_D6; ------------------------------------------------------------------------- when send_D6 => sda_o <= '1'; s_state <= send_D5; ------------------------------------------------------------------------- when send_D5 => sda_o <= '0'; s_state <= send_D4; ------------------------------------------------------------------------- when send_D4 => sda_o <= '1'; s_state <= send_D3; ------------------------------------------------------------------------- when send_D3 => sda_o <= '0'; s_state <= send_D2; ------------------------------------------------------------------------- when send_D2 => sda_o <= '1'; s_state <= send_D1; ------------------------------------------------------------------------- when send_D1 => sda_o <= '0'; s_state <= send_D0; ------------------------------------------------------------------------- when send_D0 => sda_o <= '1'; s_state <= read_D_ACK; ------------------------------------------------------------------------- when read_D_ACK => sda_o <= '0'; sda_dir_o <= '0'; s_state <= send_STOPCLK; ------------------------------------------------------------------------- when send_STOPCLK => sda_dir_o <= '1'; sda_o <= '0'; --sclen_o <= '0'; s_state <= send_STOP; ------------------------------------------------------------------------- when send_STOP => sda_o <= '1'; sclen_o <= '0'; s_state <= send_PAUS1; ------------------------------------------------------------------------- when send_PAUS1 => if (s_count ='0') then s_state <= send_PAUS2; else s_state <= waiting; end if; ------------------------------------------------------------------------- when send_PAUS2 => s_count <= '1'; s_state <= send_PAUS3; ------------------------------------------------------------------------- when send_PAUS3 => s_state <= send_PAUS4; ------------------------------------------------------------------------- when send_PAUS4 => s_state <= send_PAUS5; ------------------------------------------------------------------------- when send_PAUS5 => s_state <= send_PAUS6; ------------------------------------------------------------------------- when send_PAUS6 => s_state <= send_PAUS7; ------------------------------------------------------------------------- when send_PAUS7 => s_state <= send_START; ------------------------------------------------------ when others => if sub_i2c_i = '1' then -- VME Start I2C Cycle command detected. s_count <= '0'; s_state <= send_START; end if; end case; end if; end process p_i2cmaster; end rtl;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1402.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01402ent IS END c08s05b00x00p06n01i01402ent; ARCHITECTURE c08s05b00x00p06n01i01402arch OF c08s05b00x00p06n01i01402ent IS BEGIN TESTING: PROCESS type PT is range INTEGER'LOW to INTEGER'HIGH units sbu; end units; subtype ST is PT range 1 sbu to 10 sbu; variable ILL : PT := 11 sbu; variable V : ST; BEGIN V := ILL; -- should catch error here assert FALSE report "***FAILED TEST: c08s05b00x00p06n01i01402 - Variable assignment scalar subtype (physical type) check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01402arch;

architecture RTL of FIFO is procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 is constant width : integer := 32; begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is constant width : integer := 32; begin end procedure proc1; -- Fixes follow procedure proc1 is constant width : integer := 32; begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is constant width : integer := 32; begin end procedure proc1; begin end architecture RTL;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Sumador is Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0); Operador2 : in STD_LOGIC_VECTOR (31 downto 0); Resultado : out STD_LOGIC_VECTOR (31 downto 0)); end Sumador; architecture Behavioral of sumador is begin process(Operador1,Operador2) begin Resultado <= Operador1 + Operador2; end process; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity iq_ram is generic ( DATA_SIZE : integer := 16; ADDR_SIZE : integer := 13; AXI_SIZE : integer := 32 ); port ( -- AXi clk : in std_logic; rst : in std_logic; axi_addr : in std_logic_vector(AXI_SIZE-1 downto 0); axi_wrdata : in std_logic_vector(AXI_SIZE-1 downto 0); axi_rddata : out std_logic_vector(AXI_SIZE-1 downto 0); axi_cs : in std_logic_vector(1 downto 0); axi_rnw : in std_logic; axi_wrack : out std_logic; axi_rdack : out std_logic; axi_error : out std_logic; -- iQ SX1255 data_en : in std_logic; data_i : in std_logic_vector(DATA_SIZE-1 downto 0); data_q : in std_logic_vector(DATA_SIZE-1 downto 0); -- int CPU iRQ : out std_logic ); end entity; architecture rtl of iq_ram is component iq_ctrl is generic ( DATA_SIZE : integer := 16; ADDR_SIZE : integer := 13; AXI_SIZE : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; mux : out std_logic_vector(1 downto 0); new_sample : in std_logic; data_i_in : in std_logic_vector(DATA_SIZE-1 downto 0); data_q_in : in std_logic_vector(DATA_SIZE-1 downto 0); we_a : out std_logic; data_a : out std_logic_vector((2*DATA_SIZE)-1 downto 0); addr_a : out std_logic_vector(ADDR_SIZE-1 downto 0); irq : out std_logic ); end component; component iq_decim is generic ( DATA_SIZE : integer := 16; AXI_SIZE : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; start_acq : in std_logic; decim_in : in std_logic_vector(AXI_SIZE-1 downto 0); data_en : in std_logic; data_i_in : in std_logic_vector(DATA_SIZE-1 downto 0); data_q_in : in std_logic_vector(DATA_SIZE-1 downto 0); new_sample : out std_logic; data_i_out : out std_logic_vector(DATA_SIZE-1 downto 0); data_q_out : out std_logic_vector(DATA_SIZE-1 downto 0) ); end component; component iq_axi is generic ( AXI_SIZE : integer:= 32; ADDR_SIZE : integer := 13 ); port( -- AXi clk : in std_logic; rst : in std_logic; axi_addr : in std_logic_vector(AXI_SIZE-1 downto 0); axi_wrdata : in std_logic_vector(AXI_SIZE-1 downto 0); axi_rddata : out std_logic_vector(AXI_SIZE-1 downto 0); axi_cs : in std_logic_vector(1 downto 0); axi_rnw : in std_logic; axi_wrack : out std_logic; axi_rdack : out std_logic; axi_error : out std_logic; -- iQ FLOW start_acq : out std_logic; decim : out std_logic_vector(AXI_SIZE-1 downto 0); mux : in std_logic_vector(1 downto 0); -- RAM addr_b : out std_logic_vector(ADDR_SIZE-1 downto 0); data_b : in std_logic_vector(AXI_SIZE-1 downto 0) ); end component; component dual_port_ram is generic ( DATA : integer := 32; ADDR : integer := 13 ); port ( clk_a : in std_logic; clk_b : in std_logic; -- PORT A we_a : in std_logic; addr_a: in std_logic_vector(ADDR-1 downto 0); din_a : in std_logic_vector(DATA-1 downto 0); dout_a : out std_logic_vector(DATA-1 downto 0); -- PORT B we_b : in std_logic; addr_b: in std_logic_vector(ADDR-1 downto 0); din_b : in std_logic_vector(DATA-1 downto 0); dout_b: out std_logic_vector(DATA-1 downto 0) ); end component; signal start_acq_s : std_logic; signal we_a_s : std_logic; signal addr_a_s : std_logic_vector(ADDR_SIZE-1 downto 0); signal data_a_s : std_logic_vector(AXI_SIZE-1 downto 0); signal addr_b_s : std_logic_vector(ADDR_SIZE-1 downto 0); signal din_b_s : std_logic_vector(AXI_SIZE-1 downto 0); signal data_b_s : std_logic_vector(AXI_SIZE-1 downto 0); signal mux_s : std_logic_vector(1 downto 0); signal decim_s : std_logic_vector(AXI_SIZE-1 downto 0); signal new_sample_s : std_logic; signal data_i_s : std_logic_vector(DATA_SIZE-1 downto 0); signal data_q_s : std_logic_vector(DATA_SiZE-1 downto 0); begin CTRL: iq_ctrl generic map ( DATA_SIZE => DATA_SIZE, ADDR_SIZE => ADDR_SIZE, AXI_SIZE => AXI_SIZE ) port map ( -- Ctrl clk => clk, rst => rst, mux => mux_s, new_sample => new_sample_s, data_i_in => data_i_s, data_q_in => data_q_s, we_a => we_a_s, data_a => data_a_s, addr_a => addr_a_s, irq => irq ); DECIM: iq_decim generic map( DATA_SIZE => DATA_SIZE, AXI_SIZE => AXI_SIZE ) port map ( clk => clk, rst => rst, start_acq => start_acq_s, decim_in => decim_s, data_en => data_en, data_i_in => data_i, data_q_in => data_q, new_sample => new_sample_s, data_i_out => data_i_s, data_q_out => data_q_s ); AXI: iq_axi generic map ( AXI_SIZE => AXI_SIZE, ADDR_SIZE => ADDR_SIZE ) port map ( -- AXi clk => clk, rst => rst, axi_addr => axi_addr, axi_wrdata => axi_wrdata, axi_rddata => axi_rddata, axi_cs => axi_cs, axi_rnw => axi_rnw, axi_wrack => axi_wrack, axi_rdack => axi_rdack, axi_error => axi_error, -- IQ Ctrl start_acq => start_acq_s, decim => decim_s, mux => mux_s, -- RAM addr_b => addr_b_s, data_b => data_b_s ); din_b_s <= (others => '0'); RAM: dual_port_ram generic map ( DATA => AXI_SIZE, ADDR => ADDR_SIZE ) port map ( clk_a => clk, clk_b => clk, -- PORT A we_a => we_a_s, addr_a => addr_a_s, din_a => data_a_s, dout_a => open, -- PORT B we_b => '0', addr_b => addr_b_s, din_b => din_b_s, dout_b => data_b_s ); end rtl;

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:08:42 06/06/2016 -- Design Name: -- Module Name: C:/Users/AlvaroMoreno/Desktop/PROCESADOR2016/Sacagawea-master/test_memes.vhd -- Project Name: Sacagawea -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Dispositivos -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_memes IS END test_memes; ARCHITECTURE behavior OF test_memes IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Dispositivos PORT( ar : IN std_logic_vector(11 downto 0); clk : IN std_logic; ram_w_r : IN std_logic; bus_datos : INOUT std_logic_vector(7 downto 0); sal_leds_spartan : OUT std_logic_vector(7 downto 0); in_switches_spartan : IN std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal ar : std_logic_vector(11 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal ram_w_r : std_logic := '0'; signal in_switches_spartan : std_logic_vector(7 downto 0) := (others => '0'); --BiDirs signal bus_datos : std_logic_vector(7 downto 0); --Outputs signal sal_leds_spartan : std_logic_vector(7 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: Dispositivos PORT MAP ( ar => ar, clk => clk, ram_w_r => ram_w_r, bus_datos => bus_datos, sal_leds_spartan => sal_leds_spartan, in_switches_spartan => in_switches_spartan ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; clk <= '0'; bus_datos <= X"53"; ram_w_r <= '1'; ar <= X"400"; wait for 100 ns; clk <= '1'; bus_datos <= X"53"; wait for 100 ns; wait; end process; END;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alu is port ( op1: in std_logic_vector(31 downto 0); op2: in std_logic_vector(31 downto 0); alu_op: in std_logic_vector(3 downto 0); result: out std_logic_vector(31 downto 0); zero: out std_logic; less_than: out std_logic ); end alu; architecture arch_alu of alu is signal r, shift: std_logic_vector(31 downto 0); signal shift_op2: std_logic_vector(4 downto 0); signal addsub: std_logic_vector(32 downto 0); signal less, left, logical: std_logic; begin process(op1, op2, alu_op, addsub, less, shift_op2, shift) begin case alu_op is when "0000" => r <= op1 and op2; when "0001" => r <= op1 or op2; when "0010" => r <= op1 xor op2; when "0011" => r <= op1 nor op2; when "0100" | "0101" => r <= addsub(31 downto 0); when "0110" => r <= op2(15 downto 0) & x"0000"; when "0111" | "1000" => r <= x"0000000" & "000" & less; when others => r <= shift; end case; end process; addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2); less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31); less_than <= less; zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0)); shift_op2 <= op2(10 downto 6) when alu_op < "1100" else op2(4 downto 0); left <= '1' when alu_op = "1001" or alu_op = "1100" else '0'; logical <= '0' when alu_op = "1011" or alu_op = "1110" else '1'; barrel_shifter: entity work.bshift port map( left => left, logical => logical, shift => shift_op2, input => op1, output => shift ); result <= r; end arch_alu;

--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design for MCB Soft -- Calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working -- correctly) -- 1.2: 2/12/09: Many other changes. -- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within -- STATE -- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE -- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. -- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. -- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets -- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to -- RST_DELAY. -- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least -- 16 clocks. Added PNSKEW option. -- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. -- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. -- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced -- with 8bit TARGET_DQS_DELAY which -- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. -- Changed DQS_COUNT* to DQS_DELAY*. -- Changed MCB_SYSRST port back to wire (from reg). -- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) -- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. -- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; -- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) -- 3.4: 03/04/10: Recoded the RST_Reg logic. -- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) -- 3.6 03/10/10: Improvements to Reset logic. -- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . -- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). -- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. -- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic. -- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity. -- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that -- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. -- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT -- are set to 8 for LPDDR,DDR and DDR2 interface . -- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing -- Premable detection until the second deassertion of MCB_SYSRST. -- End Revision --********************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; entity mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic ; MCB_UIDQLOWERINC : out std_logic ; MCB_UIDQUPPERDEC : out std_logic ; MCB_UIDQUPPERINC : out std_logic ; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end entity mcb_soft_calibration; architecture trans of mcb_soft_calibration is constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); constant START : std_logic_vector(5 downto 0) := "000000"; constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; constant SKEW : std_logic_vector(5 downto 0) := "001100"; constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010"; constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011"; constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100"; constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101"; constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110"; constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111"; constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000"; constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001"; constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010"; constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011"; constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100"; constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101"; constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110"; constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111"; constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000"; constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001"; constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010"; constant WAIT7 : std_logic_vector(5 downto 0) := "100011"; constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100"; constant WAIT8 : std_logic_vector(5 downto 0) := "100101"; constant RST_DELAY : std_logic_vector(5 downto 0) := "100110"; constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111"; constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000"; constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001"; constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010"; constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011"; constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100"; constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101"; constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110"; constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111"; constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000"; constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001"; constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010"; constant WAIT9 : std_logic_vector(5 downto 0) := "110011"; constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100"; constant WAIT10 : std_logic_vector(5 downto 0) := "110101"; constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110"; constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111"; constant INCREMENT : std_logic_vector(5 downto 0) := "111000"; constant DECREMENT : std_logic_vector(5 downto 0) := "111001"; constant DONE : std_logic_vector(5 downto 0) := "111010"; --constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011"; constant RZQ : std_logic_vector(1 downto 0) := "00"; constant ZIO : std_logic_vector(1 downto 0) := "01"; constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; constant WRITE_MODE : std_logic := '0'; constant READ_MODE : std_logic := '1'; -- IOI Registers constant NoOp : std_logic_vector(7 downto 0) := "00000000"; constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; -- IOB Registers constant PDrive : std_logic_vector(7 downto 0) := "10000000"; constant PTerm : std_logic_vector(7 downto 0) := "10000001"; constant NDrive : std_logic_vector(7 downto 0) := "10000010"; constant NTerm : std_logic_vector(7 downto 0) := "10000011"; constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; constant InputControl : std_logic_vector(7 downto 0) := "10000111"; constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; -- No multi/divide is required when a 55 ohm resister is used on RZQ -- localparam MULT = 1; -- localparam DIV = 1; -- use 7/4 scaling factor when the 100 ohm RZQ is used constant MULT : integer := 7; constant DIV : integer := 4; constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required constant PNSKEWDQS : std_logic := '1'; constant MULT_S : integer := 9; constant DIV_S : integer := 8; constant MULT_W : integer := 7; constant DIV_W : integer := 8; constant DQS_NUMERATOR : integer := 3; constant DQS_DENOMINATOR : integer := 8; constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, -- 3 for three eighths constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; constant IN_TERM_PASS : std_logic := '0'; constant DYN_CAL_PASS : std_logic := '1'; function TZQINIT_MAXCNT_W return std_logic_vector is variable temp : std_logic_vector(9 downto 0) := (others=>'0'); begin if (C_MEM_TYPE = "DDR3") then temp := C_MEM_TZQINIT_MAXCNT + RST_CNT; else temp := 8 + RST_CNT; end if; return temp(9 downto 0); end function; constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W; component iodrp_mcb_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; drp_ioi_addr : in std_logic_vector(4 downto 0); sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic; MCB_UIREAD : out std_logic ); end component; component iodrp_controller is port ( memcell_address : in std_logic_vector(7 downto 0); write_data : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0); rd_not_write : in std_logic; cmd_valid : in std_logic; rdy_busy_n : out std_logic; use_broadcast : in std_logic; sync_rst : in std_logic; DRP_CLK : in std_logic; DRP_CS : out std_logic; DRP_SDI : out std_logic; DRP_ADD : out std_logic; DRP_BKST : out std_logic; DRP_SDO : in std_logic ); end component; signal P_Term : std_logic_vector(5 downto 0) := "000000"; signal N_Term : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_s : std_logic_vector(5 downto 0) := "000000"; signal N_Term_s : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_w : std_logic_vector(5 downto 0) := "000000"; signal N_Term_w : std_logic_vector(6 downto 0) := "0000000"; signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; signal STATE : std_logic_vector(5 downto 0); signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); signal Active_IODRP : std_logic_vector(1 downto 0); signal IODRPCTRLR_R_WB : std_logic := '0'; signal IODRPCTRLR_CMD_VALID : std_logic := '0'; signal IODRPCTRLR_USE_BKST : std_logic := '0'; signal MCB_CMD_VALID : std_logic := '0'; signal MCB_USE_BKST : std_logic := '0'; signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's -- SYSRST pin (MCB_SYSRST) signal IODRP_SDO : std_logic; signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit signal counter_en : std_logic := '0'; -- counter enable for "count" signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - -- state machine will wait for this to be high signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if -- the Max Value changes by more than the threshold signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with -- latency on UOREFRSHFLAG) signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); signal IODRPCTRLR_RDY_BUSY_N : std_logic; signal IODRP_CS : std_logic; signal MCB_READ_DATA : std_logic_vector(7 downto 0); signal RST_reg : std_logic; signal Block_Reset : std_logic; signal MCB_UODATAVALID_U : std_logic; signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); signal rst_tmp : std_logic; signal LastPass_DynCal : std_logic; signal First_In_Term_Done : std_logic; signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE -- parameter = "CALIBRATION" signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the -- one-time or dynamic parameters are 1 signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION signal Quarter_Max_Value : std_logic_vector(7 downto 0); signal Half_Max_Value : std_logic_vector(7 downto 0); signal PLL_LOCK_R1 : std_logic; signal PLL_LOCK_R2 : std_logic; signal MCB_RDY_BUSY_N : std_logic; signal SELFREFRESH_REQ_R1 : std_logic; signal SELFREFRESH_REQ_R2 : std_logic; signal SELFREFRESH_REQ_R3 : std_logic; signal SELFREFRESH_MCB_MODE_R1 : std_logic; signal SELFREFRESH_MCB_MODE_R2 : std_logic; signal SELFREFRESH_MCB_MODE_R3 : std_logic; signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; signal START_DYN_CAL_STATE_R1 : std_logic; signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; -- Declare intermediate signals for referenced outputs signal IODRP_ADD_xilinx0 : std_logic; signal IODRP_SDI_xilinx1 : std_logic; signal MCB_UIADD_xilinx2 : std_logic; signal MCB_UISDI_xilinx11 : std_logic; signal MCB_UICS_xilinx6 : std_logic; signal MCB_UIBROADCAST_xilinx4 : std_logic; signal MCB_UIADDR_int : std_logic_vector(4 downto 0); signal MCB_UIDONECAL_xilinx7 : std_logic; signal MCB_UIREAD_xilinx10 : std_logic; signal SELFREFRESH_MODE_xilinx11 : std_logic; signal Max_Value_int : std_logic_vector(7 downto 0); signal Rst_condition1 : std_logic; --signal Rst_condition2 : std_logic; signal non_violating_rst : std_logic; signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); signal WaitTimer : std_logic_vector(7 downto 0); signal WarmEnough : std_logic; signal WaitCountEnable : std_logic; signal State_Start_DynCal_R1 : std_logic; signal State_Start_DynCal : std_logic; signal pre_sysrst_minpulse_width_ok : std_logic; signal pre_sysrst_cnt : std_logic_vector(3 downto 0); -- This function multiplies by a constant MULT and then divides by the DIV constant function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is variable Result : integer := 0; variable temp : std_logic_vector(14 downto 0) := "000000000000000"; begin for count in 0 to (MULT-1) loop temp := temp + ("0000000" & Input); end loop; Result := (to_integer(unsigned(temp))) / (DIV); temp := std_logic_vector(to_unsigned(Result,15)); return temp(7 downto 0); end function Mult_Divide; attribute syn_preserve : boolean; attribute syn_preserve of P_Term : signal is TRUE; attribute syn_preserve of N_Term : signal is TRUE; attribute syn_preserve of P_Term_s : signal is TRUE; attribute syn_preserve of N_Term_s : signal is TRUE; attribute syn_preserve of P_Term_w : signal is TRUE; attribute syn_preserve of N_Term_w : signal is TRUE; attribute syn_preserve of P_Term_Prev : signal is TRUE; attribute syn_preserve of N_Term_Prev : signal is TRUE; attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; attribute syn_preserve of Max_Value_Previous : signal is TRUE; attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; attribute iob : string; attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; begin -- move the default assignment here to make FORMALITY happy. START_BROADCAST <= '1'; MCB_RECAL <= '0'; MCB_UIDQLOWERDEC <= '0'; MCB_UIADDR <= MCB_UIADDR_int; MCB_UIDQLOWERINC <= '0'; MCB_UIDQUPPERDEC <= '0'; MCB_UIDQUPPERINC <= '0'; Max_Value <= Max_Value_int; -- Drive referenced outputs IODRP_ADD <= IODRP_ADD_xilinx0; IODRP_SDI <= IODRP_SDI_xilinx1; MCB_UIADD <= MCB_UIADD_xilinx2; MCB_UISDI <= MCB_UISDI_xilinx11; MCB_UICS <= MCB_UICS_xilinx6; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; MCB_UIREAD <= MCB_UIREAD_xilinx10; SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; -- skip dynamic input termination if either the one-time or dynamic parameters are 1 SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high else DONE_SOFTANDHARD_CAL <= '0'; end if; end if; end process; iodrp_controller_inst : iodrp_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => IODRPCTRLR_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => IODRPCTRLR_CMD_VALID, rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, use_broadcast => '0', sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => IODRP_CS, DRP_SDI => IODRP_SDI_xilinx1, DRP_ADD => IODRP_ADD_xilinx0, DRP_SDO => IODRP_SDO, DRP_BKST => open ); iodrp_mcb_controller_inst : iodrp_mcb_controller port map ( memcell_address => IODRPCTRLR_MEMCELL_ADDR, write_data => IODRPCTRLR_WRITE_DATA, read_data => MCB_READ_DATA, rd_not_write => IODRPCTRLR_R_WB, cmd_valid => MCB_CMD_VALID, rdy_busy_n => MCB_RDY_BUSY_N, use_broadcast => MCB_USE_BKST, drp_ioi_addr => MCB_UIADDR_int, sync_rst => RST_reg, DRP_CLK => UI_CLK, DRP_CS => MCB_UICS_xilinx6, DRP_SDI => MCB_UISDI_xilinx11, DRP_ADD => MCB_UIADD_xilinx2, DRP_BKST => MCB_UIBROADCAST_xilinx4, DRP_SDO => MCB_UOSDO, MCB_UIREAD => MCB_UIREAD_xilinx10 ); process (UI_CLK, RST) begin if (RST = '1') then if (C_SIMULATION = "TRUE") then WAIT_200us_COUNTER <= X"7FF0"; else WAIT_200us_COUNTER <= (others => '0'); end if; elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '1') then WAIT_200us_COUNTER <= WAIT_200us_COUNTER; else WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; end if; end if; end process; -- init_sequence_skip: if (C_SIMULATION = "TRUE") generate -- WAIT_200us_COUNTER <= X"FFFF"; -- process -- begin -- report "The 200 us wait period required before CKE goes active has been skipped in Simulation"; -- wait; -- end process; -- end generate; gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate process (UI_CLK, RST) begin if (RST = '1') then CKE_Train <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then CKE_Train <= '0'; elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then CKE_Train <= '1'; else CKE_Train <= '0'; end if; end if; end process; end generate ; gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then CKE_Train <= '0'; end if; end process; end generate ; --******************************************** -- PLL_LOCK and RST signals --******************************************** --MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's -- SYSRST pin (MCB_SYSRST) rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND process (UI_CLK, RST) begin if (RST = '1') then --Block_Reset <= '0'; --RstCounter <= (others => '0'); --elsif (UI_CLK'event and UI_CLK = '1') then -- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) Block_Reset <= '0'; RstCounter <= (others => '0'); elsif (UI_CLK'event and UI_CLK = '1') then Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state if (Pre_SYSRST = '1') then RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 else if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute Block_Reset <= '1'; -- STATE won't exit RST_DELAY state RstCounter <= RstCounter + "1"; -- and Rst_Counter increments end if; end if; end if; --end if; end process; -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT non_violating_rst <= RST and Rst_condition1; MCB_SYSRST <= Pre_SYSRST; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RstCounter >= TZQINIT_MAXCNT) then Rst_condition1 <= '1'; else Rst_condition1 <= '0'; end if; end if; end process; -- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3) -- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process. -- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which -- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which -- will cause MCB to reset and reinitialize the memory afterwards. -- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at -- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module -- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration -- state machine will not reset during SUSPEND. -- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to -- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. -- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT -- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration. --process (UI_CLK) begin -- if (UI_CLK'event and UI_CLK = '1') then -- -- if (RstCounter < RST_CNT) then -- Rst_condition2 <= '1'; -- else -- Rst_condition2 <= '0'; -- end if; -- end if; --end process; process (UI_CLK, non_violating_rst) begin if (non_violating_rst = '1') then RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND elsif (UI_CLK'event and UI_CLK = '1') then if (WAIT_200us_COUNTER(15) = '0') then RST_reg <= '1'; else --RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long end if; end if; end process; --************************************************************* -- Stretching the pre_sysrst to satisfy the minimum pulse width --************************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (STATE = START_DYN_CAL_PRE) then pre_sysrst_cnt <= pre_sysrst_cnt + '1'; else pre_sysrst_cnt <= (others=>'0'); end if; end if; end process; pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3); --******************************************** -- SUSPEND Logic --******************************************** process (UI_CLK,RST) begin if (RST = '1') then SELFREFRESH_MCB_MODE_R1 <= '0'; SELFREFRESH_MCB_MODE_R2 <= '0'; SELFREFRESH_MCB_MODE_R3 <= '0'; SELFREFRESH_REQ_R1 <= '0'; SELFREFRESH_REQ_R2 <= '0'; SELFREFRESH_REQ_R3 <= '0'; PLL_LOCK_R1 <= '0'; PLL_LOCK_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; -- SELFREFRESH_REQ is clocked by user's application clock SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; PLL_LOCK_R1 <= PLL_LOCK; PLL_LOCK_R2 <= PLL_LOCK_R1; end if; end process; -- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. -- This is to make sure MCB get a locked sys_2x_clk before exiting -- SELFREFRESH mode. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MCB_REQ <= '0'; --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then SELFREFRESH_MCB_REQ <= '0'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then SELFREFRESH_MCB_REQ <= '1'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then -- START_DYN_CAL is next state WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; end if; end if; end process; -- Need to detect when SM entering START_DYN_CAL process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; START_DYN_CAL_STATE_R1 <= '0'; else -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; if (STATE = START_DYN_CAL) then START_DYN_CAL_STATE_R1 <= '1'; else START_DYN_CAL_STATE_R1 <= '0'; end if; if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; end if; end if; end if; end process; -- SELFREFRESH_MCB_MODE deasserted status is hold off -- until Soft_Calib has at least done one loop of DQS update. -- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before -- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before -- user logic sending new commands to MCB. process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; elsif (SELFREFRESH_MCB_MODE_R2 = '1') then SELFREFRESH_MODE_xilinx11 <= '1'; elsif (WarmEnough = '1') then SELFREFRESH_MODE_xilinx11 <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitCountEnable <= '0'; elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then WaitCountEnable <= '0'; elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then WaitCountEnable <= '1'; else WaitCountEnable <= WaitCountEnable; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal <= '0'; elsif (STATE = START_DYN_CAL) then State_Start_DynCal <= '1'; else State_Start_DynCal <= '0'; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then State_Start_DynCal_R1 <= '0'; else State_Start_DynCal_R1 <= State_Start_DynCal; end if; end if; end process; process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST = '1') then WaitTimer <= (others => '0'); WarmEnough <= '1'; elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then WaitTimer <= (others => '0'); WarmEnough <= '0'; elsif (WaitTimer = X"04") then WaitTimer <= WaitTimer ; WarmEnough <= '1'; elsif (WaitCountEnable = '1') then WaitTimer <= WaitTimer + '1'; else WaitTimer <= WaitTimer ; end if; end if; end process; --******************************************** --Comparitor for Dynamic Calibration circuit --******************************************** Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; --********************************************************************************************* --Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal --********************************************************************************************* process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then count <= "000000"; elsif (counter_en = '1') then count <= count + "000001"; else count <= "000000"; end if; end if; end process; --********************************************************************************************* -- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide --********************************************************************************************* process (UI_CLK, MCB_UODATAVALID) begin if(MCB_UODATAVALID = '1') then MCB_UODATAVALID_U <= '1'; elsif(UI_CLK'event and UI_CLK = '1') then MCB_UODATAVALID_U <= MCB_UODATAVALID; end if; end process; --************************************************************************************************************** --Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) --************************************************************************************************************** process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) begin case Active_IODRP is when RZQ => RZQ_IODRP_CS <= IODRP_CS; ZIO_IODRP_CS <= '0'; IODRP_SDO <= RZQ_IODRP_SDO; when ZIO => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= IODRP_CS; IODRP_SDO <= ZIO_IODRP_SDO; when MCB_PORT => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; when others => RZQ_IODRP_CS <= '0'; ZIO_IODRP_CS <= '0'; IODRP_SDO <= '0'; end case; end process; --****************************************************************** --State Machine's Always block / Case statement for Next State Logic -- --The WAIT1,2,etc states were required after every state where the --DRP controller was used to do a write to the IODRPs - this is because --there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller --sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added --soley for the purpose of reducing power, particularly on RZQ as --that pin is expected to have a permanent external resistor to gnd. --****************************************************************** NEXT_STATE_LOGIC: process (UI_CLK) begin if (UI_CLK'event and UI_CLK = '1') then if (RST_reg = '1') then -- Synchronous reset MCB_CMD_VALID <= '0'; MCB_UIADDR_int <= "00000"; -- take control of UI/UO port MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. MCB_UIDONECAL_xilinx7 <= '0'; MCB_USE_BKST <= '0'; MCB_UIDRPUPDATE <= '1'; Pre_SYSRST <= '1'; -- keeps MCB in reset IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; P_Term_s <= "000000"; N_Term_w <= "0000000"; P_Term_w <= "000000"; N_Term_s <= "0000000"; P_Term_Prev <= "000000"; N_Term_Prev <= "0000000"; Active_IODRP <= RZQ; MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; counter_en <= '0'; --flag that the First Dynamic Calibration completed First_Dyn_Cal_Done <= '0'; Max_Value_int <= "00000000"; Max_Value_Previous <= "00000000"; STATE <= START; DQS_DELAY <= "00000000"; DQS_DELAY_INITIAL <= "00000000"; TARGET_DQS_DELAY <= "00000000"; LastPass_DynCal <= IN_TERM_PASS; First_In_Term_Done <= '0'; MCB_UICMD <= '0'; MCB_UICMDIN <= '0'; MCB_UIDQCOUNT <= "0000"; counter_inc <= "00000000"; counter_dec <= "00000000"; else counter_en <= '0'; IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= NoOp; IODRPCTRLR_R_WB <= READ_MODE; IODRPCTRLR_USE_BKST <= '0'; MCB_CMD_VALID <= '0'; --no inc or dec MCB_UILDQSINC <= '0'; --no inc or dec MCB_UIUDQSINC <= '0'; --no inc or dec MCB_UILDQSDEC <= '0'; --no inc or dec MCB_UIUDQSDEC <= '0'; MCB_USE_BKST <= '0'; MCB_UICMDIN <= '0'; DQS_DELAY <= DQS_DELAY; TARGET_DQS_DELAY <= TARGET_DQS_DELAY; case STATE is when START => --h00 MCB_UICMDEN <= '1'; -- take control of UI/UO port MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. P_Term <= "000000"; N_Term <= "0000000"; Pre_SYSRST <= '1'; -- keeps MCB in reset LastPass_DynCal <= IN_TERM_PASS; if (SKIP_IN_TERM_CAL = 1) then --STATE <= WRITE_CALIBRATE; STATE <= WAIT_FOR_START_BROADCAST; P_Term <= "000000"; N_Term <= "0000000"; elsif (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= START; end if; --*************************** -- IOB INPUT TERMINATION CAL --*************************** when LOAD_RZQ_NTERM => --h01 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_NTERM; else STATE <= WAIT1; end if; when WAIT1 => --h02 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT1; else STATE <= LOAD_RZQ_PTERM; end if; when LOAD_RZQ_PTERM => --h03 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_RZQ_PTERM; else STATE <= WAIT2; end if; when WAIT2 => --h04 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT2; elsif ((RZQ_IN = '1') or (P_Term = "111111")) then STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM else STATE <= INC_PTERM; end if; when INC_PTERM => --h05 P_Term <= P_Term + "000001"; STATE <= LOAD_RZQ_PTERM; when MULTIPLY_DIVIDE => -- h06 -- 13/4/2011 compensate the added sync FF P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0); STATE <= LOAD_ZIO_PTERM; when LOAD_ZIO_PTERM => --h07 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_PTERM; else STATE <= WAIT3; end if; when WAIT3 => --h08 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT3; else STATE <= LOAD_ZIO_NTERM; end if; when LOAD_ZIO_NTERM => --h09 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= LOAD_ZIO_NTERM; else STATE <= WAIT4; end if; when WAIT4 => --h0A if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if; else STATE <= INC_NTERM; end if; when INC_NTERM => --h0B N_Term <= N_Term + "0000001"; STATE <= LOAD_ZIO_NTERM; when SKEW => -- h0C P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0); N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0); P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0); N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0); STATE <= WAIT_FOR_START_BROADCAST; when WAIT_FOR_START_BROADCAST => --h0D Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while -- keeping the MCB in calibration mode Active_IODRP <= MCB_PORT; if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then STATE <= BROADCAST_PTERM; P_Term_Prev <= P_Term; elsif (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT_FOR_START_BROADCAST; end if; when BROADCAST_PTERM => --h0E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through MCB_USE_BKST <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_PTERM; else STATE <= WAIT5; end if; when WAIT5 => --h0F if ((not(MCB_RDY_BUSY_N)) = '1') then STATE <= WAIT5; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; if (N_Term /= N_Term_Prev) then N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; else STATE <= OFF_RZQ_PTERM; end if; else STATE <= WAIT5; -- wait for a Refresh cycle end if; else N_Term_Prev <= N_Term; STATE <= BROADCAST_NTERM; end if; when BROADCAST_NTERM => -- h10 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); IODRPCTRLR_R_WB <= WRITE_MODE; MCB_CMD_VALID <= '1'; MCB_USE_BKST <= '1'; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (MCB_RDY_BUSY_N = '1') then STATE <= BROADCAST_NTERM; else STATE <= WAIT6; end if; when WAIT6 => -- h11 if (MCB_RDY_BUSY_N = '0') then STATE <= WAIT6; elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term if (MCB_UOREFRSHFLAG = '1')then MCB_UIDRPUPDATE <= '1'; STATE <= OFF_RZQ_PTERM; else STATE <= WAIT6; -- wait for a Refresh cycle end if; else -- if (PNSKEWDQS = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; -- else -- STATE <= OFF_RZQ_PTERM; -- end if; end if; -- ********************* when LDQS_CLK_WRITE_P_TERM => -- h12 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_P_TERM; else STATE <= LDQS_CLK_P_TERM_WAIT; end if; when LDQS_CLK_P_TERM_WAIT => --7'h13 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_P_TERM_WAIT; else STATE <= LDQS_CLK_WRITE_N_TERM; end if; when LDQS_CLK_WRITE_N_TERM => --7'h14 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_CLK_WRITE_N_TERM; else STATE <= LDQS_CLK_N_TERM_WAIT; end if; --** when LDQS_CLK_N_TERM_WAIT => --7'h15 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_CLK_N_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_P_TERM; end if; when LDQS_PIN_WRITE_P_TERM => --7'h16 IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_P_TERM; else STATE <= LDQS_PIN_P_TERM_WAIT; end if; when LDQS_PIN_P_TERM_WAIT => --7'h17 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_P_TERM_WAIT; else STATE <= LDQS_PIN_WRITE_N_TERM; end if; when LDQS_PIN_WRITE_N_TERM => --7'h18 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_LDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_PIN_WRITE_N_TERM; else STATE <= LDQS_PIN_N_TERM_WAIT; end if; when LDQS_PIN_N_TERM_WAIT => --7'h19 if (MCB_RDY_BUSY_N = '0') then STATE <= LDQS_PIN_N_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_P_TERM; end if; when UDQS_CLK_WRITE_P_TERM => --7'h1A IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_P_TERM; else STATE <= UDQS_CLK_P_TERM_WAIT; end if; when UDQS_CLK_P_TERM_WAIT => --7'h1B if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_P_TERM_WAIT; else STATE <= UDQS_CLK_WRITE_N_TERM; end if; when UDQS_CLK_WRITE_N_TERM => --7'h1C IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_CLK_WRITE_N_TERM; else STATE <= UDQS_CLK_N_TERM_WAIT; end if; when UDQS_CLK_N_TERM_WAIT => --7'h1D if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_CLK_N_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_P_TERM; end if; when UDQS_PIN_WRITE_P_TERM => --7'h1E IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_P_TERM; else STATE <= UDQS_PIN_P_TERM_WAIT; end if; when UDQS_PIN_P_TERM_WAIT => --7'h1F if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_P_TERM_WAIT; else STATE <= UDQS_PIN_WRITE_N_TERM; end if; when UDQS_PIN_WRITE_N_TERM => --7'h20 IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w; MCB_UIADDR_int <= IOI_UDQS_PIN; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= UDQS_PIN_WRITE_N_TERM; else STATE <= UDQS_PIN_N_TERM_WAIT; end if; when UDQS_PIN_N_TERM_WAIT => --7'h21 if (MCB_RDY_BUSY_N = '0') then STATE <= UDQS_PIN_N_TERM_WAIT; else STATE <= OFF_RZQ_PTERM; end if; -- ********************* when OFF_RZQ_PTERM => -- h22 Active_IODRP <= RZQ; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= PTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; P_Term <= "000000"; N_Term <= "0000000"; MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_RZQ_PTERM; else STATE <= WAIT7; end if; when WAIT7 => -- h23 if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT7; else STATE <= OFF_ZIO_NTERM; end if; when OFF_ZIO_NTERM => -- h24 Active_IODRP <= ZIO; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= NTerm; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= WRITE_MODE; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= OFF_ZIO_NTERM; else STATE <= WAIT8; end if; when WAIT8 => -- h25 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT8; else if (First_In_Term_Done = '1') then STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning else STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ end if; end if; when RST_DELAY => -- h26 --MCB_UICMDEN <= '0'; -- release control of UI/UO port if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? STATE <= RST_DELAY; else STATE <= START_DYN_CAL_PRE; end if; --*************************** --DYNAMIC CALIBRATION PORTION --*************************** when START_DYN_CAL_PRE => -- h27 LastPass_DynCal <= IN_TERM_PASS; MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '1'; -- SYSRST pulse if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually elsif (pre_sysrst_minpulse_width_ok = '1') then STATE <= WAIT_FOR_UODONE; end if; when WAIT_FOR_UODONE => -- h28 Pre_SYSRST <= '0'; -- SYSRST pulse if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration MCB_UICMDEN <= '1'; -- grab UICMDEN DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= WAIT_FOR_UODONE; end if; when LDQS_WRITE_POS_INDELAY => -- h29 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1') then STATE <= LDQS_WRITE_POS_INDELAY; else STATE <= LDQS_WAIT1; end if; when LDQS_WAIT1 => -- h2A if (MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT1; else STATE <= LDQS_WRITE_NEG_INDELAY; end if; when LDQS_WRITE_NEG_INDELAY => -- h2B IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_LDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= LDQS_WRITE_NEG_INDELAY; else STATE <= LDQS_WAIT2; end if; when LDQS_WAIT2 => -- 7'h2C if(MCB_RDY_BUSY_N = '0')then STATE <= LDQS_WAIT2; else STATE <= UDQS_WRITE_POS_INDELAY; end if; when UDQS_WRITE_POS_INDELAY => -- 7'h2D IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_POS_INDELAY; else STATE <= UDQS_WAIT1; end if; when UDQS_WAIT1 => -- 7'h2E if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT1; else STATE <= UDQS_WRITE_NEG_INDELAY; end if; when UDQS_WRITE_NEG_INDELAY => -- 7'h2F IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; IODRPCTRLR_R_WB <= WRITE_MODE; IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; MCB_UIADDR_int <= IOI_UDQS_CLK; MCB_CMD_VALID <= '1'; if (MCB_RDY_BUSY_N = '1')then STATE <= UDQS_WRITE_NEG_INDELAY; else STATE <= UDQS_WAIT2; end if; when UDQS_WAIT2 => -- 7'h30 if (MCB_RDY_BUSY_N = '0')then STATE <= UDQS_WAIT2; else DQS_DELAY <= DQS_DELAY_INITIAL; TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; STATE <= START_DYN_CAL; end if; when START_DYN_CAL => -- h31 Pre_SYSRST <= '0'; -- SYSRST not driven counter_inc <= (others => '0'); counter_dec <= (others => '0'); if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration -- Alternate between Dynamic Input Termination and Dynamic Tuning routines if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then LastPass_DynCal <= IN_TERM_PASS; STATE <= LOAD_RZQ_NTERM; else LastPass_DynCal <= DYN_CAL_PASS; STATE <= WRITE_CALIBRATE; end if; else STATE <= START_DYN_CAL; end if; when WRITE_CALIBRATE => -- h32 Pre_SYSRST <= '0'; IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= DelayControl; IODRPCTRLR_WRITE_DATA <= "00100000"; IODRPCTRLR_R_WB <= WRITE_MODE; Active_IODRP <= RZQ; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= WRITE_CALIBRATE; else STATE <= WAIT9; end if; when WAIT9 => -- h33 counter_en <= '1'; if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE STATE <= WAIT9; else STATE <= READ_MAX_VALUE; end if; when READ_MAX_VALUE => -- h34 IODRPCTRLR_CMD_VALID <= '1'; IODRPCTRLR_MEMCELL_ADDR <= MaxValue; IODRPCTRLR_R_WB <= READ_MODE; Max_Value_Previous <= Max_Value_int; if (IODRPCTRLR_RDY_BUSY_N = '1') then STATE <= READ_MAX_VALUE; else STATE <= WAIT10; end if; when WAIT10 => -- h35 if (IODRPCTRLR_RDY_BUSY_N = '0') then STATE <= WAIT10; else Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller if (First_In_Term_Done = '0') then STATE <= RST_DELAY; First_In_Term_Done <= '1'; else STATE <= ANALYZE_MAX_VALUE; end if; end if; when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle. if (First_Dyn_Cal_Done = '0')then STATE <= FIRST_DYN_CAL; elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then STATE <= DECREMENT; -- May need to Decrement TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); -- DQS_COUNT_VIRTUAL updated (could be negative value) elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then STATE <= INCREMENT; -- May need to Increment TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); else Max_Value_int <= Max_Value_Previous; STATE <= START_DYN_CAL; end if; when FIRST_DYN_CAL => -- h37 First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed STATE <= START_DYN_CAL; when INCREMENT => -- h38 STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "101" => counter_inc <= counter_inc + '1'; STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then -- if not at the upper limit yet, and you've waited 4 clks, increment MCB_UILDQSINC <= '1'; MCB_UIUDQSINC <= '1'; DQS_DELAY <= DQS_DELAY + '1'; end if; when "100" => if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; when DECREMENT => -- h39 STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH MCB_UILDQSINC <= '0'; -- Default case: no inc or dec MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec if (DQS_DELAY /= "00000000") then case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, when "011" => counter_dec <= counter_dec + '1'; STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then -- if not at the lower limit, and you've waited 4 clks, decrement MCB_UILDQSDEC <= '1'; -- decrement MCB_UIUDQSDEC <= '1'; -- decrement DQS_DELAY <= DQS_DELAY - '1'; -- SBS end if; when "010" => if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH end if; when others => STATE <= START_DYN_CAL; end case; end if; when DONE => -- h3A Pre_SYSRST <= '0'; -- SYSRST cleared MCB_UICMDEN <= '0'; -- release UICMDEN STATE <= DONE; when others => MCB_UICMDEN <= '0'; -- release UICMDEN MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. Pre_SYSRST <= '0'; -- SYSRST not driven IODRPCTRLR_CMD_VALID <= '0'; IODRPCTRLR_MEMCELL_ADDR <= "00000000"; IODRPCTRLR_WRITE_DATA <= "00000000"; IODRPCTRLR_R_WB <= '0'; IODRPCTRLR_USE_BKST <= '0'; P_Term <= "000000"; N_Term <= "0000000"; Active_IODRP <= ZIO; Max_Value_Previous <= "00000000"; MCB_UILDQSINC <= '0'; -- no inc or dec MCB_UIUDQSINC <= '0'; -- no inc or dec MCB_UILDQSDEC <= '0'; -- no inc or dec MCB_UIUDQSDEC <= '0'; -- no inc or dec counter_en <= '0'; First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed Max_Value_int <= Max_Value_int; STATE <= START; end case; end if; end if; end process; end architecture trans;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart is PORT( CLK_I : in std_logic; CLR : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); end uart; architecture Behavioral of uart is COMPONENT uart_tx PORT( CLK_I : IN std_logic; CLR : IN std_logic; CE_16 : IN std_logic; DATA : IN std_logic_vector(7 downto 0); DATA_FLAG : IN std_logic; SER_OUT : OUT std_logic; DATA_FLAGQ : OUT std_logic ); END COMPONENT; COMPONENT uart_rx PORT( CLK_I : IN std_logic; CLR : IN std_logic; CE_16 : IN std_logic; SER_IN : IN std_logic; DATA : OUT std_logic_vector(7 downto 0); DATA_FLAG : OUT std_logic ); END COMPONENT; begin tx: uart_tx PORT MAP( CLK_I => CLK_I, CLR => CLR, CE_16 => CE_16, DATA => TX_DATA, DATA_FLAG => TX_FLAG, SER_OUT => TX_SEROUT, DATA_FLAGQ => TX_FLAGQ ); rx: uart_rx PORT MAP( CLK_I => CLK_I, CLR => CLR, CE_16 => CE_16, DATA => RX_DATA, SER_IN => RX_SERIN, DATA_FLAG => RX_FLAG ); end Behavioral;

-- a_ng.vhd package TEST_TYPES is type WIDTH_TYPE is record DATA : integer; end record; end package; use work.TEST_TYPES.all; entity TEST_SUB is generic ( WIDTH : WIDTH_TYPE ); port ( DATA_I : in bit_vector(WIDTH.DATA-1 downto 0); DATA_O : out bit_vector(WIDTH.DATA-1 downto 0) ); end TEST_SUB; architecture MODEL of TEST_SUB is begin DATA_O <= DATA_I; end MODEL; use work.TEST_TYPES.all; entity TEST_NG is end TEST_NG; architecture MODEL of TEST_NG is constant WIDTH : WIDTH_TYPE := (DATA => 8); -- Could not fold this signal DATA_I : bit_vector(WIDTH.DATA-1 downto 0); signal DATA_O : bit_vector(WIDTH.DATA-1 downto 0); begin DUT: entity WORK.TEST_SUB generic map (WIDTH => WIDTH) port map (DATA_I => DATA_I, DATA_O => DATA_O); process begin DATA_I <= "00000000"; wait for 10 ns; assert(DATA_O /= "00000000") report "OK." severity NOTE; assert(DATA_O = "00000000") report "NG." severity ERROR; DATA_I <= "00000001"; wait for 10 ns; assert(DATA_O /= "00000001") report "OK." severity NOTE; assert(DATA_O = "00000001") report "NG." severity ERROR; assert FALSE report "Simulation complete." severity FAILURE; end process; end MODEL;

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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity filter_with_file_write is port( data_ext: in std_logic_vector( 7 downto 0); clock, start, rst: in std_logic; mem_b_out: out std_logic_vector( 7 downto 0); done: out std_logic); end filter_with_file_write; architecture behavior of filter_with_file_write is component datapath port( x: in std_logic_vector(7 downto 0); y: out std_logic_vector(7 downto 0); clock: in std_logic; rst_shift, enable_shift: in std_logic; rst_sum, enable_sum: in std_logic; rst_count, enable_count: in std_logic; count_out: out std_logic_vector(9 downto 0); module, cntrl: in std_logic; mux1_sel: in std_logic_vector(2 downto 0); terminal_count: out std_logic); end component; component control_unit port ( module: out std_logic; cntrl: out std_logic; enable_sum: out std_logic; enable_shift: out std_logic; clock: in std_logic; rst_shift: out std_logic; cs_a,cs_b,wr_rd_a,wr_rd_b: out std_logic; finished: out std_logic; rst_count: out std_logic; up_count: out std_logic; start: in std_logic; rst_sum: out std_logic; mux1_sel: out std_logic_vector(2 downto 0); reset: in std_logic; exceed: in std_logic); end component; component ram_1024X8 port( data_in: in std_logic_vector(7 downto 0); address: in integer range 1023 downto 0; cs: in std_logic; clk: in std_logic; wr_rd_n: in std_logic; data_out: out std_logic_vector (7 downto 0)); end component; signal mem_a_out, mem_b_in: std_logic_vector (7 downto 0); signal rst_shift, enable_shift: std_logic; signal rst_sum, enable_sum: std_logic; signal rst_count, enable_count: std_logic; signal count_out: std_logic_vector(9 downto 0); signal module, cntrl: std_logic; signal mux1_sel: std_logic_vector(2 downto 0); signal cs_a,cs_b,wr_rd_a,wr_rd_b: std_logic; signal exceed:std_logic; signal add: integer:=0; begin datapath: datapath port map(mem_a_out, mem_b_in, clock, rst_shift, enable_shift, rst_sum, enable_sum, rst_count,enable_count, count_out, module, cntrl, mux1_sel, exceed); cu: control_unit port map(module,cntrl,enable_sum, enable_shift, clock, rst_shift, cs_a, cs_b, wr_rd_a, wr_rd_b, done,rst_count,enable_count, start, rst_sum, mux1_sel, rst, exceed); add<= to_integer(unsigned(count_out)); ram_a: ram_1024x8 port map(data_ext,add, cs_a, clock, wr_rd_a, mem_a_out); ram_b: ram_1024x8 port map(mem_b_in,add, cs_b, clock, wr_rd_b, mem_b_out); process (clock) file ofile: TEXT is out "data_in_b"; variable buf:line; variable datab: integer; begin if(clock'event and clock='1') then if (cs_b = '1' and wr_rd_b = '0') then datab := to_integer(signed(mem_b_in)); write(buf,datab); writeline(ofile,buf); end if; end if; end process; end architecture;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity feedforward_p_uOut_ram is generic( mem_type : string := "block"; dwidth : integer := 64; awidth : integer := 8; mem_size : integer := 140 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of feedforward_p_uOut_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; --synthesis translate_off if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; --synthesis translate_on end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then q1 <= ram(CONV_INTEGER(addr1_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity feedforward_p_uOut is generic ( DataWidth : INTEGER := 64; AddressRange : INTEGER := 140; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of feedforward_p_uOut is component feedforward_p_uOut_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR); end component; begin feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1); end architecture;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:51:59 05/12/2014 -- Design Name: -- Module Name: encoder_interface - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity encoder_interface is generic(FREQ_DIV : positive := 100; SINGLE_CHANNEL : boolean := true); port( clk, reset : in std_logic ; channel_a, channel_b : in std_logic; period : out std_logic_vector(15 downto 0); pv : out std_logic ; count : out std_logic_vector(15 downto 0); reset_count : in std_logic ); end encoder_interface; architecture Behavioral of encoder_interface is constant DEBOUNCER_DIV : positive := 10 ; type enc_states is (IDLE, A_H, B_H, A_L, B_L); signal cur_state, next_state : enc_states ; signal period_counter, period_latched, pulse_counter : std_logic_vector(15 downto 0); signal divider_counter : std_logic_vector(15 downto 0); signal end_div : std_logic ; signal inc_counter, dec_counter, valid_cw, valid_ccw, latch_period : std_logic ; signal channel_a_deb, channel_b_deb : std_logic ; signal debouncer_counter : std_logic_vector(15 downto 0); begin -- simple debouncer process(clk, reset) begin if reset = '1' then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ; else debouncer_counter <= debouncer_counter - 1 ; end if ; end if ; end process; gen_sing : if SINGLE_CHANNEL = true generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_a_deb; end if ; end if ; end process ; end generate ; gen_no_sing : if SINGLE_CHANNEL = false generate process(clk, reset) begin if reset = '1' then channel_b_deb <= '0' ; channel_a_deb <= '0' ; elsif clk'event and clk = '1' then if debouncer_counter = 0 then channel_a_deb <= channel_a ; channel_b_deb <= channel_b; end if ; end if ; end process ; end generate ; -- end of debouncer process(clk, reset) begin if reset = '1' then cur_state <= IDLE ; elsif clk'event and clk='1' then cur_state <= next_state ; end if ; end process ; process(cur_state, channel_a_deb, channel_b_deb) begin next_state <= cur_state ; case cur_state is when IDLE => if channel_a_deb = '1' and channel_b_deb='0' then next_state <= A_H ; end if ; if channel_b_deb = '1' and channel_a_deb='0' then next_state <= A_L ; end if ; when A_H => if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; when B_H => if channel_a_deb = '0' and channel_b_deb = '1' then next_state <= A_L ; end if ; if channel_b_deb = '0' and channel_a_deb = '1' then next_state <= A_H ; end if ; when A_L => if channel_a_deb = '0' and channel_b_deb = '0' then next_state <= IDLE ; end if ; if channel_a_deb = '1' and channel_b_deb = '1' then next_state <= B_H ; end if ; when others => next_state <= IDLE ; end case ; end process ; inc_counter <= '1' when cur_state = IDLE and next_state = A_H else '0' ; dec_counter <= '1' when cur_state = A_H and next_state = IDLE else '0' ; latch_period <= '1' when cur_state = IDLE and channel_a_deb = '1' else '1' when cur_state = IDLE and channel_b_deb = '1' else '0' ; process(clk, reset) begin if reset = '1' then valid_cw <= '0' ; valid_ccw <= '0' ; elsif clk'event and clk='1' then if cur_state = IDLE and channel_a_deb='1' then valid_cw <= '1' ; elsif cur_state = A_H and channel_a_deb='0' then valid_cw <= '0' ; elsif cur_state = B_H and channel_b_deb='0' then valid_cw <= '0' ; elsif cur_state = A_L and channel_a_deb='1' then valid_cw <= '0' ; elsif cur_state = IDLE and channel_b_deb='1' then valid_cw <= '0' ; end if ; if cur_state = IDLE and channel_b_deb='1' then valid_ccw <= '1' ; elsif cur_state = A_L and channel_b_deb='0' then valid_ccw <= '0' ; elsif cur_state = B_H and channel_a_deb='0' then valid_ccw <= '0' ; elsif cur_state = A_H and channel_b_deb='1' then valid_ccw <= '0' ; elsif cur_state = IDLE and channel_a_deb='1' then valid_ccw <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then divider_counter <= (others => '0') ; elsif clk'event and clk='1' then if end_div = '1' then divider_counter <= std_logic_vector(to_unsigned(FREQ_DIV-1, 16)) ; else divider_counter <= divider_counter - 1 ; end if ; end if ; end process ; end_div <= '1' when divider_counter = 0 else '0' ; process(clk, reset) begin if reset = '1' then period_counter <= (others => '0') ; elsif clk'event and clk='1' then if latch_period = '1' then period_counter <= (others => '0') ; elsif end_div = '1' and period_counter /= X"7FFF" and period_counter /= X"8000" then period_counter <= period_counter + 1 ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then period_latched <= (others => '0') ; pv <= '0' ; elsif clk'event and clk='1' then if latch_period = '1' and ((valid_ccw = '1' and channel_b_deb='1') or (valid_cw = '1' and channel_a_deb='1') ) then if valid_ccw = '0' and valid_cw = '1' then period_latched <= period_counter ; else period_latched <= (NOT period_counter) + 1 ; end if; pv <= '1' ; elsif period_counter = X"7FFF" or period_counter = X"8000" then period_latched <= X"8000" ; pv <= '1' ; else pv <= '0' ; end if ; end if ; end process ; process(clk, reset) begin if reset = '1' then pulse_counter <= (others => '0') ; elsif clk'event and clk='1' then if reset_count = '1' then pulse_counter <= (others => '0') ; elsif inc_counter = '1' then pulse_counter <= pulse_counter + 1 ; elsif dec_counter = '1' then pulse_counter <= pulse_counter - 1 ; end if ; end if ; end process ; period <= period_latched ; count <= pulse_counter ; end Behavioral;

------------------------------------------------------------------------------- -- $Id:$ ------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and FIFO Generator when XST elaborated the client core -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd -- | -- |--- XilinxCoreLib.fifo_generator_v9_2 -- |--- XilinxCoreLib.fifo_generator_v9_3 -- | -- |--- XilinxCoreLib.blk_mem_gen_v7_1 -- |--- XilinxCoreLib.blk_mem_gen_v7_3 -- ------------------------------------------------------------------------------- -- Author: DET -- History: -- DET 02/01/2008 Initial Version -- -- DET 2/01/2008 for proc_common_v4_0 -- ~~~~~~ -- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create -- this file. -- - Changed instance of sync fifo to use new wrapper file that will adapt -- to FIFO Generator primitive. -- - Replaced "edk_generatecore" with "generatecore" utility call -- - Removed the CAM component -- ^^^^^^ -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 4.3 -- - Added Block Memory Generator Component Version 2.7 -- ^^^^^^ -- -- MSH 2/26/2009 for EDK 11.1 -- ~~~~~~ -- - Added component for Fifo Generator version 5.1 -- - Added Block Memory Generator Component Version 3.1 -- ^^^^^^ -- -- DET 3/2/2009 for EDK 11.1 -- ~~~~~~ -- - Added new Parameters and ports for Fifo Generatore 5.1. -- ^^^^^^ -- -- DET 3/30/2009 EDK 11.2 -- ~~~~~~ -- - Had to reorder parameter list of FIFO Generator 4.3 component to match -- the corresponding Verilog model due to NCSIM positional order -- dependancy of parameters in vhdl/verilog use case. -- ^^^^^^ -- -- DET 4/8/2009 EDK 11.2 -- ~~~~~~ -- - Added blk_mem_gen_v3_2 -- ^^^^^^ -- -- DET 4/9/2009 EDK 11.2 -- ~~~~~~ -- - Added fifo_generator_v5_2 -- ^^^^^^ -- -- DET 2/9/2010 For EDK 12.1 -- ~~~~~~ -- - Added fifo_generator_v5_3 -- - Added blk_mem_gen_v3_3 -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Added fifo_generator_v6_1 -- - Added blk_mem_gen_v4_1 -- ^^^^^^ -- -- DET 3/17/2010 Initial -- ~~~~~~ -- -- Per CR554253 -- - Incorporated changes to comment out FLOP_DELAY parameter from the -- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib -- model for blk_mem_gen_v4_1 but is declared as a TIME type for the -- vhdl version and an integer for the verilog. -- ^^^^^^ -- -- DET 10/04/2010 EDK 13.1 -- ~~~~~~ -- - Added fifo_generator_v7_3 -- - Added blk_mem_gen_v5_2 -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Replaced fifo_generator v7.3 with v8.1 -- - Added blk_mem_gen_v6_1 -- ^^^^^^ -- -- DET 12/17/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR587494 -- - Removed blk_mem_gen v6_1 -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- - Update to use blk_mem_gen_v6_2 -- - Remove out of date components. -- ^^^^^^ -- -- DET 3/3/2011 EDK 13.2 -- ~~~~~~ -- - Removed C_ELABORATION_DIR parameter from the component decalarion -- ^^^^^^ -- -- DET 3/7/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR596052 -- - Added removed fifo generator and Blk Mem Gen components back into -- coregen_comp_defs. -- ^^^^^^ -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v11_0; use fifo_generator_v11_0.all; library blk_mem_gen_v8_0; use blk_mem_gen_v8_0.all; PACKAGE coregen_comp_defs IS -------------------------------------------------------- -- Declare general attributes used in this file -- for defining each component being used with -- the generatecore utility attribute box_type: string; attribute GENERATOR_DEFAULT: string; ------------------------------------------------------- ------------------------------------------------------------------------------------- -- Start FIFO Generator Component for fifo_generator_v11_0 -- The Component declaration for fifo_generator_v11_0 pulled from the -- Coregen version of -- file: fifo_generator_v11_0_comp.vhd. -- -- This component is used for both dual clock (async) and synchronous fifos -- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not -- be provided in FIFO Generator V10.0 so not supported here. -- -- Note: AXI ports and parameters added for this version of FIFO Generator. -- ------------------------------------------------------------------------------------- COMPONENT fifo_generator_v11_0 GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; C_FAMILY : string := "virtex6"; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; C_HAS_MEMINIT_FILE : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; C_OPTIMIZATION_MODE : integer := 0; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; C_MSGON_VAL : integer := 1; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_SYNCHRONIZER_STAGE : integer := 2; -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3 C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3 C_HAS_AXI_WR_CHANNEL : integer := 0; C_HAS_AXI_RD_CHANNEL : integer := 0; C_HAS_SLAVE_CE : integer := 0; C_HAS_MASTER_CE : integer := 0; C_ADD_NGC_CONSTRAINT : integer := 0; C_USE_COMMON_OVERFLOW : integer := 0; C_USE_COMMON_UNDERFLOW : integer := 0; C_USE_DEFAULT_SETTINGS : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH : integer := 4; C_AXI_ADDR_WIDTH : integer := 32; C_AXI_DATA_WIDTH : integer := 64; C_AXI_LEN_WIDTH : integer := 8; C_AXI_LOCK_WIDTH : integer := 2; C_HAS_AXI_ID : integer := 0; C_HAS_AXI_AWUSER : integer := 0; C_HAS_AXI_WUSER : integer := 0; C_HAS_AXI_BUSER : integer := 0; C_HAS_AXI_ARUSER : integer := 0; C_HAS_AXI_RUSER : integer := 0; C_AXI_ARUSER_WIDTH : integer := 1; C_AXI_AWUSER_WIDTH : integer := 1; C_AXI_WUSER_WIDTH : integer := 1; C_AXI_BUSER_WIDTH : integer := 1; C_AXI_RUSER_WIDTH : integer := 1; -- AXI Streaming C_HAS_AXIS_TDATA : integer := 0; C_HAS_AXIS_TID : integer := 0; C_HAS_AXIS_TDEST : integer := 0; C_HAS_AXIS_TUSER : integer := 0; C_HAS_AXIS_TREADY : integer := 1; C_HAS_AXIS_TLAST : integer := 0; C_HAS_AXIS_TSTRB : integer := 0; C_HAS_AXIS_TKEEP : integer := 0; C_AXIS_TDATA_WIDTH : integer := 64; C_AXIS_TID_WIDTH : integer := 8; C_AXIS_TDEST_WIDTH : integer := 4; C_AXIS_TUSER_WIDTH : integer := 4; C_AXIS_TSTRB_WIDTH : integer := 4; C_AXIS_TKEEP_WIDTH : integer := 4; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 5 = Common Clock Built-in FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH : integer := 1; C_IMPLEMENTATION_TYPE_WDCH : integer := 1; C_IMPLEMENTATION_TYPE_WRCH : integer := 1; C_IMPLEMENTATION_TYPE_RACH : integer := 1; C_IMPLEMENTATION_TYPE_RDCH : integer := 1; C_IMPLEMENTATION_TYPE_AXIS : integer := 1; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Sync FIFO -- 3 = Low Latency Async FIFO C_APPLICATION_TYPE_WACH : integer := 0; C_APPLICATION_TYPE_WDCH : integer := 0; C_APPLICATION_TYPE_WRCH : integer := 0; C_APPLICATION_TYPE_RACH : integer := 0; C_APPLICATION_TYPE_RDCH : integer := 0; C_APPLICATION_TYPE_AXIS : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH : integer := 0; C_USE_ECC_WDCH : integer := 0; C_USE_ECC_WRCH : integer := 0; C_USE_ECC_RACH : integer := 0; C_USE_ECC_RDCH : integer := 0; C_USE_ECC_AXIS : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH : integer := 0; C_ERROR_INJECTION_TYPE_WDCH : integer := 0; C_ERROR_INJECTION_TYPE_WRCH : integer := 0; C_ERROR_INJECTION_TYPE_RACH : integer := 0; C_ERROR_INJECTION_TYPE_RDCH : integer := 0; C_ERROR_INJECTION_TYPE_AXIS : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH : integer := 32; C_DIN_WIDTH_WDCH : integer := 64; C_DIN_WIDTH_WRCH : integer := 2; C_DIN_WIDTH_RACH : integer := 32; C_DIN_WIDTH_RDCH : integer := 64; C_DIN_WIDTH_AXIS : integer := 1; C_WR_DEPTH_WACH : integer := 16; C_WR_DEPTH_WDCH : integer := 1024; C_WR_DEPTH_WRCH : integer := 16; C_WR_DEPTH_RACH : integer := 16; C_WR_DEPTH_RDCH : integer := 1024; C_WR_DEPTH_AXIS : integer := 1024; C_WR_PNTR_WIDTH_WACH : integer := 4; C_WR_PNTR_WIDTH_WDCH : integer := 10; C_WR_PNTR_WIDTH_WRCH : integer := 4; C_WR_PNTR_WIDTH_RACH : integer := 4; C_WR_PNTR_WIDTH_RDCH : integer := 10; C_WR_PNTR_WIDTH_AXIS : integer := 10; C_HAS_DATA_COUNTS_WACH : integer := 0; C_HAS_DATA_COUNTS_WDCH : integer := 0; C_HAS_DATA_COUNTS_WRCH : integer := 0; C_HAS_DATA_COUNTS_RACH : integer := 0; C_HAS_DATA_COUNTS_RDCH : integer := 0; C_HAS_DATA_COUNTS_AXIS : integer := 0; C_HAS_PROG_FLAGS_WACH : integer := 0; C_HAS_PROG_FLAGS_WDCH : integer := 0; C_HAS_PROG_FLAGS_WRCH : integer := 0; C_HAS_PROG_FLAGS_RACH : integer := 0; C_HAS_PROG_FLAGS_RDCH : integer := 0; C_HAS_PROG_FLAGS_AXIS : integer := 0; -- 0: No Programmable FULL -- 1: Single Programmable FULL Threshold Constant -- 3: Single Programmable FULL Threshold Input Port C_PROG_FULL_TYPE_WACH : integer := 5; C_PROG_FULL_TYPE_WDCH : integer := 5; C_PROG_FULL_TYPE_WRCH : integer := 5; C_PROG_FULL_TYPE_RACH : integer := 5; C_PROG_FULL_TYPE_RDCH : integer := 5; C_PROG_FULL_TYPE_AXIS : integer := 5; -- Single Programmable FULL Threshold Constant Assert Value C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023; -- 0: No Programmable EMPTY -- 1: Single Programmable EMPTY Threshold Constant -- 3: Single Programmable EMPTY Threshold Input Port C_PROG_EMPTY_TYPE_WACH : integer := 5; C_PROG_EMPTY_TYPE_WDCH : integer := 5; C_PROG_EMPTY_TYPE_WRCH : integer := 5; C_PROG_EMPTY_TYPE_RACH : integer := 5; C_PROG_EMPTY_TYPE_RDCH : integer := 5; C_PROG_EMPTY_TYPE_AXIS : integer := 5; -- Single Programmable EMPTY Threshold Constant Assert Value C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022; C_REG_SLICE_MODE_WACH : integer := 0; C_REG_SLICE_MODE_WDCH : integer := 0; C_REG_SLICE_MODE_WRCH : integer := 0; C_REG_SLICE_MODE_RACH : integer := 0; C_REG_SLICE_MODE_RDCH : integer := 0; C_REG_SLICE_MODE_AXIS : integer := 0 ); PORT( ------------------------------------------------------------------------------ -- Input and Output Declarations ------------------------------------------------------------------------------ -- Conventional FIFO Interface Signals backup : in std_logic := '0'; backup_marker : in std_logic := '0'; clk : in std_logic := '0'; rst : in std_logic := '0'; srst : in std_logic := '0'; wr_clk : in std_logic := '0'; wr_rst : in std_logic := '0'; rd_clk : in std_logic := '0'; rd_rst : in std_logic := '0'; din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; rd_en : in std_logic := '0'; -- optional inputs prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0'); int_clk : in std_logic := '0'; injectdbiterr : in std_logic := '0'; injectsbiterr : in std_logic := '0'; dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0'); full : out std_logic := '0'; almost_full : out std_logic := '0'; wr_ack : out std_logic := '0'; overflow : out std_logic := '0'; empty : out std_logic := '1'; almost_empty : out std_logic := '1'; valid : out std_logic := '0'; underflow : out std_logic := '0'; data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0'); prog_full : out std_logic := '0'; prog_empty : out std_logic := '1'; sbiterr : out std_logic := '0'; dbiterr : out std_logic := '0'; -- axi global signal m_aclk : in std_logic := '0'; s_aclk : in std_logic := '0'; s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1 m_aclk_en : in std_logic := '0'; s_aclk_en : in std_logic := '0'; -- axi full/lite slave write channel (write side) s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_awvalid : in std_logic := '0'; s_axi_awready : out std_logic := '0'; s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); s_axi_wlast : in std_logic := '0'; s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_wvalid : in std_logic := '0'; s_axi_wready : out std_logic := '0'; s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_bvalid : out std_logic := '0'; s_axi_bready : in std_logic := '0'; -- axi full/lite master write channel (read side) m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_awvalid : out std_logic := '0'; m_axi_awready : in std_logic := '0'; m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); m_axi_wlast : out std_logic := '0'; m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_wvalid : out std_logic := '0'; m_axi_wready : in std_logic := '0'; m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_bvalid : in std_logic := '0'; m_axi_bready : out std_logic := '0'; -- axi full/lite slave read channel (write side) s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0'); s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0'); s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_arvalid : in std_logic := '0'; s_axi_arready : out std_logic := '0'; s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0'); s_axi_rlast : out std_logic := '0'; s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); s_axi_rvalid : out std_logic := '0'; s_axi_rready : in std_logic := '0'; -- axi full/lite master read channel (read side) m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0'); m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0'); m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0'); m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0'); m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_arvalid : out std_logic := '0'; m_axi_arready : in std_logic := '0'; m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0'); m_axi_rlast : in std_logic := '0'; m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0'); m_axi_rvalid : in std_logic := '0'; m_axi_rready : out std_logic := '0'; -- axi streaming slave signals (write side) s_axis_tvalid : in std_logic := '0'; s_axis_tready : out std_logic := '0'; s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); s_axis_tlast : in std_logic := '0'; s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi streaming master signals (read side) m_axis_tvalid : out std_logic := '0'; m_axis_tready : in std_logic := '0'; m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0'); m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0'); m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0'); m_axis_tlast : out std_logic := '0'; m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0'); m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0'); m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0'); -- axi full/lite write address channel signals axi_aw_injectsbiterr : in std_logic := '0'; axi_aw_injectdbiterr : in std_logic := '0'; axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0'); axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0'); axi_aw_sbiterr : out std_logic := '0'; axi_aw_dbiterr : out std_logic := '0'; axi_aw_overflow : out std_logic := '0'; axi_aw_underflow : out std_logic := '0'; axi_aw_prog_full : out std_logic := '0'; axi_aw_prog_empty : out std_logic := '1'; -- axi_aw_almost_full : out std_logic := '0'; -- axi_aw_almost_empty : out std_logic := '1'; -- axi full/lite write data channel signals axi_w_injectsbiterr : in std_logic := '0'; axi_w_injectdbiterr : in std_logic := '0'; axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0'); axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0'); axi_w_sbiterr : out std_logic := '0'; axi_w_dbiterr : out std_logic := '0'; axi_w_overflow : out std_logic := '0'; axi_w_underflow : out std_logic := '0'; axi_w_prog_full : out std_logic := '0'; axi_w_prog_empty : out std_logic := '1'; -- axi_w_almost_full : out std_logic := '0'; -- axi_w_almost_empty : out std_logic := '1'; -- axi full/lite write response channel signals axi_b_injectsbiterr : in std_logic := '0'; axi_b_injectdbiterr : in std_logic := '0'; axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0'); axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0'); axi_b_sbiterr : out std_logic := '0'; axi_b_dbiterr : out std_logic := '0'; axi_b_overflow : out std_logic := '0'; axi_b_underflow : out std_logic := '0'; axi_b_prog_full : out std_logic := '0'; axi_b_prog_empty : out std_logic := '1'; -- axi_b_almost_full : out std_logic := '0'; -- axi_b_almost_empty : out std_logic := '1'; -- axi full/lite read address channel signals axi_ar_injectsbiterr : in std_logic := '0'; axi_ar_injectdbiterr : in std_logic := '0'; axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0'); axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0'); axi_ar_sbiterr : out std_logic := '0'; axi_ar_dbiterr : out std_logic := '0'; axi_ar_overflow : out std_logic := '0'; axi_ar_underflow : out std_logic := '0'; axi_ar_prog_full : out std_logic := '0'; axi_ar_prog_empty : out std_logic := '1'; -- axi_ar_almost_full : out std_logic := '0'; -- axi_ar_almost_empty : out std_logic := '1'; -- axi full/lite read data channel signals axi_r_injectsbiterr : in std_logic := '0'; axi_r_injectdbiterr : in std_logic := '0'; axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0'); axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0'); axi_r_sbiterr : out std_logic := '0'; axi_r_dbiterr : out std_logic := '0'; axi_r_overflow : out std_logic := '0'; axi_r_underflow : out std_logic := '0'; axi_r_prog_full : out std_logic := '0'; axi_r_prog_empty : out std_logic := '1'; -- axi_r_almost_full : out std_logic := '0'; -- axi_r_almost_empty : out std_logic := '1'; -- axi streaming fifo related signals axis_injectsbiterr : in std_logic := '0'; axis_injectdbiterr : in std_logic := '0'; axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0'); axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0'); axis_sbiterr : out std_logic := '0'; axis_dbiterr : out std_logic := '0'; axis_overflow : out std_logic := '0'; axis_underflow : out std_logic := '0'; axis_prog_full : out std_logic := '0'; axis_prog_empty : out std_logic := '1' -- axis_almost_full : out std_logic := '0'; -- axis_almost_empty : out std_logic := '1' ); END COMPONENT; -- End FIFO Generator Component --------------------------------------- ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_0 -- Component declaration for blk_mem_gen_v8_0 pulled from the -- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib -- file: blk_mem_gen_v8_0.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_0 IS GENERIC ( C_FAMILY : STRING := "virtex6"; C_XDEVICEFAMILY : STRING := "virtex6"; C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_AXI_TYPE : INTEGER := 0; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC := '0'; DBITERR : OUT STD_LOGIC := '0'; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC := '0'; S_AXI_DBITERR : OUT STD_LOGIC := '0'; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; --blk_mem_gen_v8_0 -- The following tells XST that blk_mem_gen_v8_0 is a black box which -- should be generated command given by the value of this attribute -- Note the fully qualified SIM (JAVA class) name that forms the -- basis of the core -- ATTRIBUTE box_type OF blk_mem_gen_v8_0 : COMPONENT IS "black_box"; -- ATTRIBUTE generator_default OF blk_mem_gen_v8_0 : COMPONENT IS -- "generatecore com.xilinx.ip.blk_mem_gen_v8_0.blk_mem_gen_v8_0 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e "; -- End Block Memory Generator Component for v7_1 ------------------------------- END coregen_comp_defs;

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_2 Core - Top File for the Example Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Filename: ram_16x1k_dp_tb.vhd -- Description: -- Testbench Top -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY ram_16x1k_dp_tb IS END ENTITY; ARCHITECTURE ram_16x1k_dp_tb_ARCH OF ram_16x1k_dp_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL CLKB : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; CLKB_GEN: PROCESS BEGIN CLKB <= NOT CLKB; WAIT FOR 100 NS; CLKB <= NOT CLKB; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; --STOP_SIM: PROCESS BEGIN -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS -- ASSERT FALSE -- REPORT "END SIMULATION TIME REACHED" -- SEVERITY FAILURE; --END PROCESS; -- PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; ram_16x1k_dp_synth_inst:ENTITY work.ram_16x1k_dp_synth PORT MAP( CLK_IN => CLK, CLKB_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE;

library IEEE, LFSR; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -------------------------------------------------------------------------------- entity pulse_shreg is generic ( G_period : natural := 10000 ); port( CLK : in std_logic; RESET : in std_logic; PULSE : out std_logic ); end pulse_shreg; -------------------------------------------------------------------------------- architecture rtl of pulse_shreg is subtype T_SHIFTREG is std_logic_vector(G_period-1 downto 0); constant C_ZERO : T_SHIFTREG := (0 => '1', others => '0'); signal SHIFTREG : T_SHIFTREG; begin PULSE <= '1' when SHIFTREG = C_ZERO else '0'; shreg_proc: process (CLK) is begin if rising_edge(CLK) then if RESET = '1' then SHIFTREG <= C_ZERO; else SHIFTREG <= SHIFTREG(G_period-2 downto 0) & SHIFTREG(G_period-1); end if; end if; end process shreg_proc; end rtl;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity guarded_fifo is generic ( depth : integer; bit_width : integer ); port ( -- fast side interface clk_fast_i : in std_logic; rst_fast_i : in std_logic; push_i : in std_logic; full_o : out std_logic; d_i : in std_logic_vector ( bit_width-1 downto 0 ); -- slow side interface clk_i : in std_logic; rst_i : in std_logic; dack_i : in std_logic; drdy_o : out std_logic; q_o : out std_logic_vector ( bit_width-1 downto 0 ) ); end entity; -- Take a non-guarded fifo and take control over the -- push and pull lines and prevent illegal operations. -- Forward the full and empty signals. use work.fifo_pkg.all; architecture rtl of guarded_fifo is -- fast side signal type fast_state_t is (s_idle, s_getting_data_pop, s_getting_data_nopop, s_getting_data_latch, s_providing_data, s_start_pop, s_unknown); signal full, empty, push, pop : std_logic; signal pop_request_sync, pop_request_sync_1 : std_logic; signal q, fifo_out_data_fast : std_logic_vector ( bit_width-1 downto 0 ); signal data_ready : std_logic; signal state, next_state : fast_state_t; -- slow side signals type slow_state_t is (s_block, s_noblock); signal data_ready_sync, data_ready_sync_1 : std_logic; signal data_ready_block : std_logic; signal fifo_out_data_slow : std_logic_vector ( bit_width-1 downto 0 ); signal slow_state : slow_state_t; begin -- the fifo is located on the fast side fifo : work.fifo_pkg.fifo generic map ( depth => depth, bit_width => bit_width ) port map ( clk_i => clk_fast_i, rst_i => rst_fast_i, push_i => push, pop_i => pop, full_o => full, empty_o => empty, d_i => d_i, q_o => q ); -- fast side interface of this module can be forwarded directly to the fifo full_o <= full; push <= push_i and not full; -- the fast side process has a state machine that manages popping data from the fifo if it is available -- fast_side: process begin wait until rising_edge(clk_fast_i); if rst_fast_i = '1' then state <= s_idle; next_state <= s_idle; fifo_out_data_fast <= (others => 'U'); data_ready <= '0'; else -- signal synchroinzation on the fast side (look at slow signals) pop_request_sync_1 <= dack_i; -- data acknowledge => we make a pop request to the underlying fifo pop_request_sync <= pop_request_sync_1; fifo_out_data_fast <= fifo_out_data_fast; -- managing state machine case state is when s_idle => if empty = '0' and pop_request_sync = '0' then state <= s_getting_data_pop; else state <= s_idle; end if; -- create a single pulse to get next data when s_getting_data_pop => if empty = '1' then state <= s_idle; else pop <= '1'; state <= s_getting_data_nopop; end if; when s_getting_data_nopop => pop <= '0'; data_ready <= '1'; state <= s_getting_data_latch; when s_getting_data_latch => state <= s_providing_data; fifo_out_data_fast <= q; data_ready <= '1'; when s_providing_data => if pop_request_sync = '1' then state <= s_start_pop; data_ready <= '0'; end if; when s_start_pop => if pop_request_sync = '0' then state <= s_idle; end if; when others => state <= s_unknown; end case; end if; end process; slow_side: process begin wait until rising_edge(clk_i); if rst_i = '1' then drdy_o <= '0'; data_ready_sync_1 <= '0'; data_ready_sync <= '0'; q_o <= (others => 'U'); data_ready_block <= '0'; slow_state <= s_noblock; else -- signal synchronization on the slow side (looking at fast signals) data_ready_sync_1 <= data_ready; data_ready_sync <= data_ready_sync_1; drdy_o <= data_ready_sync and not data_ready_block; if data_ready_sync = '1' then q_o <= fifo_out_data_fast; end if; case slow_state is when s_noblock => if dack_i = '1' then slow_state <= s_block; data_ready_block <= '1'; end if; when s_block => if data_ready_sync = '1' and data_ready_sync_1 = '0' then slow_state <= s_noblock; data_ready_block <= '0'; end if; end case; end if; end process; end architecture;

architecture rtl of fifo is begin my_signal <= '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal <= '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal <= (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end architecture rtl;

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity spi_sreg is generic ( size_g : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; --control signals shift : in std_logic; --shift left load : in std_logic; --load parallel --data signals din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched) dout : out std_logic_vector(size_g-1 downto 0); --parallel data out sin : in std_logic; --serial data in (to lsb) sout : out std_logic --serial data out (from msb) ); end spi_sreg; architecture rtl of spi_sreg is signal shiftReg : std_logic_vector(size_g-1 downto 0); begin theShiftRegister : process(clk, rst) begin if rst = '1' then shiftReg <= (others => '0'); elsif clk = '1' and clk'event then if shift = '1' then shiftReg <= shiftReg(size_g-2 downto 0) & sin; elsif load = '1' then shiftReg <= din; end if; end if; end process; dout <= shiftReg; sout <= shiftReg(size_g-1); end rtl;