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-- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_c7 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.1; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:10:21 11/10/2013
-- Design Name:
-- Module Name: vga - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
--pantalla debe ser top
entity project is
port
( resetN: in std_logic; -- reset
clk: in std_logic;
ps2data: inout std_logic;
ps2clk: inout std_logic;
hsyncb: inout std_logic; -- horizontal (line) sync
vsyncb: out std_logic; -- vertical (frame) sync
rgb: out std_logic_vector(8 downto 0); -- red,green,blue colors
fin_principal: out std_logic;
escalay: out std_logic_vector(4 downto 0); --Conectada a barra de leds
escalax: out std_logic_vector(7 downto 0)); -- Conectada a los 7 segmentos
end project;
architecture project_arch of project is
component puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end component puntos_muestra;
component calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end component calculo;
component conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk:in std_logic;
punto1X, punto1Y, punto2X, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end component conversor;
component divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end component;
component rams_2p is
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(6 downto 0);
addr2 : in std_logic_vector(6 downto 0);
di : in std_logic_vector(0 to 127);
do1 : out std_logic_vector(0 to 127);
do2 : out std_logic_vector(0 to 127)
);
end component;
component reconocedor is
port(ps2data: inout std_logic;
ps2clk: inout std_logic;
reset: in std_logic;
clk: in std_logic;
fin : out std_logic;
fin_coef: out std_logic_vector(15 downto 0);
salida: out std_logic_vector(49 downto 0));
end component reconocedor;
component expresion is
port(
clk: in std_logic;
salida_teclado: in std_logic_vector(49 downto 0);
addr : in std_logic_vector(7 downto 0);
do : out std_logic_vector(0 to 10)
);
end component;
component numero is
port(
clk: in std_logic;
s: in std_logic_vector(20 downto 0);
addr : in std_logic_vector(5 downto 0);
do : out std_logic_vector(0 to 9)
);
end component;
type ESTADOS is (S1, S2, S3); --ESTADOS DE LA PANTALLA
signal ESTADO, SIG_ESTADO: ESTADOS;
type ESTADOSG is (inicial, leer, calc, a_memoria, integrar1, integrar2); --ESTADOS DEL CONTROLADOR PRINCIPAL
signal estadoGen, estadoGen_sig: ESTADOSG;
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal (contando el signo, pues representamos en C2)
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB : integer := 6; --nBits-1
constant nF : integer := 127; --nF-1
constant nC : integer := 255; --nC-1
constant hInf : integer := 63;
constant hSup : integer := hInf + nF + 2;
constant vInf : integer := 63;
constant vSup : integer := vInf + nC + 2;
constant numPuntos : integer := 2;
signal clock, reset: std_logic;
--Señales de la pantalla
signal hcnt, fila, filaExp: std_logic_vector(9 downto 0); -- horizontal pixel counter
signal vcnt, auxColumna: std_logic_vector(8 downto 0); -- vertical line counter
signal columna: std_logic_vector(6 downto 0);
signal data: std_logic_vector(0 to nF);
signal data_particular,data_particularExp, data_particularNum, we: std_logic;
signal addr1, addr2, puntos1X, puntos1Y, puntos2X, puntos2Y: std_logic_vector(6 downto 0);
signal di, do1, do2, vAux, v: std_logic_vector(0 to 127);
signal b, j, jAux, a, i, iAux: std_logic_vector(nB downto 0);
signal aj, bi, biAux, ajAux: std_logic_vector(11 downto 0);
signal pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_expY, pinta_expB, pinta_num:std_logic;
signal addrExp: std_logic_vector(7 downto 0);
signal addrNum: std_logic_vector(5 downto 0);
signal doExp: std_logic_vector(0 to 10);
signal doNum: std_logic_vector(0 to 9);
signal dataExp, dataNum: std_logic_vector(0 to 15);
signal columnaExp, columnaNum: std_logic_vector(3 downto 0);
signal fin_coef: std_logic_vector(15 downto 0);
signal noPintes, noPintesAux: std_logic;
--señales del controlador principal
signal caso: std_logic_vector(1 downto 0);
signal salida_teclado: std_logic_vector(49 downto 0);
signal integral, solo_positivos, solo_positivosAux, fin_muestra, fin_teclado, ready_calculo, enable_muestra, retro_muestra, fin_puntos, enable_calculo, fin_pantalla,enable_pantalla, avanza_conv, inf, inf1, inf2, puntos_centrales, x1, x2, x3, x4, x5, xl: std_logic;
signal punto, s, limite1, limite1Aux, limite2, limite2Aux, valorIntegral, valorIntegralAux: std_logic_vector(DEC+ENT-1 downto 0);
signal numPuntos2 : std_logic_vector(6 downto 0);
signal count: std_logic_vector(3 downto 0);
signal indice: std_logic_vector(4 downto 0);
begin
calcExp: expresion port map (clock, salida_teclado, addrExp, doExp);
calInt: numero port map (clock, valorIntegral, addrNum,doNum);
muestra: puntos_muestra port map(caso, numPuntos2, enable_muestra, retro_muestra, clock, reset, fin_muestra, salida_teclado,punto, count);
calculador: calculo port map(reset, clock, enable_calculo,integral, punto, salida_teclado, s, ready_calculo);
--Por comodidad las componentes de los puntos están intercambiadas
conver: conversor port map(caso, numPuntos2, fin_pantalla, avanza_conv, s, reset, clock, puntos1Y, puntos1X, puntos2Y, puntos2X, enable_pantalla, fin_puntos, puntos_centrales,indice);
reco: reconocedor port map(ps2data, ps2clk, reset, clock, fin_teclado, fin_coef, salida_teclado);
divisor1: divisor port map (reset, clk, clock);
ram: rams_2p port map(clock, we, addr1, addr2, di, do1, do2);
--PANTALLA
reset<= resetN;
a<=puntos2Y-puntos1Y;
b<=puntos2X-puntos1X when puntos2X>puntos1X else
puntos1X-puntos2X;
auxColumna <= vcnt - (vInf+1);
columna<= auxColumna(nB+1 downto 1);
fila<= hcnt - (hInf+1);
addr2 <=fila(nB downto 0)+1;
data(0 to 127) <=do2;
data_particular <=data(conv_integer(columna));
columnaExp<= auxColumna(3 downto 0);
filaExp<= hcnt - (32);
addrExp <=filaExp(7 downto 0);
dataExp(0 to 10) <=doExp;
--Al resto de pos de dataExp le ponemos ceros
dataExp(11 to 15)<=(others=>'0');
data_particularExp <=dataExp(conv_integer(columnaExp));
columnaNum<= auxColumna(3 downto 0);
addrNum <=fila(5 downto 0);
dataNum(0 to 9) <=doNum;
--Al resto de pos de dataNum le ponemos ceros
dataNum(10 to 15)<=(others=>'0');
data_particularNum <=dataNum(conv_integer(columnaNum));
colorear: process(hcnt, vcnt, pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_num, pinta_expY, pinta_expB)
begin
if pinta_num = '1' or pinta_expY ='1' then
rgb<="111111000";
elsif pinta_expB ='1' then
rgb<="001011110";
elsif pinta_expresion = '1' then
rgb<="111111111";
elsif pinta_funcion ='1' then
rgb<="111001011";
elsif pinta_ejes = '1' then
rgb<="000000100";
elsif pinta_fondo = '1' then
rgb<="111111111";
else rgb<="000000000";
end if;
end process colorear;
pintar_fondo: process(hcnt, vcnt)
begin
pinta_fondo<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
pinta_fondo<='1';
end if;
end if;
end process pintar_fondo;
pintar_ejes: process(hcnt, vcnt, solo_positivos)
begin
pinta_ejes<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if (vcnt=192 or vcnt=193) then pinta_ejes <= '1';
elsif solo_positivos ='0' and hcnt=128 then pinta_ejes <= '1';
elsif solo_positivos ='1' and hcnt=(vInf+1) then pinta_ejes <= '1';
--escala horizontal
elsif vcnt =194 and hcnt(2 downto 0)="000" then pinta_ejes <='1';
--escala vertical
elsif solo_positivos ='0' and hcnt=129 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
elsif solo_positivos ='1' and hcnt=vInf+2 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
end if;
end if;
end if;
end process pintar_ejes;
pintar_funcion: process(hcnt, vcnt, data_particular, noPintes)
begin
pinta_funcion <= '0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if data_particular='1' and noPintes = '1' then pinta_funcion <= '1';
end if;
end if;
end if;
end process pintar_funcion;
pintar_expresion: process(hcnt, vcnt, data_particularExp, fin_coef)
begin
pinta_expresion <= '0';
pinta_expB <='0';
pinta_expY <='0';
if vcnt > vSup +15 and vcnt < (vSup+11)+15 then
if (hcnt > 32 and hcnt < 42) then
if data_particularExp='1' and fin_coef(0) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(0) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 53 and hcnt < 65) then
if data_particularExp='1' and fin_coef(1) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(1) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 82 and hcnt < 94) then
if data_particularExp='1' and fin_coef(2) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(2) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 111 and hcnt < 123) then
if data_particularExp='1' and fin_coef(3) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(3) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 132 and hcnt < 144) then
if data_particularExp='1' and fin_coef(4) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(4) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 153 and hcnt < 165) then
if data_particularExp='1' and fin_coef(5) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(5) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 170 and hcnt <= 182) then
if data_particularExp='1' and fin_coef(6) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(6) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 181 and hcnt < 193) then
if data_particularExp='1' and fin_coef(7) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(7) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 202 and hcnt < 214) then
if data_particularExp='1' and fin_coef(8) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(8) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 225 and hcnt < 237) then
if data_particularExp='1' and fin_coef(9) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(9) ='1' then pinta_expY <='1';
end if;
elsif (hcnt >= 43 and hcnt <= 53) or (hcnt >= 65 and hcnt <= 82) or (hcnt >= 94 and hcnt <=111) or (hcnt >= 123 and hcnt <= 132) or (hcnt >= 144 and hcnt <=153) or (hcnt >= 165 and hcnt <=170) or (hcnt >= 193 and hcnt <=202)or (hcnt >= 214 and hcnt <=225) or (hcnt >= 237 and hcnt < 32+217)then
if data_particularExp='1' then pinta_expresion <= '1';
end if;
end if;
end if;
end process pintar_expresion;
pintar_integral: process(hcnt, vcnt, data_particularNum)
begin
pinta_num <= '0';
if hcnt > hInf and hcnt < hInf+64 then
if vcnt >= vInf -15 and vcnt < (vInf+10)-15 then
if data_particularNum='1' then pinta_num <= '1';
end if;
end if;
end if;
end process pintar_integral;
combinacional_pantalla: process(ESTADO, enable_pantalla, j, i, v, aj, bi, puntos1X, puntos1Y, puntos2X, puntos2Y, fin_puntos, vAux, inf, inf1, inf2, a, b,solo_positivos)
begin
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
--vAux<=(others=>'0');
-- si lo pones por alguna razon deja de sintetizar, pero habria que ponerlo porque si no xilinx no
-- entiende las declaraciones parciales y pone latches
we<='0';
fin_pantalla<='0';
-- para quitar latches, cuando queramos usarlo lo pondremos explicitamente
case ESTADO is
when S1 =>
if inf = '0' then
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
we<='0';
fin_pantalla<='1';
if fin_puntos = '1' then
vAux<= (others =>'0');
else
vAux<=v;
end if;
if enable_pantalla ='1' then
vAux(conv_integer(puntos1X))<= '1';
SIG_ESTADO <= S2;
else SIG_ESTADO <= S1;
end if;
else
if solo_positivos = '1' then
we <= '0';
fin_pantalla <= '0';
SIG_ESTADO <= S2;
iAux <= (others=>'0');
vAux<=(others=>'0');
else
we <= '1';
fin_pantalla <= '0';
if inf1 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos1X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos1X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos1X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos1X)) <= (others=>'1');
end if;
di <= v or vAux;
addr1 <= puntos1Y;
iAux(nB downto 1) <= (others=>'0');
iAux(0) <= '1';
SIG_ESTADO <= S2;
end if;
end if;
when S2 =>
if inf = '0' then
fin_pantalla<='0';
ajAux<=aj;
biAux<=bi;
iAux<=i;
di<=(others=>'0');
addr1<=(others=>'0');
we<='0';
vAux <= v;
if a(nB downto 1) +aj <bi and j < b then
if puntos2X>puntos1X then
vAux(conv_integer(j+1+puntos1X))<= '1';
else
vAux(conv_integer(puntos1X-j-1))<= '1';
end if;
jAux<=j+1;
ajAux <= aj+a;
SIG_ESTADO <= S2;
else
di<=v;
we<='1';
addr1<=i+puntos1Y;
iAux <= i+1;
biAux <= bi+b;
jAux <= j;
vAux<=(others=>'0');
if i < a then
if a(nB downto 1) +aj >=bi+b then
if puntos2X>puntos1X then
vAux(conv_integer(j+puntos1X))<=v(conv_integer(j+puntos1X));
else
vAux(conv_integer(puntos1X-j))<= v(conv_integer(puntos1X-j));
end if;
end if;
SIG_ESTADO <= S2;
else
SIG_ESTADO <= S1;
vAux<=v;
end if;
end if;
else
we <= '1';
fin_pantalla <= '0';
di <= (others=>'0');
addr1 <= puntos1Y+i;
iAux <= i+1;
vAux <= (others=>'0');
if puntos1Y+iAux = puntos2Y then
SIG_ESTADO <= S3;
else
SIG_ESTADO <= S2;
end if;
end if;
when S3 =>
we <= '1';
fin_pantalla <= '1';
if inf2 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos2X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos2X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos2X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos2X)) <= (others=>'1');
end if;
di <= vAux;
addr1 <= puntos2Y;
iAux <= (others=>'0');
SIG_ESTADO <= S1;
end case;
end process combinacional_pantalla;
sincrono: process(clock, reset)
begin
-- Reset asincrono
if reset = '1' then
ESTADO <= S1;
elsif clock'event and clock = '1' then
ESTADO <= SIG_ESTADO;
end if;
end process sincrono;
registros_clock: process(vAux, clock, reset, jAux, iAux, ajAux, biAux, noPintesAux)
begin
if reset = '1' then
v<=(others=>'0');
j<=(others=>'0');
i<=(others=>'0');
aj<=(others =>'0');
bi<=(others =>'0');
noPintes <='0';
elsif clock'event and clock='1' then
v<=vAux;
j<=jAux;
i<=iAux;
aj<=ajAux;
bi<=biAux;
noPintes <=noPintesAux;
end if;
end process registros_clock;
pA: process(clock,reset)
begin
-- reset asynchronously clears pixel counter
if reset='1' then
hcnt <= "0000000000";
-- horiz. pixel counter increments on rising edge of dot clock
elsif (clock'event and clock='1') then
-- horiz. pixel counter rolls-over after 381 pixels
if hcnt<380 then
hcnt <= hcnt + 1;
else
hcnt <= "0000000000";
end if;
end if;
end process pA;
pB: process(hsyncb,reset)
begin
-- reset asynchronously clears line counter
if reset='1' then
vcnt <= "000000000";
-- vert. line counter increments after every horiz. line
elsif (hsyncb'event and hsyncb='1') then
-- vert. line counter rolls-over after 528 lines
if vcnt<527 then
vcnt <= vcnt + 1;
else
vcnt <= "000000000";
end if;
end if;
end process pB;
C: process(clock,reset)
begin
-- reset asynchronously sets horizontal sync to inactive
if reset='1' then
hsyncb <= '1';
-- horizontal sync is recomputed on the rising edge of every dot clock
elsif (clock'event and clock='1') then
-- horiz. sync is low in this interval to signal start of a new line
if (hcnt>=291 and hcnt<337) then
hsyncb <= '0';
else
hsyncb <= '1';
end if;
end if;
end process;
D: process(hsyncb,reset)
begin
-- reset asynchronously sets vertical sync to inactive
if reset='1' then
vsyncb <= '1';
-- vertical sync is recomputed at the end of every line of pixels
elsif (hsyncb'event and hsyncb='1') then
-- vert. sync is low in this interval to signal start of a new frame
if (vcnt>=490 and vcnt<492) then
vsyncb <= '0';
else
vsyncb <= '1';
end if;
end if;
end process;
--CONTROLADOR PRINCIPAL
with salida_teclado(4 downto 0) select
x3 <= '0' when "00000",
'1' when others;
with salida_teclado(9 downto 5) select
x2 <= '0' when "00000",
'1' when others;
with salida_teclado(14 downto 10) select
x1 <= '0' when "00000",
'1' when others;
with salida_teclado(49 downto 45) select
xl <= '0' when "00000",
'1' when others;
x4 <= x1 or x2 or x3;
x5 <= x4 or xl;
inf <= puntos_centrales and x5;
--'0' es positivo, '1' es negativo
pinf1y2: process(salida_teclado, x1, x2, x3)
begin
if salida_teclado(4) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x3 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(9) = '1' then
inf1 <= '1';
inf2 <= '1';
elsif x2 = '1' then
inf1 <= '0';
inf2 <= '0';
elsif salida_teclado(14) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x1 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(49) = '1' then -- a partir de aqui el limite lo domina el logaritmo
inf1 <= '0'; -- para quitar latches
inf2 <= '0';
else -- o el caso de que no usemos los inf
inf1 <= '0'; -- para quitar latches
inf2 <= '1';
end if;
end process pinf1y2;
sincronoGen: process(clock, reset)
begin
if reset = '1' then
estadoGen <= inicial;
elsif clock'event and clock = '1' then
estadoGen <= estadoGen_sig;
end if;
end process sincronoGen;
--En función de si hay potencias negativas o solo evaluamos en puntos negativos (como en el caso del logaritmo
--elegimos un caso u otro: ver puntos_muestra.vhd y conversor.vhd)
p_numero: process(x4, solo_positivos)
begin
if solo_positivos = '0' then
caso <= "10";
numPuntos2 <= "0100000";
else
if x4 = '0' then
caso <= "00";
numPuntos2 <= "0100001";
else
caso <= "01";
numPuntos2 <= "0100000";
end if;
end if;
end process p_numero;
maquina_estadoGens: process(estadoGen, enable_muestra, enable_calculo, ready_calculo, fin_puntos, fin_teclado, fin_muestra, salida_teclado, solo_positivos, valorIntegral, limite1, limite2, noPintes, s)
begin
valorIntegralAux <= valorIntegral;
solo_positivosAux <= solo_positivos;
retro_muestra <= '0';
limite1Aux <= limite1;
limite2Aux <= limite2;
noPintesAux<=noPintes;
case estadoGen is
-- estadoGen de inicio
when inicial =>
integral <= '1';
enable_muestra <= '0'; -- Cuando está a 1, la salida devuelve el siguiente punto de muestra a ser evaluado.
enable_calculo <= '0';
avanza_conv <= '0'; -- Avanza el conversor al siguiente estadoGen. En cada estadoGen con el prefijo S, se guarda
-- cada punto obtenido de calculo.vhd, con el fin de aplicar la conversión a coordenadas
-- en memoria/pantalla.
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer;
-- Criterio de divergencia de la integral
if solo_positivos = '0' then
if salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else valorIntegralAux <= limite2 - limite1;
end if;
else
if salida_teclado(4 downto 0) /= "00000" then
if salida_teclado(4) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(14 downto 10) /= "00000" then
if salida_teclado(14) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else
valorIntegralAux <= limite2 - limite1;
end if;
end if;
when leer =>
integral <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
avanza_conv <= '0';
if fin_teclado = '0' then
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer; -- fin_teclado indica el momento en el que salida_teclado tiene
else
estadoGen_sig <= calc; -- la información adecuada (los coeficientes del polinomio)
if salida_teclado(49 downto 45) = "00000" then
solo_positivosAux <= '0';
else solo_positivosAux <= '1';
end if;
avanza_conv <= '1';
end if;
-- calc: estadoGen de cálculo de la imagen de un punto muestra. Hay 14 puntos a calcular, por tanto antes de pasar al
-- siguiente estadoGen, a_memoria, volvemos a pasar 13 veces a este estadoGen (cuando ready_calculo = 1, por tanto, se ha
-- calculado la imagen del punto. En este caso, avanzamos el conversor y el módulo muestra)
when calc =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
if ready_calculo = '0' then
estadoGen_sig <= calc;
enable_muestra <= '0';
else enable_muestra <= '1';
avanza_conv <= '1';
if fin_muestra = '0' then
estadoGen_sig <= calc;
else
estadoGen_sig <= a_memoria;
end if;
end if;
-- estadoGen de transferencia a memoria/pantalla. En el módulo conversor, corresponde a los estadoGens con prefijo
when a_memoria =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
noPintesAux<='1';
if fin_puntos = '1' then
estadoGen_sig <= integrar1;
integral <= '1';
else
estadoGen_sig <= a_memoria;
end if;
when integrar1 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar1;
else retro_muestra <= '1';
estadoGen_sig <= integrar2;
limite1Aux <= s;
end if;
when integrar2 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
retro_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar2;
else enable_muestra <= '1';
estadoGen_sig <= inicial;
limite2Aux <= s;
end if;
end case;
end process maquina_estadoGens;
fin_principal <= fin_puntos;
escalay <= indice;
with count select
escalax <= "11101101" when "1011",
"11100110" when "1100",
"11001111" when "1101",
"11011011" when "1110",
"10000110" when "1111",
"00111111" when "0000",
"00000110" when "0001",
"11111111" when others;
registros_controlador: process (clock, estadoGen, solo_positivosAux, limite1Aux, limite2Aux, valorIntegralAux, reset)
begin
if reset = '1' then
valorIntegral <= (others => '0');
solo_positivos <= '0';
limite1 <= (others => '0');
limite2 <= (others => '0');
elsif clock'event and clock = '1' then
solo_positivos <= solo_positivosAux;
limite1 <= limite1Aux;
limite2 <= limite2Aux;
valorIntegral <= valorIntegralAux;
end if;
end process registros_controlador;
end project_arch; |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:10:21 11/10/2013
-- Design Name:
-- Module Name: vga - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
--pantalla debe ser top
entity project is
port
( resetN: in std_logic; -- reset
clk: in std_logic;
ps2data: inout std_logic;
ps2clk: inout std_logic;
hsyncb: inout std_logic; -- horizontal (line) sync
vsyncb: out std_logic; -- vertical (frame) sync
rgb: out std_logic_vector(8 downto 0); -- red,green,blue colors
fin_principal: out std_logic;
escalay: out std_logic_vector(4 downto 0); --Conectada a barra de leds
escalax: out std_logic_vector(7 downto 0)); -- Conectada a los 7 segmentos
end project;
architecture project_arch of project is
component puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end component puntos_muestra;
component calculo is
port(reset, clk, enable, integral: in std_logic;
num: in std_logic_vector(20 downto 0);
c: in std_logic_vector(49 downto 0);
s: out std_logic_vector(20 downto 0);
ready: out std_logic);
end component calculo;
component conversor is
port( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector(6 downto 0);
fin_pantalla: in std_logic;
avanza: in std_logic;
punto: in std_logic_vector(20 downto 0);
reset, clk:in std_logic;
punto1X, punto1Y, punto2X, punto2Y: out std_logic_vector(6 downto 0);
enable_pantalla, fin_conv, inf: out std_logic;
indice_o: out std_logic_vector(4 downto 0)); -- Para mostrarlo en la barra de LEDs
end component conversor;
component divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end component;
component rams_2p is
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(6 downto 0);
addr2 : in std_logic_vector(6 downto 0);
di : in std_logic_vector(0 to 127);
do1 : out std_logic_vector(0 to 127);
do2 : out std_logic_vector(0 to 127)
);
end component;
component reconocedor is
port(ps2data: inout std_logic;
ps2clk: inout std_logic;
reset: in std_logic;
clk: in std_logic;
fin : out std_logic;
fin_coef: out std_logic_vector(15 downto 0);
salida: out std_logic_vector(49 downto 0));
end component reconocedor;
component expresion is
port(
clk: in std_logic;
salida_teclado: in std_logic_vector(49 downto 0);
addr : in std_logic_vector(7 downto 0);
do : out std_logic_vector(0 to 10)
);
end component;
component numero is
port(
clk: in std_logic;
s: in std_logic_vector(20 downto 0);
addr : in std_logic_vector(5 downto 0);
do : out std_logic_vector(0 to 9)
);
end component;
type ESTADOS is (S1, S2, S3); --ESTADOS DE LA PANTALLA
signal ESTADO, SIG_ESTADO: ESTADOS;
type ESTADOSG is (inicial, leer, calc, a_memoria, integrar1, integrar2); --ESTADOS DEL CONTROLADOR PRINCIPAL
signal estadoGen, estadoGen_sig: ESTADOSG;
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal (contando el signo, pues representamos en C2)
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
constant nB : integer := 6; --nBits-1
constant nF : integer := 127; --nF-1
constant nC : integer := 255; --nC-1
constant hInf : integer := 63;
constant hSup : integer := hInf + nF + 2;
constant vInf : integer := 63;
constant vSup : integer := vInf + nC + 2;
constant numPuntos : integer := 2;
signal clock, reset: std_logic;
--Señales de la pantalla
signal hcnt, fila, filaExp: std_logic_vector(9 downto 0); -- horizontal pixel counter
signal vcnt, auxColumna: std_logic_vector(8 downto 0); -- vertical line counter
signal columna: std_logic_vector(6 downto 0);
signal data: std_logic_vector(0 to nF);
signal data_particular,data_particularExp, data_particularNum, we: std_logic;
signal addr1, addr2, puntos1X, puntos1Y, puntos2X, puntos2Y: std_logic_vector(6 downto 0);
signal di, do1, do2, vAux, v: std_logic_vector(0 to 127);
signal b, j, jAux, a, i, iAux: std_logic_vector(nB downto 0);
signal aj, bi, biAux, ajAux: std_logic_vector(11 downto 0);
signal pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_expY, pinta_expB, pinta_num:std_logic;
signal addrExp: std_logic_vector(7 downto 0);
signal addrNum: std_logic_vector(5 downto 0);
signal doExp: std_logic_vector(0 to 10);
signal doNum: std_logic_vector(0 to 9);
signal dataExp, dataNum: std_logic_vector(0 to 15);
signal columnaExp, columnaNum: std_logic_vector(3 downto 0);
signal fin_coef: std_logic_vector(15 downto 0);
signal noPintes, noPintesAux: std_logic;
--señales del controlador principal
signal caso: std_logic_vector(1 downto 0);
signal salida_teclado: std_logic_vector(49 downto 0);
signal integral, solo_positivos, solo_positivosAux, fin_muestra, fin_teclado, ready_calculo, enable_muestra, retro_muestra, fin_puntos, enable_calculo, fin_pantalla,enable_pantalla, avanza_conv, inf, inf1, inf2, puntos_centrales, x1, x2, x3, x4, x5, xl: std_logic;
signal punto, s, limite1, limite1Aux, limite2, limite2Aux, valorIntegral, valorIntegralAux: std_logic_vector(DEC+ENT-1 downto 0);
signal numPuntos2 : std_logic_vector(6 downto 0);
signal count: std_logic_vector(3 downto 0);
signal indice: std_logic_vector(4 downto 0);
begin
calcExp: expresion port map (clock, salida_teclado, addrExp, doExp);
calInt: numero port map (clock, valorIntegral, addrNum,doNum);
muestra: puntos_muestra port map(caso, numPuntos2, enable_muestra, retro_muestra, clock, reset, fin_muestra, salida_teclado,punto, count);
calculador: calculo port map(reset, clock, enable_calculo,integral, punto, salida_teclado, s, ready_calculo);
--Por comodidad las componentes de los puntos están intercambiadas
conver: conversor port map(caso, numPuntos2, fin_pantalla, avanza_conv, s, reset, clock, puntos1Y, puntos1X, puntos2Y, puntos2X, enable_pantalla, fin_puntos, puntos_centrales,indice);
reco: reconocedor port map(ps2data, ps2clk, reset, clock, fin_teclado, fin_coef, salida_teclado);
divisor1: divisor port map (reset, clk, clock);
ram: rams_2p port map(clock, we, addr1, addr2, di, do1, do2);
--PANTALLA
reset<= resetN;
a<=puntos2Y-puntos1Y;
b<=puntos2X-puntos1X when puntos2X>puntos1X else
puntos1X-puntos2X;
auxColumna <= vcnt - (vInf+1);
columna<= auxColumna(nB+1 downto 1);
fila<= hcnt - (hInf+1);
addr2 <=fila(nB downto 0)+1;
data(0 to 127) <=do2;
data_particular <=data(conv_integer(columna));
columnaExp<= auxColumna(3 downto 0);
filaExp<= hcnt - (32);
addrExp <=filaExp(7 downto 0);
dataExp(0 to 10) <=doExp;
--Al resto de pos de dataExp le ponemos ceros
dataExp(11 to 15)<=(others=>'0');
data_particularExp <=dataExp(conv_integer(columnaExp));
columnaNum<= auxColumna(3 downto 0);
addrNum <=fila(5 downto 0);
dataNum(0 to 9) <=doNum;
--Al resto de pos de dataNum le ponemos ceros
dataNum(10 to 15)<=(others=>'0');
data_particularNum <=dataNum(conv_integer(columnaNum));
colorear: process(hcnt, vcnt, pinta_funcion, pinta_ejes, pinta_fondo, pinta_expresion, pinta_num, pinta_expY, pinta_expB)
begin
if pinta_num = '1' or pinta_expY ='1' then
rgb<="111111000";
elsif pinta_expB ='1' then
rgb<="001011110";
elsif pinta_expresion = '1' then
rgb<="111111111";
elsif pinta_funcion ='1' then
rgb<="111001011";
elsif pinta_ejes = '1' then
rgb<="000000100";
elsif pinta_fondo = '1' then
rgb<="111111111";
else rgb<="000000000";
end if;
end process colorear;
pintar_fondo: process(hcnt, vcnt)
begin
pinta_fondo<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
pinta_fondo<='1';
end if;
end if;
end process pintar_fondo;
pintar_ejes: process(hcnt, vcnt, solo_positivos)
begin
pinta_ejes<='0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if (vcnt=192 or vcnt=193) then pinta_ejes <= '1';
elsif solo_positivos ='0' and hcnt=128 then pinta_ejes <= '1';
elsif solo_positivos ='1' and hcnt=(vInf+1) then pinta_ejes <= '1';
--escala horizontal
elsif vcnt =194 and hcnt(2 downto 0)="000" then pinta_ejes <='1';
--escala vertical
elsif solo_positivos ='0' and hcnt=129 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
elsif solo_positivos ='1' and hcnt=vInf+2 and (vcnt(3 downto 0) ="0000" or vcnt(3 downto 0) ="0001") then pinta_ejes <='1';
end if;
end if;
end if;
end process pintar_ejes;
pintar_funcion: process(hcnt, vcnt, data_particular, noPintes)
begin
pinta_funcion <= '0';
if hcnt > hInf and hcnt < hSup then
if vcnt > vInf and vcnt < vSup then
if data_particular='1' and noPintes = '1' then pinta_funcion <= '1';
end if;
end if;
end if;
end process pintar_funcion;
pintar_expresion: process(hcnt, vcnt, data_particularExp, fin_coef)
begin
pinta_expresion <= '0';
pinta_expB <='0';
pinta_expY <='0';
if vcnt > vSup +15 and vcnt < (vSup+11)+15 then
if (hcnt > 32 and hcnt < 42) then
if data_particularExp='1' and fin_coef(0) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(0) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 53 and hcnt < 65) then
if data_particularExp='1' and fin_coef(1) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(1) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 82 and hcnt < 94) then
if data_particularExp='1' and fin_coef(2) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(2) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 111 and hcnt < 123) then
if data_particularExp='1' and fin_coef(3) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(3) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 132 and hcnt < 144) then
if data_particularExp='1' and fin_coef(4) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(4) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 153 and hcnt < 165) then
if data_particularExp='1' and fin_coef(5) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(5) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 170 and hcnt <= 182) then
if data_particularExp='1' and fin_coef(6) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(6) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 181 and hcnt < 193) then
if data_particularExp='1' and fin_coef(7) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(7) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 202 and hcnt < 214) then
if data_particularExp='1' and fin_coef(8) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(8) ='1' then pinta_expY <='1';
end if;
elsif (hcnt > 225 and hcnt < 237) then
if data_particularExp='1' and fin_coef(9) ='0' then pinta_expB <='1';
elsif data_particularExp='1' and fin_coef(9) ='1' then pinta_expY <='1';
end if;
elsif (hcnt >= 43 and hcnt <= 53) or (hcnt >= 65 and hcnt <= 82) or (hcnt >= 94 and hcnt <=111) or (hcnt >= 123 and hcnt <= 132) or (hcnt >= 144 and hcnt <=153) or (hcnt >= 165 and hcnt <=170) or (hcnt >= 193 and hcnt <=202)or (hcnt >= 214 and hcnt <=225) or (hcnt >= 237 and hcnt < 32+217)then
if data_particularExp='1' then pinta_expresion <= '1';
end if;
end if;
end if;
end process pintar_expresion;
pintar_integral: process(hcnt, vcnt, data_particularNum)
begin
pinta_num <= '0';
if hcnt > hInf and hcnt < hInf+64 then
if vcnt >= vInf -15 and vcnt < (vInf+10)-15 then
if data_particularNum='1' then pinta_num <= '1';
end if;
end if;
end if;
end process pintar_integral;
combinacional_pantalla: process(ESTADO, enable_pantalla, j, i, v, aj, bi, puntos1X, puntos1Y, puntos2X, puntos2Y, fin_puntos, vAux, inf, inf1, inf2, a, b,solo_positivos)
begin
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
--vAux<=(others=>'0');
-- si lo pones por alguna razon deja de sintetizar, pero habria que ponerlo porque si no xilinx no
-- entiende las declaraciones parciales y pone latches
we<='0';
fin_pantalla<='0';
-- para quitar latches, cuando queramos usarlo lo pondremos explicitamente
case ESTADO is
when S1 =>
if inf = '0' then
di<=(others=>'0');
addr1<=(others=>'0');
biAux<=(others=>'0');
ajAux<=(others=>'0');
iAux<=(others=>'0');
jAux<=(others=>'0');
we<='0';
fin_pantalla<='1';
if fin_puntos = '1' then
vAux<= (others =>'0');
else
vAux<=v;
end if;
if enable_pantalla ='1' then
vAux(conv_integer(puntos1X))<= '1';
SIG_ESTADO <= S2;
else SIG_ESTADO <= S1;
end if;
else
if solo_positivos = '1' then
we <= '0';
fin_pantalla <= '0';
SIG_ESTADO <= S2;
iAux <= (others=>'0');
vAux<=(others=>'0');
else
we <= '1';
fin_pantalla <= '0';
if inf1 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos1X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos1X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos1X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos1X)) <= (others=>'1');
end if;
di <= v or vAux;
addr1 <= puntos1Y;
iAux(nB downto 1) <= (others=>'0');
iAux(0) <= '1';
SIG_ESTADO <= S2;
end if;
end if;
when S2 =>
if inf = '0' then
fin_pantalla<='0';
ajAux<=aj;
biAux<=bi;
iAux<=i;
di<=(others=>'0');
addr1<=(others=>'0');
we<='0';
vAux <= v;
if a(nB downto 1) +aj <bi and j < b then
if puntos2X>puntos1X then
vAux(conv_integer(j+1+puntos1X))<= '1';
else
vAux(conv_integer(puntos1X-j-1))<= '1';
end if;
jAux<=j+1;
ajAux <= aj+a;
SIG_ESTADO <= S2;
else
di<=v;
we<='1';
addr1<=i+puntos1Y;
iAux <= i+1;
biAux <= bi+b;
jAux <= j;
vAux<=(others=>'0');
if i < a then
if a(nB downto 1) +aj >=bi+b then
if puntos2X>puntos1X then
vAux(conv_integer(j+puntos1X))<=v(conv_integer(j+puntos1X));
else
vAux(conv_integer(puntos1X-j))<= v(conv_integer(puntos1X-j));
end if;
end if;
SIG_ESTADO <= S2;
else
SIG_ESTADO <= S1;
vAux<=v;
end if;
end if;
else
we <= '1';
fin_pantalla <= '0';
di <= (others=>'0');
addr1 <= puntos1Y+i;
iAux <= i+1;
vAux <= (others=>'0');
if puntos1Y+iAux = puntos2Y then
SIG_ESTADO <= S3;
else
SIG_ESTADO <= S2;
end if;
end if;
when S3 =>
we <= '1';
fin_pantalla <= '1';
if inf2 = '1' then --bit + sig bit + abajo
vAux(conv_integer(puntos2X) to 127) <= (others=>'1');
vAux(0 to conv_integer(puntos2X)-1) <= (others=>'0');
else
vAux(conv_integer(puntos2X)+1 to 127) <= (others=>'0');
vAux(0 to conv_integer(puntos2X)) <= (others=>'1');
end if;
di <= vAux;
addr1 <= puntos2Y;
iAux <= (others=>'0');
SIG_ESTADO <= S1;
end case;
end process combinacional_pantalla;
sincrono: process(clock, reset)
begin
-- Reset asincrono
if reset = '1' then
ESTADO <= S1;
elsif clock'event and clock = '1' then
ESTADO <= SIG_ESTADO;
end if;
end process sincrono;
registros_clock: process(vAux, clock, reset, jAux, iAux, ajAux, biAux, noPintesAux)
begin
if reset = '1' then
v<=(others=>'0');
j<=(others=>'0');
i<=(others=>'0');
aj<=(others =>'0');
bi<=(others =>'0');
noPintes <='0';
elsif clock'event and clock='1' then
v<=vAux;
j<=jAux;
i<=iAux;
aj<=ajAux;
bi<=biAux;
noPintes <=noPintesAux;
end if;
end process registros_clock;
pA: process(clock,reset)
begin
-- reset asynchronously clears pixel counter
if reset='1' then
hcnt <= "0000000000";
-- horiz. pixel counter increments on rising edge of dot clock
elsif (clock'event and clock='1') then
-- horiz. pixel counter rolls-over after 381 pixels
if hcnt<380 then
hcnt <= hcnt + 1;
else
hcnt <= "0000000000";
end if;
end if;
end process pA;
pB: process(hsyncb,reset)
begin
-- reset asynchronously clears line counter
if reset='1' then
vcnt <= "000000000";
-- vert. line counter increments after every horiz. line
elsif (hsyncb'event and hsyncb='1') then
-- vert. line counter rolls-over after 528 lines
if vcnt<527 then
vcnt <= vcnt + 1;
else
vcnt <= "000000000";
end if;
end if;
end process pB;
C: process(clock,reset)
begin
-- reset asynchronously sets horizontal sync to inactive
if reset='1' then
hsyncb <= '1';
-- horizontal sync is recomputed on the rising edge of every dot clock
elsif (clock'event and clock='1') then
-- horiz. sync is low in this interval to signal start of a new line
if (hcnt>=291 and hcnt<337) then
hsyncb <= '0';
else
hsyncb <= '1';
end if;
end if;
end process;
D: process(hsyncb,reset)
begin
-- reset asynchronously sets vertical sync to inactive
if reset='1' then
vsyncb <= '1';
-- vertical sync is recomputed at the end of every line of pixels
elsif (hsyncb'event and hsyncb='1') then
-- vert. sync is low in this interval to signal start of a new frame
if (vcnt>=490 and vcnt<492) then
vsyncb <= '0';
else
vsyncb <= '1';
end if;
end if;
end process;
--CONTROLADOR PRINCIPAL
with salida_teclado(4 downto 0) select
x3 <= '0' when "00000",
'1' when others;
with salida_teclado(9 downto 5) select
x2 <= '0' when "00000",
'1' when others;
with salida_teclado(14 downto 10) select
x1 <= '0' when "00000",
'1' when others;
with salida_teclado(49 downto 45) select
xl <= '0' when "00000",
'1' when others;
x4 <= x1 or x2 or x3;
x5 <= x4 or xl;
inf <= puntos_centrales and x5;
--'0' es positivo, '1' es negativo
pinf1y2: process(salida_teclado, x1, x2, x3)
begin
if salida_teclado(4) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x3 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(9) = '1' then
inf1 <= '1';
inf2 <= '1';
elsif x2 = '1' then
inf1 <= '0';
inf2 <= '0';
elsif salida_teclado(14) = '1' then
inf1 <= '0';
inf2 <= '1';
elsif x1 = '1' then
inf1 <= '1';
inf2 <= '0';
elsif salida_teclado(49) = '1' then -- a partir de aqui el limite lo domina el logaritmo
inf1 <= '0'; -- para quitar latches
inf2 <= '0';
else -- o el caso de que no usemos los inf
inf1 <= '0'; -- para quitar latches
inf2 <= '1';
end if;
end process pinf1y2;
sincronoGen: process(clock, reset)
begin
if reset = '1' then
estadoGen <= inicial;
elsif clock'event and clock = '1' then
estadoGen <= estadoGen_sig;
end if;
end process sincronoGen;
--En función de si hay potencias negativas o solo evaluamos en puntos negativos (como en el caso del logaritmo
--elegimos un caso u otro: ver puntos_muestra.vhd y conversor.vhd)
p_numero: process(x4, solo_positivos)
begin
if solo_positivos = '0' then
caso <= "10";
numPuntos2 <= "0100000";
else
if x4 = '0' then
caso <= "00";
numPuntos2 <= "0100001";
else
caso <= "01";
numPuntos2 <= "0100000";
end if;
end if;
end process p_numero;
maquina_estadoGens: process(estadoGen, enable_muestra, enable_calculo, ready_calculo, fin_puntos, fin_teclado, fin_muestra, salida_teclado, solo_positivos, valorIntegral, limite1, limite2, noPintes, s)
begin
valorIntegralAux <= valorIntegral;
solo_positivosAux <= solo_positivos;
retro_muestra <= '0';
limite1Aux <= limite1;
limite2Aux <= limite2;
noPintesAux<=noPintes;
case estadoGen is
-- estadoGen de inicio
when inicial =>
integral <= '1';
enable_muestra <= '0'; -- Cuando está a 1, la salida devuelve el siguiente punto de muestra a ser evaluado.
enable_calculo <= '0';
avanza_conv <= '0'; -- Avanza el conversor al siguiente estadoGen. En cada estadoGen con el prefijo S, se guarda
-- cada punto obtenido de calculo.vhd, con el fin de aplicar la conversión a coordenadas
-- en memoria/pantalla.
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer;
-- Criterio de divergencia de la integral
if solo_positivos = '0' then
if salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else valorIntegralAux <= limite2 - limite1;
end if;
else
if salida_teclado(4 downto 0) /= "00000" then
if salida_teclado(4) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(9 downto 5) /= "00000" then
if salida_teclado(9) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
elsif salida_teclado(14 downto 10) /= "00000" then
if salida_teclado(14) = '0' then
valorIntegralAux <= "011111111111111111111";
else
valorIntegralAux <= "100000000000000000000";
end if;
else
valorIntegralAux <= limite2 - limite1;
end if;
end if;
when leer =>
integral <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
avanza_conv <= '0';
if fin_teclado = '0' then
solo_positivosAux <= solo_positivos;
estadoGen_sig <= leer; -- fin_teclado indica el momento en el que salida_teclado tiene
else
estadoGen_sig <= calc; -- la información adecuada (los coeficientes del polinomio)
if salida_teclado(49 downto 45) = "00000" then
solo_positivosAux <= '0';
else solo_positivosAux <= '1';
end if;
avanza_conv <= '1';
end if;
-- calc: estadoGen de cálculo de la imagen de un punto muestra. Hay 14 puntos a calcular, por tanto antes de pasar al
-- siguiente estadoGen, a_memoria, volvemos a pasar 13 veces a este estadoGen (cuando ready_calculo = 1, por tanto, se ha
-- calculado la imagen del punto. En este caso, avanzamos el conversor y el módulo muestra)
when calc =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
if ready_calculo = '0' then
estadoGen_sig <= calc;
enable_muestra <= '0';
else enable_muestra <= '1';
avanza_conv <= '1';
if fin_muestra = '0' then
estadoGen_sig <= calc;
else
estadoGen_sig <= a_memoria;
end if;
end if;
-- estadoGen de transferencia a memoria/pantalla. En el módulo conversor, corresponde a los estadoGens con prefijo
when a_memoria =>
integral <= '0';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_muestra <= '0';
enable_calculo <= '0';
noPintesAux<='1';
if fin_puntos = '1' then
estadoGen_sig <= integrar1;
integral <= '1';
else
estadoGen_sig <= a_memoria;
end if;
when integrar1 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar1;
else retro_muestra <= '1';
estadoGen_sig <= integrar2;
limite1Aux <= s;
end if;
when integrar2 =>
integral <= '1';
solo_positivosAux <= solo_positivos;
avanza_conv <= '0';
enable_calculo <= '1';
enable_muestra <= '0';
retro_muestra <= '0';
if ready_calculo = '0' then
estadoGen_sig <= integrar2;
else enable_muestra <= '1';
estadoGen_sig <= inicial;
limite2Aux <= s;
end if;
end case;
end process maquina_estadoGens;
fin_principal <= fin_puntos;
escalay <= indice;
with count select
escalax <= "11101101" when "1011",
"11100110" when "1100",
"11001111" when "1101",
"11011011" when "1110",
"10000110" when "1111",
"00111111" when "0000",
"00000110" when "0001",
"11111111" when others;
registros_controlador: process (clock, estadoGen, solo_positivosAux, limite1Aux, limite2Aux, valorIntegralAux, reset)
begin
if reset = '1' then
valorIntegral <= (others => '0');
solo_positivos <= '0';
limite1 <= (others => '0');
limite2 <= (others => '0');
elsif clock'event and clock = '1' then
solo_positivos <= solo_positivosAux;
limite1 <= limite1Aux;
limite2 <= limite2Aux;
valorIntegral <= valorIntegralAux;
end if;
end process registros_controlador;
end project_arch; |
-------------------------------------------------------------------------------
--! @file onewire_dongle_top.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief 1-wire ID and temperature sensor USB dongle.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proasic3;
use proasic3.all;
--! @brief Entity declaration of onewire_dongle_top
--! @details
--! When push-button is pressed, read 1-wire bus and transmit all values over
--! UART at 115200 baud.
entity onewire_dongle_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_pad_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! @}
--! @name Push-button and LEDs
--! @{
--! Push-button (active-low)
pb_n_i : in std_ulogic;
--! LEDs
leds_o : out std_ulogic_vector(2 downto 0);
--! @}
--! @name UART
--! @{
--! Receive signal
uart_rx_i : in std_ulogic;
--! Transmit signal
uart_tx_o : out std_ulogic;
--! @}
--! @name 1-wire bus
--! @{
--! Receive signal
ow_rx_i : in std_ulogic;
--! Transmit signal
ow_tx_o : out std_ulogic;
--! Strong pull-up
ow_spup_o : out std_ulogic);
--! @}
end entity onewire_dongle_top;
--! RTL implementation of onewire_dongle_top
architecture rtl of onewire_dongle_top is
-----------------------------------------------------------------------------
--! @name Components
-----------------------------------------------------------------------------
--! @{
-- Input buffer to force INBUF on clock (can't use pin 10 otherwise)
component INBUF_LVCMOS33
port (
PAD : in std_logic;
Y : out std_logic);
end component;
--! @}
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
type state_t is (IDLE, FULL_RUN, GET_DATA, DATA);
type reg_t is record
state : state_t;
rd : std_ulogic;
addr : unsigned(4 downto 0);
end record;
constant init_c : reg_t := (
state => IDLE,
rd => '0',
addr => "00000");
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal clk_i : std_ulogic;
signal rst_n : std_ulogic;
signal pb_n : std_ulogic;
signal ow_rx : std_ulogic;
signal uart_rx : std_ulogic;
signal ow_discover : std_ulogic;
signal ow_get_temp : std_ulogic;
signal ow_busy : std_ulogic;
signal ow_done : std_ulogic;
signal ow_device_count : std_ulogic_vector(4 downto 0);
signal ow_error_too_many : std_ulogic;
signal ow_rd_addr : std_ulogic_vector(4 downto 0);
signal ow_rd_en : std_ulogic;
signal ow_rd_data : std_ulogic_vector(63 downto 0);
signal ow_rd_data_en : std_ulogic;
signal tx_done : std_ulogic;
signal uart_data : std_ulogic_vector(7 downto 0);
signal uart_data_en : std_ulogic;
signal uart_done : std_ulogic;
signal uart_cmd : std_ulogic_vector(7 downto 0);
signal uart_cmd_en : std_ulogic;
signal trigger_discover : std_ulogic;
signal trigger_get_temp : std_ulogic;
signal nxt_reg : reg_t;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
leds_o(0) <= ow_busy;
leds_o(1) <= '0' when ow_device_count = "00000" else '1';
leds_o(2) <= ow_error_too_many;
-----------------------------------------------------------------------------
-- Signal Assignments
-----------------------------------------------------------------------------
trigger_discover <= '1' when uart_cmd = x"01" and uart_cmd_en = '1' else '0';
trigger_get_temp <= '1' when uart_cmd = x"10" and uart_cmd_en = '1' else '0';
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
-- Input buffer to force INBUF on clock (can't use pin 10 otherwise)
INBUF_inst : INBUF_LVCMOS33
port map (
PAD => clk_pad_i,
Y => clk_i);
reset_gen_inst : entity work.reset_generator
port map (
clk_i => clk_i,
rst_asy_i => rst_asy_n_i,
rst_o => rst_n);
ext_inputs_inst : entity work.external_inputs
generic map (
init_value_g => '1',
num_inputs_g => 3,
filter_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i(0) => pb_n_i,
sig_i(1) => ow_rx_i,
sig_i(2) => uart_rx_i,
sig_o(0) => pb_n,
sig_o(1) => ow_rx,
sig_o(2) => uart_rx);
onewire_idtemp_inst : entity work.onewire_idtemp
generic map (
clk_frequency_g => 40e6,
max_devices_g => 16,
invert_bus_g => true,
invert_pullup_g => true)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
discover_i => ow_discover,
get_temp_i => ow_get_temp,
busy_o => ow_busy,
done_o => ow_done,
device_count_o => ow_device_count,
error_too_many_o => ow_error_too_many,
rd_addr_i => ow_rd_addr,
rd_en_i => ow_rd_en,
rd_data_o => ow_rd_data,
rd_data_en_o => ow_rd_data_en,
rd_busy_o => open,
strong_pullup_o => ow_spup_o,
rx_i => ow_rx,
tx_o => ow_tx_o);
array_tx_inst : entity work.array_tx
generic map (
data_count_g => 8,
data_width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
data_i => ow_rd_data,
data_en_i => ow_rd_data_en,
busy_o => open,
done_o => tx_done,
tx_data_o => uart_data,
tx_data_en_o => uart_data_en,
tx_done_i => uart_done);
uart_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 347)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
data_i => uart_data,
data_en_i => uart_data_en,
busy_o => open,
done_o => uart_done,
tx_o => uart_tx_o);
uart_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 347)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
rx_i => uart_rx,
data_o => uart_cmd,
data_en_o => uart_cmd_en,
error_o => open);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_n) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_n = '0' then
reset;
elsif rising_edge(clk_i) then
reg <= nxt_reg;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, pb_n, ow_busy, ow_done, tx_done, trigger_discover,
trigger_get_temp) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.rd <= '0';
ow_discover <= '0';
ow_get_temp <= '0';
ow_rd_addr <= std_ulogic_vector(reg.addr);
ow_rd_en <= reg.rd;
case reg.state is
when IDLE =>
if pb_n = '0' and ow_busy = '0' then
ow_discover <= '1';
nxt_reg.state <= FULL_RUN;
elsif trigger_discover = '1' and ow_busy = '0' then
ow_discover <= '1';
nxt_reg.state <= GET_DATA;
elsif trigger_get_temp = '1' and ow_busy = '0' then
ow_get_temp <= '1';
nxt_reg.state <= GET_DATA;
end if;
when FULL_RUN =>
if ow_done = '1' then
ow_get_temp <= '1';
nxt_reg.state <= GET_DATA;
end if;
when GET_DATA =>
if ow_done = '1' then
nxt_reg.rd <= '1';
nxt_reg.state <= DATA;
end if;
when DATA =>
if tx_done = '1' then
if reg.addr = "11111" then
nxt_reg <= init_c;
else
nxt_reg.addr <= reg.addr + 1;
nxt_reg.rd <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
|
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS Corp
-- Tool Versions : WebPACK 6.3.03i
--
-- Description:
-- SDRAM controller
--
-- Revision:
-- n.a. (because of hacking by Hellwig Geisse)
--
-- Additional Comments:
-- 1.4.0:
-- Added generic parameter to enable/disable independent active rows in each bank.
-- 1.3.0:
-- Modified to allow independently active rows in each bank.
-- 1.2.0:
-- Modified to allow pipelining of read/write operations.
-- 1.1.0:
-- Initial release.
--
-- License:
-- This code can be freely distributed and modified as long as
-- this header is not removed.
--------------------------------------------------------------------
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity sdramCntl is
port(
-- host side
clk : in std_logic; -- master clock
clk_ok : in std_logic; -- true if clock is stable
rd : in std_logic; -- initiate read operation
wr : in std_logic; -- initiate write operation
done : out std_logic; -- read or write operation is done
hAddr : in std_logic_vector(23 downto 0); -- address from host to SDRAM
hDIn : in std_logic_vector(15 downto 0); -- data from host to SDRAM
hDOut : out std_logic_vector(15 downto 0); -- data from SDRAM to host
-- SDRAM side
cke : out std_logic; -- clock-enable to SDRAM
ce_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- SDRAM row address strobe
cas_n : out std_logic; -- SDRAM column address strobe
we_n : out std_logic; -- SDRAM write enable
ba : out std_logic_vector(1 downto 0); -- SDRAM bank address
sAddr : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sDIn : in std_logic_vector(15 downto 0); -- data from SDRAM
sDOut : out std_logic_vector(15 downto 0); -- data to SDRAM
sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut
dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true
dqml : out std_logic -- enable lower-byte of SDRAM databus if true
);
end sdramCntl;
architecture arch of sdramCntl is
constant YES : std_logic := '1';
constant NO : std_logic := '0';
-- select one of two integers based on a Boolean
function int_select(s : in boolean; a : in integer; b : in integer) return integer is
begin
if s then
return a;
else
return b;
end if;
return a;
end function int_select;
constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller
constant INPUT : std_logic := '0';
constant NOP : std_logic := '0'; -- no operation
constant READ : std_logic := '1'; -- read operation
constant WRITE : std_logic := '1'; -- write operation
-- SDRAM timing parameters
constant Tinit : natural := 200; -- min initialization interval (us)
constant Tras : natural := 45; -- min interval between active to precharge commands (ns)
constant Trcd : natural := 20; -- min interval between active and R/W commands (ns)
constant Tref : natural := 64_000_000; -- maximum refresh interval (ns)
constant Trfc : natural := 66; -- duration of refresh operation (ns)
constant Trp : natural := 20; -- min precharge command duration (ns)
constant Twr : natural := 15; -- write recovery time (ns)
constant Txsr : natural := 75; -- exit self-refresh time (ns)
-- SDRAM timing parameters converted into clock cycles (based on FREQ = 50_000)
constant NORM : natural := 1_000_000; -- normalize ns * KHz
constant INIT_CYCLES : natural := 1+((Tinit*50_000)/1000); -- SDRAM power-on initialization interval
constant RAS_CYCLES : natural := 1+((Tras*50_000)/NORM); -- active-to-precharge interval
constant RCD_CYCLES : natural := 1+((Trcd*50_000)/NORM); -- active-to-R/W interval
constant REF_CYCLES : natural := 1+(((Tref/8192)*50_000)/NORM); -- interval between row refreshes
constant RFC_CYCLES : natural := 1+((Trfc*50_000)/NORM); -- refresh operation interval
constant RP_CYCLES : natural := 1+((Trp*50_000)/NORM); -- precharge operation interval
constant WR_CYCLES : natural := 1+((Twr*50_000)/NORM); -- write recovery time
constant XSR_CYCLES : natural := 1+((Txsr*50_000)/NORM); -- exit self-refresh time
constant MODE_CYCLES : natural := 2; -- mode register setup time
constant CAS_CYCLES : natural := 3; -- CAS latency
constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM
-- timer registers that count down times for various SDRAM operations
signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time
signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time
signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time
signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes
signal rfshCntr_r, rfshCntr_x : natural range 0 to 8192; -- counts refreshes that are neede
signal nopCntr_r, nopCntr_x : natural range 0 to 10000; -- counts consecutive NOP operations
signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start
-- states of the SDRAM controller state machine
type cntlState is (
INITWAIT, -- initialization - waiting for power-on initialization to complete
INITPCHG, -- initialization - initial precharge of SDRAM banks
INITSETMODE, -- initialization - set SDRAM mode
INITRFSH, -- initialization - do initial refreshes
RW, -- read/write/refresh the SDRAM
ACTIVATE, -- open a row of the SDRAM for reading/writing
REFRESHROW, -- refresh a row of the SDRAM
SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low
);
signal state_r, state_x : cntlState; -- state register and next state
-- commands that are sent to the SDRAM to make it perform certain operations
-- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml)
subtype sdramCmd is unsigned(5 downto 0);
constant NOP_CMD : sdramCmd := "011100";
constant ACTIVE_CMD : sdramCmd := "001100";
constant READ_CMD : sdramCmd := "010100";
constant WRITE_CMD : sdramCmd := "010000";
constant PCHG_CMD : sdramCmd := "001011";
constant MODE_CMD : sdramCmd := "000011";
constant RFSH_CMD : sdramCmd := "000111";
-- SDRAM mode register
-- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS
subtype sdramMode is std_logic_vector(12 downto 0);
constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000";
-- the host address is decomposed into these sets of SDRAM address components
constant ROW_LEN : natural := 13; -- number of row address bits
constant COL_LEN : natural := 9; -- number of column address bits
signal bank : std_logic_vector(ba'range); -- bank address bits
signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank
signal col : std_logic_vector(sAddr'range); -- column address within row
-- registers that store the currently active row in each bank of the SDRAM
constant NUM_ACTIVE_ROWS : integer := 1;
type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range);
signal activeRow_r, activeRow_x : activeRowType;
signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active
signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits
signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row
signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated
-- there is a command bit embedded within the SDRAM column address
constant CMDBIT_POS : natural := 10; -- position of command bit
constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank
constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge
constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank
constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks
-- status signals that indicate when certain operations are in progress
signal wrInProgress : std_logic; -- write operation in progress
signal rdInProgress : std_logic; -- read operation in progress
signal activateInProgress : std_logic; -- row activation is in progress
-- these registers track the progress of read and write operations
signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress
signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle)
-- registered outputs to host
signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host
-- registered outputs to SDRAM
signal cke_r, cke_x : std_logic; -- clock enable
signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits
signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits
signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address
signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus
signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit
begin
-----------------------------------------------------------
-- attach some internal signals to the I/O ports
-----------------------------------------------------------
-- attach registered SDRAM control signals to SDRAM input pins
(ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits
cke <= cke_r; -- SDRAM clock enable
ba <= ba_r; -- SDRAM bank address
sAddr <= sAddr_r; -- SDRAM address
sDOut <= sData_r; -- SDRAM output data bus
sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable
-- attach some port signals
hDOut <= hDOut_r; -- data back to host
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r,
activeFlag_r, activeRow_r, activeBank_r,
rdPipeline_r, wrPipeline_r,
nopCntr_r, rfshCntr_r, timer_r, rasTimer_r,
wrTimer_r, refTimer_r, cmd_r, cke_r)
begin
-----------------------------------------------------------
-- setup default values for signals
-----------------------------------------------------------
cke_x <= YES; -- enable SDRAM clock
cmd_x <= NOP_CMD; -- set SDRAM command to no-operation
sDataDir_x <= INPUT; -- accept data from the SDRAM
sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM
state_x <= state_r; -- reload these registers and flags
activeFlag_x <= activeFlag_r; -- with their existing values
activeRow_x <= activeRow_r;
activeBank_x <= activeBank_r;
rfshCntr_x <= rfshCntr_r;
-----------------------------------------------------------
-- setup default value for the SDRAM address
-----------------------------------------------------------
-- extract bank field from host address
ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
bank <= ba_x;
bankIndex <= 0;
-- extract row, column fields from host address
row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
-- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
col <= (others => '0'); -- set it to all zeroes
col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0);
-- by default, set SDRAM address to the column address with interspersed
-- command bit set to disable auto-precharge
sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF
& col(CMDBIT_POS-1 downto 0);
-----------------------------------------------------------
-- manage the read and write operation pipelines
-----------------------------------------------------------
-- determine if read operations are in progress by the presence of
-- READ flags in the read pipeline
if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then
rdInProgress <= YES;
else
rdInProgress <= NO;
end if;
-- enter NOPs into the read and write pipeline shift registers by default
rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1);
wrPipeline_x(0) <= NOP;
-- transfer data from SDRAM to the host data register if a read flag has exited the pipeline
-- (the transfer occurs 1 cycle before we tell the host the read operation is done)
if rdPipeline_r(1) = READ then
-- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
hDOut_x <= sDIn(hDOut'range);
else
-- retain contents of host data registers if no data from the SDRAM has arrived yet
hDOut_x <= hDOut_r;
end if;
done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done
-----------------------------------------------------------
-- manage row activation
-----------------------------------------------------------
-- request a row activation operation if the row of the current address
-- does not match the currently active row in the bank, or if no row
-- in the bank is currently active
if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then
doActivate <= YES;
else
doActivate <= NO;
end if;
-----------------------------------------------------------
-- manage self-refresh
-----------------------------------------------------------
-- enter self-refresh if neither a read or write is requested for 10000 consecutive cycles.
if (rd = YES) or (wr = YES) then
-- any read or write resets NOP counter and exits self-refresh state
nopCntr_x <= 0;
doSelfRfsh <= NO;
elsif nopCntr_r /= 10000 then
-- increment NOP counter whenever there is no read or write operation
nopCntr_x <= nopCntr_r + 1;
doSelfRfsh <= NO;
else
-- start self-refresh when counter hits maximum NOP count and leave counter unchanged
nopCntr_x <= nopCntr_r;
doSelfRfsh <= YES;
end if;
-----------------------------------------------------------
-- update the timers
-----------------------------------------------------------
-- row activation timer
if rasTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the row activation is still inprogress
rasTimer_x <= rasTimer_r - 1;
activateInProgress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag
-- to indicate the row activation operation is done
rasTimer_x <= rasTimer_r;
activateInProgress <= NO;
end if;
-- write operation timer
if wrTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the write operation is still inprogress
wrTimer_x <= wrTimer_r - 1;
wrInPRogress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag that
-- indicates a write operation is in progress
wrTimer_x <= wrTimer_r;
wrInPRogress <= NO;
end if;
-- refresh timer
if refTimer_r /= 0 then
refTimer_x <= refTimer_r - 1;
else
-- on timeout, reload the timer with the interval between row refreshes
-- and increment the counter for the number of row refreshes that are needed
refTimer_x <= REF_CYCLES;
rfshCntr_x <= rfshCntr_r + 1;
end if;
-- main timer for sequencing SDRAM operations
if timer_r /= 0 then
-- decrement the timer and do nothing else since the previous operation has not completed yet.
timer_x <= timer_r - 1;
else
-- the previous operation has completed once the timer hits zero
timer_x <= timer_r; -- by default, leave the timer at zero
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
case state_r is
-----------------------------------------------------------
-- let clock stabilize and then wait for the SDRAM to initialize
-----------------------------------------------------------
when INITWAIT =>
-- wait for SDRAM power-on initialization once the clock is stable
timer_x <= INIT_CYCLES; -- set timer for initialization duration
state_x <= INITPCHG;
-----------------------------------------------------------
-- precharge all SDRAM banks after power-on initialization
-----------------------------------------------------------
when INITPCHG =>
cmd_x <= PCHG_CMD;
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for precharge operation duration
rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge
state_x <= INITRFSH;
-----------------------------------------------------------
-- refresh the SDRAM a number of times after initial precharge
-----------------------------------------------------------
when INITRFSH =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- set timer to refresh operation duration
rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter
if rfshCntr_r = 1 then
state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done
end if;
-----------------------------------------------------------
-- set the mode register of the SDRAM
-----------------------------------------------------------
when INITSETMODE =>
cmd_x <= MODE_CMD;
sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits
timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration
state_x <= RW;
-----------------------------------------------------------
-- process read/write/refresh operations after initialization is done
-----------------------------------------------------------
when RW =>
-----------------------------------------------------------
-- highest priority operation: row refresh
-- do a refresh operation if the refresh counter is non-zero
-----------------------------------------------------------
if rfshCntr_r /= 0 then
-- wait for any row activations, writes or reads to finish before doing a precharge
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= REFRESHROW; -- refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- do a host-initiated read operation
-----------------------------------------------------------
elsif rd = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current read is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- read from the currently active row if no previous read operation
-- is in progress or if pipeline reads are enabled
-- we can always initiate a read even if a write is already in progress
elsif (rdInProgress = NO) then
cmd_x <= READ_CMD; -- initiate a read of the SDRAM
-- insert a flag into the pipeline shift register that will exit the end
-- of the shift register when the data from the SDRAM is available
rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1);
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated write operation
-----------------------------------------------------------
elsif wr = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current write is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- write to the currently active row if no previous read operations are in progress
elsif rdInProgress = NO then
cmd_x <= WRITE_CMD; -- initiate the write operation
sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM
-- set timer so precharge doesn't occur too soon after write operation
wrTimer_x <= WR_CYCLES;
-- insert a flag into the 1-bit pipeline shift register that will exit on the
-- next cycle. The write into SDRAM is not actually done by that time, but
-- this doesn't matter to the host
wrPipeline_x(0) <= WRITE;
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated self-refresh operation
-----------------------------------------------------------
elsif doSelfRfsh = YES then
-- wait until all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- no operation
-----------------------------------------------------------
else
state_x <= RW; -- continue to look for SDRAM operations to execute
end if;
-----------------------------------------------------------
-- activate a row of the SDRAM
-----------------------------------------------------------
when ACTIVATE =>
cmd_x <= ACTIVE_CMD;
sAddr_x <= (others => '0'); -- output the address for the row to be activated
sAddr_x(row'range) <= row;
activeBank_x <= bank;
activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address
activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active
rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur
timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur
state_x <= RW; -- return to do read/write operation that initiated this activation
-----------------------------------------------------------
-- refresh a row of the SDRAM
-----------------------------------------------------------
when REFRESHROW =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- refresh operation interval
rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes
state_x <= RW; -- process more SDRAM operations after refresh is done
-----------------------------------------------------------
-- place the SDRAM into self-refresh and keep it there until further notice
-----------------------------------------------------------
when SELFREFRESH =>
if (doSelfRfsh = YES) then
-- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle
cke_x <= NO; -- disable the SDRAM clock
else
-- else exit self-refresh mode and start processing read and write operations
cke_x <= YES; -- restart the SDRAM clock
rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh
activeFlag_x <= (others => NO); -- self-refresh deactivates all rows
timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume
state_x <= RW;
end if;
-----------------------------------------------------------
-- unknown state
-----------------------------------------------------------
when others =>
state_x <= INITWAIT; -- reset state if in erroneous state
end case;
end if;
end process combinatorial;
-----------------------------------------------------------
-- update registers on the appropriate clock edge
-----------------------------------------------------------
update : process(clk_ok, clk)
begin
if clk_ok = NO then
-- asynchronous reset
state_r <= INITWAIT;
activeFlag_r <= (others => NO);
rfshCntr_r <= 0;
timer_r <= 0;
refTimer_r <= REF_CYCLES;
rasTimer_r <= 0;
wrTimer_r <= 0;
nopCntr_r <= 0;
rdPipeline_r <= (others => '0');
wrPipeline_r <= (others => '0');
cke_r <= NO;
cmd_r <= NOP_CMD;
ba_r <= (others => '0');
sAddr_r <= (others => '0');
sData_r <= (others => '0');
sDataDir_r <= INPUT;
hDOut_r <= (others => '0');
elsif rising_edge(clk) then
state_r <= state_x;
activeBank_r <= activeBank_x;
activeRow_r <= activeRow_x;
activeFlag_r <= activeFlag_x;
rfshCntr_r <= rfshCntr_x;
timer_r <= timer_x;
refTimer_r <= refTimer_x;
rasTimer_r <= rasTimer_x;
wrTimer_r <= wrTimer_x;
nopCntr_r <= nopCntr_x;
rdPipeline_r <= rdPipeline_x;
wrPipeline_r <= wrPipeline_x;
cke_r <= cke_x;
cmd_r <= cmd_x;
ba_r <= ba_x;
sAddr_r <= sAddr_x;
sData_r <= sData_x;
sDataDir_r <= sDataDir_x;
hDOut_r <= hDOut_x;
end if;
end process update;
end arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lz4_pkg.all;
entity lz4_entryDict is
generic (
constant FIFO_DEPTH : positive := 1000 -- 1 KB fifo
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryBytes_i : in std_logic_vector(7 downto 0);
litLength_o : out std_logic_vector(9 downto 0);
offset_o : out std_logic_vector(9 downto 0);
matchLength_o : out std_logic_vector(9 downto 0);
internalStream_o : out std_logic_vector(7 downto 0)
);
end lz4_entryDict;
architecture behavior of lz4_entryDict is
-- buffer for the part that will be streamed to the assembly module
type out_memory is array (0 to FIFO_DEPTH -1) of std_logic_vector (7 downto 0);
signal outputBuffer : out_memory;
-- fifo memory
type fifo_memory is array (0 to FIFO_DEPTH -1) of std_logic_vector (7 downto 0);
signal memory : fifo_memory;
-- FSM
type States is (Beginning, Match, NoMatch, NoMoreMatch, Ending);
signal currentstate, nextstate: States;
-- store the pointers
signal dict_d_s : std_logic_vector(9 downto 0);
signal dict_u_s : std_logic_vector(9 downto 0);
signal ut_d_s : std_logic_vector(9 downto 0);
signal ut_u_s : std_logic_vector(9 downto 0);
signal output_p : integer range 0 to FIFO_DEPTH -1 := 0;
begin
-- ##################################################
-- synchronous process
process (clk_i, reset_i)
begin
-- Reset
if (reset_i = '1') then
currentstate <= Beginning;
elsif clk_i'event then
-- State update
currentstate <= nextstate;
end if;
end process;
-- ##################################################
-- output memory management process
process
variable readout_p : integer range 0 to FIFO_DEPTH-1 := 0;
begin
if outputBuffer(readout_p) /= "UUUUUUUU" then
internalStream_o <= outputBuffer(readout_p);
readout_p := readout_p + 1;
end if;
wait for 4*clk_period;
end process;
-- ##################################################
-- fifo process
process (currentstate, entryBytes_i, clk_i)
-- pointers
variable wr_p : integer range 0 to FIFO_DEPTH-1 := 0; -- write entry
variable rd_p : integer range 0 to FIFO_DEPTH-1 := 0; -- read output
variable dict_d_p : integer range 0 to FIFO_DEPTH-1 := 0;
variable dict_u_p : integer range 0 to FIFO_DEPTH-1 := 0;
variable ut_d_p : integer range 0 to FIFO_DEPTH-1 := 0;
variable ut_u_p : integer range 0 to FIFO_DEPTH-1 := 0;
-- previous value of the entry byte
variable previousB : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------------
begin
-- write the entry byte in the fifo
-- [[ BAD!! ]]: skips if two simlar bytes following...
if entryBytes_i /= previousB and entryBytes_i /= "UUUUUUUU" then
memory(wr_p) <= entryBytes_i;
wr_p := wr_p + 1;
previousB := entryBytes_i;
end if;
if rising_edge(clk_i) then
-- beginning of the FSM
case currentstate is
when Beginning =>
-- wait for a minimal numbre of values in the fifo
if wr_p >= 20 then
-- start position of the pointer couples
dict_u_p := 0;
dict_d_p := 3;
ut_u_p := 4;
ut_d_p := 7;
-- check of a minmatch (4 bytes of match)
if memory(ut_u_p) = memory(dict_u_p) and
memory(ut_d_p-2) = memory(dict_d_p-2) and
memory(ut_d_p-1) = memory(dict_d_p-1) and
memory(ut_d_p) = memory(dict_d_p) then
nextstate <= Match;
else
nextstate <= NoMatch;
end if;
else
if entryBytes_i = "UUUUUUUU" and wr_p > 1 then
nextstate <= Ending;
else
nextstate <= Beginning;
end if;
end if;
-- ************
-- NoMatch state
when NoMatch =>
-- report "write pointer = " & integer'image(wr_p);
-- report "under test pointer: up/down = " & integer'image(ut_u_p) & "/" & integer'image(ut_d_p);
-- report "dictionary pointer: up/down = " & integer'image(dict_u_p) & "/" & integer'image(dict_d_p);
-- tests if the pointer read the last written value
if ut_d_p <= wr_p then
-- test for a new minmatch
if memory(ut_u_p) = memory(dict_u_p) and
memory(ut_d_p-2) = memory(dict_d_p-2) and
memory(ut_d_p-1) = memory(dict_d_p-1) and
memory(ut_d_p) = memory(dict_d_p) then
dict_u_s <= std_logic_vector(to_unsigned(dict_u_p, 10));
dict_d_s <= std_logic_vector(to_unsigned(dict_d_p, 10));
ut_u_s <= std_logic_vector(to_unsigned(ut_u_p, 10));
ut_d_s <= std_logic_vector(to_unsigned(ut_d_p, 10));
nextstate <= Match;
else
-- move the "ut" pointers one byte down
ut_u_p := ut_u_p + 1;
ut_d_p := ut_d_p + 1;
nextstate <= NoMatch;
end if;
elsif dict_d_p <= wr_p + 5 then
-- test for a new minmatch
if memory(ut_u_p) = memory(dict_u_p) and
memory(ut_d_p-2) = memory(dict_d_p-2) and
memory(ut_d_p-1) = memory(dict_d_p-1) and
memory(ut_d_p) = memory(dict_d_p) then
nextstate <= Match;
else
nextstate <= NoMatch;
end if;
-- same position as in beginning
-- but 1 byte after
dict_u_p := dict_u_p + 1;
dict_d_p := dict_d_p + 1;
ut_u_p := dict_d_p + 1;
ut_d_p := dict_d_p + 4;
else
nextstate <= Ending;
end if;
-- ************
-- Match state
when Match =>
if memory(to_integer(unsigned(ut_d_s)) ) = memory(to_integer(unsigned(dict_d_s)) ) then
--enlarge the space between the couples of pointers
ut_d_p := ut_d_p + 1;
dict_d_p := dict_d_p + 1;
dict_u_s <= std_logic_vector(to_unsigned(dict_u_p, 10));
dict_d_s <= std_logic_vector(to_unsigned(dict_d_p, 10));
ut_u_s <= std_logic_vector(to_unsigned(ut_u_p, 10));
ut_d_s <= std_logic_vector(to_unsigned(ut_d_p, 10));
nextstate <= Match;
else
nextstate <= NoMoreMatch;
end if;
-- ************
-- NoMoreMatch state
when NoMoreMatch =>
litLength_o <= ut_u_s;
offset_o <= std_logic_vector(unsigned(ut_u_s) - unsigned(dict_u_s) );
matchLength_o <= std_logic_vector(unsigned(ut_d_s) - unsigned(ut_u_s));
-- stream out the literal in the output buffer
for i in 0 to to_integer(unsigned(ut_u_s)) - 1 loop
outputBuffer(i+output_p) <= memory(i);
end loop;
output_p <= to_integer(unsigned(ut_u_s));
-- move the uncheck part in the beginning of the fifo
for i in to_integer(unsigned(ut_d_s)) to wr_p-1 loop
memory(i - to_integer(unsigned(ut_d_s))) <= memory(i);
end loop;
-- jump te write pointer backward to the end of the already written part
wr_p := wr_p - to_integer(unsigned(ut_d_s));
nextstate <= Beginning;
-- ************
-- Ending state
when Ending =>
-- stream out the literal in the output buffer
for i in 0 to wr_p - 1 loop
outputBuffer(i+output_p) <= memory(i);
end loop;
output_p <= wr_p -1;
-- loop in there until the end once the file is completely compressed
nextstate <= Ending;
end case;
end if;
end process;
end;
|
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := CONFIG_MIG_7SERIES;
constant CFG_MIG_7SERIES_MODEL : integer := CONFIG_MIG_7SERIES_MODEL;
|
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := CONFIG_MIG_7SERIES;
constant CFG_MIG_7SERIES_MODEL : integer := CONFIG_MIG_7SERIES_MODEL;
|
-- rgb_mux.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils_v1_00_a;
use utils_v1_00_a.ipif_reg;
use utils_v1_00_a.ipif_reg_logic;
---
-- Multiplexor on RGB bus. Allows to switch between 2 input
-- RGB branches. The switch command is performed over IPIF
-- interface (usually from a processor core).
---
entity rgb_mux is
generic (
IPIF_AWIDTH : integer := 32;
IPIF_DWIDTH : integer := 32;
DEFAULT_SRC : integer := 0
);
port (
CLK : in std_logic;
CE : in std_logic;
RST : in std_logic;
Bus2IP_Addr : in std_logic_vector(IPIF_AWIDTH - 1 downto 0);
Bus2IP_CS : in std_logic_vector(0 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(IPIF_DWIDTH - 1 downto 0);
Bus2IP_BE : in std_logic_vector(IPIF_DWIDTH/8 - 1 downto 0);
IP2Bus_Data : out std_logic_vector(IPIF_DWIDTH - 1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IN0_R : in std_logic_vector(7 downto 0);
IN0_G : in std_logic_vector(7 downto 0);
IN0_B : in std_logic_vector(7 downto 0);
IN0_DE : in std_logic;
IN0_HS : in std_logic;
IN0_VS : in std_logic;
IN1_R : in std_logic_vector(7 downto 0);
IN1_G : in std_logic_vector(7 downto 0);
IN1_B : in std_logic_vector(7 downto 0);
IN1_DE : in std_logic;
IN1_HS : in std_logic;
IN1_VS : in std_logic;
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
---
-- Branch switch is performed only during vertical pulse.
-- It first waits for the pulse of current line and then
-- waits (generating pulse) for a pulse of the target line.
-- Thus the change can drive the output screen black for a while.
--
-- Address space:
-- <address> <access> <description> <width> <default>
-- 0x00000000 RO device type id 16b 1
-- 0x00000004 RW select of line 1b generic DEFAULT_SRC
-- * Reading from the register obtains current state.
-- Thus after a write the new value can not usually be
-- read immediately. The delay can be about one frame.
-- * Changing of line can not be cancelled. When another value
-- is written durning the lines change and it is different
-- from the new one another transition will occur.
---
architecture full of rgb_mux is
type state_t is (s_src0, s_src1, s_sync0_to_1, s_0_to_sync1, s_sync1_to_0, s_1_to_sync0);
signal state : state_t;
signal nstate : state_t;
signal sync0 : std_logic;
signal sync1 : std_logic;
signal pulse_start0 : std_logic;
signal pulse_start1 : std_logic;
signal src_sel_be : std_logic;
signal src_sel_we : std_logic;
signal src_sel_in : std_logic;
signal src_sel : std_logic;
signal cur_sel : std_logic;
signal reg_r : std_logic_vector(7 downto 0);
signal reg_g : std_logic_vector(7 downto 0);
signal reg_b : std_logic_vector(7 downto 0);
signal reg_de : std_logic;
signal reg_hs : std_logic;
signal reg_vs : std_logic;
signal ipif_cs : std_logic_vector(1 downto 0);
signal ipif_data : std_logic_vector(63 downto 0);
signal ipif_wrack : std_logic_vector(1 downto 0);
signal ipif_rdack : std_logic_vector(1 downto 0);
signal ipif_error : std_logic_vector(1 downto 0);
signal ipif_gerror : std_logic;
signal ipif_werror : std_logic;
signal ipif_rerror : std_logic;
begin
---
-- Device ID register
---
reg_id : entity utils_v1_00_a.ipif_reg
generic map (
REG_DWIDTH => 16,
REG_DEFAULT => X"0001",
IPIF_DWIDTH => IPIF_DWIDTH,
IPIF_MODE => 0
)
port map (
CLK => CLK,
RST => RST,
IP2Bus_Data => ipif_data(31 downto 0),
IP2Bus_WrAck => ipif_wrack(0),
IP2Bus_RdAck => ipif_rdack(0),
IP2Bus_Error => ipif_error(0),
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_CS => ipif_cs(0),
REG_DI => (15 downto 0 => 'X'),
REG_WE => '0'
);
---
-- MUX select register
---
cfg_sel : entity utils_v1_00_a.ipif_reg_logic
generic map (
REG_DWIDTH => 1,
IPIF_DWIDTH => IPIF_DWIDTH,
IPIF_MODE => 2
)
port map (
CLK => CLK,
RST => RST,
IP2Bus_Data => ipif_data(63 downto 32),
IP2Bus_WrAck => ipif_wrack(1),
IP2Bus_RdAck => ipif_rdack(1),
IP2Bus_Error => ipif_error(1),
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_CS => ipif_cs(1),
REG_DO(0) => cur_sel,
REG_BE(0) => src_sel_be,
REG_DI(0) => src_sel_in,
REG_WE => src_sel_we
);
src_selp : process(CLK, RST, src_sel_we, src_sel_be, src_sel_in)
begin
if rising_edge(CLK) then
if RST = '1' then
if DEFAULT_SRC = 0 then
src_sel <= '0';
else
src_sel <= '1';
end if;
elsif src_sel_we = '1' and src_sel_be = '1' then
src_sel <= src_sel_in;
end if;
end if;
end process;
---
-- IPIF address logic
---
ipif_cs(0) <= Bus2IP_CS(0) when Bus2IP_Addr = X"00000000" else '0';
ipif_cs(1) <= Bus2IP_CS(0) when Bus2IP_Addr = X"00000004" else '0';
-- invalid address request
ipif_gerror <= Bus2IP_CS(0) when ipif_cs = "00" else '0';
IP2Bus_Data <= ipif_data(63 downto 32) when ipif_cs = "10" else
ipif_data(31 downto 0);
ipif_werror <= ipif_gerror when Bus2IP_CS(0) = '1' and Bus2IP_RNW = '0' else '0';
ipif_rerror <= ipif_gerror when Bus2IP_CS(0) = '1' and Bus2IP_RNW = '1' else '0';
IP2Bus_WrAck <= ipif_wrack(0) or ipif_wrack(1) or ipif_werror;
IP2Bus_RdAck <= ipif_rdack(0) or ipif_rdack(1) or ipif_rerror;
IP2Bus_Error <= ipif_error(0) or ipif_error(1) or ipif_gerror;
----------------------------------
sync0 <= IN0_HS or IN0_VS;
sync1 <= IN1_HS or IN1_VS;
----------------------------------
detect_start_of_pulse0 : entity work.detect_start_of_pulse
port map (
CLK => CLK,
RST => RST,
SYNC => sync0,
SOP => pulse_start0
);
detect_start_of_pulse1 : entity work.detect_start_of_pulse
port map (
CLK => CLK,
RST => RST,
SYNC => sync1,
SOP => pulse_start1
);
----------------------------------
fsm_state : process(CLK, RST, nstate)
begin
if rising_edge(CLK) then
if RST = '1' then
if DEFAULT_SRC = 0 then
state <= s_src0;
else
state <= s_src1;
end if;
else
state <= nstate;
end if;
end if;
end process;
fsm_next : process(CLK, state, src_sel, IN0_HS, IN0_VS, IN1_HS, IN1_VS)
begin
nstate <= state;
case state is
when s_src0 =>
if src_sel = '1' and IN0_HS = '0' and IN0_VS = '0' and pulse_start1 = '1' then
nstate <= s_src1;
elsif src_sel = '1' and IN0_HS = '0' and IN0_VS = '0' then
nstate <= s_0_to_sync1;
elsif src_sel = '1' then
nstate <= s_sync0_to_1;
end if;
when s_sync0_to_1 =>
if IN0_HS = '0' and IN0_VS = '0' then
nstate <= s_0_to_sync1;
end if;
when s_0_to_sync1 =>
if pulse_start1 = '1' then
nstate <= s_src1;
end if;
when s_src1 =>
if src_sel = '0' and IN1_HS = '0' and IN1_VS = '0' and pulse_start0 = '1' then
nstate <= s_src0;
elsif src_sel = '0' and IN1_HS = '0' and IN1_VS = '0' then
nstate <= s_1_to_sync0;
elsif src_sel = '0' then
nstate <= s_sync1_to_0;
end if;
when s_sync1_to_0 =>
if IN1_HS = '0' and IN1_VS = '0' then
nstate <= s_1_to_sync0;
end if;
when s_1_to_sync0 =>
if pulse_start0 = '1' then
nstate <= s_src0;
end if;
end case;
end process;
fsm_output : process(CLK, state)
begin
case state is
when s_src0 | s_sync0_to_1 =>
cur_sel <= '0';
when s_0_to_sync1 =>
cur_sel <= '0';
when s_src1 | s_sync1_to_0 =>
cur_sel <= '1';
when s_1_to_sync0 =>
cur_sel <= '1';
end case;
end process;
---------------------------------
reg_r <= IN0_R when cur_sel = '0' else
IN1_R;
reg_g <= IN0_G when cur_sel = '0' else
IN1_G;
reg_b <= IN0_B when cur_sel = '0' else
IN1_B;
reg_de <= IN0_DE when cur_sel = '0' else
IN1_DE;
reg_hs <= IN0_HS when cur_sel = '0' else
IN1_HS;
reg_vs <= IN0_VS when cur_sel = '0' else
IN1_VS;
regp : process(CLK, CE, reg_r, reg_g, reg_b, reg_de, reg_hs, reg_vs)
begin
if rising_edge(CLK) then
if CE = '1' then
OUT_R <= reg_r;
OUT_G <= reg_g;
OUT_B <= reg_b;
OUT_DE <= reg_de;
OUT_HS <= reg_hs;
OUT_VS <= reg_vs;
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memctrl is
Port (
CLK : in std_logic;
RESET : in std_logic;
MEM_A : in std_logic_vector(19 downto 0);
MEM_DI : in std_logic_vector(7 downto 0);
MEM_DO : out std_logic_vector(7 downto 0);
MEM_RW : in std_logic;
MEM_REQ : in std_logic;
MEM_ACK : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
SRAM_OE : out std_logic;
SRAM_WE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic );
end memctrl;
architecture Behavioral of memctrl is
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
-- STATEMACHINE
type STATE_TYPE is (IDLE, READ1, WRITE1, WRITE2, DONE);
signal STATE : STATE_TYPE := IDLE;
begin
SRAM_D <= SRAM_DI;
SRAM_DO <= SRAM_D;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
SRAM_A <= (others=>'0');
SRAM_DI <= (others=>'Z');
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
SRAM_WE <= '1';
SRAM_UB <= '1';
SRAM_LB <= '1';
MEM_DO <= "11111111";
MEM_ACK <= '0';
else
MEM_ACK <= '0';
case STATE is
when IDLE =>
if MEM_REQ = '1' then
SRAM_A <= MEM_A(18 downto 1);
if MEM_A(19) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if MEM_A(0) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
if MEM_RW = '0' then
SRAM_OE <= '0';
STATE <= READ1;
else
SRAM_DI <= MEM_DI & MEM_DI;
SRAM_WE <= '0';
STATE <= WRITE1;
end if;
end if;
when READ1 =>
if MEM_A(0) = '0' then
MEM_DO <= SRAM_DO(7 downto 0);
else
MEM_DO <= SRAM_DO(15 downto 8);
end if;
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_OE <= '1';
MEM_ACK <= '1';
STATE <= DONE;
when WRITE1 =>
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_WE <= '1';
STATE <= WRITE2;
when WRITE2 =>
SRAM_DI <= (others=>'Z');
MEM_ACK <= '1';
STATE <= DONE;
when DONE =>
STATE <= IDLE;
when others =>
STATE <= IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RD_DATA_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Altera Cyclone flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture cyclone of t400_por is
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
-- pragma translate_off
-- initialize for simulation only
:= (others => '0')
-- pragma translate_on
;
signal por_n_q : std_logic
-- pragma translate_off
-- initialize for simulation only
:= '0'
-- pragma translate_on
;
-- Specify power-up level of por counter and por source.
-- Refer to "Quartus II Integrated Synthesis", section "Altera Attribute".
attribute altera_attribute : string;
attribute altera_attribute of por_cnt_q : signal is "-name POWER_UP_LEVEL LOW";
attribute altera_attribute of por_n_q : signal is "-name POWER_UP_LEVEL LOW";
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specifiec number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = delay_g-1 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q + 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end cyclone;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
--##############################################################################
-- mcu80_mcu : light8080-based Micro Controller Unit
--##############################################################################
-- This MCU is meant as an usage example for the light8080 core. The code shows
-- how to interface the core to internal BRAM and other modules.
-- This module is not meant to be used in real applications though it can be
-- used as the starting point for one.
--
-- Please see the comments below for usage instructions.
-- Please see the LICENSE file in the project root for license matters.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu80_pkg.all;
--##############################################################################
-- Interface pins:
------------------
-- p1_i : Input port P1.
-- p2_o : Output port P2.
-- rxd_i : UART RxD pin.
-- txd_o : UART TxD pin.
-- extint_i : External interrupt inputs, wired straight to the irq controller.
-- EXCEPT for the one used by the UART -- see generic UART_IRQ_LINE.
-- clk : Master clock, rising edge active.
-- reset : Synchronous reset, 1 cycle active to reset all SoC.
--
--------------------------------------------------------------------------------
-- Generics:
------------
-- OBJ_CODE (mandatory, no default value):
-- Table that will be used to initialize internal BRAM, starting at address 0.
--
-- DEFAULT_RAM_SIZE (default = 0):
-- Internal RAM size. If set to zero, the RAM size will be determined from the
-- size of OBJ_CODE as the smallest power of 2 larger than OBJ_CODE'length.
--
-- UART_IRQ_LINE (defaults to 4):
-- Index of the irq controller input the internal UART is wired to, or >3 to
-- leave the UART unconnected to the IRQ controller.
-- The irq controller input used for the uart will be unconnected to the SoC
-- input port.
--
-- UART_HARDWIRED (defaults to true):
-- True when the UART baud rate is hardwired. the baud rate registers will be
--
-- BAUD_RATE (defaults to 19200):
-- UART default baud rate. When th UART is hardwired, the baud rate can't be
-- changed at run time.
-- Note that you have to set generic z. This value is needed to compute the
-- UART baud rate constants.
--
-- SIMULATION (Defaults to False):
-- When True, a number of internal signals are connected to global package
-- signals.
-- This gives the TB access to those signals without using VHDL2008 features
-- (not yet supported in GHDL) or equivalent proprietary schemes.
-- Set it to True in the TB, ignore it otherwise.
--------------------------------------------------------------------------------
-- I/O port map:
----------------
--
-- 080h..083h UART registers.
-- 084h P1 input port (read only, writes are ignored).
-- 086h P2 output port (write only, reads undefined data).
-- 088h IRQ enable register.
--
-- Please see the comments in the source of the relevant modules for a more
-- detailed explanation of their behavior.
--
-- All i/o ports other than the above read as 00h.
--------------------------------------------------------------------------------
-- Notes:
---------
-- -# If you do not set a default memory size, you then have to take care to
-- control the size of the object code table.
-- -# If you do set the default memory size, the code will not warn you if the
-- object code does not fit inside, it will silentl truncate it.
-- -# The internal memory block is mirrored over the entire address map.
-- -# There is no write protection to any address range: you can overwrite the
-- program. If you do that there's no way to recover it but reloading the
-- FPGA, a reset will not do.
--##############################################################################
entity mcu80 is
generic (
OBJ_CODE : obj_code_t; -- RAM initialization constant
DEFAULT_RAM_SIZE: integer := 0; -- RAM size or 0 to stretch
UART_IRQ_LINE : integer := 4; -- [0..3] or >3 for none
UART_HARDWIRED: boolean := true; -- UART baud rate is hardwired
BAUD_RATE : integer := 19200; -- UART (default) baud rate
CLOCK_FREQ : integer := 50E6; -- Clock frequency in Hz
SIMULATION : boolean := False -- True when instantiated in TB
);
port (
p1_i : in std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
rxd_i : in std_logic;
txd_o : out std_logic;
extint_i : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic
);
end mcu80;
--##############################################################################
--
--##############################################################################
architecture hardwired of mcu80 is
-- Helper functions ------------------------------------------------------------
-- soc_ram_size: compute size of internal RAM
-- If default_size is /= 0, the size is the default. If it is zero, then the
-- size the smallest power of 2 larger than obj_code_size.
function soc_ram_size(default_size, obj_code_size: integer) return integer is
begin
if default_size=0 then
-- Default is zero: use a RAM as big as necessary for the obj code table
-- rounding to the neares power of 2.
return 2**log2(obj_code_size);
else
-- Default is not zero: use the default and do NOT check to see if the
-- object code fits.
return default_size;
end if;
end function soc_ram_size;
-- Custom types ----------------------------------------------------------------
subtype t_byte is std_logic_vector(7 downto 0);
subtype io_addr_t is unsigned(7 downto 0);
-- CPU signals -----------------------------------------------------------------
signal cpu_vma : std_logic;
signal cpu_rd : std_logic;
signal cpu_wr : std_logic;
signal cpu_io : std_logic;
signal cpu_fetch : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_i : std_logic_vector(7 downto 0);
signal cpu_data_o : std_logic_vector(7 downto 0);
signal cpu_intr : std_logic;
signal cpu_inte : std_logic;
signal cpu_inta : std_logic;
signal cpu_halt : std_logic;
-- Aux CPU signals -------------------------------------------------------------
-- io_wr: asserted in IO write cycles
signal io_wr : std_logic;
-- io_rd: asserted in IO read cycles
signal io_rd : std_logic;
-- io_addr: IO port address, lowest 8 bits of address bus
signal io_addr : unsigned(7 downto 0);
-- io_rd_data: data coming from IO ports (io input mux)
signal io_rd_data : std_logic_vector(7 downto 0);
-- cpu_io_reg: registered cpu_io, used to control mux after cpu_io deasserts
signal cpu_io_reg : std_logic;
-- UART ------------------------------------------------------------------------
signal uart_ce : std_logic;
signal uart_data_rd : std_logic_vector(7 downto 0);
signal uart_irq : std_logic;
-- RAM -------------------------------------------------------------------------
constant RAM_SIZE : integer := soc_ram_size(DEFAULT_RAM_SIZE,OBJ_CODE'length);
constant RAM_ADDR_SIZE : integer := log2(RAM_SIZE);
signal ram_rd_data : std_logic_vector(7 downto 0);
signal ram_we : std_logic;
signal ram : ram_t(0 to RAM_SIZE-1) := objcode_to_bram(OBJ_CODE, RAM_SIZE);
signal ram_addr : unsigned(RAM_ADDR_SIZE-1 downto 0);
-- IRQ controller interface ----------------------------------------------------
signal irqcon_we : std_logic;
signal irqcon_data_rd: std_logic_vector(7 downto 0);
signal irq : std_logic_vector(3 downto 0);
-- IO ports addresses ----------------------------------------------------------
constant ADDR_UART_0 : io_addr_t := X"80"; -- UART registers (80h..83h)
constant ADDR_UART_1 : io_addr_t := X"81"; -- UART registers (80h..83h)
constant ADDR_UART_2 : io_addr_t := X"82"; -- UART registers (80h..83h)
constant ADDR_UART_3 : io_addr_t := X"83"; -- UART registers (80h..83h)
constant P1_DATA_REG : io_addr_t := X"84"; -- port 1 data register
constant P2_DATA_REG : io_addr_t := X"86"; -- port 2 data register
constant INTR_EN_REG : io_addr_t := X"88"; -- interrupts enable register
begin
cpu: entity work.light8080
port map (
clk => clk,
reset => reset,
vma => cpu_vma,
rd => cpu_rd,
wr => cpu_wr,
io => cpu_io,
fetch => cpu_fetch,
addr_out => cpu_addr,
data_in => cpu_data_i,
data_out => cpu_data_o,
intr => cpu_intr,
inte => cpu_inte,
inta => cpu_inta,
halt => cpu_halt
);
io_rd <= cpu_io and cpu_rd;
io_wr <= '1' when cpu_io='1' and cpu_wr='1' else '0';
io_addr <= unsigned(cpu_addr(7 downto 0));
-- Register some control signals that are needed to control multiplexors the
-- cycle after the control signal asserts -- e.g. cpu_io.
control_signal_registers:
process(clk)
begin
if clk'event and clk='1' then
cpu_io_reg <= cpu_io;
end if;
end process control_signal_registers;
-- Input data mux -- remember, no 3-state buses within the FPGA --------------
cpu_data_i <=
irqcon_data_rd when cpu_inta = '1' else
io_rd_data when cpu_io_reg = '1' else
ram_rd_data;
-- BRAM ----------------------------------------------------------------------
ram_we <= '1' when cpu_io='0' and cpu_wr='1' else '0';
ram_addr <= unsigned(cpu_addr(RAM_ADDR_SIZE-1 downto 0));
memory:
process(clk)
begin
if clk'event and clk='1' then
if ram_we = '1' then
ram(to_integer(ram_addr)) <= cpu_data_o;
end if;
ram_rd_data <= ram(to_integer(ram_addr));
end if;
end process memory;
-- Interrupt controller ------------------------------------------------------
-- FIXME interrupts unused in this version
irq_control: entity work.mcu80_irq
port map (
clk => clk,
reset => reset,
irq_i => irq,
data_i => cpu_data_o,
data_o => irqcon_data_rd,
addr_i => cpu_addr(0),
data_we_i => irqcon_we,
cpu_inta_i => cpu_inta,
cpu_intr_o => cpu_intr,
cpu_fetch_i => cpu_fetch
);
irq_line_connections:
for i in 0 to 3 generate
begin
uart_irq_connection:
if i = UART_IRQ_LINE generate
begin
irq(i) <= uart_irq or extint_i(i);
end generate;
other_irq_connections:
if i /= UART_IRQ_LINE generate
irq(i) <= extint_i(i);
end generate;
end generate irq_line_connections;
irqcon_we <= '1' when io_addr=INTR_EN_REG and io_wr='1' else '0';
-- UART -- simple UART with hardwired baud rate ------------------------------
-- NOTE: the serial port does NOT have interrupt capability (yet)
uart : entity work.mcu80_uart
generic map (
BAUD_RATE => BAUD_RATE,
CLOCK_FREQ => CLOCK_FREQ
)
port map (
clk_i => clk,
reset_i => reset,
irq_o => uart_irq,
data_i => cpu_data_o,
data_o => uart_data_rd,
addr_i => cpu_addr(1 downto 0),
ce_i => uart_ce,
wr_i => io_wr,
rd_i => io_rd,
rxd_i => rxd_i,
txd_o => txd_o
);
-- UART write enable
uart_ce <= '1' when
io_addr(7 downto 2) = ADDR_UART_0(7 downto 2)
else '0';
-- IO ports -- Simple IO ports with hardcoded direction ----------------------
-- These are meant as an usage example mostly
output_ports:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- Reset values for all io ports
p2_o <= (others => '0');
else
if io_wr = '1' then
if to_integer(io_addr) = P2_DATA_REG then
p2_o <= cpu_data_o;
end if;
end if;
end if;
end if;
end process output_ports;
-- Input IO data multiplexor
with io_addr select io_rd_data <=
p1_i when P1_DATA_REG,
uart_data_rd when ADDR_UART_0,
uart_data_rd when ADDR_UART_1,
uart_data_rd when ADDR_UART_2,
uart_data_rd when ADDR_UART_3,
irqcon_data_rd when INTR_EN_REG,
X"00" when others;
-- Simulation support ------------------------------------------------------
Internal_signal_extraction:
if SIMULATION generate
-- 'Connect' all the internal signals we want to watch to members of
-- the info record.
-- This does not require VHDL 2008 support or proprietary tricks.
mon_addr <= cpu_addr;
mon_fetch <= cpu_fetch;
mon_wdata <= cpu_data_o;
mon_we <= cpu_wr;
mon_uart_ce <= uart_ce;
end generate Internal_signal_extraction;
end hardwired;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function calcualtes a observation for a particle
-- A pointer to the input data is given. The user process can
-- ask for data at a specific address.
--
-- Thus, all needed data can be loaded into the entity. Thus,
-- the observation can be calculated via input data. When no more
-- data is needed, the observation is stored into the local ram.
--
-- If the observation is stored in the ram, the finished signal has
-- to be set to '1'.
--
------------------------------------------------------------------------------------
entity uf_extract_observation is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input/measurement data address
input_data_address : in std_logic_vector(0 to 31);
-- get data block
get_data_needed : out std_logic;
get_data_address : out std_logic_vector(0 to 31);
get_data_length : out integer;
-- receive data block
receive_data_en : in std_logic;
receive_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- recieved data
receive_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end uf_extract_observation;
architecture Behavioral of uf_extract_observation is
component pipelined_divider
port (
clk: in std_logic;
ce: in std_logic;
aclr: in std_logic;
sclr: in std_logic;
dividend: in std_logic_VECTOR(31 downto 0);
divisor: in std_logic_VECTOR(31 downto 0);
quot: out std_logic_VECTOR(31 downto 0);
remd: out std_logic_VECTOR(31 downto 0);
rfd: out std_logic);
end component;
type hsv_function is array ( 0 to 255) of integer;
-- GRANULARITY
constant GRAN_EXP : integer := 14;
constant GRANULARITY : integer := 2**GRAN_EXP;
constant hd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9);
constant sdvd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9);
-- states
type t_state is (STATE_INIT, STATE_READ_PARAMETER, STATE_INIT_HISTOGRAM,
STATE_READ_PARTICLE, STATE_ANALYZE_PARTICLE,
STATE_CALCULATE_HISTOGRAM, STATE_NORMALIZE_HISTOGRAM,
STATE_COPY_HISTOGRAM, STATE_FINISH);
signal state : t_state;
-----------------------------------------------------
-- signals needed for divider component
-----------------------------------------------------
-- clock enable
signal ce : std_logic;
-- synchronous clear
signal sclr : std_logic := '0';
-- asynchronous clear
signal aclr : std_logic := '0';
-- dividend
signal dividend : std_logic_vector(31 downto 0) := (others => '0');
-- divisor
signal divisor : std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
-- quotient
signal quotient : std_logic_vector(31 downto 0) := (others => '0');
-- remainder
signal remainder : std_logic_vector(31 downto 0) := (others => '0');
-- ready for data
signal rfd : std_logic;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- HSV signals
signal H : std_logic_vector(0 to 7) := (others => '0');
signal S : std_logic_vector(0 to 7) := (others => '0');
signal V : std_logic_vector(0 to 7) := (others => '0');
constant S_THRESH : integer := 25;
constant V_THRESH : integer := 50;
signal hd : natural range 0 to 9 := 0;
signal sd : natural range 0 to 9 := 0;
signal vd : natural range 0 to 9 := 0;
signal value : natural := 0;
-- copy histogram
signal copy_histo_en : std_logic := '0'; -- handshake signal
signal copy_histo_done : std_logic := '0'; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
signal copy_histo_data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- update histogram
signal update_histo_en : std_logic := '0'; -- handshake signal
signal update_histo_done : std_logic := '0'; -- handshake signal
signal update_histo_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
-- calculate histogram
signal calculate_histo_en : std_logic := '0'; -- handshake signal
signal calculate_histo_done : std_logic := '0'; -- handshake signal
-- clear histogram
signal clear_histo_en : std_logic := '0'; -- handshake signal
signal clear_histo_done : std_logic := '0'; -- handshake signal
signal clear_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- normalize histogram
signal normalize_histo_en : std_logic := '0'; -- handshake signal
signal normalize_histo_done : std_logic := '0'; -- handshake signal
signal normalize_histo : std_logic := '0'; -- set histo_ram value
signal normalize_histo_value : std_logic_vector(31 downto 0) := (others=>'0'); -- new normalized histo value
signal normalize_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- read particle data
signal read_particle_en : std_logic := '0'; -- handshake signal
signal read_particle_done : std_logic := '0'; -- handshake signal
signal read_particle_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- read parameter
signal read_parameter_en : std_logic := '0'; -- handshake signal
signal read_parameter_done : std_logic := '0'; -- handshake signal
signal read_parameter_addr : std_logic_vector(C_TASK_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- analyze particle
signal analyze_particle_en : std_logic := '0'; -- handshake signal
signal analyze_particle_done : std_logic := '0'; -- handshake signal
-- prefetch line
signal prefetch_line_en : std_logic := '0'; -- handshake signal
signal prefetch_line_done : std_logic := '0'; -- handshake signal
signal prefetch_line_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- histogram
type t_ram is array (109 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(6 downto 0); -- current histogram bucket
signal histo_inc : std_logic := '0'; -- enables incrementing
signal histo_clear : std_logic := '0'; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal scale : integer := 0;
signal width : integer := 0;
signal height : integer := 0;
-- input data
-- left upper corner
signal x1 : integer := 0;
signal y1 : integer := 0;
-- right bottom corner
signal x2 : integer := 0;
signal y2 : integer := 2;
-- current pixel
signal px : integer := 0;
signal py : integer := 0;
-- frame values
signal size_x : integer := 480;
signal size_y : integer := 360;
-- temporary signals
signal temp_x : integer := 0;
signal temp_y : integer := 0;
signal temp : integer := 0;
-- input data offset
signal get_data_offset : integer := 0;
-- number of lines
signal number_of_lines : integer := 0;
-- length of line
signal line_length : integer := 0;
-- sum of histogram
signal sum : integer := 0;
-- signal for counter
signal i : integer := 0;
signal j : integer := 0;
begin
divider : pipelined_divider
port map ( clk => clk, ce => ce, aclr => aclr, sclr => sclr, dividend => dividend,
divisor => divisor, quot => quotient, remd => remainder, rfd => rfd);
-- burst ram interface
o_RAMClk <= clk;
ce <= enable;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
-- @author: Andreas Agne, changed by Markus Happe
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
histo_ram_proc : process(clk)
begin
if rising_edge(clk) then
-- TRY: CLOCKED VERSION
--histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
if histo_inc = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= histo_ram(CONV_INTEGER(histo_bucket)) + 1;
elsif histo_clear = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= (others=>'0');
elsif normalize_histo = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= normalize_histo_value;
end if;
end if;
end process;
-- calculate histogram. Prefetch line. Parallel execution of
-- line prefetching (framwork) and histogram calculation (user proc.)
calc_histo_proc : process(clk, reset, calculate_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or calculate_histo_en = '0' then
step := 0;
prefetch_line_en <= '0';
update_histo_en <= '0';
calculate_histo_done <= '0';
elsif rising_edge(clk) then
case step is
-- (i) prefetch 1st line
-- (ii) prefetch next line and update histogram for current line
-- (iii) update histogram for last line
when 0 =>
-- prefetch first line
prefetch_line_en <= '1';
update_histo_en <= '0';
number_of_lines <= 1 + y2 - y1;
py <= y1;
step := step + 1;
when 1 =>
-- prefetch first line completed
if (prefetch_line_done = '1') then
prefetch_line_en <= '0';
number_of_lines <= number_of_lines - 1;
step := step + 1;
end if;
when 2 =>
-- update histogram start
update_histo_en <= '1';
step := step + 1;
when 3 =>
-- update histogram stop
if (update_histo_done = '1') then
update_histo_en <= '0';
step := step + 1;
end if;
when 4 =>
-- more lines?
if (number_of_lines <= 0) then
step := step + 1;
else
step := step - 3;
prefetch_line_en <= '1';
py <= py + 1;
end if;
-- when 2 =>
-- -- start parallel execution, or start last update
-- if (number_of_lines <= 0) then
-- -- last line allready prefetched
-- update_histo_en <= '1';
-- prefetch_line_en <= '0';
-- step := step + 2;
-- else
-- -- more lines to go
-- prefetch_line_en <= '1';
-- update_histo_en <= '1';
-- py <= py + 1;
-- step := step + 1;
-- end if;
--
-- when 3 =>
-- -- parallel execution completed
-- if (prefetch_line_done = '1' and update_histo_done = '1') then
-- prefetch_line_en <= '0';
-- update_histo_en <= '0';
-- number_of_lines <= number_of_lines - 1;
-- step := step - 1;
-- end if;
--
-- when 4 =>
-- -- last line
-- if (update_histo_done = '1') then
-- update_histo_en <= '0';
-- step := step + 1;
-- end if;
when 5 =>
-- finished
calculate_histo_done <= '1';
end case;
end if;
end process;
-- prefetch pixel line for histogram calculation
prefetch_line_proc : process(clk, reset, prefetch_line_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or prefetch_line_en = '0' then
step := 0;
prefetch_line_done <= '0';
--receive_data_ack <= '0';
get_data_needed <= '0';
get_data_length <= 0;
elsif rising_edge(clk) then
case step is
-- (i) calculate get data address, length
-- (ii) ask framework for data
when 0 =>
receive_data_ack <= '0';
get_data_needed <= '0';
-- calculate get_data_offset (1 of 3)
get_data_offset <= py * 1024;
step := step + 1;
when 1 =>
-- calculate get_data_offset (2 of 3)
get_data_offset <= get_data_offset + x1;
line_length <= 1 + x2;
step := step + 1;
when 2 =>
-- calculate get_data_offset (3 of 3)
get_data_offset <= get_data_offset * 4;
line_length <= line_length - x1;
step := step + 1;
when 3 =>
-- get data by framework, ask framework for data
get_data_address <= input_data_address + get_data_offset;
get_data_length <= line_length * 4;
get_data_needed <= '1';
step := step + 1;
when 4 =>
-- receive answer from framework
if (receive_data_en = '1') then
receive_data_ack <= '1';
get_data_needed <= '0';
prefetch_line_address <= receive_data_address;
step := step + 1;
end if;
when 5 =>
-- finished
receive_data_ack <= '1';
prefetch_line_done <= '1';
end case;
end if;
end process;
-- update histogram for one line, stored in cache
update_histogramm : process(clk, reset, update_histo_en, enable)
variable step : natural range 0 to 7;
variable my_step : natural range 0 to 7;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
my_step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
if enable = '0' then
-- framework maybe interrupted
step := 7;
histo_inc <= '0';
else
case step is
-- (i) load first pixel
-- (ii) update histogram for current pixel and load next one (if needed)
when 0 =>
-- start to read 1st pixel
update_histo_addr <= prefetch_line_address;
px <= x1;
step := step + 1;
my_step := 1;
when 1 =>
-- wait one cycle (for local ram data to become valid)
step := step + 1;
my_step := 2;
when 2 =>
-- update histogram (1 of 2)
-- extract H, S, V values
H(0 to 7) <= i_RamData( 24 to 31);
S(0 to 7) <= i_RamData( 16 to 23);
V(0 to 7) <= i_RamData( 8 to 15);
-- do not increment histogram in this step
histo_inc <= '0';
-- get next pixel
update_histo_addr <= update_histo_addr + 1;
step := step + 1;
my_step := 3;
when 3 =>
-- update histogram (2 of 2)
-- calculate histogram bucket for current pixel and update
if( S_THRESH <= S and V_THRESH <= V) then
update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(((10
* sdvd_values(TO_INTEGER(UNSIGNED(S))))
+ hd_values(TO_INTEGER(UNSIGNED(H)))), 7));
else
update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED((100
+ sdvd_values(TO_INTEGER(UNSIGNED(V)))), 7));
end if;
-- increment histogram value at update_histo_bucket
histo_inc <= '1';
-- update current pixel position
px <= px + 1;
-- more pixels in line?
if (x2 <= px) then
-- no more pixels
step := step + 1;
my_step := 4;
else
-- more pixels to go
step := step - 1;
my_step := 2;
end if;
when 4 =>
-- updating finished
histo_inc <= '0';
update_histo_done <= '1';
my_step := 4;
when 5 =>
-- additional wait cycle for step 2
step := step - 3;
when 6 =>
-- additional wait cycle for step 3
step := step - 3;
when 7 =>
if (my_step = 1) then
step := 0;
elsif (my_step = 2) then
step := 5;
elsif (my_step = 3) then
step := 6;
else
step := my_step;
end if;
histo_inc <= '0';
end case;
end if;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
-- @author: Andreas Agne
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_RAMWE <= '0';
copy_histo_data <= (others => '0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
step := step + 1;
when 2 => -- copy remaining histogram buckets to burst ram
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
if (108 <= copy_histo_bucket) then
step := step + 1;
end if;
when 3 => -- wait (1 of 2)
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= histo_value;
step := step + 1;
when 4 => -- wait (2 of 2)
o_RAMWE <= '1';
step := step + 1;
when 5 => -- write n
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(110, 32));
step := step + 1;
when 6 => -- write dummy
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(0, 32));
step := step + 1;
when 7 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
copy_histo_bucket <= (others => '0');
o_RAMWE <= '0';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
-- @author: Andreas Agne
clear_histogram_proc : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 3;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if 108 <= clear_histo_bucket then
step := step + 1;
end if;
when 2 =>
step := step + 1;
when 3 => -- set handshake signal
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to normalizing the histograme
normalize_histogram_proc : process(clk, reset, normalize_histo_en, ce)
variable step : natural range 0 to 7;
begin
if reset = '1' or normalize_histo_en = '0' then
step := 0;
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '0';
elsif ce = '0' then
elsif rising_edge(clk) then
case step is
when 0 =>
-- init sum calculation
i <= 0;
sum <= 0;
step := step + 1;
when 1 =>
-- calculate sum
sum <= sum + CONV_INTEGER(histo_ram(i));
if (i < 109) then
i <= i + 1;
else
step := step + 1;
end if;
-- init
when 2 =>
normalize_histo_bucket <= (others => '0');
normalize_histo <= '0';
i <= 0;
step := step + 1;
-- modify histo_values (histo_value * GRANULARITY) and sum up histogram
-- first histo_value
when 3 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
i <= 1;
step := step + 1;
-- other histo_values
when 4 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
if (i < 109) then
i <= i + 1;
end if;
if (normalize_histo_bucket < 109) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
else
step := step + 1;
end if;
when 5 =>
-- start division
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
divisor <= STD_LOGIC_VECTOR(TO_SIGNED(sum, 32));
i <= 0;
step := step + 1;
when 6 =>
-- put all 110 histogram values into pipelined divider.
-- pipelined divider has a latency of 36 clock cycles
-- 36 = 32 (width of dividend) + 4 (see: coregen datasheed)
-- one clock cycle per division
if (i<110) then
-- put histogram values to pipeline
dividend <= histo_ram(i);
i <= i + 1;
end if;
if (i > 36) then
-- collect division results
normalize_histo <= '1';
normalize_histo_value <= quotient;
if (normalize_histo_bucket < 109 and i > 37) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
elsif (109 <= normalize_histo_bucket) then
step := step + 1;
end if;
end if;
when 7 =>
-- set handshake signal;
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '1';
end case;
end if;
end process;
-- reads parameter
read_parameter_proc: process (clk, reset, read_parameter_en)
variable step : natural range 0 to 4;
begin
if reset = '1' or read_parameter_en = '0' then
step := 0;
read_parameter_done <= '0';
parameter_loaded_ack <= '0';
elsif rising_edge(clk) then
case step is
when 0 =>
--! read parameter values
read_parameter_addr <= local_ram_start_address_if;
parameter_loaded_ack <= '0';
step := step + 1;
when 1 =>
--! wait one cycle
read_parameter_addr <= local_ram_start_address_if + 1;
step := step + 1;
when 2 =>
--! read size_x
size_x <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 3 =>
--! read size_y
size_y <= TO_INTEGER(SIGNED(i_RAMData));
parameter_loaded_ack <= '1';
step := step + 1;
when 4 =>
if (parameter_loaded = '0') then
read_parameter_done <= '1';
parameter_loaded_ack <= '0';
end if;
end case;
end if;
end process;
-- reads particle data needed for histogram calculation
read_particle_proc: process (clk, reset, read_particle_en, ce)
variable step : natural range 0 to 8;
begin
if reset = '1' or read_particle_en = '0' then
step := 0;
read_particle_done <= '0';
--local_ram_address_if <= local_ram_start_address_if;
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! increment local ram address to get x value
local_ram_address_if <= local_ram_start_address_if + 1;
step := step + 1;
when 1 =>
--! read particle values
read_particle_addr <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
step := step + 1;
when 2 =>
--! wait one cycle
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 3 =>
--! read x
x <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 6;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 4 =>
--! read y
y <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 5 =>
--! read scale
scale <= TO_INTEGER(SIGNED(i_RAMData));
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 6 =>
--! read width
width <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 7 =>
--! read height
height <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 8 =>
read_particle_done <= '1';
end case;
end if;
end process;
-- analyzes particle data needed for histogram calculation
analyze_particle_proc: process (clk, reset, analyze_particle_en, ce)
variable step : natural range 0 to 13;
begin
if reset = '1' or analyze_particle_en = '0' then
step := 0;
analyze_particle_done <= '0';
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
temp_x <= width - 1;
temp_y <= height - 1;
step := step + 1;
when 1 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x / 2;
step := step + 1;
when 2 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y / 2;
step := step + 1;
when 3 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x * scale;
step := step + 1;
when 4 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y * scale;
step := step + 1;
when 5 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x - temp_x;
step := step + 1;
when 6 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x + temp_x;
step := step + 1;
when 7 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y - temp_y;
step := step + 1;
when 8 =>
--! calculate (x1, y1) and (x2, y2)
y2 <= y + temp_y;
step := step + 1;
when 9 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x1 / GRANULARITY;
step := step + 1;
when 10 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y1 / GRANULARITY;
if (x1 > size_x-1) then
x1 <= size_x - 1;
elsif (x1 < 0) then
x1 <= 0;
end if;
step := step + 1;
when 11 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x2 / GRANULARITY;
if (y1 > size_y-1) then
y1 <= size_y - 1;
elsif (y1 < 0) then
y1 <= 0;
end if;
step := step + 1;
when 12 =>
--! calculate (x1, y1) and (x2, y2)
y2 <= y2 / GRANULARITY;
if (x2 > size_x-1) then
x2 <= size_x - 1;
elsif (x2 < 0) then
x2 <= 0;
end if;
step := step + 1;
when 13 =>
--! finished
if (y2 > size_y-1) then
y2 <= size_y - 1;
elsif (y2 < 0) then
y2 <= 0;
end if;
if (y2 < y1) then
if (y2 > 0) then
y1 <= y2;
else
y1 <= 0;
end if;
end if;
if (x2 < x1) then
x1 <= x2;
end if;
analyze_particle_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
-- @author: Andreas Agne
-- updated
mux_proc: process(update_histo_en, copy_histo_en, clear_histo_en, normalize_histo_en,
read_particle_en, read_particle_addr, normalize_histo_bucket,
update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket,
copy_histo_data, read_parameter_en, read_parameter_addr)
variable addr : std_logic_vector(C_TASK_BURST_AWIDTH - 1 downto 0);
variable data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
variable bucket : std_logic_vector(6 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
data := (others => '0');
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
data := copy_histo_data;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
data := (others => '0');
elsif normalize_histo_en = '1' then
addr := (others => '0');
bucket := normalize_histo_bucket;
data := (others => '0');
elsif read_particle_en = '1' then
addr := read_particle_addr;
bucket := (others => '0');
data := (others => '0');
elsif read_parameter_en = '1' then
addr := read_parameter_addr;
bucket := (others => '0');
data := (others => '0');
else
addr := (others => '0');
bucket := (others => '0');
data := (others => '0');
end if;
o_RAMData <= data;
o_RAMAddr <= addr(C_TASK_BURST_AWIDTH - 1 downto 0);
histo_bucket <= bucket;
end process;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- --
-- 1) initialize histogram, finished = '0' (if new_particle = '1') --
-- --
-- 2) read particle data --
-- --
-- 3) extract needed information --
-- --
-- 4) calculate histogram --
-- --
-- 5) normalize histogram --
-- --
-- 6) write histogram into local ram --
-- --
-- 7) finshed = '1', wait for new_particle = '1' --
-- --
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= STATE_INIT;
new_particle_ack <= '0';
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
state <= STATE_INIT;
new_particle_ack <= '0';
clear_histo_en <= '0';
read_particle_en <= '0';
analyze_particle_en <= '0';
calculate_histo_en <= '0';
normalize_histo_en <= '0';
copy_histo_en <= '0';
finished <= '0';
elsif enable = '1' then
case state is
when STATE_INIT =>
--! init data
finished <= '0';
calculate_histo_en <= '0';
copy_histo_en <= '0';
read_particle_en <= '0';
analyze_particle_en <= '0';
normalize_histo_en <= '0';
if (new_particle = '1') then
new_particle_ack <= '1';
clear_histo_en <= '1';
state <= STATE_INIT_HISTOGRAM;
elsif (parameter_loaded = '1') then
read_parameter_en <= '1';
state <= STATE_READ_PARAMETER;
end if;
when STATE_READ_PARAMETER =>
--! init histogram
if (read_parameter_done = '1') then
read_parameter_en <= '0';
state <= STATE_INIT;
end if;
when STATE_INIT_HISTOGRAM =>
--! init histogram
if (clear_histo_done = '1') then
new_particle_ack <= '0';
clear_histo_en <= '0';
read_particle_en <= '1';
state <= STATE_READ_PARTICLE;
end if;
when STATE_READ_PARTICLE =>
--! read particle values
if (read_particle_done = '1') then
analyze_particle_en <= '1';
read_particle_en <= '0';
state <= STATE_ANALYZE_PARTICLE;
end if;
when STATE_ANALYZE_PARTICLE =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
if (analyze_particle_done = '1') then
analyze_particle_en <= '0';
calculate_histo_en <= '1';
state <= STATE_CALCULATE_HISTOGRAM;
end if;
when STATE_CALCULATE_HISTOGRAM =>
-- get next pixel for histogram calculation
if (calculate_histo_done = '1') then
calculate_histo_en <= '0';
normalize_histo_en <= '1';
state <= STATE_NORMALIZE_HISTOGRAM;
end if;
when STATE_NORMALIZE_HISTOGRAM =>
--! normalize histogram
if (normalize_histo_done = '1') then
normalize_histo_en <= '0';
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
end if;
when STATE_COPY_HISTOGRAM =>
--! normalize histogram
if (copy_histo_done = '1') then
copy_histo_en <= '0';
state <= STATE_FINISH;
end if;
when STATE_FINISH =>
--! write finished signal
finished <= '1';
if (new_particle = '1') then
state <= STATE_INIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.test_package.all;
entity test is
generic(
MEMORY_SIZE : natural := 4096
);
port(
val_in : in std_logic_vector(63 downto 0)
);
end entity test;
architecture behaviour of test is
signal tmp : std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
begin
tmp <= val_in(log2(MEMORY_SIZE) - 1 downto 0);
end architecture behaviour;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--ALU
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity ALU is
generic(width: integer := sizeof_Word);
port(
Ei: in std_logic := '0';
Eo: out std_logic;
IP: in std_logic_vector(7 downto 0);
AC: in word;
DR: in word;
Q: out word;
cAND: in std_logic;
cADD: in std_logic;
cDR : in std_logic;
cINR: in std_logic;
cCOM: in std_logic;
cSHR: in std_logic;
cSHL: in std_logic
);
end ALU;
architecture Structure of ALU is
signal inst: std_logic_vector(7 downto 0);
signal andc,addc,shrc,shlc: word;
signal addeo: std_logic;
begin
andc <= AC and DR;
fa: fulladder port map('0', AC, DR, addc, addeo);
shlc(width-1 downto 1) <= AC(width-2 downto 0);
shlc(0) <= Ei;
shrc(width-2 downto 0) <= AC(width-1 downto 1);
shrc(width-1) <= Ei;
Q <= andc when cAND = '1'
else addc when cADD = '1'
else DR when cDR = '1'
else "00000000"&IP when cINR = '1'
else not AC when cCOM = '1'
else shrc when cSHR = '1'
else shlc when cSHL = '1'
else AC;
Eo <= addeo when cADD = '1'
else AC(0) when cSHR = '1'
else AC(width-1) when cSHL = '1'
else '0' when cAND = '1'
else '0' when cDR = '1'
else '0' when cINR = '1'
else '0' when cCOM = '1'
else Ei;
end architecture; |
entity repro2 is
generic (l : natural := 10);
end repro2;
architecture behav of repro2 is
begin
process
variable v : string (0 to l);
alias a : string is v;
begin
v := (others => ' ');
a := (others => 'x');
wait;
end process;
end behav;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
package PK_GEN_PULSO is
component GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
-- se detecta flanco en input
);
end component;
end PK_GEN_PULSO;
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
-- se detecta flanco en input
);
end;
architecture BEHAV of GEN_PULSO is
-- states
type state_type IS
(st_espero0, st_espero1, st_flanco_detectado);
attribute enum_encoding : string;
attribute enum_encoding of state_type : type is "one-hot"; -- "default", "sequential", "gray", "johnson", or "one-hot"
signal STATE, NXSTATE : state_type;
-- info sobre codificación: http://quartushelp.altera.com/13.0/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm
--- CONSTANT st_espero0 : std_logic_vector(1 DOWNTO 0):= "00";
--- CONSTANT st_espero1 : std_logic_vector(1 DOWNTO 0):= "01";
--- CONSTANT st_flanco_detectado : std_logic_vector(1 DOWNTO 0):= "11";
--- signal STATE, NXSTATE : std_logic_vector(1 DOWNTO 0);
begin
-- Process donde se genera la salida
-- dependiente de estado y entrada
-- y proximo estado.
combin: process (STATE, input)
begin
case STATE is
when st_espero0 =>
if input ='1' then
NXSTATE <= st_espero0;
else
NXSTATE <= st_espero1;
end if;
edge_detected <= '0';
when st_espero1 =>
if input ='0' then
NXSTATE <= st_espero1;
else
NXSTATE <= st_flanco_detectado;
end if;
edge_detected <= '0';
when st_flanco_detectado =>
if input ='0' then
NXSTATE <= st_espero1;
else
NXSTATE <= st_espero0;
end if;
edge_detected <= '1';
when others =>
NXSTATE <= st_espero1;
edge_detected <= '0';
end case;
end process;
-- Process donde se generan los FF
-- sensibles a flanco
-- de subida de la máquina de estado
sync:process (clk,reset,STATE)
begin
if reset = '1' then
STATE <= st_espero1;
elsif clk'event and clk = '1' then
STATE <= NXSTATE;
end if;
end process;
end BEHAV;
|
------------------------------------------------------------------------
-- PhoenixOnBoardMemCtrl.vhd -- Digilent C1 Memory Module programming controller
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2005 Digilent, Inc.
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.03i
-- WebPack
------------------------------------------------------------------------
-- This is the source file for the PhoenixOnBoardMemCtrl component,
-- provided by the Digilent Component Library.
-- This file contains the design for a programming controller.
-- This component, in conjunction with a communication module
-- (Phoenix OnBoard USB controller),
-- a PC application program (a Digilent utility or user generated)
-- and the EppCtrl Digilent Library component allows the user to
-- read or write the RAM and Flash memory chips on the
-- Digilent Phoenix board.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- PhoenixOnBoardMemCtrl acts as a "client" for EppCtrl.
-- It implements the following Epp data registers:
------------------------------------------------------------------------
-- EPP Register Interface
-- Register Function
-- -------- --------
-- 0 Memory control register (read/write)
-- 1 Memory address bits 0-7 (read/write)
-- 2 Memory address bits 8-15 (read/write)
-- 3 Memory address bits 16-18 (read/write)
-- 4 Memory data write holding register (read/write) -see Note 1
-- 5 Memory data read register (read) - see Note 2
-- Registers 6 and 7 are used for block transfers
-- 6 RAM auto read/write register (read/write) - see Note 3
-- 7 Flash auto read/write register (read/write) - see Note 4
--
-- Reading from or writing to registers 0...5 generates a simple
-- Register Transfer (see the EppCtrl.vhd header):
-- the HandShakeReqOut is inactive when regEppAdrInDummy(2:0) = 0...5.
-- (see the EppCtrl.vhd Component Header)
-- Registers 6 and 7 belong to the "Process Launch" type,
-- both for read and write operations (see the EppCtrl.vhd header):
-- the HandShakeReqOut activates when regEppAdrInDummy(2:0) = 6...7.
-- Consequently, at each Epp Data Register read or write cycle for this
-- address, the EppCtrl component activates the ctlEppStart signal.
-- As response, the PhoenixOnBoardMemCtrl:
-- - performs the actions explained by Note 3 or 4.
-- - activates the ctlMsmDoneOut signal
-- - waits for the ctlEppStart signal to go inactive.
-- - inactivates the ctlMsmDoneOut signal
-- - returns to the idle state (stMsmReady)
--
-- Note 1: Writing to "registers" 6 or 7 updates register 4.
-- Note 2: This is not a physical register. The memory data bus content
-- is read at this address.
-- Note 3: Writing to "register" 6, when in byte mode:
-- - updates the register 4 content AND
-- - launches an automatic RAM write cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - increments the Memory address register by 1.
-- Reading from address 7, when in byte mode:
-- - launches an automatic RAM read cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the content of the
-- addressed Flash location
-- - increments the Memory address register by 1.
-- Writing to "register" 6, when in word mode and even address:
-- - launches a blind cycle to update the auxiliary register.
-- No RAM cycle is launched.
-- - increments the Memory address register by 1.
-- Writing to "register" 6, when in word mode and odd address:
-- - updates the register 4 content AND
-- - launches an automatic RAM write cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- (a word is written to RAM:
-- - memory address bus is set to the word address (A0 = 0)
-- - memory data bus is set with the previous stored value
-- of auxiliary register as lower byte and curent value of
-- register 4 as higher byte)
-- - increments the Memory address register to the next even.
-- Reading from address 6, when in word mode and even address:
-- - launches an automatic RAM read cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the lower byte of
-- the addressed RAM location (sent over the Epp)
-- - loads the auxiliary register with the upper byte of
-- the addressed RAM location (not yet sent over the Epp)
-- - increments the Memory address register by 1.
-- Reading from address 6, when in word mode and odd address:
-- - launches a blind cycle to send the previous stored value
-- of the auxiliary register. No RAM cycle is performed.
-- - increments the Memory address register by 1.
--
-- Note 4: Writing to "register" 7, when in byte mode:
-- - updates the register 4 content AND
-- - launches an automatic Flash write cycle:
-- - generates the appropriate control signal sequence
-- - waits for the internal Flash write procedure to complete
-- - increments the Memory address register by 1.
-- Reading from address 7, when in byte mode:
-- - launches an automatic Flash read cycle:
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the content of the
-- addressed Flash location
-- - increments the Memory address register by 1.
-- Writing to "register" 7, when in word mode and even address:
-- - launches a blind cycle to update the auxiliary register.
-- No Flash cycle is launched.
-- - increments the Memory address register by 1.
-- Writing to "register" 7, when in word mode and odd address:
-- - updates the register 4 content AND
-- - launches an automatic Flash write cycle:
-- - generates the appropriate control signal sequence
-- (a word is written to Flash:
-- - memory address bus is set to the word address (A0 = 0)
-- - memory data bus is set with the previous stored value
-- of auxiliary register as lower byte and curent value of
-- register 4 as higher byte)
-- - waits for the internal Flash write procedure to complete
-- - increments the Memory address register to the next even.
-- Reading from address 7, when in word mode and even address:
-- - launches an automatic Flash read cycle:
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the lower byte of
-- the addressed Flash location (sent over the Epp)
-- - loads the auxiliary register with the upper byte of
-- the addressed Flash location (not yet sent over the Epp)
-- - increments the Memory address register by 1.
-- Reading from address 7, when in word mode and odd address:
-- - launches a blind cycle to send the previous stored value
-- of the auxiliary register. No Flash cycle is performed.
-- - increments the Memory address register by 1.
--
-- Memory control register
-- Bit Function
-- -------- --------
-- 0 (0x01) Output enable (read strobe) |
-- 1 (0x02) Write enable (write strobe) | active LOW signals
-- 2 (0x04) RAM chip select (not used) |
-- 3 (0x08) Flash chip select |
-- 4 (0x10) Memory module during programming
-- (memory is not available for a user application)
-- (not yet implemented)
-- 5 (0x20) Byte enable ('0') or word enable ('1')
-- The Epp interfaces can only handle 8 bit data.
-- Word mode (16 bit) is only available for Automatic Read/Write,
-- both RAM (using register 6) and Flash (using register 7).
-- A "Word write" operation consists in two Epp (byte) cycles:
-- the first one, at even address, launces a "blind cycle",
-- which only stores the lower data byte in an auxiliary register.
-- the second one, at odd address, combines the two data bytes to a
-- data word on the memory data bus, and writes it to memory.
-- A "Word read" operation consists in two Epp (byte) cycles:
-- the first one, at even address, reads the data word from memory,
-- sends the lower data byte over the Epp bus and stores the upper
-- byte in an auxiliary register.
-- the second one, at odd address, launces a "blind cycle",
-- which only sends the upper data byte over the Epp bus.
-- Manual mode is only allowed for Flash
-- (Celullar RAM would hold CS active to long, blocking refresh cycles)
-- Manual "Word" mode for flash reads the upper data bus byte for odd
-- addresses and the lower data bus byte for even addresses.
-- Manual "Byte" mode for flash reads the lower data bus byte
-- for both odd and even addresses:
-- These features are completely transparent to the Epp host, which only
-- needs to set the appropriate value in the Memory Control and
-- memory address registers and read/write the data registers (4...7).
------------------------------------------------------------------------
-- Revision History:
-- 10/21/2004(MirceaD): created
-- 12/19/2005(MirceaD): modified for PhoenixOnBoard Memory
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PhoenixOnBoardMemCtrl is
Port(
clk : in std_logic; -- system clock (50MHz)
-- Epp interface signals
HandShakeReqOut: out std_logic; -- User Handshake Request
ctlMsmStartIn: in std_logic; -- Automatic process Start
ctlMsmDoneOut: out std_logic; -- Automatic process Done
ctlMsmDwrIn: in std_logic; -- Data Write pulse
ctlEppRdCycleIn: in std_logic; -- Indicates a READ Epp cycle
EppRdDataOut: inout std_logic_vector(7 downto 0);-- Data Input bus
EppWrDataIn: in std_logic_vector(7 downto 0); -- Data Output bus
regEppAdrIn: in std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content (bits 7:3 ignored)
ComponentSelect : in std_logic;
-- active HIGH, selects the current MemCtrl instance
-- If a single "client" component (CxMemCfg or other) is connected
-- to a "host" component (EppCtrl or other), ComponentSelect signal
-- can be held permanently active (connected to Vcc).
-- When more "client" components (CxMemCfg or other) are connected
-- to a "host" component (EppCtrl or other), the ComponentSelect
-- input of each client must be synthesized by decoding the higher
-- bits of regEppAdrOut bus, such a way to provide a distinct
-- address range for each.
-- C1MemCfg component requires 8 Epp data registers
-- (address range xxxxx000...xxxxx111)
-- Memory bus signals
MemDB: inout std_logic_vector(15 downto 0);-- Memory data bus
MemAdr: out std_logic_vector(23 downto 1);-- Memory Address bus
FlashByte: out std_logic; -- Byte enable('0') or word enable('1')
RamCS: out std_logic; -- RAM CS
FlashCS: out std_logic; -- Flash CS
MemWR: out std_logic; -- memory write
MemOE: out std_logic; -- memory read (Output Enable),
-- also controls the MemDB direction
RamUB: out std_logic; -- RAM Upper byte enable
RamLB: out std_logic; -- RAM Lower byte enable
RamCre: out std_logic; -- Cfg Register enable
RamAdv: out std_logic; -- RAM Address Valid pin
RamClk: out std_logic; -- RAM Clock
RamWait: in std_logic; -- RAM Wait pin
FlashRp: out std_logic; -- Flash RP pin
FlashStSts: in std_logic; -- Flash ST-STS pin
MemCtrlEnabled: out std_logic; -- MemCtrl takes bus control
ReadReq: in std_logic;
DataRdy: out std_logic;
DataOut :out std_logic_vector(7 downto 0);
DataAck: in std_logic;
Reset: in std_logic
);
end PhoenixOnBoardMemCtrl;
architecture Behavioral of PhoenixOnBoardMemCtrl is
component debounce
PORT( clk : IN STD_LOGIC;
input : IN STD_LOGIC;
output : OUT STD_LOGIC);
end component;
------------------------------------------------------------------------
-- Constant and Signal Declarations
------------------------------------------------------------------------
-- The following constants define the state codes for the Memory
-- control state machine. This state machine controls the sequence
-- of operations needed to perform a write sequence or a read sequence
-- on either flash or RAM memory.
-- The states are such a way assigned that each transition
-- changes a single state register bit (Grey code - like)
constant stMsmReady: std_logic_vector(3 downto 0) := "0000";
constant stMsmFwr01: std_logic_vector(3 downto 0) := "0001";
constant stMsmFwr02: std_logic_vector(3 downto 0) := "0101";
constant stMsmFwr03: std_logic_vector(3 downto 0) := "0111";
constant stMsmFwr04: std_logic_vector(3 downto 0) := "1111";
constant stMsmFwr05: std_logic_vector(3 downto 0) := "1011";
constant stMsmFwr06: std_logic_vector(3 downto 0) := "1001";
constant stMsmFwr07: std_logic_vector(3 downto 0) := "1101";
constant stMsmAdInc: std_logic_vector(3 downto 0) := "1100";
constant stMsmDone : std_logic_vector(3 downto 0) := "1000";
constant stMsmBlind: std_logic_vector(3 downto 0) := "0100";
constant stMsmDir01: std_logic_vector(3 downto 0) := "0010";
constant stMsmDWr02: std_logic_vector(3 downto 0) := "0110";
constant stMsmDir03: std_logic_vector(3 downto 0) := "1110";
constant stMsmDRd02: std_logic_vector(3 downto 0) := "1010";
-- Epp Data register addresses
constant MemCtrlReg: std_logic_vector(2 downto 0) := "000";
-- 0 Memory control register (read/write)
constant MemAdrL: std_logic_vector(2 downto 0) := "001";
-- 1 Memory address bits 0-7 (read/write)
constant MemAdrM: std_logic_vector(2 downto 0) := "010";
-- 2 Memory address bits 8-15 (read/write)
constant MemAdrH: std_logic_vector(2 downto 0) := "011";
-- 3 Memory address bits 16-21 (read/write)
constant MemDataWr: std_logic_vector(2 downto 0) := "100";
-- 4 Memory data write holding register (read/write) - see Note 1
constant MemDataRd: std_logic_vector(2 downto 0) := "101";
-- 5 Memory data read register (read) - see Note 2
-- Register 7 is used for block transfers
constant RamAutoRW: std_logic_vector(2 downto 0) := "110";
-- 6 RAM auto write register (read/write) - see Note 4
constant FlashAutoRW: std_logic_vector(2 downto 0) := "111";
-- 7 Flash auto write register (read/write) - see Note 4
-- State register and next state for the FSMs
signal stMsmCur : std_logic_vector(3 downto 0) := stMsmReady;
signal stMsmNext : std_logic_vector(3 downto 0);
-- Counter used to generate delays
signal DelayCnt : std_logic_vector(4 downto 0);
-- The attribute lines below prevent the ISE compiler to extract and
-- optimize the state machines.
-- WebPack 5.1 doesn't need them (the default value is NO)
-- WebPack 6.2 has the default value YES, so without these lines,
-- it would "optimize" the state machines.
-- Although the overall circuit would be optimized, the particular goal
-- of "glitch free output signals" may not be reached.
-- That is the reason of implementing the state machine as described in
-- the constant declarations above.
attribute fsm_extract : string;
attribute fsm_extract of stMsmCur: signal is "no";
attribute fsm_extract of stMsmNext: signal is "no";
attribute fsm_encoding : string;
attribute fsm_encoding of stMsmCur: signal is "user";
attribute fsm_encoding of stMsmNext: signal is "user";
attribute signal_encoding : string;
attribute signal_encoding of stMsmCur: signal is "user";
attribute signal_encoding of stMsmNext: signal is "user";
-- Signals dealing with memory chips
signal regMemCtl: std_logic_vector(7 downto 0):= x"0f";
-- Memory Control register ( MemCtrl disabled )
signal regMemAdr: std_logic_vector(23 downto 0):= x"000000";
-- Memory Address register
signal carryoutL:std_logic:='0';
-- Carry out for memory address low byte
signal carryoutM:std_logic:='0';
-- Carry out for memory address middle byte
signal regMemWrData: std_logic_vector(15 downto 0) := x"0000";
-- Memory Write Data register
signal regMemRdData: std_logic_vector(7 downto 0) := x"00";
-- Memory Read Data register
signal regMemRdDataAux: std_logic_vector(7 downto 0) := x"00";
-- Auxiliary Memory Read Data register
signal busMemIn: std_logic_vector(15 downto 0);
--signal busMemInHigh: std_logic_vector(7 downto 0);
signal busMemOut: std_logic_vector(15 downto 0);
-- Signals in the memory control register
signal ctlMcrOe: std_logic; -- Output enable (read strobe)
signal ctlMcrWr: std_logic; -- Write enable (write strobe)
signal ctlMcrRAMCs: std_logic; -- RAM chip select
signal ctlMcrFlashCs: std_logic; -- Flash chip select
signal ctlMcrEnable: std_logic; -- '1' => Enables the MemCtrl
signal ctlMcrWord: std_logic; -- PC enerated Word signal
-- Byte enable ('0') or word enable ('1')
signal ctlMcrDir: std_logic; -- composed out of previous ones
-- Signals used by Memory control state machine
signal ctlMsmOe : std_logic;
signal ctlMsmWr : std_logic;
signal ctlMsmRAMCs : std_logic;
signal ctlMsmFlashCs : std_logic;
signal ctlMsmDir : std_logic;
signal ctlMsmAdrInc : std_logic;
signal ctlMsmWrCmd : std_logic;
signal ctlEppRdCycleInDummy : std_logic;
signal ctlMsmStartInDummy : std_logic;
signal regEppAdrInDummy : std_logic_vector(7 downto 0);
signal ctlMsmDwrInDummy :std_logic;
signal EppWrDataInDummy : std_logic_vector(7 downto 0);
signal MemReadSig : std_logic;
signal counter : integer range 0 to 10 := 0;
signal redir : std_logic;
signal DataFromMem : std_logic_vector(7 downto 0);
signal Rst : std_logic := '0';
signal stage : integer range 0 to 10 := 0;
signal counter2 : integer range 0 to 91 := 0;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Data Retrieval Section
ctlEppRdCycleInDummy <= ctlEppRdCycleIn or MemReadSig;
ctlMsmStartInDummy <= ctlMsmStartIn or MemReadSig;
ctlMsmDwrInDummy <= ctlMsmDwrIn or Rst;
DataOut <= DataFromMem;
process (ReadReq, DataAck, clk)
BEGIN
if (ReadReq = '1') then
MemReadSig <= '1';
redir <= '1';
end if;
if (MemReadSig = '1' and (clk'event and clk = '1')) then
counter <= counter + 1;
end if;
if (counter = 8) then
DataFromMem <= EppRdDataOut;
MemReadSig <= '0';
counter <= 0;
DataRdy <= '1';
end if;
if (DataAck = '1') then
DataRdy <= '0';
redir <= '0';
end if;
end process;
process (redir, stage)
Begin
if stage = 2 then
regEppAdrInDummy <= "00000001";
elsif stage = 4 then
regEppAdrInDummy <= "00000010";
elsif stage = 6 then
regEppAdrInDummy <= "00000011";
elsif redir = '0' then
regEppAdrInDummy <= regEppAdrIn;
else
regEppAdrInDummy <= "00000110";
end if;
end process;
-------------------------------
process (reset, counter2)
Begin
if (Reset = '1') then
stage <= 1;
elsif (counter2 = 15) then
stage <= 2;
elsif (counter2 = 30) then
stage <= 3;
elsif (counter2 = 45) then
stage <= 4;
elsif (counter2 = 60) then
stage <= 5;
elsif (counter2 = 75) then
stage <= 6;
elsif (counter2 = 90) then
stage <= 0;
end if;
end process;
process (clk)
begin
if stage = 1 then
counter2 <= 1;
elsif (clk'event and clk = '1' and stage /= 0 and reset = '0') then
counter2 <= counter2 + 1;
end if;
end process;
process (stage)
Begin
EppWrDataInDummy <= EppWrDataIn;
rst <= '0';
if stage = 2 or stage = 4 or stage = 6 then
EppWrDataInDummy <= "00000000";
rst <= '1';
else
rst <= '0';
EppWrDataInDummy <= EppWrDataIn;
end if;
end process;
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
MemCtrlEnabled <= ctlMcrEnable;
-- Epp signals
-- Port signals
EppRdDataOut <=
regMemCtl when regEppAdrInDummy(2 downto 0) = MemCtrlReg
and ComponentSelect = '1' else
regMemAdr(7 downto 0) when regEppAdrInDummy(2 downto 0) = MemAdrL
and ComponentSelect = '1' else
regMemAdr(15 downto 8) when regEppAdrInDummy(2 downto 0) = MemAdrM
and ComponentSelect = '1' else
regMemAdr(23 downto 16)
when regEppAdrInDummy(2 downto 0) = MemAdrH
and ComponentSelect = '1' else
regMemWrData(7 downto 0) when regEppAdrInDummy(2 downto 0) = MemDataWr
and regMemAdr(0) ='0' -- even address
and ComponentSelect = '1' else
regMemWrData(15 downto 8) when regEppAdrInDummy(2 downto 0) = MemDataWr
and regMemAdr(0) ='1' -- odd address
and ComponentSelect = '1' else
regMemRdData when regEppAdrInDummy(2 downto 0) = RamAutoRW
and ComponentSelect = '1' else
regMemRdData when regEppAdrInDummy(2 downto 0) = FlashAutoRW
and ComponentSelect = '1' else
-- Manual mode is only allowed for Flash
-- (Celullar RAM would hold CS active to long, blocking refresh cycles)
-- Manual "Word" mode for flash reads the upper data bus byte
-- when address odd:
busMemIn(15 downto 8) when ctlMcrWord = '1' -- Word Mode
and regMemAdr(0) = '1' -- odd address
and ComponentSelect = '1' else
-- Manual "Byte" mode for flash reads the lower data bus byte
-- for both odd and even addresses:
busMemIn(7 downto 0) when ComponentSelect = '1' else
"00000000"; -- prepared to "OR" EppRdDataOut to some other busses
-- Memory signals
-- Memory control register
ctlMcrOe <= regMemCtl(0); -- Output enable (read strobe)
ctlMcrWr <= regMemCtl(1); -- Write enable (write strobe)
ctlMcrRAMCs <= regMemCtl(2); -- RAM chip select
ctlMcrFlashCs <= regMemCtl(3); -- Flash chip select
ctlMcrEnable <= regMemCtl(4); -- MemCtrl enable ('1') or disable ('0')
ctlMcrWord <= regMemCtl(5); -- Byte enable ('0') or word enable ('1')
-- Memory control bus driven either by automatic state machine or by
-- memory control register
RamCS <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrRAMCs when stMsmCur = stMsmReady else -- MemCtrl Idle
ctlMsmRAMCs; -- MemCtrl generated RAM CS;
FlashCS <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrFlashCs when stMsmCur = stMsmReady and -- MemCtrl Idle
ctlMcrRamCs = '1' else -- RAM priority
ctlMsmFlashCs; -- MemCtrl generated Flash CS;
MemOE <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrOe when stMsmCur = stMsmReady else -- MemCtrl Idle
ctlMsmOe; -- MemCtrl generated RAM CS;
MemWR <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrWr when stMsmCur = stMsmReady and -- MemCtrl Idle
ctlMcrOe = '1' else -- OE priority
ctlMsmWr; -- MemCtrl generated RAM CS;
FlashByte <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrWord; -- PC generated Word signal;
-- Byte enable ('0') or word enable ('1')
RamLB <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0' when ctlMcrWord = '1' or -- word mode
regMemAdr(0) ='0' else -- even address
'1';
RamUB <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0' when ctlMcrWord = '1' or -- word mode
regMemAdr(0) ='1' else -- odd address
'1';
-- Memory control signals not yet used
RamClk <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous mode
RamCre <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous default mode
RamAdv <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous mode
FlashRp <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'1'; -- no reset, no power down
busMemIn <= MemDB;
busMemOut <= "00000000" & "01000000" when ctlMsmWrCmd = '1' else -- WrC
"00000000" & regMemWrData(15 downto 8)
when ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1'and -- odd addr
regEppAdrInDummy(2 downto 0) = FlashAutoRW
-- Flash accessed
else -- any other: -- all RAM
-- Flash word
-- Flash byte even
regMemWrData;-- when ctlMcrWord = '1';
MemAdr <= "ZZZZZZZ" & "ZZZZZZZZ" & "ZZZZZZZZ"
when ctlMcrEnable = '0' else -- MemCtrl Disabled
regMemAdr(23 downto 1);
ctlMcrDir <= ctlMcrOe and -- ctlMcrOe inactive
((not ctlMcrFlashCs) or -- ctlMcrFlashCs active
(not ctlMcrRAMCs)); -- ctlMcrRAMCs active
MemDB <= busMemOut when ctlMcrEnable = '1' and -- MemCtrl Enabled
(ctlMsmDir = '1' or -- Msm controlled
ctlMcrDir = '1') else -- Mcr controlled
"ZZZZZZZZ" & "ZZZZZZZZ";
-- Handshake signal
HandShakeReqOut <= '1' when (regEppAdrInDummy(2 downto 0) = RamAutoRW or
regEppAdrInDummy(2 downto 0) = FlashAutoRW)
and ComponentSelect = '1' else
'0';
-- Memory state machine related signals
-- Control commands generated by the memory state machine.
with stMsmCur select
ctlMsmOe <= '0' when stMsmDRd02|stMsmFwr05|stMsmFwr07,
'1' when others; -- Output enable (read strobe)
with stMsmCur select
ctlMsmWr <= '0' when stMsmDWr02|stMsmFwr01|stMsmFwr03,
'1' when others; -- Write enable (write strobe)
-- with stMsmCur select
-- ctlMsmFlashCs <= '0' when "---1"|"010-", -- FlashCS
-- '1' when others; -- Flash chip select
ctlMsmFlashCs <= '0'
when (stMsmCur = stMsmFwr01 or
stMsmCur = stMsmFwr02 or
stMsmCur = stMsmFwr03 or
stMsmCur = stMsmFwr04 or
stMsmCur = stMsmFwr05 or
stMsmCur = stMsmFwr06 or
stMsmCur = stMsmFwr07) or
((stMsmCur = stMsmDir01 or
stMsmCur = stMsmDWr02 or
stMsmCur = stMsmDRd02 or
stMsmCur = stMsmDir03) and
regEppAdrInDummy(2 downto 0) = FlashAutoRW) else
'1';
-- with stMsmCur select
-- ctlMsmRamCs <= '0' when "--10", -- RamCS
-- '1' when others; -- Flash chip select
ctlMsmRamCs <= '0'
when ((stMsmCur = stMsmDir01 or
stMsmCur = stMsmDWr02 or
stMsmCur = stMsmDRd02 or
stMsmCur = stMsmDir03) and
regEppAdrInDummy(2 downto 0) = RamAutoRW) else
'1';
with stMsmCur select
ctlMsmDir <= '1' when "0--1"|"011-", -- stMsmFwr01-03, stMsmDWr02
'0' when others;-- Memory bus direction: 1=toward memory
with stMsmCur select
ctlMsmAdrInc <= '1' when stMsmAdInc,
'0' when others; -- Flag to automatically increment
-- the address after a step of automatic memory access.
with stMsmCur select
ctlMsmWrCmd <= '1' when stMsmFwr01|stMsmFwr02,
'0' when others;
-- Flag to place write command on the BusMemOut
with stMsmCur select
ctlMsmDoneOut <= '1' when stMsmDone,
'0' when others;
-- Flag to tell the Epp state machine the current access cycle ended
-- Memory Control Register
process (clk, ctlMsmDwrInDummy)
begin
if clk = '1' and clk'Event then
if ctlMsmDwrInDummy = '1' and -- write cycle
regEppAdrInDummy(2 downto 0) = MemCtrlReg and -- MemCtrlReg addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl component selected
regMemCtl <= EppWrDataInDummy;
end if;
end if;
end process;
-- Memory Address Register/Counter
MsmAdrL: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' then -- automatic memory cycle
regMemAdr(7 downto 0) <= regMemAdr(7 downto 0) + 1; -- inc. address
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrL and-- MemAdrL reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(7 downto 0) <= EppWrDataInDummy; -- update MemAdrL content
end if;
end if;
end process;
carryoutL <= '1' when regMemAdr(7 downto 0) = x"ff" else
'0'; -- Lower byte carry out
MsmAdrM: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' then -- lower byte rollover
regMemAdr(15 downto 8) <= regMemAdr(15 downto 8) + 1;--inc. address
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrM and-- MemAdrM reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(15 downto 8) <= EppWrDataInDummy; -- update MemAdrM content
end if;
end if;
end process;
carryoutM <= '1' when regMemAdr(15 downto 8) = x"ff" else
'0'; -- Middle byte carry out
MsmAdrH: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' and -- lower byte rollover
carryoutM = '1' then -- middle byte rollover
regMemAdr(23 downto 16) <= regMemAdr(23 downto 16) + 1;--inc. addr.
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrH and-- MemAdrM reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(23 downto 16) <= EppWrDataInDummy;-- update MemAdrH
end if;
end if;
end process;
-- Memory write data holding register
process (clk, ctlMsmDwrInDummy)
begin
if clk = '1' and clk'Event then
if ctlMsmDwrInDummy = '1' and -- Epp write cycle
(regEppAdrInDummy(2 downto 0) = RamAutoRW or -- | Any register holding
regEppAdrInDummy(2 downto 0) = FlashAutoRW or-- | data to be written
regEppAdrInDummy(2 downto 0) = MemDataWr) and-- | to memory
ComponentSelect = '1' then
if regMemAdr(0) = '0' then -- even address
regMemWrData(7 downto 0) <= EppWrDataInDummy; -- update lower regMemWrData
else -- odd address
regMemWrData(15 downto 8) <= EppWrDataInDummy; -- update upper regMemWrData
end if;
end if;
end if;
end process;
-- Memory read register: - holds data after an automatic read
process (clk)
begin
if clk = '1' and clk'Event then
if stMsmCur = stMsmDRd02 then -- direct read state
if ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '1' then -- odd address
null; -- should never happen
elsif ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '0' then -- even address
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
regMemRdDataAux <= busMemIn(15 downto 8); -- update auxiliary regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '0' then -- even address
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1' and -- odd address
regEppAdrInDummy(2 downto 0) = RamAutoRW then
regMemRdData <= busMemIn(15 downto 8); -- update regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1' and -- odd address
regEppAdrInDummy(2 downto 0) = FlashAutoRW then
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
end if;
elsif stMsmCur = stMsmBlind then
if ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '1' then -- odd address
regMemRdData <= regMemRdDataAux; -- update regMemRdData
end if;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Memory Control State Machine
------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'Event then
stMsmCur <= stMsmNext;
end if;
end process;
process (stMsmCur)
variable flagMsmCycle: std_logic; -- 1 => Msm cycle requested
variable flagBlindCycle: std_logic; -- 1 => Blind Msm cycle requested:
-- no memory cycle, but either:
-- store the low regMemWrData byte in preparation for a 16 bit write or
-- send the high regMemWrData byte after a 16 bit read cycle
variable flagFlashAutoWr: std_logic;
-- 1 => Flash Auto Write Cycle cycle requested:
begin
if ctlMsmStartInDummy = '1' and -- process launch
ComponentSelect = '1' and -- comp. selected
((regEppAdrInDummy(2 downto 0) = FlashAutoRW) or
(regEppAdrInDummy(2 downto 0) = RamAutoRW)) then
flagMsmCycle := '1';
else
flagMsmCycle := '0';
end if;
if ctlMcrWord = '1' and -- 16 bit mode
((ctlEppRdCycleInDummy = '0' and -- write cycle
regMemAdr(0) = '0') or -- even address
(ctlEppRdCycleInDummy = '1' and -- read cycle
regMemAdr(0) = '1')) then -- odd address
flagBlindCycle := '1';
else
flagBlindCycle := '0';
end if;
if regEppAdrInDummy = FlashAutoRW and -- auto flash cycle requested
ctlEppRdCycleInDummy = '0' then -- write cycle
flagFlashAutoWr := '1';
else
flagFlashAutoWr := '0';
end if;
case stMsmCur is
-- Idle state waiting for the beginning of an EPP cycle
when stMsmReady =>
if flagMsmCycle = '1' then
if flagBlindCycle = '1' then
stMsmNext <= stMsmBlind; -- Blind state
elsif flagFlashAutoWr = '1' then
stMsmNext <= stMsmFwr01; -- Flash auto write (with write cmd)
else
stMsmNext <= stMsmDir01; -- Direct access (without cmds)
end if;
else
stMsmNext <= stMsmReady;
end if;
-- Automatic flash write cont.
when stMsmFwr01 =>
if DelayCnt = "00101" then
stMsmNext <= stMsmFwr02;
else
stMsmNext <= stMsmFwr01;
end if;
when stMsmFwr02 =>
if DelayCnt = "00111" then
stMsmNext <= stMsmFwr03;
else
stMsmNext <= stMsmFwr02;
end if;
when stMsmFwr03 =>
if DelayCnt = "01101" then
stMsmNext <= stMsmFwr04;
else
stMsmNext <= stMsmFwr03;
end if;
when stMsmFwr04 =>
if DelayCnt = "01101" then
stMsmNext <= stMsmFwr05;
else
stMsmNext <= stMsmFwr04;
end if;
when stMsmFwr05 =>
if DelayCnt = "--101" then
if busMemIn(7) = '0' then
stMsmNext <= stMsmFwr06;
else
stMsmNext <= stMsmFwr04;
end if;
else
stMsmNext <= stMsmFwr05;
end if;
when stMsmFwr06 =>
if DelayCnt = "--111" then
stMsmNext <= stMsmFwr07;
else
stMsmNext <= stMsmFwr06;
end if;
when stMsmFwr07 =>
if DelayCnt = "--101" then
if busMemIn(7) = '1' then
stMsmNext <= stMsmAdInc;
else
stMsmNext <= stMsmFwr06;
end if;
else
stMsmNext <= stMsmFwr07;
end if;
-- Direct access cont.
when stMsmDir01 =>
-- if DelayCnt = "---11" then
if ctlEppRdCycleInDummy = '1' then
stMsmNext <= stMsmDRd02; -- Direct write
else
stMsmNext <= stMsmDWr02; -- Direct read
end if;
-- else
-- stMsmNext <= stMsmDir01; -- keep state
-- end if;
-- Direct write
when stMsmDWr02 =>
if DelayCnt = "--000" then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDWr02; -- keep state
end if;
-- Direct read cont.
when stMsmDRd02 =>
if DelayCnt = "--000" then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDRd02; -- keep state
end if;
when stMsmDir03 =>
-- if DelayCnt = "---11" then
stMsmNext <= stMsmAdInc;
-- else
-- stMsmNext <= stMsmDir03; -- keep state
-- end if;
when stMsmAdInc =>
stMsmNext <= stMsmDone;
when stMsmDone =>
if ctlMsmStartInDummy = '1' then
stMsmNext <= stMsmDone;
else
stMsmNext <= stMsmReady;
end if;
-- Automatic flash read cont.
when stMsmBlind =>
stMsmNext <= stMsmAdInc;
-- Unknown states
when others =>
stMsmNext <= stMsmReady;
end case;
end process;
------------------------------------------------------------------------
-- Delay Counter
------------------------------------------------------------------------
process (clk)
begin
if clk'event and clk = '1' then
if stMsmCur = stMsmReady then
DelayCnt <= "00000";
else
DelayCnt <= DelayCnt + 1;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end GC_fifo_top;
architecture xilinx of GC_fifo_top is
SIGNAL clk_i : std_logic;
component GC_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : GC_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
entity foo is end;
architecture bar of foo is
constant TOLER: DISTANCE := 1.5 nm;
constant PI: REAL := 3.141592;
constant CYCLE_TIME: TIME := 100 ns;
constant Propagation_Delay: DELAY_LENGTH;
begin end;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 22,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "22"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "22"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_sync_fifo is
generic(
N : integer := 16;
DEPTH : integer := 4;
D_N : integer := 2
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
oCOUNT : out vl_logic_vector;
iWR_EN : in vl_logic;
iWR_DATA : in vl_logic_vector;
oWR_FULL : out vl_logic;
iRD_EN : in vl_logic;
oRD_DATA : out vl_logic_vector;
oRD_EMPTY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of D_N : constant is 1;
end mist1032sa_sync_fifo;
|
--
-- Copyright 2016 Ognjen Glamocanin
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
port(
clk: in std_logic;
--A1, read chanell 1
raddress1: in std_logic_vector(3 downto 0);
rdata1: out std_logic_vector(31 downto 0);
--A2, read chanell 2
raddress2: in std_logic_vector(3 downto 0);
rdata2: out std_logic_vector(31 downto 0);
--A3, write chanell 1
waddress1: in std_logic_vector(3 downto 0);
wdata1: in std_logic_vector(31 downto 0);
write1: in std_logic
);
end entity register_file;
--REGISTER FILE WITH ASYNCHRONOUS READING
architecture behavioral of register_file is
--R15 IS A ZERO_REGISTER
type reg_file_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal reg_file_s: reg_file_type := (15 => X"00000000", others => X"00000000");
begin
--process modelling writing:
write_reg_file: process (clk) is
begin
if(clk'event and clk='1') then
if(write1 = '1') then
if(conv_integer(waddress1)=15) then
null;
else
reg_file_s(conv_integer(waddress1)) <= wdata1;
end if;
end if;
end if;
end process;
--asynchronous reading:
rdata1 <= reg_file_s(conv_integer(raddress1));
rdata2 <= reg_file_s(conv_integer(raddress2));
end architecture behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Mux_2 is
port(
clk : in vl_logic;
res : in vl_logic;
x : in vl_logic_vector(31 downto 0);
y : in vl_logic_vector(31 downto 0);
en : in vl_logic;
\out\ : out vl_logic_vector(31 downto 0)
);
end Mux_2;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_address_unpack is
port (
addr_pack : in std_logic_vector(31 downto 0);
x_addr : out std_logic_vector(9 downto 0);
y_addr : out std_logic_vector(9 downto 0)
);
end vga_address_unpack;
architecture Behavioral of vga_address_unpack is
begin
x_addr <= addr_pack(9 downto 0);
y_addr <= addr_pack(19 downto 10);
end Behavioral;
|
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : rmii_transceiver
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Receiver / transmitter for RMII
-- TODO: Implement 10 Mbps mode
--
-- NOTE: The receive stream will include the FCS, and also an
-- additional byte, which indicates the correctness of the FCS.
-- This byte will be FF when correct and 00 when incorrect. It
-- coincides with eof. So CRC checking is done, CRC stripping is
-- not. The transmit path appends CRC after receiving the last
-- byte through the stream bus (thus after eof).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_transceiver is
port (
clock : in std_logic; -- 50 MHz reference clock
reset : in std_logic;
rmii_crs_dv : in std_logic;
rmii_rxd : in std_logic_vector(1 downto 0);
rmii_tx_en : out std_logic;
rmii_txd : out std_logic_vector(1 downto 0);
-- stream bus alike interface to MAC
eth_rx_data : out std_logic_vector(7 downto 0);
eth_rx_sof : out std_logic;
eth_rx_eof : out std_logic;
eth_rx_valid : out std_logic;
eth_tx_data : in std_logic_vector(7 downto 0);
eth_tx_eof : in std_logic;
eth_tx_valid : in std_logic;
eth_tx_ready : out std_logic;
-- Mode switch
ten_meg_mode : in std_logic );
end entity;
architecture rtl of rmii_transceiver is
type t_state is (idle, preamble, data0, data1, data2, data3, crc, gap);
signal rx_state : t_state;
signal tx_state : t_state;
signal crs_dv : std_logic;
signal rxd : std_logic_vector(1 downto 0);
signal rx_valid : std_logic;
signal rx_first : std_logic;
signal rx_end : std_logic;
signal rx_shift : std_logic_vector(7 downto 0) := (others => '0');
signal bad_carrier : std_logic;
signal rx_crc_sync : std_logic;
signal rx_crc_dav : std_logic;
signal rx_crc_data : std_logic_vector(3 downto 0) := (others => '0');
signal rx_crc : std_logic_vector(31 downto 0);
signal crc_ok : std_logic;
signal tx_count : natural range 0 to 63;
signal tx_crc_dav : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_data : std_logic_vector(1 downto 0);
signal tx_crc : std_logic_vector(31 downto 0);
begin
p_receive: process(clock)
begin
if rising_edge(clock) then
-- synchronize
crs_dv <= rmii_crs_dv;
rxd <= rmii_rxd;
bad_carrier <= '0';
rx_valid <= '0';
rx_end <= '0';
rx_crc_dav <= '0';
eth_rx_valid <= '0';
if rx_valid = '1' or rx_end = '1' then
eth_rx_eof <= rx_end;
eth_rx_sof <= rx_first;
if rx_end = '1' then
eth_rx_data <= (others => crc_ok);
else
eth_rx_data <= rx_shift;
end if;
eth_rx_valid <= '1';
rx_first <= '0';
end if;
case rx_state is
when idle =>
if crs_dv = '1' then
if rxd = "01" then
rx_state <= preamble;
elsif rxd = "10" then
bad_carrier <= '1';
end if;
end if;
when preamble =>
rx_first <= '1';
if crs_dv = '0' then
rx_state <= idle;
else -- dv = 1
if rxd = "11" then
rx_state <= data0;
elsif rxd = "01" then
rx_state <= preamble;
else
bad_carrier <= '1';
rx_state <= idle;
end if;
end if;
when data0 => -- crs_dv = CRS
rx_shift(1 downto 0) <= rxd;
rx_state <= data1;
when data1 => -- crs_dv = DV
rx_shift(3 downto 2) <= rxd;
rx_state <= data2;
if crs_dv = '0' then
rx_end <= '1';
rx_state <= idle;
else
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(1 downto 0);
end if;
when data2 => -- crs_dv = CRS
rx_shift(5 downto 4) <= rxd;
rx_state <= data3;
when data3 => -- crs_dv = DV
rx_shift(7 downto 6) <= rxd;
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(5 downto 4);
rx_state <= data0;
rx_valid <= '1';
when others =>
null;
end case;
if reset='1' then
eth_rx_sof <= '0';
eth_rx_eof <= '0';
eth_rx_data <= (others => '0');
rx_first <= '0';
rx_state <= idle;
end if;
end if;
end process;
rx_crc_sync <= '1' when rx_state = preamble else '0';
i_receive_crc: entity work.crc32
generic map (
g_data_width => 4
)
port map(
clock => clock,
clock_en => '1',
sync => rx_crc_sync,
data => rx_crc_data,
data_valid => rx_crc_dav,
crc => rx_crc
);
crc_ok <= '1' when (rx_crc = X"2144DF1C") else '0';
p_transmit: process(clock)
begin
if rising_edge(clock) then
case tx_state is
when idle =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if eth_tx_valid = '1' then
tx_state <= preamble;
tx_count <= 13;
end if;
when preamble =>
rmii_tx_en <= '1';
if tx_count = 0 then
rmii_txd <= "11";
tx_state <= data0;
else
rmii_txd <= "01";
tx_count <= tx_count - 1;
end if;
when data0 =>
if eth_tx_valid = '0' then
tx_state <= idle;
rmii_tx_en <= '0';
rmii_txd <= "00";
else
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(1 downto 0);
tx_state <= data1;
end if;
when data1 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(3 downto 2);
tx_state <= data2;
when data2 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(5 downto 4);
tx_state <= data3;
when data3 =>
tx_count <= 15;
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(7 downto 6);
if eth_tx_eof = '1' then
tx_state <= crc;
else
tx_state <= data0;
end if;
when crc =>
rmii_tx_en <= '1';
rmii_txd <= tx_crc(31 - tx_count*2 downto 30 - tx_count*2);
if tx_count = 0 then
tx_count <= 63;
tx_state <= gap;
else
tx_count <= tx_count - 1;
end if;
when gap =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if tx_count = 0 then
tx_state <= idle;
else
tx_count <= tx_count - 1;
end if;
when others =>
null;
end case;
if reset='1' then
rmii_tx_en <= '0';
rmii_txd <= "00";
tx_state <= idle;
end if;
end if;
end process;
eth_tx_ready <= '1' when tx_state = data3 else '0';
tx_crc_sync <= '1' when tx_state = preamble else '0';
with tx_state select tx_crc_data <=
eth_tx_data(1 downto 0) when data0,
eth_tx_data(3 downto 2) when data1,
eth_tx_data(5 downto 4) when data2,
eth_tx_data(7 downto 6) when data3,
"00" when others;
with tx_state select tx_crc_dav <=
'1' when data0 | data1 | data2 | data3,
'0' when others;
i_transmit_crc: entity work.crc32
generic map (
g_data_width => 2
)
port map(
clock => clock,
clock_en => '1',
sync => tx_crc_sync,
data => tx_crc_data,
data_valid => tx_crc_dav,
crc => tx_crc
);
end architecture;
|
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memctrl_pkg.all;
entity toplevel is
port(
mcOp_in : in std_logic_vector(1 downto 0);
a_in : in std_logic;
b_in : in std_logic;
x_out : out std_logic
);
end entity;
architecture behavioural of toplevel is
signal mcOp : MCOpType;
begin
u1: memctrl
port map(
mcOp_in => mcOp,
a_in => a_in,
b_in => b_in,
x_out => x_out
);
mcOp <=
MC_READ when mcOp_in = "01" else
MC_WRITE when mcOp_in = "10" else
MC_NOP;
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr,clk : in std_logic; -- Asynchronous reset and Clock Signal
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic);
end rc5_key;
architecture key_exp of rc5_key is
signal i_cnt : std_logic_vector(04 downto 00); -- s_array counter
signal j_cnt : std_logic_vector(04 downto 00); -- l_array counter
signal r_cnt : std_logic_vector(06 downto 00); -- overall counterer; counts to 78
signal a : std_logic_vector(31 downto 00);
signal a_circ : std_logic_vector(31 downto 00);
signal a_reg : std_logic_vector(31 downto 00); -- register A
signal b : std_logic_vector(31 downto 00);
signal b_circ : std_logic_vector(31 downto 00);
signal b_reg : std_logic_vector(31 downto 00); -- register B
signal temp : std_logic_vector(31 downto 00);
--Key Expansion state machine has five states: idle, key in, expansion and ready
signal state : rc5_key_StateType;
signal l : rc5_rom_4;
signal s : rc5_rom_26;
begin
-- it is not a data-dependent rotation!
--A = S[i] = (S[i] + A + B) <<< 3;
a <= s(conv_integer(i_cnt)) + a_reg + b_reg; --S + A + B
a_circ <= a(28 downto 0) & a(31 downto 29); --rot by 3
-- this is a data-dependent rotation!
--B = L[j] = (L[j] + A + B) <<< (A + B);
b <= l(conv_integer(j_cnt)) + a_circ + b_reg; --L + A + B
-- rot by A + B
temp <= a_circ + b_reg;
with temp(4 downto 0) select
b_circ <= b(30 downto 0) & b(31) when "00001", --01
b(29 downto 0) & b(31 downto 30) when "00010", --02
b(28 downto 0) & b(31 downto 29) when "00011", --03
b(27 downto 0) & b(31 downto 28) when "00100", --04
b(26 downto 0) & b(31 downto 27) when "00101", --05
b(25 downto 0) & b(31 downto 26) when "00110", --06
b(24 downto 0) & b(31 downto 25) when "00111", --07
b(23 downto 0) & b(31 downto 24) when "01000", --08
b(22 downto 0) & b(31 downto 23) when "01001", --09
b(21 downto 0) & b(31 downto 22) when "01010", --10
b(20 downto 0) & b(31 downto 21) when "01011", --11
b(19 downto 0) & b(31 downto 20) when "01100", --12
b(18 downto 0) & b(31 downto 19) when "01101", --13
b(17 downto 0) & b(31 downto 18) when "01110", --14
b(16 downto 0) & b(31 downto 17) when "01111", --15
b(15 downto 0) & b(31 downto 16) when "10000", --16
b(14 downto 0) & b(31 downto 15) when "10001", --17
b(13 downto 0) & b(31 downto 14) when "10010", --18
b(12 downto 0) & b(31 downto 13) when "10011", --19
b(11 downto 0) & b(31 downto 12) when "10100", --20
b(10 downto 0) & b(31 downto 11) when "10101", --21
b(09 downto 0) & b(31 downto 10) when "10110", --22
b(08 downto 0) & b(31 downto 09) when "10111", --23
b(07 downto 0) & b(31 downto 08) when "11000", --24
b(06 downto 0) & b(31 downto 07) when "11001", --25
b(05 downto 0) & b(31 downto 06) when "11010", --26
b(04 downto 0) & b(31 downto 05) when "11011", --27
b(03 downto 0) & b(31 downto 04) when "11100", --28
b(02 downto 0) & b(31 downto 03) when "11101", --29
b(01 downto 0) & b(31 downto 02) when "11110", --30
b(0) & b(31 downto 01) when "11111", --31
b when others;
state_block:
process(clr, clk)
begin
if (clr = '0') then
state <= st_idle;
elsif (rising_edge(clk)) then
case state is
when st_idle =>
if(key_vld = '1') then
state <= st_key_in;
end if;
when st_key_in =>
state <= st_key_exp;
when st_key_exp =>
if (r_cnt = "1001101") then
state <= st_ready;
end if;
when st_ready =>
IF( key_vld='1') THEN -- /= is not equals to
state <= st_key_in; --in event of new key start at key_in
--state otherwise would be a timing issue
--state<=ST_IDLE; --If Input Changes then restart
END IF;
end case;
end if;
end process;
a_reg_block:
process(clr, clk)
begin
if(clr = '0') then
a_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
a_reg <= a_circ;
end if;
end if;
end process;
b_reg_block:
process(clr, clk)
begin
if(clr = '0') then
b_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
b_reg <= b_circ;
end if;
end if;
end process;
s_array_counter_block:
process(clr, clk)
begin
if(clr='0') then i_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(state=ST_KEY_EXP) then
if(i_cnt="11001") then i_cnt <= (others=>'0');
else i_cnt <= i_cnt + 1;
end if;
end if;
end if;
end process;
l_array_counter_block:
process(clr, clk)
begin
if(clr='0') then j_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(j_cnt="00011") then j_cnt<=(others=>'0');
else j_cnt <= j_cnt + 1;
end if;
end if;
end process;
overall_counter_block:
process(clr, clk)
begin
if (clr = '0') then
r_cnt <= "0000000";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
--S[0] = 0xB7E15163 (Pw)
--for i=1 to 25 do S[i] = S[i-1]+ 0x9E3779B9 (Qw)
--array s
process(clr, clk)
begin
if (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";
s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";
s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";
s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";
s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";
s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";
s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";
s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";
s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;--i = (i + 1) mod 26;
end if;
end if;
end process;
--l array
process(clr, clk)
begin
if(clr = '0') then
l(0) <= (others=>'0');
l(1) <= (others=>'0');
l(2) <= (others=>'0');
l(3) <= (others=>'0');
elsif (rising_edge(clk)) then
if(state = st_key_in) then
l(0) <= key(31 downto 0);
l(1) <= key(63 downto 32);
l(2) <= key(95 downto 64);
l(3) <= key(127 downto 96);
elsif(state = st_key_exp) then
l(conv_integer(j_cnt)) <= b_circ; --j = (j + 1) mod 4;
end if;
end if;
end process;
skey <= s;
with state select
key_rdy <= '1' when st_ready,
'0' when others;
end key_exp; |
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- PLAYER CONTROLLER
--------------------------------------------------------------------------------
-- TODO:
-- Remove output clock_o;
-- Define constants/generics instead of magic numbers
-- Change aux_x/aux_y to something more explanatory
--------------------------------------------------------------------------------
entity pc is
generic
(
-- screen limits (follows game resolution)
res_x : integer := 160;
res_y : integer := 120;
-- used to take into account the dimensions of the ship
aux_y : integer := 0;
aux_x : integer := 1;
-- y-position of the player ship
pos_y : integer := 5;
-- clock divider
clock_div : integer := 2
);
port
(
-- input commands for reset or movement
reset_i, enable_i : in std_logic;
-- movement direction ('0' = left, 1' = right)
right_flag_i : in std_logic;
-- clock input
clock_i : in std_logic;
-- player position output
clock_o : out std_logic; -- TODO: remove
position_x_o : buffer integer range 0 to res_x;
position_y_o : out integer range 0 to res_y
);
end entity;
architecture behavior of pc is
-- clock signal for updating x position
signal clock_s : std_logic;
begin
-- counter that generates the clock signal for updating x position
pc_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
-- register: keeps the position of the player ship
pc_movement:
process (reset_i, enable_i,clock_s)
begin
-- asynchronous reset of x coordinate
if reset_i = '1' then
position_x_o <= res_x/2 - aux_x/2;
else
-- move the ship according to right_flag_i input
if rising_edge(clock_s) and enable_i ='1' then
if right_flag_i = '1' then
position_x_o <= position_x_o + 1; -- move right
elsif right_flag_i = '0' then
position_x_o <= position_x_o - 1; -- move left
end if;
-- check boundaries
if position_x_o + aux_x > res_x-5 then
position_x_o <= res_x-aux_x-5;
end if;
if position_x_o < 5 then
position_x_o <= 5;
end if;
end if;
end if;
end process;
-- updates output position with new y-position
position_y_o <= pos_y + aux_y/2;
end architecture;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2010 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Feb 18, 2010
-- Design Name: IVK
-- Module Name: ivk_video_det.vhd
-- Project Name: IVK
-- Target Devices: Spartan-6
-- Avnet Boards: IVK
--
-- Tool versions: ISE 12.1
--
-- Description:
--
-- Dependencies:
--
-- Revision: Feb 18, 2010: 1.01 Initial version
-- Mar 02, 2010: 1.02 Add optionnal VDMA Write Port
-- Mar 10, 2010: 1.04 Force FSYNC to active high polarity
-- Apr 13, 2010: 1.05 Add support for 16bit data width on XSVI input
-- May 14, 2010: 2.01 Update for 12.1
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library ivk_video_det_v2_01_a;
use ivk_video_det_v2_01_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity ivk_video_det is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_GEN_FSYNC : integer := 0;
C_GEN_XSVI_OUT : integer := 1;
C_GEN_WD_VDMA : integer := 0;
--C_VIDEO_INTERFACE : integer := 0;
C_XSVII_DATA_WIDTH : integer := 24;
C_XSVIO_DATA_WIDTH : integer := 24;
C_VDMA_DATA_WIDTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "spartan6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
-- Global Reset (asynchronous)
reset : in std_logic;
clk : in std_logic;
-- XSVI Input Port
xsvi_vsync_i : in std_logic;
xsvi_hsync_i : in std_logic;
xsvi_vblank_i : in std_logic;
xsvi_hblank_i : in std_logic;
xsvi_active_video_i : in std_logic;
xsvi_video_data_i : in std_logic_vector((C_XSVII_DATA_WIDTH-1) downto 0);
-- XSVI Output Port
xsvi_vsync_o : out std_logic;
xsvi_hsync_o : out std_logic;
xsvi_vblank_o : out std_logic;
xsvi_hblank_o : out std_logic;
xsvi_active_video_o : out std_logic;
xsvi_video_data_o : out std_logic_vector((C_XSVIO_DATA_WIDTH-1) downto 0);
-- VDMA Write Port
--vdma_wcmd_clk : out std_logic;
vdma_wd_clk : out std_logic;
vdma_wd_write : out std_logic;
vdma_wd_data : out std_logic_vector((C_VDMA_DATA_WIDTH-1) downto 0);
vdma_wd_data_be : out std_logic_vector(((C_VDMA_DATA_WIDTH/8)-1) downto 0);
-- Frame Sync Output Port
fsync_o : out std_logic;
-- Debug Ports
debug1_o : out std_logic_vector((5+C_XSVII_DATA_WIDTH-1) downto 0);
debug2_o : out std_logic_vector(31 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity ivk_video_det;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of ivk_video_det is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity ivk_video_det_v2_01_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_GEN_FSYNC => C_GEN_FSYNC,
C_GEN_XSVI_OUT => C_GEN_XSVI_OUT,
C_GEN_WD_VDMA => C_GEN_WD_VDMA,
--C_VIDEO_INTERFACE => C_VIDEO_INTERFACE,
C_XSVII_DATA_WIDTH => C_XSVII_DATA_WIDTH,
C_XSVIO_DATA_WIDTH => C_XSVIO_DATA_WIDTH,
C_VDMA_DATA_WIDTH => C_VDMA_DATA_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_FAMILY => C_FAMILY
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
-- Global Reset (asynchronous)
reset => reset,
clk => clk,
-- XSVI Input Port
xsvi_vsync_i => xsvi_vsync_i,
xsvi_hsync_i => xsvi_hsync_i,
xsvi_vblank_i => xsvi_vblank_i,
xsvi_hblank_i => xsvi_hblank_i,
xsvi_active_video_i => xsvi_active_video_i,
xsvi_video_data_i => xsvi_video_data_i,
-- XSVI Output Port
xsvi_vsync_o => xsvi_vsync_o,
xsvi_hsync_o => xsvi_hsync_o,
xsvi_vblank_o => xsvi_vblank_o,
xsvi_hblank_o => xsvi_hblank_o,
xsvi_active_video_o => xsvi_active_video_o,
xsvi_video_data_o => xsvi_video_data_o,
-- VDMA Write Port
--vdma_wcmd_clk => vdma_wcmd_clk,
vdma_wd_clk => vdma_wd_clk,
vdma_wd_write => vdma_wd_write,
vdma_wd_data => vdma_wd_data,
vdma_wd_data_be => vdma_wd_data_be,
-- Frame Sync Output Port
fsync_o => fsync_o,
-- Debug Ports
debug1_o => debug1_o,
debug2_o => debug2_o,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end rtl;
|
-- file : boutons.vhdl
-- created : sam. oct. 30 18:56:10 CEST 2010 par [email protected]
-- This package wraps a single C function that reads the parallel
-- printer port's status lines (pins 10 to 13 of the DB25 connector)
--
-- compile with :
-- $ gcc -c boutons.c -o boutons_c.o
-- $ ghdl -a boutons.vhdl
-- $ ghdl -e -Wl,boutons_c.o boutons
-- run with :
-- $ ./passport $PWD/boutons
--
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee; use ieee.std_logic_1164.all;
package boutons is
procedure lecture_boutons (bouton1, bouton2, bouton3, bouton4: out std_ulogic);
attribute foreign of lecture_boutons :
procedure is "VHPIDIRECT lecture_boutons";
end boutons;
package body boutons is
procedure lecture_boutons (bouton1, bouton2, bouton3, bouton4: out std_ulogic) is
begin
assert false report "VHPI" severity failure;
end lecture_boutons;
end boutons;
--------------------------------------------------------------------
library work; use work.boutons.all;
library ieee; use ieee.std_logic_1164.all;
entity test_boutons is
end test_boutons;
architecture test of test_boutons is
begin
process
variable b1, b2, b3, b4 : std_ulogic;
begin
-- affiche et modifie les variables :
lecture_boutons(b1, b2, b3, b4);
-- affiche les variables modifiées :
report "b1:" & std_ulogic'image(b1)
& " b2:" & std_ulogic'image(b2)
& " b3:" & std_ulogic'image(b3)
& " b4:" & std_ulogic'image(b4);
wait;
end process;
end test;
|
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2121.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02121ent IS
END c07s02b04x00p20n01i02121ent;
ARCHITECTURE c07s02b04x00p20n01i02121arch OF c07s02b04x00p20n01i02121ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_8 is character_v (1 to 8);
SUBTYPE character_4 is character_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : character_4;
variable l_operand : character_4 := ('A','z','A','z');
variable r_operand : character_4 := ('z','z','A','A');
alias l_alias : character_v (1 to 2) is l_operand (2 to 3);
alias r_alias : character_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ('z','A','A','A')) and (result(1)='z'))
report "***PASSED TEST: c07s02b04x00p20n01i02121"
severity NOTE;
assert ((result = ('z','A','A','A')) and (result(1)='z'))
report "***FAILED TEST: c07s02b04x00p20n01i02121 - Concatenation of two CHARACTER aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02121arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2121.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02121ent IS
END c07s02b04x00p20n01i02121ent;
ARCHITECTURE c07s02b04x00p20n01i02121arch OF c07s02b04x00p20n01i02121ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_8 is character_v (1 to 8);
SUBTYPE character_4 is character_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : character_4;
variable l_operand : character_4 := ('A','z','A','z');
variable r_operand : character_4 := ('z','z','A','A');
alias l_alias : character_v (1 to 2) is l_operand (2 to 3);
alias r_alias : character_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ('z','A','A','A')) and (result(1)='z'))
report "***PASSED TEST: c07s02b04x00p20n01i02121"
severity NOTE;
assert ((result = ('z','A','A','A')) and (result(1)='z'))
report "***FAILED TEST: c07s02b04x00p20n01i02121 - Concatenation of two CHARACTER aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02121arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2121.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02121ent IS
END c07s02b04x00p20n01i02121ent;
ARCHITECTURE c07s02b04x00p20n01i02121arch OF c07s02b04x00p20n01i02121ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_8 is character_v (1 to 8);
SUBTYPE character_4 is character_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : character_4;
variable l_operand : character_4 := ('A','z','A','z');
variable r_operand : character_4 := ('z','z','A','A');
alias l_alias : character_v (1 to 2) is l_operand (2 to 3);
alias r_alias : character_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ('z','A','A','A')) and (result(1)='z'))
report "***PASSED TEST: c07s02b04x00p20n01i02121"
severity NOTE;
assert ((result = ('z','A','A','A')) and (result(1)='z'))
report "***FAILED TEST: c07s02b04x00p20n01i02121 - Concatenation of two CHARACTER aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02121arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(15 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(63 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(7 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(15 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 3,
C_FLUSH_ON_FSYNC => 3,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 16,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 4096,
C_MM2S_LINEBUFFER_THRESH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 16,
C_INCLUDE_S2MM_DRE => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 4096,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Using aliases to protected type methods cause an exception.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue 1:
-- When analyzed in VHDL-93 mode an error is reported:
-- .\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93
-- .\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'
-- Line 1 is perfectly clear, but what is the intension of line 2?
-- Is this follow up error necessary or should it have another message text?
--
-- Issue 2:
-- Calling an aliases to a shared variable's method causes an exception in GHDL:
-- ******************** GHDL Bug occured ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-01-27; git branch: paebbels/master'; hash: d424eb8) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: trans.adb:487
-- ******************************************************************
-- The alias definition by itself is not causing any errors. In my big example, I
-- could at least use an alias to a procedure without parameters. This short example
-- throws exceptions on all 4 variants (with/without parameter; with/without return value).
--
-- You can comment/uncomment the alias/wrapping function/procedure to cause the error.
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl
-- PS> ghdl.exe -r --std=08 test
--
-- Expected output:
-- .\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet: 7 expected: 7
-- .\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet: 3 expected: 3
-- .\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet: 0 expected: 0
--
-- =============================================================================
-- Protected type package
-- =============================================================================
package pkg is
type T_INTEGER is protected
procedure Clear;
procedure Set(Value : INTEGER);
impure function Get return INTEGER;
impure function Exchange(Value : INTEGER) return INTEGER;
end protected;
end package;
package body pkg is
type T_INTEGER is protected body
variable LocalVariable : INTEGER := 7;
procedure Clear is
begin
LocalVariable := 0;
end procedure;
procedure Set(Value : INTEGER) is
begin
LocalVariable := Value;
end procedure;
impure function Get return INTEGER is
begin
return LocalVariable;
end function;
impure function Exchange(Value : INTEGER) return INTEGER is
variable Result : INTEGER;
begin
Result := LocalVariable;
LocalVariable := Value;
return Result;
end function;
end protected body;
end package body;
-- =============================================================================
-- Wrapper package
-- =============================================================================
use work.pkg.all;
package wrapper is
shared variable MyBoolean : T_INTEGER;
-- alias wrapClear is MyBoolean.Clear[]; -- if this alias is used, GHDL crashes
alias wrapperClear is MyBoolean.Clear[]; -- unused alias => no crash
procedure wrapClear; -- wrapped by a call chain => no crash
-- alias wrapSet is MyBoolean.Set[INTEGER];
procedure wrapSet(Value : INTEGER);
-- alias wrapGet is MyBoolean.Get[return INTEGER];
impure function wrapGet return INTEGER;
-- alias wrapExchange is MyBoolean.Exchange[INTEGER return INTEGER];
impure function wrapExchange(Value : INTEGER) return INTEGER;
end package;
package body wrapper is
procedure wrapClear is
begin
MyBoolean.Clear;
end procedure;
procedure wrapSet(Value : INTEGER) is
begin
MyBoolean.Set(Value);
end procedure;
impure function wrapGet return INTEGER is
begin
return MyBoolean.Get;
end function;
impure function wrapExchange(Value : INTEGER) return INTEGER is
begin
return MyBoolean.Exchange(Value);
end function;
end package body;
-- =============================================================================
-- Testbench
-- =============================================================================
use work.wrapper.all;
entity test is
end entity;
architecture tb of test is
begin
process
begin
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 7" severity NOTE;
wrapSet(5);
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 5" severity NOTE;
report "wrapExcahnge: " & INTEGER'image(wrapExchange(3)) & " expected: 5" severity NOTE;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 3" severity NOTE;
wrapperClear;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 0" severity NOTE;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- file name : sip_router_async_s1d2_x4_b_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -sip_router_async_s1d2_x4_b_stellar_cmd
-- arch_itecture - arch_sip_router_async_s1d2_x4_b_stellar_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- specify libraries.
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------------------------
-- entity declaration
--------------------------------------------------------------------------------
entity sip_router_async_s1d2_x4_b_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port
(
reset :in std_logic;
--command if
clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
--register interface
clk_reg :in std_logic; --register interface is synchronous to this clock
out_reg :out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val :out std_logic; --the out_reg has valid data (pulse)
out_reg_addr :out std_logic_vector(27 downto 0);--out register address
in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val :in std_logic; --pulse to indicate requested register is valid
in_reg_req :out std_logic; --pulse to request data
in_reg_addr :out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_out_val :out std_logic;
mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val :in std_logic --pulse to indicate mailbox is valid
);
end entity sip_router_async_s1d2_x4_b_stellar_cmd ;
--------------------------------------------------------------------------------
-- arch_itecture declaration
--------------------------------------------------------------------------------
architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd of sip_router_async_s1d2_x4_b_stellar_cmd is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0";
constant cmd_rd :std_logic_vector(3 downto 0) :=x"2";
constant cmd_wr :std_logic_vector(3 downto 0) :=x"1";
constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4";
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal register_wr :std_logic;
signal register_rd :std_logic;
signal out_cmd_val_sig :std_logic;
signal in_reg_addr_sig :std_logic_vector(27 downto 0);
signal mbx_in_val_sig :std_logic;
signal mbx_received :std_logic;
signal mbx_out_val_sig :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end component;
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_wr,
inbusy =>open,
pulseout =>out_reg_val
);
p2p1: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_rd,
inbusy =>open,
pulseout =>in_reg_req
);
p2p2: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>in_reg_val,
inbusy =>open,
pulseout =>out_cmd_val_sig
);
p2p3: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>mbx_in_val,
inbusy =>open,
pulseout =>mbx_in_val_sig
);
p2p4: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg ,
rst =>reset,
pulsein =>mbx_out_val_sig,
inbusy =>open,
pulseout =>mbx_out_val
);
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then
mbx_received <= '1';
elsif( mbx_received ='1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig='1') then
out_cmd(31 downto 0) <=in_reg;
out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr;
out_cmd(63 downto 60)<=cmd_rd_ack;
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd(31 downto 0) <=mbx_in_reg;
out_cmd(59 downto 32)<=start_addr;
out_cmd(63 downto 60)<=cmd_mbx;
else
out_cmd(63 downto 0)<=(others=>'0');
end if;
if (out_cmd_val_sig='1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
out_reg_addr <= in_cmd(59 downto 32)-start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then
mbx_out_reg <= in_cmd(31 downto 0);
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then
mbx_out_val_sig <= '1';
else
mbx_out_val_sig <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
end architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd ; -- of sip_router_async_s1d2_x4_b_stellar_cmd
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k2_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_k3_k2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k3_k2_rtl_conf / inst_k3_k2_e
--
configuration inst_k3_k2_rtl_conf of inst_k3_k2_e is
for rtl
-- Generated Configuration
end for;
end inst_k3_k2_rtl_conf;
--
-- End of Generated Configuration inst_k3_k2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: car_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : car.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 6000
-- C_READ_DEPTH_A : 6000
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 6000
-- C_READ_DEPTH_B : 6000
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY car_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END car_prod;
ARCHITECTURE xilinx OF car_prod IS
COMPONENT car_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : car_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_bb
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_bb-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_bb-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_bb
--
entity ent_bb is
-- Generics:
-- No Generated Generics for Entity ent_bb
-- Generated Port Declaration:
-- No Generated Port for Entity ent_bb
end ent_bb;
--
-- End of Generated Entity ent_bb
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- --------------------------------------------------------------------
--
-- Copyright 2002 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE [Draft] Standard 1076.3
-- reduce_pkg
-- This source file may not be copied, sold, or included
-- with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this
-- [draft] standard and may be distributed in compiled form in any manner so
-- long as the compiled form does not allow direct decompilation of the
-- original source file. This source file may be copied for individaul use
-- between licensed users.
--
-- The IEEE disclaims any responsibility or liability for damages resulting
-- from misinterpretation or misue of said information by the user.
--
-- [This source file represents a portion of the IEEE Draft Standard and is
-- unapproved and subject to change.]
--
-- < statement about permission to modify >
--
-- Title : REDUCE_PKG < IEEE std # 1076.3 >
--
-- Library : This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL/Synthesis, PAR 1076.3
--
-- Purpose : Reduction operations. This allows a vector to
-- be collapsed into a signle bit. Similar to the built
-- in functions in Verilog.
--
-- Limitation:
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 1.3
-- Date : 8 July 2002
-- Added "to_x01" on all inputs.
-- Made "and_reduce" return a "1" in the NULL case.
-- -------------------------------------------------------------------------
-- Version: 1.2
-- Date : 21 June 2002
-- Fixed some basic logic errors.
-- -------------------------------------------------------------------------
-- Version: 1.1
-- Date : 13 May 2002
-- Modified to deal with null arrays, added IEEE header.
-- -------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- Package definition
package reduce_pack is
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- bit_vector versions
FUNCTION and_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
end reduce_pack;
-- Package body.
package body reduce_pack is
-- done in a recursively called function.
function and_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '1'; -- Change for version 1.3
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) and BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper and Lower;
end if;
end if;
return Result;
end;
function nand_reduce (arg : std_logic_vector )
return std_logic is
begin
return not and_reduce (arg);
end;
function or_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) or BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper or Lower;
end if;
end if;
return Result;
end;
function nor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not or_reduce ( arg );
end;
function xor_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper xor Lower;
end if;
end if;
return Result;
end;
function xnor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not xor_reduce ( arg );
end;
function and_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : SIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : UNSIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : SIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : UNSIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : SIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : UNSIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : SIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : UNSIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : SIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : SIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : bit_vector )
return bit is
begin
return to_bit (and_reduce (to_stdlogicvector ( arg )));
end;
function nand_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nand_reduce (to_stdlogicvector ( arg )));
end;
function or_reduce (arg : bit_vector )
return bit is
begin
return to_bit (or_reduce (to_stdlogicvector ( arg )));
end;
function nor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nor_reduce (to_stdlogicvector ( arg )));
end;
function xor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xor_reduce (to_stdlogicvector ( arg )));
end;
function xnor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xnor_reduce (to_stdlogicvector ( arg )));
end;
end reduce_pack;
|
library verilog;
use verilog.vl_types.all;
entity Testbench is
end Testbench;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_ofdm_tx_tc.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_ofdm_tx_tc
-- Source Path: hdl_ofdm_tx_tc
-- Hierarchy Level: 1
--
-- Master clock enable input: clk_enable
--
-- enb : identical to clk_enable
-- enb_1_1_1 : identical to clk_enable
-- enb_1_16_0 : 16x slower than clk with last phase
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY hdl_ofdm_tx_tc IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
enb : OUT std_logic;
enb_1_1_1 : OUT std_logic;
enb_1_16_0 : OUT std_logic
);
END hdl_ofdm_tx_tc;
ARCHITECTURE rtl OF hdl_ofdm_tx_tc IS
-- Signals
SIGNAL count16 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL phase_all : std_logic;
SIGNAL phase_0 : std_logic;
SIGNAL phase_0_tmp : std_logic;
BEGIN
Counter16 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
count16 <= to_unsigned(1, 4);
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
IF count16 >= to_unsigned(15, 4) THEN
count16 <= to_unsigned(0, 4);
ELSE
count16 <= count16 + to_unsigned(1, 4);
END IF;
END IF;
END IF;
END PROCESS Counter16;
phase_all <= '1' WHEN clk_enable = '1' ELSE '0';
temp_process1 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
phase_0 <= '0';
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
phase_0 <= phase_0_tmp;
END IF;
END IF;
END PROCESS temp_process1;
phase_0_tmp <= '1' WHEN count16 = to_unsigned(15, 4) AND clk_enable = '1' ELSE '0';
enb <= phase_all AND clk_enable;
enb_1_1_1 <= phase_all AND clk_enable;
enb_1_16_0 <= phase_0 AND clk_enable;
END rtl;
|
entity bounds38 is
end entity;
architecture test of bounds38 is
type int_vec_2d is array (natural range <>, natural range <>) of integer;
function double (x : in int_vec_2d) return int_vec_2d is
variable result : int_vec_2d(x'range(2), x'range(1));
variable sum : integer;
begin
for i in result'range(1) loop
for j in result'range(2) loop
result(i, j) := x(i, j) * 2; -- Error
end loop;
end loop;
return result;
end function;
signal s3, s4 : int_vec_2d(1 to 2, 5 to 7) := (others => (others => 0));
begin
p2: s4 <= double(s3);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TB_ALLINALL is
end entity TB_ALLINALL;
architecture TB_ALLINALL_BODY of TB_ALLINALL is
component ALLINALL is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
JCHYBA : out std_logic; -- detekovano s 1 chybou
SHODA : out std_logic -- detekovana uplna shoda
);
end component;
signal T_PS2_DATA, T_PS2_CLK, T_CLK, T_RESET, T_JCHYBA, T_SHODA : std_logic;
signal TS1, TS2, TS3, TS4 : std_logic_vector(7 downto 0); -- testove data
begin
UUT : ALLINALL port map (PS2_DATA => T_PS2_DATA, PS2_CLK => T_PS2_CLK, RESET => T_RESET,
JCHYBA => T_JCHYBA, SHODA => T_SHODA, CLK => T_CLK);
-- hodiny
HOD : process
begin
T_CLK <= '0';
wait for 10 ns;
T_CLK <= '1';
wait for 10 ns;
end process;
RES : process
begin
T_RESET <= '1';
wait for 100 ns;
T_RESET <= '0';
wait;
end process;
TESTOVANI : process
procedure TEST (TS: in std_logic_vector(7 downto 0)) is
begin
T_PS2_DATA <= '1';
T_PS2_CLK <= '1';
--T_RESET <= '1';
--wait for 100 ns;
--T_RESET <= '0';
wait for 20 us;
-- pocatecni bit
T_PS2_DATA <= '0';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- data bity
for I in 0 to 7 loop
T_PS2_DATA <= TS(I);
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
end loop;
-- paritni bit
T_PS2_DATA <= '1';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- stop bit
T_PS2_DATA <= '1';
wait for 10 us;
T_PS2_CLK <= '0';
wait for 40 us;
T_PS2_CLK <= '1';
wait for 30 us;
-- overujeme, jestli se nastavil KEY_PRESS
--assert not T_KEY_PRESS'stable(100 us) report "chybne nastaven KEY_PRESS" severity error;
end procedure;
begin
TS1 <= "00101011"; -- F
TS2 <= "00111100"; -- U
TS3 <= "01001011"; -- L
TS4 <= "00111010"; -- M
-- vysilame KEY F
TEST(TS1);
wait for 1 ms;
-- vysilame KEY U
TEST(TS2);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 5 ms;
assert T_SHODA = '1' report "neni detekovana shoda" severity error;
-- vysilame KEY F
TEST(TS1);
wait for 1 ms;
-- vysilame KEY U
TEST(TS2);
wait for 1 ms;
-- vysilame KEY M
TEST(TS4);
wait for 1 ms;
-- vysilame KEY L
TEST(TS3);
wait for 5 ms;
assert T_JCHYBA <= '1' report "neni detekovana jedna chyba" severity error;
wait;
end process;
end architecture; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity my_video_filter_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
width :out STD_LOGIC_VECTOR(15 downto 0);
height :out STD_LOGIC_VECTOR(15 downto 0)
);
end entity my_video_filter_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of my_video_filter_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#10#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#14#;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#18#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#1c#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_width : UNSIGNED(15 downto 0);
signal int_height : UNSIGNED(15 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
width <= STD_LOGIC_VECTOR(int_width);
height <= STD_LOGIC_VECTOR(int_height);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity my_video_filter_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
width :out STD_LOGIC_VECTOR(15 downto 0);
height :out STD_LOGIC_VECTOR(15 downto 0)
);
end entity my_video_filter_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of my_video_filter_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#10#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#14#;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#18#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#1c#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_width : UNSIGNED(15 downto 0);
signal int_height : UNSIGNED(15 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
width <= STD_LOGIC_VECTOR(int_width);
height <= STD_LOGIC_VECTOR(int_height);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if there is a change in state then D_SET will be set to a high
input_monitor: process (CLK)
begin
if (CLK'event and CLK = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- uart.vhd
-- VHDL do circuito da UART
library ieee;
use ieee.std_logic_1164.all;
entity uart is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
transmite_dado: in std_logic;
dado_trans: in std_logic_vector(6 downto 0);
saida: out std_logic;
dado_rec: out std_logic_vector(6 downto 0);
tem_dado_rec: out std_logic;
transm_andamento: out std_logic;
fim_transmissao: out std_logic
);
end uart;
architecture estrutural of uart is
component transmissao_serial is
port(
clock: in std_logic;
reset: in std_logic;
transmite_dado: in std_logic;
dados_trans: in std_logic_vector(6 downto 0);
saida: out std_logic;
fim_transmissao: out std_logic;
transmissao_andamento: out std_logic;
depuracao_tick: out std_logic
);
end component;
component recepcao_serial is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
dado_rec: out std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dep_paridade_ok: out std_logic;
dep_tick_rx: out std_logic;
dep_estados: out std_logic_vector(5 downto 0);
dep_habilita_recepcao: out std_logic
);
end component;
signal sinal_dado_rec: std_logic_vector(11 downto 0);
begin
transmissao: transmissao_serial port map (clock, reset, transmite_dado, dado_trans, saida, fim_transmissao, transm_andamento, open);
recepcao: recepcao_serial port map(clock, reset, entrada, recebe_dado, sinal_dado_rec, tem_dado_rec, open, open, open, open);
dado_rec <= sinal_dado_rec(8 downto 2);
--display_1: hex7seg_en port map(sinal_dado_rec(5), sinal_dado_rec(4), sinal_dado_rec(3), sinal_dado_rec(2), '1', dado_rec(0), dado_rec(1), dado_rec(2), dado_rec(3), dado_rec(4), dado_rec(5), dado_rec(6));
--display_2: hex7seg_en port map('0', sinal_dado_rec(8), sinal_dado_rec(7), sinal_dado_rec(6), '1', dado_rec(7), dado_rec(8), dado_rec(9), dado_rec(10), dado_rec(11), dado_rec(12), dado_rec(13));
end estrutural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:32:44 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.2 2005/07/15 16:20:08 wig Exp $
-- $Date: 2005/07/15 16:20:08 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:08 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
s_open_i : in std_ulogic;
s_open_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
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