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-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_1_stub.vhdl
-- Design : zqynq_lab_1_design_auto_pc_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
begin
end;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_ctrl_regs IS
END tb_ctrl_regs;
ARCHITECTURE behavior OF tb_ctrl_regs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl_regs
PORT(
Clk : IN std_logic;
PktIn : IN std_logic;
DataIn : IN std_logic_vector(7 downto 0);
PktOut : OUT std_logic;
DataOut : OUT std_logic_vector(7 downto 0);
Regs : OUT std_logic_vector(79 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut : std_logic;
signal DataOut : std_logic_vector(7 downto 0);
signal Regs : std_logic_vector(79 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl_regs PORT MAP (
Clk => Clk,
PktIn => PktIn,
DataIn => DataIn,
PktOut => PktOut,
DataOut => DataOut,
Regs => Regs
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 200 ns;
PktIn <= '1';
wait for Clk_period * 8;
for i in 1 to 1 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
DataIn <= X"00";
wait for Clk_period * 7;
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2188.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02188ent IS
END c07s02b00x00p01n02i02188ent;
ARCHITECTURE c07s02b00x00p01n02i02188arch OF c07s02b00x00p01n02i02188ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 3;
constant b : integer := 5;
variable c : integer;
BEGIN
c := a/-b; -- Failure_here
-- signed operator cannot follow /.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02188 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02188arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2188.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02188ent IS
END c07s02b00x00p01n02i02188ent;
ARCHITECTURE c07s02b00x00p01n02i02188arch OF c07s02b00x00p01n02i02188ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 3;
constant b : integer := 5;
variable c : integer;
BEGIN
c := a/-b; -- Failure_here
-- signed operator cannot follow /.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02188 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02188arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2188.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02188ent IS
END c07s02b00x00p01n02i02188ent;
ARCHITECTURE c07s02b00x00p01n02i02188arch OF c07s02b00x00p01n02i02188ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 3;
constant b : integer := 5;
variable c : integer;
BEGIN
c := a/-b; -- Failure_here
-- signed operator cannot follow /.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02188 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02188arch;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component FIFO;
component fifo is
end component Fifo;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00441ent IS
END c03s02b01x01p19n01i00441ent;
ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
function complex_scalar(s : record_cons_arrayofarray) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_arrayofarray is
begin
return C53;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_arrayofarray;
signal S2 : record_cons_arrayofarray;
signal S3 : record_cons_arrayofarray := C53;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C53) and (S2 = C53))
report "***PASSED TEST: c03s02b01x01p19n01i00441"
severity NOTE;
assert ((S1 = C53) and (S2 = C53))
report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00441arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00441ent IS
END c03s02b01x01p19n01i00441ent;
ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
function complex_scalar(s : record_cons_arrayofarray) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_arrayofarray is
begin
return C53;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_arrayofarray;
signal S2 : record_cons_arrayofarray;
signal S3 : record_cons_arrayofarray := C53;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C53) and (S2 = C53))
report "***PASSED TEST: c03s02b01x01p19n01i00441"
severity NOTE;
assert ((S1 = C53) and (S2 = C53))
report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00441arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00441ent IS
END c03s02b01x01p19n01i00441ent;
ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
function complex_scalar(s : record_cons_arrayofarray) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_arrayofarray is
begin
return C53;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_arrayofarray;
signal S2 : record_cons_arrayofarray;
signal S3 : record_cons_arrayofarray := C53;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C53) and (S2 = C53))
report "***PASSED TEST: c03s02b01x01p19n01i00441"
severity NOTE;
assert ((S1 = C53) and (S2 = C53))
report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00441arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_8K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (12 downto 0);
D_uP : in std_logic_vector (7 downto 0);
Q_uP : out std_logic_vector (7 downto 0));
end RAM_8K;
architecture BEHAVIORAL of RAM_8K is
type ram_type is array (8191 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (8191 downto 0 => X"ff");
attribute RAM_STYLE : string;
attribute RAM_STYLE of RAM : signal is "BLOCK";
begin
process (clk)
begin
if rising_edge(clk) then
if (we_UP = '1' and ce = '1') then
RAM(conv_integer(addr_uP(12 downto 0))) <= D_up;
end if;
Q_up <= RAM(conv_integer(addr_uP(12 downto 0)));
end if;
end process;
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_8K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (12 downto 0);
D_uP : in std_logic_vector (7 downto 0);
Q_uP : out std_logic_vector (7 downto 0));
end RAM_8K;
architecture BEHAVIORAL of RAM_8K is
type ram_type is array (8191 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type := (8191 downto 0 => X"ff");
attribute RAM_STYLE : string;
attribute RAM_STYLE of RAM : signal is "BLOCK";
begin
process (clk)
begin
if rising_edge(clk) then
if (we_UP = '1' and ce = '1') then
RAM(conv_integer(addr_uP(12 downto 0))) <= D_up;
end if;
Q_up <= RAM(conv_integer(addr_uP(12 downto 0)));
end if;
end process;
end BEHAVIORAL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity timer is
port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
terminal rc_ext : electrical );
end entity timer;
----------------------------------------------------------------
architecture behavioral of timer is
constant half_vdd : real := 2.5;
constant clamp_on_resistance : real := 0.01;
constant clamp_off_resistance : real := 10.0E6;
quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
signal q_n : std_ulogic := '1';
begin
if q_n = '1' use
i_clamp == v_rc_ext / clamp_on_resistance;
else
i_clamp == v_rc_ext / clamp_off_resistance;
end use;
timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
begin
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
end if;
end process timer_state;
clamp_change : process ( q_n ) is
begin
break;
end process clamp_change;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity timer is
port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
terminal rc_ext : electrical );
end entity timer;
----------------------------------------------------------------
architecture behavioral of timer is
constant half_vdd : real := 2.5;
constant clamp_on_resistance : real := 0.01;
constant clamp_off_resistance : real := 10.0E6;
quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
signal q_n : std_ulogic := '1';
begin
if q_n = '1' use
i_clamp == v_rc_ext / clamp_on_resistance;
else
i_clamp == v_rc_ext / clamp_off_resistance;
end use;
timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
begin
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
end if;
end process timer_state;
clamp_change : process ( q_n ) is
begin
break;
end process clamp_change;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity timer is
port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
terminal rc_ext : electrical );
end entity timer;
----------------------------------------------------------------
architecture behavioral of timer is
constant half_vdd : real := 2.5;
constant clamp_on_resistance : real := 0.01;
constant clamp_off_resistance : real := 10.0E6;
quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
signal q_n : std_ulogic := '1';
begin
if q_n = '1' use
i_clamp == v_rc_ext / clamp_on_resistance;
else
i_clamp == v_rc_ext / clamp_off_resistance;
end use;
timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
begin
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
end if;
end process timer_state;
clamp_change : process ( q_n ) is
begin
break;
end process clamp_change;
end architecture behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_4;
USE fifo_generator_v13_1_4.fifo_generator_v13_1_4;
ENTITY fifo_bt_txd IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_bt_txd;
ARCHITECTURE fifo_bt_txd_arch OF fifo_bt_txd IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_bt_txd_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_4 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_bt_txd_arch: ARCHITECTURE IS "fifo_generator_v13_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_bt_txd_arch : ARCHITECTURE IS "fifo_bt_txd,fifo_generator_v13_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_bt_txd_arch: ARCHITECTURE IS "fifo_bt_txd,fifo_generator_v13_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_ME" &
"MINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THR" &
"ESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERF" &
"ACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WID" &
"TH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYP" &
"E_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_E" &
"RROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10" &
",C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=10" &
"23,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSE" &
"RT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_4
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_bt_txd_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
use work.issue_pkg."=";
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = work.issue_pkg.one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
use work.issue_pkg."=";
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = work.issue_pkg.one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with 2 bit select.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4x1 is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
B : in STD_LOGIC_VECTOR (9 downto 0);
C : in STD_LOGIC_VECTOR (9 downto 0);
D : in STD_LOGIC_VECTOR (9 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
X : out STD_LOGIC_VECTOR (9 downto 0));
end Mux4x1;
architecture Behavioral of Mux4x1 is
begin
with SEL select X <=
A when "00",
B when "01",
C when "10",
D when "11",
A when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with 2 bit select.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4x1 is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
B : in STD_LOGIC_VECTOR (9 downto 0);
C : in STD_LOGIC_VECTOR (9 downto 0);
D : in STD_LOGIC_VECTOR (9 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
X : out STD_LOGIC_VECTOR (9 downto 0));
end Mux4x1;
architecture Behavioral of Mux4x1 is
begin
with SEL select X <=
A when "00",
B when "01",
C when "10",
D when "11",
A when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with 2 bit select.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4x1 is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
B : in STD_LOGIC_VECTOR (9 downto 0);
C : in STD_LOGIC_VECTOR (9 downto 0);
D : in STD_LOGIC_VECTOR (9 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
X : out STD_LOGIC_VECTOR (9 downto 0));
end Mux4x1;
architecture Behavioral of Mux4x1 is
begin
with SEL select X <=
A when "00",
B when "01",
C when "10",
D when "11",
A when others;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity aggr02 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end aggr02;
architecture behav of aggr02 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
begin
res := (0 => '0', others => '1');
return res;
end gen_mask;
begin
b <= a and gen_mask (8);
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15200)
`protect data_block
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|
`protect begin_protected
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|
`protect begin_protected
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`protect begin_protected
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|
`protect begin_protected
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`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15200)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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|
`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the full adder.
library ieee;
use ieee.std_logic_1164.all;
entity full_adder_tb is
end full_adder_tb;
architecture TB of full_adder_tb is
signal a, b, sum, c_in, c_out : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.full_adder
port map (
a => a,
b => b,
c_in => c_in,
sum => sum,
c_out => c_out
);
-- Stimulus process
process
begin
a <= '0';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '0';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '0';
c_in <= '1';
wait for 10 ns;
a <= '0';
b <= '1';
c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '1';
wait;
end process;
end TB;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.sim_protected.all;
package simulation is
-- Legacy interface for pre VHDL-2002
-- ===========================================================================
procedure simInitialize;
procedure simFinalize;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID);
impure function simIsStopped return BOOLEAN;
procedure simWriteMessage(Message : in STRING := "");
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure simFail(Message : in STRING := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "");
-- Random Numbers
-- ===========================================================================
type T_SIM_SEED is record
Seed1 : INTEGER;
Seed2 : INTEGER;
end record;
procedure initializeSeed(Seed : inout T_SIM_SEED);
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL);
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME);
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package;
package body simulation is
-- legacy procedures
-- ===========================================================================
-- TODO: undocumented group
procedure simInitialize is
begin
globalSimulationStatus.initialize;
end procedure;
procedure simFinalize is
begin
globalSimulationStatus.finalize;
end procedure;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID is
begin
return globalSimulationStatus.createTest(Name);
end function;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID is
begin
return globalSimulationStatus.registerProcess(Name);
end function;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is
begin
globalSimulationStatus.deactivateProcess(ProcID);
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return globalSimulationStatus.isStopped;
end function;
-- TODO: undocumented group
procedure simWriteMessage(Message : in STRING := "") is
begin
globalSimulationStatus.writeMessage(Message);
end procedure;
procedure simFail(Message : in STRING := "") is
begin
globalSimulationStatus.fail(Message);
end procedure;
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "") is
begin
globalSimulationStatus.assertion(cond, Message);
end procedure;
-- ===========================================================================
-- Random Numbers
-- ===========================================================================
procedure initializeSeed(Seed : inout T_SIM_SEED) is
begin
Seed.Seed1 := 5;
Seed.Seed2 := 3423;
end procedure;
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
Value := scale(rand, Minimum, Maximum);
end procedure ;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is
variable rand1 : REAL;
variable rand2 : REAL;
begin
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
-- Box Muller transformation
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1);
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2);
-- standard normal distribution: mean 0, variance 1
Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean;
end procedure;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
while (TRUE) loop
getNormalDistibutedRandomValue(Seed, rand, StandardDeviation, Mean);
exit when ((Minimum <= rand) and (rand <= Maximum));
end loop;
Value := rand;
end procedure;
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
signal Clock : out STD_LOGIC;
constant Period : in TIME;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
constant Delay : TIME := Period * PhaseAsFactor;
constant TimeHigh : TIME := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
constant TimeLow : TIME := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
constant ClockAfterRun_cy : POSITIVE := 1;
begin
report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & CR &
"Period: " & TIME'image(Period) & CR &
"Phase: " & T_PHASE'image(Phase) & CR &
"DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & CR &
"PhaseAsFactor: " & REAL'image(PhaseAsFactor) & CR &
"WanderAsFactor: " & REAL'image(WanderAsFactor) & CR &
"DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & CR &
"Delay: " & TIME'image(Delay) & CR &
"TimeHigh: " & TIME'image(TimeHigh) & CR &
"TimeLow: " & TIME'image(TimeLow)
severity NOTE;
if (Delay = 0 ns) then
null;
elsif (Delay <= TimeLow) then
Clock <= '0';
wait for Delay;
else
Clock <= '1';
wait for Delay - TimeLow;
Clock <= '0';
wait for TimeLow;
end if;
Clock <= '1';
while (not globalSimulationStatus.isStopped) loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
type T_SIM_NORMAL_DIST_PARAMETER is record
StandardDeviation : REAL;
Mean : REAL;
end record;
type T_JITTER_DISTRIBUTION is array (NATURAL range <>) of T_SIM_NORMAL_DIST_PARAMETER;
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME) is
constant TimeHigh : TIME := Period * 0.5;
constant TimeLow : TIME := Period - TimeHigh;
constant JitterPeakPeak : REAL := 0.1; -- UI
constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
constant JitterDistribution : T_JITTER_DISTRIBUTION := (0 => (0.6, 0.0)); --((0.2, -0.3), (0.3, -0.1), (0.5, 0.0), (0.3, 0.1), (0.2, 0.3));
variable Seed : T_SIM_SEED;
variable rand : REAL;
variable sum : REAL;
variable Jitter : REAL;
begin
Clock <= '1';
initializeSeed(Seed);
while (not globalSimulationStatus.isStopped) loop
sum := 0.0;
for i in JitterDistribution'range loop
getNormalDistibutedRandomValue(Seed, rand, JitterDistribution(i).StandardDeviation, JitterDistribution(i).Mean, -1.0, 1.0);
sum := sum + rand;
end loop;
Debug <= integer(sum * 1000.0);
Jitter := JitterAsFactor * sum;
-- Debug <= integer(rand * 256.0 + 256.0);
wait for TimeHigh + (Period * Jitter);
Clock <= '0';
wait for TimeLow + (Period * Jitter);
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until rising_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until falling_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
variable p : TIME;
variable rp : TIME;
begin
-- WORKAROUND: for QuestaSim/ModelSim
-- Version: 10.4c
-- Issue:
-- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
-- regardless of the passed function parameters
p := Pause;
rp := ResetPulse;
return (0 => p, 1 => rp);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.sim_protected.all;
package simulation is
-- Legacy interface for pre VHDL-2002
-- ===========================================================================
procedure simInitialize;
procedure simFinalize;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID);
impure function simIsStopped return BOOLEAN;
procedure simWriteMessage(Message : in STRING := "");
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure simFail(Message : in STRING := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "");
-- Random Numbers
-- ===========================================================================
type T_SIM_SEED is record
Seed1 : INTEGER;
Seed2 : INTEGER;
end record;
procedure initializeSeed(Seed : inout T_SIM_SEED);
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL);
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME);
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package;
package body simulation is
-- legacy procedures
-- ===========================================================================
-- TODO: undocumented group
procedure simInitialize is
begin
globalSimulationStatus.initialize;
end procedure;
procedure simFinalize is
begin
globalSimulationStatus.finalize;
end procedure;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID is
begin
return globalSimulationStatus.createTest(Name);
end function;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID is
begin
return globalSimulationStatus.registerProcess(Name);
end function;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is
begin
globalSimulationStatus.deactivateProcess(ProcID);
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return globalSimulationStatus.isStopped;
end function;
-- TODO: undocumented group
procedure simWriteMessage(Message : in STRING := "") is
begin
globalSimulationStatus.writeMessage(Message);
end procedure;
procedure simFail(Message : in STRING := "") is
begin
globalSimulationStatus.fail(Message);
end procedure;
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "") is
begin
globalSimulationStatus.assertion(cond, Message);
end procedure;
-- ===========================================================================
-- Random Numbers
-- ===========================================================================
procedure initializeSeed(Seed : inout T_SIM_SEED) is
begin
Seed.Seed1 := 5;
Seed.Seed2 := 3423;
end procedure;
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
Value := scale(rand, Minimum, Maximum);
end procedure ;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is
variable rand1 : REAL;
variable rand2 : REAL;
begin
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
-- Box Muller transformation
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1);
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2);
-- standard normal distribution: mean 0, variance 1
Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean;
end procedure;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
while (TRUE) loop
getNormalDistibutedRandomValue(Seed, rand, StandardDeviation, Mean);
exit when ((Minimum <= rand) and (rand <= Maximum));
end loop;
Value := rand;
end procedure;
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
signal Clock : out STD_LOGIC;
constant Period : in TIME;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
constant Delay : TIME := Period * PhaseAsFactor;
constant TimeHigh : TIME := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
constant TimeLow : TIME := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
constant ClockAfterRun_cy : POSITIVE := 1;
begin
report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & CR &
"Period: " & TIME'image(Period) & CR &
"Phase: " & T_PHASE'image(Phase) & CR &
"DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & CR &
"PhaseAsFactor: " & REAL'image(PhaseAsFactor) & CR &
"WanderAsFactor: " & REAL'image(WanderAsFactor) & CR &
"DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & CR &
"Delay: " & TIME'image(Delay) & CR &
"TimeHigh: " & TIME'image(TimeHigh) & CR &
"TimeLow: " & TIME'image(TimeLow)
severity NOTE;
if (Delay = 0 ns) then
null;
elsif (Delay <= TimeLow) then
Clock <= '0';
wait for Delay;
else
Clock <= '1';
wait for Delay - TimeLow;
Clock <= '0';
wait for TimeLow;
end if;
Clock <= '1';
while (not globalSimulationStatus.isStopped) loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
type T_SIM_NORMAL_DIST_PARAMETER is record
StandardDeviation : REAL;
Mean : REAL;
end record;
type T_JITTER_DISTRIBUTION is array (NATURAL range <>) of T_SIM_NORMAL_DIST_PARAMETER;
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME) is
constant TimeHigh : TIME := Period * 0.5;
constant TimeLow : TIME := Period - TimeHigh;
constant JitterPeakPeak : REAL := 0.1; -- UI
constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
constant JitterDistribution : T_JITTER_DISTRIBUTION := (0 => (0.6, 0.0)); --((0.2, -0.3), (0.3, -0.1), (0.5, 0.0), (0.3, 0.1), (0.2, 0.3));
variable Seed : T_SIM_SEED;
variable rand : REAL;
variable sum : REAL;
variable Jitter : REAL;
begin
Clock <= '1';
initializeSeed(Seed);
while (not globalSimulationStatus.isStopped) loop
sum := 0.0;
for i in JitterDistribution'range loop
getNormalDistibutedRandomValue(Seed, rand, JitterDistribution(i).StandardDeviation, JitterDistribution(i).Mean, -1.0, 1.0);
sum := sum + rand;
end loop;
Debug <= integer(sum * 1000.0);
Jitter := JitterAsFactor * sum;
-- Debug <= integer(rand * 256.0 + 256.0);
wait for TimeHigh + (Period * Jitter);
Clock <= '0';
wait for TimeLow + (Period * Jitter);
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until rising_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until falling_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
variable p : TIME;
variable rp : TIME;
begin
-- WORKAROUND: for QuestaSim/ModelSim
-- Version: 10.4c
-- Issue:
-- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
-- regardless of the passed function parameters
p := Pause;
rp := ResetPulse;
return (0 => p, 1 => rp);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
-- ************************************
-- Automatically Generated FSM
-- crc
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity crc is
generic(
G_INPUT_WIDTH : integer := 32;
G_ADDR_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "1011"
);
port
(
array_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array_dIN0 : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_dOUT0 : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (G_INPUT_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_channelDataOut : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity crc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of crc is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
read_data,
extra1,
do_crc
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal i, i_next : std_logic_vector(0 to 7);
signal j, j_next : std_logic_vector(0 to 31);
signal result, result_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal size, size_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal in_array_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
array_addr0 <= in_array_addr0(2 to 31) & "00"; --The external memory is organized in this way.
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
i_next,
j_next,
result_next,
size_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
i <= (others => '0');
j <= (others => '0');
result <= (others => '0');
size <= (others => '0');
current_state <= reset;
else
-- Transition to next state
i <= i_next;
j <= j_next;
result <= result_next;
size <= size_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
array_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
i,
j,
result,
size,
current_state) is
begin
-- Default signal assignments
i_next <= i;
j_next <= j;
result_next <= result;
size_next <= size;
in_array_addr0 <= (others => '0');
array_dIN0 <= (others => '0');
array_rENA0 <= '0';
array_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when do_crc =>
if ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) and ( result(conv_integer(i)) = '0' ) then
i_next <= i + 1;
next_state <= do_crc;
elsif ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) then
result_next(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) <= result(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) xor divisor;
i_next <= i + 1;
next_state <= do_crc;
else
in_array_addr0 <= j;
array_dIN0 <= result;
array_wENA0 <= (others => '1');
array_rENA0 <= '1';
next_state <= read_data;
j_next <= j + 1;
end if;
when extra1 =>
i_next <= conv_std_logic_vector(0,8);
result_next <= array_dOUT0;
next_state <= do_crc;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
j_next <= "00000000000000000" & chan1_channelDataOut(17 to 31);
size_next <= "00000000000000000" & chan1_channelDataOut(2 to 16);
chan1_channelRead <= '1';
next_state <= read_data;
end if;
when read_data =>
if ( j < size ) then
in_array_addr0 <= j;
array_rENA0 <= '1';
next_state <= extra1;
elsif chan1_full /= '0' then
next_state <= read_data;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
|
-- ************************************
-- Automatically Generated FSM
-- crc
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity crc is
generic(
G_INPUT_WIDTH : integer := 32;
G_ADDR_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "1011"
);
port
(
array_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
array_dIN0 : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_dOUT0 : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (G_INPUT_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_channelDataOut : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity crc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of crc is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
read_data,
extra1,
do_crc
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal i, i_next : std_logic_vector(0 to 7);
signal j, j_next : std_logic_vector(0 to 31);
signal result, result_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal size, size_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
signal in_array_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
array_addr0 <= in_array_addr0(2 to 31) & "00"; --The external memory is organized in this way.
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
i_next,
j_next,
result_next,
size_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
i <= (others => '0');
j <= (others => '0');
result <= (others => '0');
size <= (others => '0');
current_state <= reset;
else
-- Transition to next state
i <= i_next;
j <= j_next;
result <= result_next;
size <= size_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
array_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
i,
j,
result,
size,
current_state) is
begin
-- Default signal assignments
i_next <= i;
j_next <= j;
result_next <= result;
size_next <= size;
in_array_addr0 <= (others => '0');
array_dIN0 <= (others => '0');
array_rENA0 <= '0';
array_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when do_crc =>
if ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) and ( result(conv_integer(i)) = '0' ) then
i_next <= i + 1;
next_state <= do_crc;
elsif ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) then
result_next(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) <= result(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) xor divisor;
i_next <= i + 1;
next_state <= do_crc;
else
in_array_addr0 <= j;
array_dIN0 <= result;
array_wENA0 <= (others => '1');
array_rENA0 <= '1';
next_state <= read_data;
j_next <= j + 1;
end if;
when extra1 =>
i_next <= conv_std_logic_vector(0,8);
result_next <= array_dOUT0;
next_state <= do_crc;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
j_next <= "00000000000000000" & chan1_channelDataOut(17 to 31);
size_next <= "00000000000000000" & chan1_channelDataOut(2 to 16);
chan1_channelRead <= '1';
next_state <= read_data;
end if;
when read_data =>
if ( j < size ) then
in_array_addr0 <= j;
array_rENA0 <= '1';
next_state <= extra1;
elsif chan1_full /= '0' then
next_state <= read_data;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_4_0;
USE blk_mem_gen_v8_4_0.blk_mem_gen_v8_4_0;
ENTITY design_1_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_0;
ARCHITECTURE design_1_blk_mem_gen_0_0_arch OF design_1_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_4_0 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_4_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_0_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_4_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_4_0,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM" &
"E=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_" &
"WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C" &
"_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clkb: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 1200, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
BEGIN
U0 : blk_mem_gen_v8_4_0
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_430 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_430;
architecture augh of add_430 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_430 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_430;
architecture augh of add_430 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir_ahb_dma_apb
-- File: fir_ahb_dma_apb.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter peripheral example for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
library techmap;
use techmap.gencomp.all;
entity fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset : in std_ulogic);
end fir_ahb_dma_apb;
architecture fir_abh_rtl of fir_ahb_dma_apb is
component fir port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end component;
type fir_in_type is record
start : std_ulogic;
in_data : std_logic_vector(31 downto 0);
end record;
type fir_out_type is record
data_read : std_ulogic;
data_write : std_ulogic;
out_data : std_logic_vector(31 downto 0);
end record;
type fifo_type is record
wen : std_ulogic;
ren : std_logic;
idata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(8 downto 0);
waddr : std_logic_vector(8 downto 0);
end record;
type apbreg_type is record
control : std_logic_vector(31 downto 0);
address_in : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
type apbreg_control is record
clear_control : std_ulogic;
clear_timer : std_ulogic;
en_timer : std_ulogic;
end record;
type fsm_state is (idle, idata_request, idata_wait, core_wait, odata_request, odata_wait);
signal pstate, nstate : fsm_state;
type regs is record
cgrant : std_logic_vector(8 downto 0);
cready : std_logic_vector(8 downto 0);
cokay : std_logic_vector(8 downto 0);
cidata : std_logic_vector(8 downto 0);
codata : std_logic_vector(8 downto 0);
address : std_logic_vector(31 downto 0);
address_out : std_logic_vector(31 downto 0);
end record;
signal dmain : dma_in_type;
signal dmaout : dma_out_type;
signal ifir : fir_in_type;
signal ofir : fir_out_type;
signal fifo_in, fifo_out, regfifo_out : fifo_type;
signal fifo_o1data, fifo_o2data : std_logic_vector(31 downto 0);
signal reg_apb, reg_apb_in : apbreg_type;
signal reg_control : apbreg_control;
signal reg, reg_in : regs;
signal rst_core : std_ulogic;
signal ofir_wen : std_logic;
signal ofir_data : std_logic_vector(31 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_CONTRIB, CONTRIB_CORE2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
rst_core <= not(rstn) or rm_reset;
-- APB interface signals
apbo.pirq <= (others => '0'); --no interrupt
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- DMA2AHB signals
dmain.Beat <= HINCR;
dmain.Size <= HSIZE32;
dmain.Reset <= not(rstn);
dmain.Data <= fifo_o2data;
fifo_in.idata <= dmaout.Data;
-- FIFOs / Core signals
ifir.in_data <= fifo_o1data;
fifo_in.waddr <= reg.cready;
fifo_in.raddr <= reg.cidata;
fifo_out.waddr <= reg.codata;
fifo_out.idata <= ofir.out_data;
fifo_in.ren <= ofir.data_read;
fifo_out.wen <= ofir.data_write;
comb : process(reg_apb, apbi, reg_control, pstate, reg, dmaout, regfifo_out, ofir)
variable readdata : std_logic_vector(31 downto 0);
variable regvi : apbreg_type;
variable regv : regs;
variable vfifo_out : fifo_type;
begin
-- APB interface ----------------------
-- assign register outputs to variables
regvi := reg_apb;
-- read register
readdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" =>
readdata := reg_apb.control;
when "01" =>
readdata := reg_apb.address_in;
when "10" =>
readdata := reg_apb.address_out;
when "11" =>
readdata := reg_apb.timer;
when others =>
readdata := (others => '0');
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
regvi.control := apbi.pwdata;
when "01" =>
regvi.address_in := apbi.pwdata;
when "10" =>
regvi.address_out := apbi.pwdata;
when others =>
end case;
end if;
-- timer
if reg_control.clear_timer='1' then
regvi.timer := (others=>'0');
elsif reg_control.en_timer='1' then
regvi.timer := regvi.timer+'1';
end if;
-- clear control registers
if reg_control.clear_control='1' then
regvi.control := std_logic_vector(to_unsigned(2,32));
end if;
-- assign variables to register inputs
reg_apb_in <= regvi;
-- drive bus with read data
apbo.prdata <= readdata;
-------------------------------------
-- fsm (read, execute, write --------
regv := reg;
vfifo_out := regfifo_out;
ifir.start <= '0';
fifo_in.wen <= '0';
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Store <= '0';
dmain.Lock <= '0';
reg_control.clear_timer<='0';
reg_control.en_timer<='0';
reg_control.clear_control<='0';
case pstate is
when idle =>
if (reg_apb.control=std_logic_vector(to_unsigned(1,32))) then
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
reg_control.clear_timer<='1';
else
nstate <= pstate;
end if;
regv.address := reg_apb.address_in;
regv.cgrant := (others=>'0');
regv.cready := (others=>'0');
regv.cidata := (others=>'0');
regv.codata := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address;
when idata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(100,9)) then
nstate <= idata_wait;
else
nstate <= idata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when idata_wait =>
if regv.cready=std_logic_vector(to_unsigned(100,9)) then
nstate <= core_wait;
ifir.start <= '1';
else
nstate <= idata_wait;
end if;
fifo_in.wen <= dmaout.Ready;
dmain.Address <= reg.address;
when core_wait =>
if regv.codata=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_request;
else
nstate <= core_wait;
end if;
regv.address_out := reg_apb.address_out;
regv.cready := (others=>'0');
regv.cgrant := (others=>'0');
regv.cokay := (others=>'0');
dmain.Address <= reg.address_out;
when odata_request =>
if regv.cgrant=std_logic_vector(to_unsigned(91,9)) then
nstate <= odata_wait;
dmain.Request <= '0';
dmain.Burst <= '0';
dmain.Lock <= '0';
dmain.Store <= '0';
else
nstate <= odata_request;
dmain.Request <= '1';
dmain.Burst <= '1';
dmain.Lock <= '1';
dmain.Store <= '1';
end if;
dmain.Address <= reg.address_out;
when odata_wait =>
if regv.cokay=std_logic_vector(to_unsigned(91,9)) then
nstate <= idle;
reg_control.clear_control<='1';
else
nstate <= odata_wait;
end if;
dmain.Address <= reg.address_out;
end case;
if (pstate/=idle) then
reg_control.en_timer<='1';
end if;
-------------------------------------
-- counters update ------------------
if (dmaout.Ready='1') then
regv.cready := regv.cready+1;
end if;
if (dmaout.Okay='1') then
regv.cokay := regv.cokay+1;
regv.address_out := regv.address_out+4;
end if;
if (dmaout.Grant='1') then
regv.cgrant := regv.cgrant+1;
regv.address := regv.address+4;
end if;
if (ofir.data_read='1') then
regv.cidata := regv.cidata+1;
end if;
if (ofir.data_write='1') then
regv.codata := regv.codata+1;
end if;
-------------------------------------
vfifo_out.raddr := regv.cokay;
reg_in <= regv;
fifo_out.raddr <= vfifo_out.raddr;
end process;
regs_proc : process(clk,rstn)
begin
if (rstn='0') then
reg_apb.control <= (others => '0');
reg_apb.address_in <= (others => '0');
reg_apb.address_out <= (others => '0');
reg_apb.timer <= (others => '0');
reg.cgrant <= (others => '0');
reg.cready <= (others => '0');
reg.cokay <= (others => '0');
reg.cidata <= (others => '0');
reg.codata <= (others => '0');
reg.address <= (others => '0');
reg.address_out <= (others => '0');
pstate <= idle;
elsif rising_edge(clk) then
reg_apb <= reg_apb_in;
reg <= reg_in;
pstate <= nstate;
end if;
end process;
regs_core: process(clk,rst_core)
begin
if (rst_core='1') then
ofir.data_write <= '0';
ofir.out_data <= (others => '0');
elsif rising_edge(clk) then
ofir.data_write<=ofir_wen;
ofir.out_data<=ofir_data;
end if;
end process;
-- DMA2AHB
fir_dma_to_ahb : dma2ahb generic map (
hindex=>hindex, vendorid=>VENDOR_CONTRIB, deviceid=>CONTRIB_CORE2)
port map (hclk=>clk, hresetn=>rstn, dmain=>dmain, dmaout=>dmaout, ahbin=>ahbin, ahbout=>ahbout);
-- FIR core
fir_core : fir port map (clk => clk, rst => rst_core, start => ifir.start, in_data => ifir.in_data, in_data_read => ofir.data_read,
out_data => ofir_data, out_data_write => ofir_wen);
-- Input data buffer
ram0 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, fifo_in.ren, fifo_in.raddr, fifo_o1data, clk, fifo_in.wen, fifo_in.waddr, fifo_in.idata);
-- Output data buffer
ram1 : syncram_2p generic map ( tech => technology, abits => 9, dbits => 32)
port map (clk, '1', fifo_out.raddr, fifo_o2data, clk, fifo_out.wen, fifo_out.waddr, fifo_out.idata); -- First word Fall Through
end fir_abh_rtl;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - usb_tlp.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity usb_tlp is
generic (
VENDOR_ID : std_logic_vector(15 downto 0) := X"DEAD";
PRODUCT_ID : std_logic_vector(15 downto 0) := X"BEEF";
MANUFACTURER : string := "";
PRODUCT : string := "";
SERIAL : string := "";
CONFIG_DESC : BYTE_ARRAY := (
-- Configuration descriptor
X"09", -- bLength = 9
X"02", -- bDescriptionType = Configuration Descriptor
X"12", X"00", -- wTotalLength = 18
X"01", -- bNumInterfaces = 1
X"01", -- bConfigurationValue
X"00", -- iConfiguration
X"C0", -- bmAttributes = Self-powered
X"32", -- bMaxPower = 100 mA
-- Interface descriptor
X"09", -- bLength = 9
X"04", -- bDescriptorType = Interface Descriptor
X"00", -- bInterfaceNumber = 0
X"00", -- bAlternateSetting
X"00", -- bNumEndpoints = 0
X"00", -- bInterfaceClass
X"00", -- bInterfaceSubClass
X"00", -- bInterfaceProtocol
X"00" -- iInterface
);
HIGH_SPEED : boolean := true
);
port (
ulpi_data_in : in std_logic_vector(7 downto 0);
ulpi_data_out : out std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk60 : in std_logic;
usb_clk : out std_logic;
usb_reset : out std_logic;
usb_idle : out std_logic;
usb_suspend : out std_logic;
usb_configured : out std_logic;
usb_crc_error : out std_logic;
-- Pulse when SOF packet received
usb_sof : out std_logic;
-- Control transfer signals
ctl_xfer_endpoint : out std_logic_vector(3 downto 0);
ctl_xfer_type : out std_logic_vector(7 downto 0);
ctl_xfer_request : out std_logic_vector(7 downto 0);
ctl_xfer_value : out std_logic_vector(15 downto 0);
ctl_xfer_index : out std_logic_vector(15 downto 0);
ctl_xfer_length : out std_logic_vector(15 downto 0);
ctl_xfer_accept : in std_logic;
ctl_xfer : out std_logic;
ctl_xfer_done : in std_logic;
ctl_xfer_data_out : out std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : out std_logic;
ctl_xfer_data_in : in std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : in std_logic;
ctl_xfer_data_in_last : in std_logic;
ctl_xfer_data_in_ready : out std_logic;
-- Bulk transfer signals
blk_xfer_endpoint : out std_logic_vector(3 downto 0);
blk_in_xfer : out std_logic;
blk_out_xfer : out std_logic;
-- Has complete packet
blk_xfer_in_has_data : in std_logic;
blk_xfer_in_data : in std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : in std_logic;
blk_xfer_in_data_ready : out std_logic;
blk_xfer_in_data_last : in std_logic;
-- Can accept full packet
blk_xfer_out_ready_read : in std_logic;
blk_xfer_out_data : out std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : out std_logic
);
end usb_tlp;
architecture usb_tlp of usb_tlp is
signal axis_rx_tvalid : std_logic;
signal axis_rx_tready : std_logic;
signal axis_rx_tlast : std_logic;
signal axis_rx_tdata : std_logic_vector(7 downto 0);
signal axis_tx_tvalid : std_logic;
signal axis_tx_tready : std_logic;
signal axis_tx_tlast : std_logic;
signal axis_tx_tdata : std_logic_vector(7 downto 0);
signal usb_vbus_valid : std_logic;
signal trn_type : std_logic_vector(1 downto 0);
signal trn_address : std_logic_vector(6 downto 0);
signal trn_endpoint : std_logic_vector(3 downto 0);
signal trn_start : std_logic;
signal rx_trn_data_type : std_logic_vector(1 downto 0);
signal rx_trn_end : std_logic;
signal rx_trn_data : std_logic_vector(7 downto 0);
signal rx_trn_valid : std_logic;
signal rx_trn_hsk_type : std_logic_vector(1 downto 0);
signal rx_trn_hsk_received : std_logic;
signal tx_trn_hsk_type : std_logic_vector(1 downto 0);
signal tx_trn_send_hsk : std_logic;
signal tx_trn_hsk_sended : std_logic;
signal tx_trn_data_type : std_logic_vector(1 downto 0);
signal tx_trn_data_start : std_logic;
signal tx_trn_data : std_logic_vector(7 downto 0);
signal tx_trn_data_valid : std_logic;
signal tx_trn_data_ready : std_logic;
signal tx_trn_data_last : std_logic;
signal ctl_xfer_endpoint_int : std_logic_vector(3 downto 0);
signal ctl_xfer_type_int : std_logic_vector(7 downto 0);
signal ctl_xfer_request_int : std_logic_vector(7 downto 0);
signal ctl_xfer_value_int : std_logic_vector(15 downto 0);
signal ctl_xfer_index_int : std_logic_vector(15 downto 0);
signal ctl_xfer_length_int : std_logic_vector(15 downto 0);
signal ctl_xfer_accept_int : std_logic;
signal ctl_xfer_int : std_logic;
signal ctl_xfer_done_int : std_logic;
signal ctl_xfer_accept_std : std_logic;
signal ctl_xfer_std : std_logic;
signal ctl_xfer_done_std : std_logic;
signal ctl_xfer_data_out_int : std_logic_vector(7 downto 0);
signal ctl_xfer_data_out_valid_int : std_logic;
signal ctl_xfer_data_in_int : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid_int : std_logic;
signal ctl_xfer_data_in_last_int : std_logic;
signal ctl_xfer_data_in_ready_int : std_logic;
signal ctl_xfer_data_in_std : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid_std : std_logic;
signal ctl_xfer_data_in_last_std : std_logic;
signal current_configuration : std_logic_vector(7 downto 0);
signal usb_reset_int : std_logic;
signal usb_crc_error_int : std_logic;
signal standart_request : std_logic;
signal device_address : std_logic_vector(6 downto 0);
begin
ULPI : ulpi_port
generic map (
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => '0',
ulpi_data_in => ulpi_data_in,
ulpi_data_out => ulpi_data_out,
ulpi_dir => ulpi_dir,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_reset => ulpi_reset,
ulpi_clk => ulpi_clk60,
axis_rx_tvalid => axis_rx_tvalid,
axis_rx_tready => axis_rx_tready,
axis_rx_tlast => axis_rx_tlast,
axis_rx_tdata => axis_rx_tdata,
axis_tx_tvalid => axis_tx_tvalid,
axis_tx_tready => axis_tx_tready,
axis_tx_tlast => axis_tx_tlast,
axis_tx_tdata => axis_tx_tdata,
usb_vbus_valid => usb_vbus_valid,
usb_reset => usb_reset_int,
usb_idle => usb_idle,
usb_suspend => usb_suspend
);
PACKET_CONTROLLER : usb_packet
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
axis_rx_tvalid => axis_rx_tvalid,
axis_rx_tready => axis_rx_tready,
axis_rx_tlast => axis_rx_tlast,
axis_rx_tdata => axis_rx_tdata,
axis_tx_tvalid => axis_tx_tvalid,
axis_tx_tready => axis_tx_tready,
axis_tx_tlast => axis_tx_tlast,
axis_tx_tdata => axis_tx_tdata,
trn_type => trn_type,
trn_address => trn_address,
trn_endpoint => trn_endpoint,
trn_start => trn_start,
rx_trn_data_type => rx_trn_data_type,
rx_trn_end => rx_trn_end,
rx_trn_data => rx_trn_data,
rx_trn_valid => rx_trn_valid,
rx_trn_hsk_type => rx_trn_hsk_type,
rx_trn_hsk_received => rx_trn_hsk_received,
tx_trn_hsk_type => tx_trn_hsk_type,
tx_trn_send_hsk => tx_trn_send_hsk,
tx_trn_hsk_sended => tx_trn_hsk_sended,
tx_trn_data_type => tx_trn_data_type,
tx_trn_data_start => tx_trn_data_start,
tx_trn_data => tx_trn_data,
tx_trn_data_valid => tx_trn_data_valid,
tx_trn_data_ready => tx_trn_data_ready,
tx_trn_data_last => tx_trn_data_last,
start_of_frame => usb_sof,
crc_error => usb_crc_error_int,
device_address => device_address
);
TRANSFER_CONTROLLER : usb_xfer
generic map (
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
trn_type => trn_type,
trn_address => trn_address,
trn_endpoint => trn_endpoint,
trn_start => trn_start,
rx_trn_data_type => rx_trn_data_type,
rx_trn_end => rx_trn_end,
rx_trn_data => rx_trn_data,
rx_trn_valid => rx_trn_valid,
rx_trn_hsk_type => rx_trn_hsk_type,
rx_trn_hsk_received => rx_trn_hsk_received,
tx_trn_hsk_type => tx_trn_hsk_type,
tx_trn_send_hsk => tx_trn_send_hsk,
tx_trn_hsk_sended => tx_trn_hsk_sended,
tx_trn_data_type => tx_trn_data_type,
tx_trn_data_start => tx_trn_data_start,
tx_trn_data => tx_trn_data,
tx_trn_data_valid => tx_trn_data_valid,
tx_trn_data_ready => tx_trn_data_ready,
tx_trn_data_last => tx_trn_data_last,
crc_error => usb_crc_error_int,
ctl_xfer_endpoint => ctl_xfer_endpoint_int,
ctl_xfer_type => ctl_xfer_type_int,
ctl_xfer_request => ctl_xfer_request_int,
ctl_xfer_value => ctl_xfer_value_int,
ctl_xfer_index => ctl_xfer_index_int,
ctl_xfer_length => ctl_xfer_length_int,
ctl_xfer_accept => ctl_xfer_accept_int,
ctl_xfer => ctl_xfer_int,
ctl_xfer_done => ctl_xfer_done_int,
ctl_xfer_data_out => ctl_xfer_data_out_int,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid_int,
ctl_xfer_data_in => ctl_xfer_data_in_int,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid_int,
ctl_xfer_data_in_last => ctl_xfer_data_in_last_int,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready_int,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid
);
STD_REQ_CONTROLLER : usb_std_request
generic map (
VENDOR_ID => VENDOR_ID,
PRODUCT_ID => PRODUCT_ID,
MANUFACTURER => MANUFACTURER,
PRODUCT => PRODUCT,
SERIAL => SERIAL,
CONFIG_DESC => CONFIG_DESC,
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
ctl_xfer_endpoint => ctl_xfer_endpoint_int,
ctl_xfer_type => ctl_xfer_type_int,
ctl_xfer_request => ctl_xfer_request_int,
ctl_xfer_value => ctl_xfer_value_int,
ctl_xfer_index => ctl_xfer_index_int,
ctl_xfer_length => ctl_xfer_length_int,
ctl_xfer_accept => ctl_xfer_accept_std,
ctl_xfer => ctl_xfer_int,
ctl_xfer_done => ctl_xfer_done_std,
ctl_xfer_data_out => ctl_xfer_data_out_int,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid_int,
ctl_xfer_data_in => ctl_xfer_data_in_std,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid_std,
ctl_xfer_data_in_last => ctl_xfer_data_in_last_std,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready_int,
device_address => device_address,
current_configuration => current_configuration,
configured => usb_configured,
standart_request => standart_request
);
usb_clk <= ulpi_clk60;
usb_reset <= usb_reset_int;
usb_crc_error <= usb_crc_error_int;
ctl_xfer_endpoint <= ctl_xfer_endpoint_int;
ctl_xfer_type <= ctl_xfer_type_int;
ctl_xfer_request <= ctl_xfer_request_int;
ctl_xfer_value <= ctl_xfer_value_int;
ctl_xfer_index <= ctl_xfer_index_int;
ctl_xfer_length <= ctl_xfer_length_int;
ctl_xfer_accept_int <= ctl_xfer_accept_std when standart_request = '1' else
ctl_xfer_accept;
ctl_xfer <= ctl_xfer_int when standart_request = '0' else
'0';
ctl_xfer_done_int <= ctl_xfer_done_std when standart_request = '1' else
ctl_xfer_done;
ctl_xfer_data_out <= ctl_xfer_data_out_int;
ctl_xfer_data_out_valid <= ctl_xfer_data_out_valid_int when standart_request = '0' else
'0';
ctl_xfer_data_in_int <= ctl_xfer_data_in_std when standart_request = '1' else
ctl_xfer_data_in;
ctl_xfer_data_in_valid_int <= ctl_xfer_data_in_valid_std when standart_request = '1' else
ctl_xfer_data_in_valid;
ctl_xfer_data_in_last_int <= ctl_xfer_data_in_last_std when standart_request = '1' else
ctl_xfer_data_in_last;
ctl_xfer_data_in_ready <= ctl_xfer_data_in_ready_int when standart_request = '0' else
'0';
end usb_tlp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RightShift is
port (
c_in : in unsigned(3 downto 0) := "0001";
c_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0) := "0000";
data_out : out unsigned(3 downto 0)
);
end entity RightShift;
architecture Behavioural of RightShift is
begin
c_out <= c_in;
data_out <= data_in srl to_integer(c_in(1 downto 0));
end architecture Behavioural; |
architecture RTL of ENTITY_NAME is
for all : blah
use entity work.blah(rtl);
for all : blah
use entity work.blah(rtl);
end for;
for others : blah
use entity work.blah(rtl);
end for;
for first : blah
use entity work.blah(rtl);
end for;
for first, second : blah
use entity work.blah(rtl);
end for;
for first, second, third : blah
use entity work.blah(rtl);
end for;
for first, second, third : blah
use entity work.blah(rtl)
generic map (
G_ONE => a,
G_TWO => b
);
end for;
for first, second, third : blah
use entity work.blah(rtl)
generic map (
G_ONE => a,
G_TWO => b
)
port map (
I_INPUT => a,
O_OUTPUT => b
);
end for;
for first, second, third : blah
use entity work.blah(rtl)
port map (
I_INPUT => a,
O_OUTPUT => b
);
end for;
for first, second, third : blah
generic map (
G_ONE => a,
G_TWO => b
);
end for;
for first, second, third : blah
generic map (
G_ONE => a,
G_TWO => b
)
port map (
I_INPUT => a,
O_OUTPUT => b
);
end for;
for first, second, third : blah
port map (
I_INPUT => a,
O_OUTPUT => b
);
end for;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p85n01i03181ent IS
END c14s01b00x00p85n01i03181ent;
ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p85n01i03181"
severity NOTE;
assert ( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p85n01i03181arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p85n01i03181ent IS
END c14s01b00x00p85n01i03181ent;
ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p85n01i03181"
severity NOTE;
assert ( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p85n01i03181arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p85n01i03181ent IS
END c14s01b00x00p85n01i03181ent;
ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p85n01i03181"
severity NOTE;
assert ( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p85n01i03181arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc699.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:40 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00699ent IS
END c03s04b01x00p23n01i00699ent;
ARCHITECTURE c03s04b01x00p23n01i00699arch OF c03s04b01x00p23n01i00699ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of CHARACTER;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : CHARACTER := '1';
variable VAR : CHARACTER;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00699"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00699 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00699arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc699.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:40 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00699ent IS
END c03s04b01x00p23n01i00699ent;
ARCHITECTURE c03s04b01x00p23n01i00699arch OF c03s04b01x00p23n01i00699ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of CHARACTER;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : CHARACTER := '1';
variable VAR : CHARACTER;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00699"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00699 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00699arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc699.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:40 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00699ent IS
END c03s04b01x00p23n01i00699ent;
ARCHITECTURE c03s04b01x00p23n01i00699arch OF c03s04b01x00p23n01i00699ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of CHARACTER;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : CHARACTER := '1';
variable VAR : CHARACTER;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00699"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00699 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00699arch;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
END component fifo;
component fifo is
End component fifo;
begin
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-08T14:22:41+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_PaceEnforcer.all;
entity enforcer_PaceEnforcer_NO_AP_VP is
port
(
clk : in std_logic;
reset : in std_logic;
t : in unsigned(63 downto 0); --current time in nanoseconds
e : out std_logic; --if enforcement occured
--the input signals
--the enforce signals
q : in enforced_signals_PaceEnforcer;
q_prime : out enforced_signals_PaceEnforcer
);
end entity;
architecture behaviour of enforcer_PaceEnforcer_NO_AP_VP is
begin
--trigger process
process(reset, clk, q, t)
variable q_enf: enforced_signals_PaceEnforcer;
begin
if(rising_edge(clk)) then
--default values
q_enf := q;
e <= '0';
--policies begin
if(((q_enf.AP and q_enf.VP) = '0') ) then
e <= '1';
--recover
q_enf.VP := '0';
q_enf.AP := '0';
end if;
--Triggers begin (triggers are after policies because a policy might edit a value that a trigger depends on)
q_prime <= q_enf;
end if;
end process;
end architecture;
|
-- Twofish_ecb_decryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_decryption_monte_carlo_testbench256 is
end ecb_decryption_monte_carlo_testbench256;
architecture ecb_decryption256_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round256
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_decryption_circuit: twofish_decryption_round256
port map (
in1_tdr256 => to_round(127 downto 96),
in2_tdr256 => to_round(95 downto 64),
in3_tdr256 => to_round(63 downto 32),
in4_tdr256 => to_round(31 downto 0),
in_Sfirst_tdr256 => Sfirst,
in_Ssecond_tdr256 => Ssecond,
in_Sthird_tdr256 => Sthird,
in_Sfourth_tdr256 => Sfourth,
in_key_up_tdr256 => key_up,
in_key_down_tdr256 => key_down,
out1_tdr256 => to_encr_reg128(127 downto 96),
out2_tdr256 => to_encr_reg128(95 downto 64),
out3_tdr256 => to_encr_reg128(63 downto 32),
out4_tdr256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_decryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_decryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_decryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Decryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process ecb_dmc_proc;
end ecb_decryption256_monte_carlo_testbench_arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lojbC_shiftReg;
architecture rtl of start_for_Loop_lojbC_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lojbC is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lojbC is
component start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lojbC_shiftReg : start_for_Loop_lojbC_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pit is
Port (
CLK : in STD_LOGIC;
IRQ : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1');
end pit;
architecture Behavioral of pit is
signal count : integer range 0 to 1000000000 := 0;
signal cur : integer range 0 to 1000000000 := 0;
signal irqen : boolean := false;
begin
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
-- update counter
if (cur = count) then
cur <= 0;
else
cur <= cur + 1;
end if;
-- interrupt pin
if (count = 0) then
IRQ <= '0';
elsif (cur = count and irqen) then
IRQ <= '1';
elsif (IAK = '1') then
IRQ <= '0';
end if;
-- bus interface
if (CS = '1') then
if (RW = '1') then
count <= to_integer(unsigned(Din));
irqen <= true;
else
Dout <= std_logic_vector(to_unsigned(cur, 32));
end if;
else
Dout <= x"00000000";
end if;
end if;
end process;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Controller is
port(
Op : in vl_logic_vector(5 downto 0);
Rs : in vl_logic_vector(4 downto 0);
Rt : in vl_logic_vector(4 downto 0);
Rd : in vl_logic_vector(4 downto 0);
Shamt : in vl_logic_vector(4 downto 0);
Func : in vl_logic_vector(5 downto 0);
RegDt0 : out vl_logic;
ID_RsRead : out vl_logic;
ID_RtRead : out vl_logic;
Ex_top : out vl_logic_vector(1 downto 0);
BranchSel : out vl_logic;
OverflowEn : out vl_logic;
Condition : out vl_logic_vector(2 downto 0);
Branch : out vl_logic;
PC_write : out vl_logic_vector(2 downto 0);
Mem_Write_Byte_en: out vl_logic_vector(3 downto 0);
Rd_Write_Byte_en: out vl_logic_vector(3 downto 0);
MemWBSrc : out vl_logic;
Jump : out vl_logic;
ALUShiftSel : out vl_logic;
MemDataSrc : out vl_logic_vector(2 downto 0);
ALUSrcA : out vl_logic;
ALUSrcB : out vl_logic;
ALUOp : out vl_logic_vector(3 downto 0);
RegDst : out vl_logic_vector(1 downto 0);
ShiftAmountSrc : out vl_logic;
Shift_Op : out vl_logic_vector(1 downto 0)
);
end Controller;
|
library verilog;
use verilog.vl_types.all;
entity dffp is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
d : in vl_logic;
clrn : in vl_logic;
prn : in vl_logic
);
end dffp;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: prime_FIFO_plain.vhd
-- /___/ /\ Timestamp: Thu Sep 19 21:45:01 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/prime_FIFO_plain.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/prime_FIFO_plain.vhd
-- Device : 7k325tffg900-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/prime_FIFO_plain.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/prime_FIFO_plain.vhd
-- # of Entities : 2
-- Design Name : prime_FIFO_plain
-- Xilinx : /opt/Xilinx/14.6/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin;
architecture STRUCTURE of reset_builtin is
signal wr_rst_reg_3 : STD_LOGIC;
signal rd_rst_reg_15 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal rd_rst_reg_GND_25_o_MUX_2_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_rd_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_WR_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0019 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_WR_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_WR_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0019(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0019(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0019(5)
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_reg_3,
Q => wr_rst_fb(4)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => NlwRenamedSig_OI_n0019(5),
Q => power_on_wr_rst(5)
);
rd_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(1),
Q => rd_rst_fb(0)
);
rd_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(2),
Q => rd_rst_fb(1)
);
rd_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(3),
Q => rd_rst_fb(2)
);
rd_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(4),
Q => rd_rst_fb(3)
);
rd_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_reg_15,
Q => rd_rst_fb(4)
);
power_on_rd_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(1),
Q => power_on_rd_rst(0)
);
power_on_rd_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(2),
Q => power_on_rd_rst(1)
);
power_on_rd_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(3),
Q => power_on_rd_rst(2)
);
power_on_rd_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(4),
Q => power_on_rd_rst(3)
);
power_on_rd_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(5),
Q => power_on_rd_rst(4)
);
power_on_rd_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => NlwRenamedSig_OI_n0019(5),
Q => power_on_rd_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_3
);
rd_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_reg_GND_25_o_MUX_2_o,
PRE => RST,
Q => rd_rst_reg_15
);
WR_RST_I_1_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_3,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_WR_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_3,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
Mmux_rd_rst_reg_GND_25_o_MUX_2_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => rd_rst_fb(0),
I1 => rd_rst_reg_15,
O => rd_rst_reg_GND_25_o_MUX_2_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity prime_FIFO_plain is
port (
rst : in STD_LOGIC := 'X';
wr_clk : in STD_LOGIC := 'X';
rd_clk : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end prime_FIFO_plain;
architecture STRUCTURE of prime_FIFO_plain is
component reset_builtin
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin
port map (
CLK => N1,
WR_CLK => wr_clk,
RD_CLK => rd_clk,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0005",
ALMOST_FULL_OFFSET => X"000C",
DATA_WIDTH => 72,
DO_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => FALSE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "7SERIES",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => prog_full,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => rd_clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => wr_clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
|
-------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00003FFF",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01011ent IS
END c06s03b00x00p10n01i01011ent;
ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
procedure check (x: in integer; y: in boolean; signal z :out integer) is
begin
z <= 5;
end;
signal p: integer ;
signal q: boolean ;
signal k: integer ;
BEGIN
TESTING: PROCESS
BEGIN
check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
wait for 10 ns;
assert NOT(k=5)
report "***PASSED TEST: c06s03b00x00p10n01i01011"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01011ent IS
END c06s03b00x00p10n01i01011ent;
ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
procedure check (x: in integer; y: in boolean; signal z :out integer) is
begin
z <= 5;
end;
signal p: integer ;
signal q: boolean ;
signal k: integer ;
BEGIN
TESTING: PROCESS
BEGIN
check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
wait for 10 ns;
assert NOT(k=5)
report "***PASSED TEST: c06s03b00x00p10n01i01011"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01011ent IS
END c06s03b00x00p10n01i01011ent;
ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
procedure check (x: in integer; y: in boolean; signal z :out integer) is
begin
z <= 5;
end;
signal p: integer ;
signal q: boolean ;
signal k: integer ;
BEGIN
TESTING: PROCESS
BEGIN
check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
wait for 10 ns;
assert NOT(k=5)
report "***PASSED TEST: c06s03b00x00p10n01i01011"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01011arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end add_200;
architecture augh of add_200 is
signal carry_inA : std_logic_vector(40 downto 0);
signal carry_inB : std_logic_vector(40 downto 0);
signal carry_res : std_logic_vector(40 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(39 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end add_200;
architecture augh of add_200 is
signal carry_inA : std_logic_vector(40 downto 0);
signal carry_inB : std_logic_vector(40 downto 0);
signal carry_res : std_logic_vector(40 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(39 downto 1);
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY Unsigned_Mult IS
PORT (
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END Unsigned_Mult;
ARCHITECTURE Unsigned_Mult_arch OF Unsigned_Mult IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Unsigned_Mult_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintex7",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 0,
C_A_WIDTH => 32,
C_A_TYPE => 0,
C_B_WIDTH => 32,
C_B_TYPE => 0,
C_OUT_HIGH => 63,
C_OUT_LOW => 0,
C_MULT_TYPE => 1,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => '1',
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END Unsigned_Mult_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.types_pkg.all;
package robot_layer_1_pkg is
constant MOTOR_COUNT : natural := 6;
constant QEI_COUNT : natural := 4+1;
component robot_layer_1 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic;
reset : in std_logic;
regs_data_in_value : out std_logic_vector(RegCnt*32-1 downto 0) := (others => '0');
regs_data_in_read : in std_logic_vector(RegCnt-1 downto 0);
regs_data_out_value : in std_logic_vector(RegCnt*32-1 downto 0);
regs_data_out_write : in std_logic_vector(RegCnt-1 downto 0);
----------- ADC (//) ---------
ad0_sclk : out std_logic;
ad0_miso : in std_logic;
ad0_drdy : in std_logic;
ad0_sync : out std_logic;
ad0_clk : out std_logic;
--------- ADC (muxed) --------
ad1_sclk : out std_logic;
ad1_mosi : out std_logic;
ad1_miso : in std_logic;
ad1_ss : out std_logic;
ad1_drdy : in std_logic;
ad1_rst : out std_logic;
---------- H BRIDGE ----------
m0_pwma : out std_logic;
m0_pwmb : out std_logic;
m01_fault: in std_logic; --m01_fault
m1_pwma : out std_logic;
m1_pwmb : out std_logic;
m01_resetn: out std_logic; --m01_resetn
m2_pwma : out std_logic;
m2_pwmb : out std_logic;
m3_pwma : out std_logic;
m3_pwmb : out std_logic;
m2345_fault: in std_logic; --m2345_fault
m4_pwma : out std_logic;
m4_pwmb : out std_logic;
m5_pwma : out std_logic;
m5_pwmb : out std_logic;
m2345_resetn: out std_logic; --m2345_resetn
---------- QEI ----------
qei0_a : in std_logic;
qei0_b : in std_logic;
qei1_a : in std_logic;
qei1_b : in std_logic;
qei2_a : in std_logic;
qei2_b : in std_logic;
qei2_z : in std_logic;
qei3_a : in std_logic;
qei3_b : in std_logic;
qei3_z : in std_logic;
---------- ESC ----------
esc0_pwm : out std_logic;
esc0_dir : out std_logic;
esc1_pwm : out std_logic;
esc1_dir : out std_logic;
------- PWM (Servos) ------
s : out std_logic_vector(8-1 downto 0);
--------- IOs ----------
io_0 : inout std_logic;
io_1 : inout std_logic;
io_2 : inout std_logic;
io_3 : inout std_logic;
io_4 : inout std_logic;
io_5 : inout std_logic;
io_6 : inout std_logic;
io_7 : inout std_logic;
--------- UART ----------
uart0_rx : in std_logic;
uart0_tx : out std_logic;
uart1_rx : in std_logic;
uart1_tx : out std_logic;
uart2_rx : in std_logic;
uart2_tx : out std_logic;
uart2_custom : out std_logic;
uart3_rx : in std_logic;
uart3_tx : out std_logic;
uart3_custom : out std_logic;
--------- I2C ----------
i2c0_scl : inout std_logic;
i2c0_sda : inout std_logic;
i2c0_reset : out std_logic;
i2c1_scl : inout std_logic;
i2c1_sda : inout std_logic;
i2c1_reset : out std_logic;
--------- SPI ----------
spi0_sclk : in std_logic;
spi0_mosi : in std_logic;
spi0_miso : in std_logic;
spi0_ss : in std_logic;
spi1_sclk : out std_logic;
spi1_mosi : out std_logic;
spi1_miso : in std_logic;
spi1_ss : out std_logic;
--! Use SPI1
imu_ss : out std_logic;
imu_drdy : in std_logic;
imu_fsync : in std_logic;
---------- LED -----------
led_green : out std_logic;
led_red : out std_logic;
--------- MGMT -----------
lv_mux : out std_logic_vector(2-1 downto 0);
buzzer : out std_logic;
----------/ NANO SOC LED --------/
LED : out std_logic_vector(8-1 downto 0);
----------/ NANO SOC SW --------/
SW : in std_logic_vector(4-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 2 --------
---------------------------------
--------- UART ----------
uart_tx : in std_logic_vector(4-1 downto 0);
uart_rx : out std_logic_vector(4-1 downto 0);
motor_value : in int16_t(MOTOR_COUNT-1 downto 0);
motor_current : out int24_t(MOTOR_COUNT-1 downto 0);
motor_fault : out std_logic_vector(MOTOR_COUNT-1 downto 0);
qei_value : out int16_t(QEI_COUNT-1 downto 0);
qei_ref : out std_logic_vector(QEI_COUNT-1 downto 0)
);
end component;
end package;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Company: Caltech EE 119B
-- Engineer: Albert Gural and Bryan He
--
-- Design Name: AVR-Processor
-- Module Name: DMAUnit - DataFlow
-- Project Name: AVR-Processor
-- Target Devices: Xilinx Spartan III XC3S1200EFGG3204C
-- Tool versions: Xilinx ISE 14.7
-- Description: Controlls addressing to external memory
--
-- Revision: 1.0
-- For file history, see https://github.com/agural/AVR-Processor
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library opcodes;
use opcodes.opcodes.all;
library ALUCommands;
use ALUCommands.ALUCommands.all;
entity DMAUnit is
port (
clock : in std_logic; -- system clock
MemAddr : in std_logic_vector(15 downto 0); -- memory address to access (input)
InRd : in std_logic; -- when to read from memory
InWr : in std_logic; -- when to write to memory
OutRd : out std_logic; -- timed output for when to read from memory
OutWr : out std_logic; -- timed output for when to write to memory
MemAB : out std_logic_vector(15 downto 0) -- memory address (latched output)
);
end DMAUnit;
architecture DataFlow of DMAUnit is
begin
OutRd <= InRd or clock;
OutWr <= InWr or clock;
MemAB <= MemAddr;
end DataFlow;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
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|
`protect begin_protected
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`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
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|
`protect begin_protected
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|
--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8k is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8k;
architecture Behavioral of sort8k is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
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