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--
-- DSI Shield
-- Copyright (C) 2013-2014 twl <[email protected]>
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- rev2_top.vhd - top level for rev 2.2. PCB FPGA
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
-- Table 1: PLL Settings for the supported displays.
-- Display Type Refresh Mul Sys_Div Phy_Div PHY_Freq Clock period
-- Droid DNA 48 Hz 26 7 1 650 MHz 1538 ps
-- Optimus P880 60 Hz 30 8 2 375 MHz 2666 ps
-- Iphone 4 60 Hz 31 8 2 387.5 MHz 2580 ps
entity rev2_top is
generic (
g_with_hdmi : boolean := true;
-- DDR clock-to-data delay
g_data_delay : integer := 0; --70;
-- DDR data-to-DQs delay
g_dqs_delay : integer := 40; --140; --75 - 45;
g_clock_delay : integer := 40; --70;
g_addr_delay : integer := 0; --70;
-- PLL configuration:
-- Fsys = 25 MHz * g_pll_mul / g_pll_sys_div
-- Fphy = 25 MHz * g_pll_mul / g_pll_phy_div
-- PLL multiplier
g_pll_mul : integer := 31;
-- System clock PLL divider
g_pll_sys_div : integer := 8;
-- DSI PHY clock PLL divider
g_pll_phy_div : integer := 2;
-- DSI PHY clock period, in picoseconds
g_clock_period_ps : integer := 1538;
g_simulation : boolean := false
);
port (
clk_25m_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- HDMI
-------------------------------------------------------------------------------
hdmi_rx_p_i : in std_logic_vector(3 downto 0);
hdmi_rx_n_i : in std_logic_vector(3 downto 0);
hdmi_scl_b : inout std_logic;
hdmi_sda_b : inout std_logic;
hdmi_hpd_o : out std_logic;
hdmi_p5v_notif_i : in std_logic;
-------------------------------------------------------------------------------
-- SDRAM
-------------------------------------------------------------------------------
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0);
-------------------------------------------------------------------------------
-- DSI ports
-------------------------------------------------------------------------------
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(3 downto 0);
dsi_hs_n_o : out std_logic_vector(3 downto 0);
dsi_lp_p_o : out std_logic_vector(3 downto 0);
dsi_lp_n_o : out std_logic_vector(3 downto 0);
dsi_resetb_o : out std_logic;
dsi_gpio0_o : out std_logic;
dsi_gpio1_o : out std_logic;
lcd_pwren_o : out std_logic;
bl_dim_o : out std_logic;
vid_resetn_o : out std_logic;
-- SPI Flash interface (bit-banged)
spi_cs_n_rst_b : inout std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_sck_o : out std_logic;
dbg_o : out std_logic_vector(3 downto 0)
);
end rev2_top;
architecture rtl of rev2_top is
constant c_fml_depth : integer := 25;
component dsi_core is
generic(
g_pixels_per_clock : integer := 2;
g_lanes : integer := 4;
g_fifo_size : integer := 4096;
g_invert_lanes : integer := 5; -- lanes 0 and 2 inverted IP4
g_invert_clock : integer := 0;
--g_invert_lanes : integer := 5; -- lanes 0 and 2 inverted E980
--g_invert_clock : integer := 1; -- clock inverted
g_clock_period_ps : integer := 2000
);
port(
clk_sys_i : in std_logic;
clk_dsi_i : in std_logic;
clk_phy_i : in std_logic;
clk_dsi_shifted_i : in std_logic;
clk_phy_shifted_i : in std_logic;
rst_n_i : in std_logic;
pll_locked_i : in std_logic;
pix_almost_full_o : out std_logic;
pix_i : in std_logic_vector (24 * g_pixels_per_clock-1 downto 0) := (others => '0');
pix_wr_i : in std_logic;
pix_vsync_i : in std_logic;
pix_next_frame_o : out std_logic;
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_clk_lp_oe_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_hs_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_oe_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_reset_n_o : out std_logic;
dsi_gpio_o : out std_logic_vector(2 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fml_wb_bridge
generic (
sdram_depth : integer := 26);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
fml_adr : out std_logic_vector(sdram_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fmlarb
generic(
fml_depth : integer;
fml_width : integer);
port (
sys_clk : in std_logic;
sys_rst : in std_logic;
-- Interface 0 has higher priority than the others
m0_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m0_stb : in std_logic := '0';
m0_we : in std_logic := '0';
m0_ack : out std_logic;
m0_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m0_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m0_do : out std_logic_vector(fml_width-1 downto 0);
m1_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m1_stb : in std_logic := '0';
m1_we : in std_logic := '0';
m1_ack : out std_logic;
m1_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m1_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m1_do : out std_logic_vector(fml_width-1 downto 0);
m2_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m2_stb : in std_logic := '0';
m2_we : in std_logic := '0';
m2_ack : out std_logic;
m2_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m2_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m2_do : out std_logic_vector(fml_width-1 downto 0);
m3_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m3_stb : in std_logic := '0';
m3_we : in std_logic := '0';
m3_ack : out std_logic;
m3_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m3_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m3_do : out std_logic_vector(fml_width-1 downto 0);
m4_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m4_stb : in std_logic := '0';
m4_we : in std_logic := '0';
m4_ack : out std_logic;
m4_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m4_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m4_do : out std_logic_vector(fml_width-1 downto 0);
m5_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m5_stb : in std_logic := '0';
m5_we : in std_logic := '0';
m5_ack : out std_logic;
m5_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m5_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m5_do : out std_logic_vector(fml_width-1 downto 0);
s_adr : out std_logic_vector(fml_depth-1 downto 0);
s_stb : out std_logic;
s_we : out std_logic;
s_eack : in std_logic;
s_sel : out std_logic_vector(fml_width/8-1 downto 0);
s_di : in std_logic_vector(fml_width-1 downto 0);
s_do : out std_logic_vector(fml_width-1 downto 0)
);
end component;
component hpdmc
generic (
csr_addr : integer := 0;
sdram_depth : integer := 25;
sdram_columndepth : integer := 10;
data_delay : integer := 0;
dqs_delay : integer := 0;
clock_delay : integer := 0;
addr_delay : integer := 0
);
port (
sys_clk : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic;
csr_a : in std_logic_vector(13 downto 0);
csr_we : in std_logic;
csr_di : in std_logic_vector(31 downto 0);
csr_do : out std_logic_vector(31 downto 0);
fml_adr : in std_logic_vector(sdram_depth-1 downto 0);
fml_stb : in std_logic;
fml_we : in std_logic;
fml_eack : out std_logic;
fml_sel : in std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0)
);
end component;
component reset_gen is
port (
clk_sys_i : in std_logic;
spi_cs_n_rst_i : in std_logic;
mask_reset_i : in std_logic;
rst_sys_n_o : out std_logic);
end component reset_gen;
component pll_drp_sequencer
port (
clk_sys_i : in std_logic;
clk_reconf_i : in std_logic;
r_pll_ctl0_i : in std_logic_vector(31 downto 0);
r_pll_ctl1_i : in std_logic_vector(31 downto 0);
r_pll_status_o : out std_logic_vector(31 downto 0);
pll_locked_i : in std_logic;
pll_rst_o : out std_logic;
pll_di_o : out std_logic_vector(15 downto 0);
pll_do_i : in std_logic_vector(15 downto 0);
pll_drdy_i : in std_logic;
pll_daddr_o : out std_logic_vector(4 downto 0);
pll_den_o : out std_logic;
pll_dwe_o : out std_logic;
busy_o : out std_logic
);
end component;
component fml_framebuffer
generic (
g_fml_depth : integer
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pix_almost_full_i : in std_logic;
pix_wr_o : out std_logic;
pix_o : out std_logic_vector(47 downto 0);
pix_vsync_o : out std_logic;
pix_next_frame_i : in std_logic;
fml_adr : out std_logic_vector(g_fml_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
r_fb_enable_i : in std_logic;
r_fb_pix32_i : in std_logic;
r_fb_addr_i : in std_logic_vector(g_fml_depth-1 downto 0);
r_fb_size_i : in std_logic_vector(g_fml_depth-1 downto 0)
);
end component;
component sysctl_regs
generic (
g_fml_depth : integer;
g_default_pll_mul : integer;
g_default_pll_sys_div : integer
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
r_fb_enable_o : out std_logic;
r_fb_pix32_o : out std_logic;
r_fb_addr_o : out std_logic_vector(g_fml_depth-1 downto 0);
r_fb_size_o : out std_logic_vector(g_fml_depth-1 downto 0);
r_mixer_ctl_i : in std_logic_vector(7 downto 0);
r_mixer_ctl_o : out std_logic_vector(7 downto 0);
r_edid_addr_o : out std_logic_vector(7 downto 0);
r_edid_data_o : out std_logic_vector(7 downto 0);
r_edid_wr_o : out std_logic;
r_pwm_ctl_o : out std_logic_vector(7 downto 0);
r_pll_ctl0_o : out std_logic_vector(31 downto 0);
r_pll_ctl1_o : out std_logic_vector(31 downto 0);
r_pll_status_i : in std_logic_vector(31 downto 0);
r_gpio_o : out std_logic_vector(31 downto 0);
r_gpio_i : in std_logic_vector(31 downto 0)
);
end component;
component dvi_decoder
port (
tmdsclk_p : in std_logic;
tmdsclk_n : in std_logic;
blue_p : in std_logic;
blue_n : in std_logic;
green_p : in std_logic;
green_n : in std_logic;
red_p : in std_logic;
red_n : in std_logic;
exrst : in std_logic;
pclk : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
de : out std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
green_vld : out std_logic;
pixel : out std_logic_vector(47 downto 0);
pixel_valid : out std_logic;
link_up : out std_logic
);
end component;
component edid_eeprom is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
scl_b : inout std_logic;
sda_b : inout std_logic;
edid_en_i : in std_logic;
scl_master_i : in std_logic;
sda_master_i : in std_logic;
sda_master_o : out std_logic;
hdmi_p5v_notif_i : in std_logic;
hdmi_hpd_en_o : out std_logic;
addr_i : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(7 downto 0);
wr_i : in std_logic);
end component;
component video_mixer is
port(
clk_sys_i : in std_logic;
clk_dvi_i : in std_logic;
rst_n_i : in std_logic;
fb_almost_full_o : out std_logic;
fb_wr_i : in std_logic;
fb_pixel_i : in std_logic_vector(47 downto 0);
fb_vsync_i : in std_logic;
fb_next_frame_o : out std_logic;
dvi_de_i : in std_logic;
dvi_hsync_i : in std_logic;
dvi_vsync_i : in std_logic;
dvi_pixel_i : in std_logic_vector(47 downto 0);
dvi_valid_i : in std_logic;
dvi_link_up_i : in std_logic;
dsif_almost_full_i : in std_logic;
dsif_wr_o : out std_logic;
dsif_pix_o : out std_logic_vector(47 downto 0);
dsif_vsync_o : out std_logic;
dsif_next_frame_i : in std_logic;
mixer_ctl_i : in std_logic_vector(7 downto 0);
mixer_ctl_o : out std_logic_vector(7 downto 0)
);
end component;
constant c_cnx_slave_ports : integer := 1;
constant c_cnx_master_ports : integer := 6;
constant c_master_cpu_i : integer := 0;
constant c_slave_dpram : integer := 0;
constant c_slave_uart : integer := 1;
constant c_slave_dsi : integer := 2;
constant c_slave_ddram_csr : integer := 3;
constant c_slave_csr : integer := 4;
constant c_slave_ddram_mem : integer := 5;
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"00000000", -- 64KB of fpga memory
1 => x"c0010000",
2 => x"c0020000",
3 => x"c0030000",
4 => x"c0040000",
5 => x"80000000"); -- DDR
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"ffff0000",
1 => x"ffff0000",
2 => x"ffff0000",
3 => x"ffff0000",
4 => x"ffff0000",
5 => x"c0000000");
signal cpu_iwb_out : t_wishbone_master_out;
signal cpu_iwb_in : t_wishbone_master_in;
signal rst_n_sys, rst_sys, rst_n_dsi, clk_phy, clk_sys, clk_dsi, clk_sys_n, pll_locked_n, dsi_wr : std_logic;
signal dsi_lp_p_int, dsi_lp_n_int, dsi_lp_oe : std_logic_vector(3 downto 0);
signal dsi_clk_lp_p, dsi_clk_lp_n, dsi_clk_lp_oe : std_logic;
attribute keep : string;
attribute keep of clk_phy : signal is "true";
attribute keep of clk_sys : signal is "true";
attribute keep of clk_sys_n : signal is "true";
attribute keep of clk_dsi : signal is "true";
signal csr_we : std_logic;
signal dsi_wr_sync : std_logic_vector(7 downto 0);
signal pll_clk_in, pll_clk_fb, pll_clk_dsi : std_logic;
signal pll_clk_sys, pll_clk_sys_n : std_logic;
signal dsif_almost_full : std_logic;
signal dsif_wr : std_logic;
signal dsif_pix : std_logic_vector(47 downto 0);
signal dsif_vsync : std_logic;
signal dsif_next_frame : std_logic;
signal fb_almost_full : std_logic;
signal fb_wr : std_logic;
signal fb_pix : std_logic_vector(47 downto 0);
signal fb_vsync : std_logic;
signal fb_next_frame : std_logic;
type t_fml_link is record
adr : std_logic_vector(24 downto 0);
stb, we, ack, eack : std_logic;
d_m2s : std_logic_vector(31 downto 0);
d_s2m : std_logic_vector(31 downto 0);
sel : std_logic_vector(3 downto 0);
end record;
signal ddrc, fwb, frameb : t_fml_link;
signal hdmi_link_up, hdmi_pclk, hdmi_vsync, hdmi_hsync, hdmi_de, hdmi_valid : std_logic;
signal hdmi_pixel : std_logic_vector(47 downto 0);
signal r_mixer_ctl_tomix, r_mixer_ctl_tocsr : std_logic_vector(7 downto 0);
signal r_edid_addr, r_edid_data : std_logic_vector(7 downto 0);
signal r_edid_wr : std_logic;
signal r_fb_pix32, r_fb_enable : std_logic;
signal r_fb_addr, r_fb_size : std_logic_vector(c_fml_depth-1 downto 0);
signal r_gpio_in, r_gpio_out : std_logic_vector(31 downto 0);
signal r_pll_ctl1, r_pll_ctl0, r_pll_status : std_logic_vector(31 downto 0);
signal r_pwm_ctl : std_logic_vector(7 downto 0);
signal dsi_gpio : std_logic_vector(2 downto 0);
signal pwm_prescaler : unsigned(6 downto 0);
signal pwm_count : unsigned(4 downto 0); -- 100 MHz / 4096 = 5 kHz
component xurv_core is
generic (
g_internal_ram_size : integer;
g_internal_ram_init_file : string;
g_simulation : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
cpu_rst_i : in std_logic := '0';
irq_i : in std_logic_vector(7 downto 0) := x"00";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
host_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
host_slave_o : out t_wishbone_slave_out);
end component xurv_core;
component chipscope_icon is
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0));
end component chipscope_ila;
signal CONTROL : std_logic_vector(35 downto 0);
signal TRIG0 : std_logic_vector(7 downto 0);
signal uart_txd_int : std_logic;
signal clk_phy_shifted : std_logic;
signal clk_dsi_shifted : std_logic;
signal pll_clk_dsi_shifted : std_logic;
signal pll_sys_clk_sel, pll_clk_sys_buf : std_logic;
signal pll_rst : std_logic;
signal pll_do : std_logic_vector(15 downto 0);
signal pll_den : std_logic;
signal pll_dwe : std_logic;
signal pll_daddr : std_logic_vector(4 downto 0);
signal pll_di : std_logic_vector(15 downto 0);
signal pll_drdy : std_logic;
signal pll_locked : std_logic;
signal backlight_pwm : std_logic;
signal dcm_clk_sys, dcm_clk_sys_n : std_logic;
signal pll_locked_synced : std_logic;
signal pll_locked_n_masked : std_logic;
signal pll_reconfiguring : std_logic;
signal pll_clk_in_bufio : std_logic;
signal pll_clk_in_reconf : std_logic;
signal mask_reset_input : std_logic;
signal rst_n_sys_pre : std_logic;
begin -- rtl
uart_txd_o <= uart_txd_int;
rst_sys <= not rst_n_sys;
U_Sync_DSI_Reset : gc_sync_ffs
port map (
clk_i => clk_dsi,
rst_n_i => '1',
data_i => rst_n_sys,
synced_o => rst_n_dsi);
--BUFIO2_1: BUFIO2
-- generic map (
-- DIVIDE_BYPASS => true,
-- DIVIDE => 1,
-- I_INVERT => false,
-- USE_DOUBLER => false)
-- port map (
-- DIVCLK => pll_clk_in,
-- IOCLK => open,
-- SERDESSTROBE => open,
-- I => clk_25m_i);
U_IbufG_CLKIn : IBUFG
port map (
I => clk_25m_i,
O => pll_clk_in
);
-- U_IbufG_CLKIn: BUFG
-- port map (
-- I => pll_clk_in,
-- O => pll_clk_in_reconf
-- );
pll_clk_in_reconf <= pll_clk_in;
U_PLL : PLL_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => g_pll_mul,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => g_pll_phy_div,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => g_pll_phy_div,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => g_pll_phy_div * 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => g_pll_phy_div * 8,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DIVIDE => g_pll_sys_div,
CLKOUT4_PHASE => 0.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DIVIDE => g_pll_sys_div,
CLKOUT5_PHASE => 180.000,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 40.000,
CLKIN2_PERIOD => 40.000,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map (
CLKIN1 => pll_clk_in,
CLKIN2 => '0',
CLKINSEL => '1', -- select CLKIN1
CLKFBOUT => pll_clk_fb,
CLKOUT0 => clk_phy,
CLKOUT1 => clk_phy_shifted,
CLKOUT2 => open,
CLKOUT3 => pll_clk_dsi,
CLKOUT4 => pll_clk_sys,
CLKOUT5 => pll_clk_sys_n,
LOCKED => pll_locked,
RST => pll_rst,
CLKFBIN => pll_clk_fb,
DO => pll_do,
DI => pll_di,
DRDY => pll_drdy,
DADDR => pll_daddr,
DCLK => pll_clk_in_reconf,
DEN => pll_den,
DWE => pll_dwe,
REL => '0'
);
U_PLL_Reconf : pll_drp_sequencer
port map (
clk_sys_i => clk_sys,
clk_reconf_i => pll_clk_in_reconf,
r_pll_ctl0_i => r_pll_ctl0,
r_pll_ctl1_i => r_pll_ctl1,
r_pll_status_o => r_pll_status,
pll_locked_i => pll_locked,
pll_rst_o => pll_rst,
pll_di_o => pll_di,
pll_do_i => pll_do,
pll_drdy_i => pll_drdy,
pll_daddr_o => pll_daddr,
pll_den_o => pll_den,
pll_dwe_o => pll_dwe,
busy_o => pll_reconfiguring);
pll_locked_n <= not pll_locked;
U_BufG_CLK_DSI : BUFG
port map (
I => pll_clk_dsi,
O => clk_dsi);
--U_BufG_CLK_DSI_Shifted: BUFG
-- port map (
-- I => pll_clk_dsi_shifted,
-- O => clk_dsi_shifted);
U_BufG_CLK_SYS : BUFG
port map (
I => pll_clk_sys,
O => clk_sys);
--U_BufG_CLK_SYS : BUFGCE
-- port map (
-- O => clk_sys,
-- I => pll_clk_sys,
-- CE => pll_reconfiguring);
--U_BufG_CLK_SYS_N : BUFGCE
-- port map (
-- O => clk_sys_n,
-- I => pll_clk_sys_n,
-- CE => pll_reconfiguring);
--U_BufG_CLK_DSI : BUFGMUX
-- port map (
-- O => clk_dsi,
-- I0 => pll_clk_dsi,
-- I1 => '0',
-- S => pll_reconfiguring);
U_BufG_CLK_SYS_N : BUFG
port map (
I => pll_clk_sys_n,
O => clk_sys_n);
pll_locked_n_masked <= pll_locked_n or pll_rst;
--dbg_o(0) <= clk_sys_div2;
--dbg_o(1) <= clk_sys_sh_div2;
--dbg_o(2) <= clk_dsi_div2;
--dbg_o(3) <= rst_n_sys;
dbg_o <= (others => '0');
U_Sync_PLL_Lock : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => pll_locked,
synced_o => pll_locked_synced);
U_Reset_Gen : reset_gen
port map (
clk_sys_i => clk_sys,
mask_reset_i => mask_reset_input,
spi_cs_n_rst_i => spi_cs_n_rst_b,
rst_sys_n_o => rst_n_sys_pre);
rst_n_sys <= rst_n_sys_pre and pll_locked_synced; -- and rst_n_sys_pre;
U_Intercon : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
g_num_slaves => c_cnx_master_ports,
g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_CPU : xurv_core
generic map (
g_internal_ram_size => 32768,
g_internal_ram_init_file => "",
g_simulation => g_simulation)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
cpu_rst_i => rst_sys,
irq_i => x"00",
dwb_o => cnx_slave_in(0),
dwb_i => cnx_slave_out(0)
);
U_UART : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_slave_uart),
slave_o => cnx_master_in(c_slave_uart),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_int);
csr_we <= cnx_master_out(c_slave_ddram_csr).cyc and cnx_master_out(c_slave_ddram_csr).stb and
cnx_master_out(c_slave_ddram_csr).we;
U_DDR_Controller : hpdmc
generic map (
data_delay => g_data_delay,
dqs_delay => g_dqs_delay,
clock_delay => g_clock_delay,
addr_delay => g_addr_delay)
port map (
sys_clk => clk_sys,
sys_clk_n => clk_sys_n,
sys_rst => rst_sys,
csr_a => cnx_master_out(c_slave_ddram_csr).adr(15 downto 2),
csr_we => csr_we,
csr_di => cnx_master_out(c_slave_ddram_csr).dat,
csr_do => cnx_master_in(c_slave_ddram_csr).dat,
fml_adr => ddrc.adr(24 downto 0),
fml_stb => ddrc.stb,
fml_we => ddrc.we,
fml_eack => ddrc.eack,
fml_sel => ddrc.sel,
fml_di => ddrc.d_m2s,
fml_do => ddrc.d_s2m,
sdram_clk_p => sdram_clk_p,
sdram_clk_n => sdram_clk_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_we_n => sdram_we_n,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_adr => sdram_adr,
sdram_ba => sdram_ba,
sdram_dm => sdram_dm,
sdram_dq => sdram_dq,
sdram_dqs => sdram_dqs);
U_FML_Arb : fmlarb
generic map (
fml_width => 32,
fml_depth => c_fml_depth)
port map (
sys_clk => clk_sys,
sys_rst => rst_sys,
m0_adr => frameb.adr,
m0_stb => frameb.stb,
m0_we => frameb.we,
m0_ack => frameb.ack,
m0_sel => frameb.sel,
m0_do => frameb.d_s2m,
m1_adr => fwb.adr,
m1_stb => fwb.stb,
m1_we => fwb.we,
m1_ack => fwb.ack,
m1_sel => fwb.sel,
m1_di => fwb.d_m2s,
m1_do => fwb.d_s2m,
s_adr => ddrc.adr,
s_stb => ddrc.stb,
s_we => ddrc.we,
s_eack => ddrc.eack,
s_sel => ddrc.sel,
s_di => ddrc.d_s2m,
s_do => ddrc.d_m2s);
U_FML_WB_Bridge : fml_wb_bridge
generic map (
sdram_depth => 25)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
fml_adr => fwb.adr,
fml_stb => fwb.stb,
fml_we => fwb.we,
fml_ack => fwb.ack,
fml_sel => fwb.sel,
fml_di => fwb.d_s2m,
fml_do => fwb.d_m2s,
wb_adr_i => cnx_master_out(c_slave_ddram_mem).adr,
wb_cyc_i => cnx_master_out(c_slave_ddram_mem).cyc,
wb_we_i => cnx_master_out(c_slave_ddram_mem).we,
wb_sel_i => cnx_master_out(c_slave_ddram_mem).sel,
wb_stb_i => cnx_master_out(c_slave_ddram_mem).stb,
wb_dat_i => cnx_master_out(c_slave_ddram_mem).dat,
wb_dat_o => cnx_master_in(c_slave_ddram_mem).dat,
wb_stall_o => cnx_master_in(c_slave_ddram_mem).stall,
wb_ack_o => cnx_master_in(c_slave_ddram_mem).ack
);
U_DSI_Core : dsi_core
generic map
(g_clock_period_ps => g_clock_period_ps)
port map (
clk_dsi_i => clk_dsi,
clk_dsi_shifted_i => clk_dsi,
clk_sys_i => clk_sys,
clk_phy_i => clk_phy,
clk_phy_shifted_i => clk_phy_shifted,
rst_n_i => rst_n_dsi,
pll_locked_i => pll_locked,
pix_i => dsif_pix,
pix_almost_full_o => dsif_almost_full,
pix_vsync_i => dsif_vsync,
pix_next_frame_o => dsif_next_frame,
pix_wr_i => dsif_wr,
dsi_clk_p_o => dsi_clk_p_o,
dsi_clk_n_o => dsi_clk_n_o,
dsi_clk_lp_n_o => dsi_clk_lp_n,
dsi_clk_lp_p_o => dsi_clk_lp_p,
dsi_clk_lp_oe_o => dsi_clk_lp_oe,
dsi_hs_p_o => dsi_hs_p_o,
dsi_hs_n_o => dsi_hs_n_o,
dsi_lp_p_o => dsi_lp_p_int,
dsi_lp_n_o => dsi_lp_n_int,
dsi_lp_oe_o => dsi_lp_oe,
dsi_reset_n_o => dsi_resetb_o,
dsi_gpio_o => dsi_gpio,
wb_adr_i => cnx_master_out(c_slave_dsi).adr,
wb_cyc_i => cnx_master_out(c_slave_dsi).cyc,
wb_we_i => cnx_master_out(c_slave_dsi).we,
wb_sel_i => cnx_master_out(c_slave_dsi).sel,
wb_stb_i => cnx_master_out(c_slave_dsi).stb,
wb_dat_i => cnx_master_out(c_slave_dsi).dat,
wb_dat_o => cnx_master_in(c_slave_dsi).dat,
wb_stall_o => cnx_master_in(c_slave_dsi).stall,
wb_ack_o => cnx_master_in(c_slave_dsi).ack
);
U_Framebuffer : fml_framebuffer
generic map (
g_fml_depth => c_fml_depth
)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
pix_almost_full_i => fb_almost_full,
pix_wr_o => fb_wr,
pix_o => fb_pix,
pix_vsync_o => fb_vsync,
pix_next_frame_i => fb_next_frame,
fml_adr => frameb.adr,
fml_stb => frameb.stb,
fml_we => frameb.we,
fml_ack => frameb.ack,
fml_sel => frameb.sel,
fml_di => frameb.d_s2m,
r_fb_addr_i => r_fb_addr,
r_fb_size_i => r_fb_size,
r_fb_pix32_i => r_fb_pix32,
r_fb_enable_i => r_fb_enable
);
U_Sysctl_Regs : sysctl_regs
generic map (
g_fml_depth => c_fml_depth,
g_default_pll_mul => g_pll_mul,
g_default_pll_sys_div => g_pll_sys_div)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
wb_adr_i => cnx_master_out(c_slave_csr).adr,
wb_cyc_i => cnx_master_out(c_slave_csr).cyc,
wb_we_i => cnx_master_out(c_slave_csr).we,
wb_sel_i => cnx_master_out(c_slave_csr).sel,
wb_stb_i => cnx_master_out(c_slave_csr).stb,
wb_dat_i => cnx_master_out(c_slave_csr).dat,
wb_dat_o => cnx_master_in(c_slave_csr).dat,
wb_stall_o => cnx_master_in(c_slave_csr).stall,
wb_ack_o => cnx_master_in(c_slave_csr).ack,
r_fb_enable_o => r_fb_enable,
r_fb_pix32_o => r_fb_pix32,
r_fb_addr_o => r_fb_addr,
r_fb_size_o => r_fb_size,
r_mixer_ctl_i => r_mixer_ctl_tocsr,
r_mixer_ctl_o => r_mixer_ctl_tomix,
r_edid_addr_o => r_edid_addr,
r_edid_data_o => r_edid_data,
r_edid_wr_o => r_edid_wr,
r_pwm_ctl_o => r_pwm_ctl,
r_pll_ctl0_o => r_pll_ctl0,
r_pll_ctl1_o => r_pll_ctl1,
r_pll_status_i => r_pll_status,
r_gpio_o => r_gpio_out,
r_gpio_i => r_gpio_in);
gen_with_hdmi_sampler : if (g_with_hdmi = true) generate
U_HDMI_RX : dvi_decoder
port map
(
tmdsclk_p => hdmi_rx_p_i(3),
tmdsclk_n => hdmi_rx_n_i(3),
blue_p => hdmi_rx_p_i(0),
blue_n => hdmi_rx_n_i(0),
green_p => hdmi_rx_p_i(1),
green_n => hdmi_rx_n_i(1),
red_p => hdmi_rx_p_i(2),
red_n => hdmi_rx_n_i(2),
exrst => rst_sys,
pclk => hdmi_pclk,
hsync => hdmi_hsync,
vsync => hdmi_vsync,
de => hdmi_de,
pixel => hdmi_pixel,
link_up => hdmi_link_up,
pixel_valid => hdmi_valid
);
end generate gen_with_hdmi_sampler;
mask_reset_input <= r_gpio_out(3);
spi_cs_n_rst_b <= r_gpio_out(4) when mask_reset_input = '1' else 'Z';
spi_sck_o <= r_gpio_out(5);
spi_mosi_o <= r_gpio_out(6);
r_gpio_in(6) <= spi_miso_i;
U_EDID_EEPROM : edid_eeprom
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
edid_en_i => r_gpio_out(0),
scl_master_i => r_gpio_out(1),
sda_master_i => r_gpio_out(2),
sda_master_o => r_gpio_in(2),
scl_b => hdmi_scl_b,
sda_b => hdmi_sda_b,
hdmi_p5v_notif_i => hdmi_p5v_notif_i,
hdmi_hpd_en_o => hdmi_hpd_o,
addr_i => r_edid_addr,
data_i => r_edid_data,
wr_i => r_edid_wr);
U_Video_Mixer : video_mixer
port map (
clk_sys_i => clk_sys,
clk_dvi_i => hdmi_pclk,
rst_n_i => rst_n_sys,
fb_almost_full_o => fb_almost_full,
fb_wr_i => fb_wr,
fb_pixel_i => fb_pix,
fb_vsync_i => fb_vsync,
fb_next_frame_o => fb_next_frame,
dvi_de_i => hdmi_de,
dvi_hsync_i => hdmi_hsync,
dvi_vsync_i => hdmi_vsync,
dvi_pixel_i => hdmi_pixel,
dvi_valid_i => hdmi_valid,
dvi_link_up_i => hdmi_link_up,
dsif_almost_full_i => dsif_almost_full,
dsif_wr_o => dsif_wr,
dsif_pix_o => dsif_pix,
dsif_vsync_o => dsif_vsync,
dsif_next_frame_i => dsif_next_frame,
mixer_ctl_i => r_mixer_ctl_tomix,
mixer_ctl_o => r_mixer_ctl_tocsr
);
gen_lp_tristates : for i in 0 to 3 generate
dsi_lp_p_o(i) <= '1' when (dsi_lp_p_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
dsi_lp_n_o(i) <= '1' when (dsi_lp_n_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
end generate gen_lp_tristates;
dsi_clk_lp_p_o <= '1' when (dsi_clk_lp_p = '1' and dsi_clk_lp_oe = '1') else 'Z';
dsi_clk_lp_n_o <= '1' when (dsi_clk_lp_n = '1' and dsi_clk_lp_oe = '1') else 'Z';
process(clk_sys)
begin
if rising_edge(clk_sys) then
cnx_master_in(c_slave_ddram_csr).ack <= cnx_master_out(c_slave_ddram_csr).stb and cnx_master_out(c_slave_ddram_csr).cyc;
end if;
end process;
cnx_master_in(c_slave_dsi).err <= '0';
cnx_master_in(c_slave_ddram_csr).stall <= '0';
cnx_master_in(c_slave_ddram_csr).err <= '0';
cnx_master_in(c_slave_ddram_mem).err <= '0';
dsi_gpio1_o <= dsi_gpio(0);
dsi_gpio0_o <= 'Z';
p_bl_pwm : process(clk_sys)
begin
if rising_edge(clk_sys) then
if rst_n_sys = '0' then
pwm_prescaler <= (others => '0');
pwm_count <= (others => '0');
bl_dim_o <= '0';
else
pwm_prescaler <= pwm_prescaler + 1;
if(pwm_prescaler = 0) then
pwm_count <= pwm_count + 1;
end if;
if(pwm_count < unsigned(r_pwm_ctl)) then
bl_dim_o <= '1';
else
bl_dim_o <= '0';
end if;
end if;
end if;
end process;
lcd_pwren_o <= '1';
vid_resetn_o <= '1';
end rtl;
|
--!
--! @file: example8_4.vhd
--! @brief: Shift register with Component and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
--------------------------------------
entity shift_register is
generic (M: positive := 4; -- num. of stages
N: positive := 8); -- bits per stage
port (
clk, load: in std_logic;
x: in std_logic_vector(N-1 downto 0);
d: in twoD(0 to M-1, N-1 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity shift_register;
--------------------------------------
architecture circuit of shift_register is
signal u: twoD(0 to M, N-1 downto 0);
signal v: twoD(0 to M-1, N-1 downto 0);
begin
-- transfer of x -> u and u -> y
gen1: for i in N-1 downto 0 generate
u(0,i) <= x(i); -- mapping input of entity to input of first stage
y(i) <= u(M, i); -- mapping the output of the last stage to the output of entity
end generate gen1;
-- update internal stages
gen2: for i in 0 to M-1 generate
gen3: for j in N-1 downto 0 generate
mux1: mux port map (
a => u(i, j),
b => d(i, j),
sel => load,
x => v(i, j)
);
dff1: flipflop port map (
d => v(i,j),
clk => clk,
q => u(i + 1, j)
);
end generate gen3;
end generate gen2;
end architecture circuit;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- globals for projects using my modules
package globals is
constant FPGA_CLK_FREQ : integer := 100000000; -- 100 MHz
subtype byte_t is std_logic_vector(7 downto 0);
-- register interface
--constant REG_ADDR_W : integer := 5;
subtype reg_addr_t is std_logic_vector(REG_ADDR_W - 1 downto 0);
constant reg_addr_invl : std_logic_vector(REG_ADDR_W - 1 downto 0) := ( others => '1' );
type reg_bus_t is record
wr : std_logic;
data : byte_t;
addr : reg_addr_t;
end record reg_bus_t;
end globals;
package body globals is
end globals;
|
entity \test\ is end;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity axi_data is
port (
s_axi_aclk: in std_logic;
s_axi_aresetn: in std_logic;
s_axi_arvalid: in std_logic;
s_axi_awvalid: in std_logic;
s_axi_bready: in std_logic;
s_axi_rready: in std_logic;
s_axi_wvalid: in std_logic;
s_axi_arprot: in std_logic_vector(2 downto 0);
s_axi_awprot: in std_logic_vector(2 downto 0);
s_axi_araddr: in std_logic_vector(31 downto 0);
s_axi_awaddr: in std_logic_vector(31 downto 0);
s_axi_wdata: in std_logic_vector(31 downto 0);
s_axi_wstrb: in std_logic_vector(3 downto 0);
s_axi_arready: out std_logic;
s_axi_awready: out std_logic;
s_axi_bvalid: out std_logic;
s_axi_rvalid: out std_logic;
s_axi_wready: out std_logic;
s_axi_bresp: out std_logic_vector(1 downto 0);
s_axi_rresp: out std_logic_vector(1 downto 0);
s_axi_rdata: out std_logic_vector(31 downto 0);
near_full: in std_logic;
dataout_wr: out std_logic;
dataout: out fifo_t
);
end axi_data;
architecture beh_axi_data of axi_data is
-- Speed at 180 MHz: 144 ns / sample (without sample generation)
-- Speed at 100 MHz: 200 ns / sample (without sample generation)
constant addr_width: integer:= 32;
constant data_width: integer:= 32;
constant w32bytes: integer:= data_width/8;
signal awready: std_logic;
signal wready: std_logic;
signal bvalid: std_logic;
signal arready: std_logic;
signal rdata: std_logic_vector(addr_width-1 downto 0);
signal rvalid: std_logic;
subtype reg_t is std_logic_vector(data_width-1 downto 0);
signal databus: std_logic_vector(data_width-1 downto 0);
signal reg: reg_t;
signal stat_reg: reg_t;
signal reg_rden: std_logic;
signal reg_wren: std_logic;
signal datawr: std_logic:= '0';
begin
stat_reg(0) <= near_full;
stat_reg(reg_t'high downto 1) <= (others => '0');
dataout_wr <= datawr;
dataout.input <= reg(1*cgp_t'length-1 downto 0*cgp_t'length);
dataout.output <= reg(2*cgp_t'length-1 downto 1*cgp_t'length);
-- The register is updated when reg_wren = 1 and there is a rising edge on
-- s_axi_clk. The register value is valid in the next cycle, therefore we
-- need to delay this signal.
process (s_axi_aclk) is
begin
if rising_edge(s_axi_aclk) then
datawr <= reg_wren;
end if;
end process;
s_axi_awready <= awready;
s_axi_wready <= wready;
s_axi_bvalid <= bvalid;
s_axi_arready <= arready;
s_axi_rdata <= rdata;
s_axi_rvalid <= rvalid;
reg_wren <= wready and s_axi_wvalid and awready and s_axi_awvalid;
reg_rden <= arready and s_axi_arvalid and (not rvalid);
process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
awready <= '0';
wready <= '0';
bvalid <= '0';
arready <= '0';
rvalid <= '0';
rdata <= (others => '0');
else
if (awready = '0' and s_axi_awvalid = '1' and
s_axi_wvalid = '1') then
awready <= '1';
else
awready <= '0';
end if;
if (wready = '0' and s_axi_wvalid = '1' and
s_axi_awvalid = '1') then
wready <= '1';
else
wready <= '0';
end if;
if (awready = '1' and s_axi_awvalid = '1' and wready = '1'
and s_axi_wvalid = '1' and bvalid = '0') then
bvalid <= '1';
elsif (s_axi_bready = '1' and bvalid = '1') then
bvalid <= '0';
end if;
if (arready = '0' and s_axi_arvalid = '1') then
arready <= '1';
else
arready <= '0';
end if;
if (arready = '1' and s_axi_arvalid = '1' and rvalid = '0')
then
rvalid <= '1';
elsif (rvalid = '1' and s_axi_rready = '1') then
rvalid <= '0';
end if;
if (reg_rden = '1') then
rdata <= databus;
end if;
end if;
end if;
end process;
write_process: process (s_axi_aclk) is
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
reg <= (others => '0');
else
if (reg_wren = '1')
then
for j in 0 to w32bytes-1 loop
if s_axi_wstrb(j) = '1' then
reg((j+1)*8-1 downto j*8) <=
s_axi_wdata((j+1)*8-1 downto j*8);
end if;
end loop;
end if;
end if;
end if;
end process;
process (stat_reg, s_axi_aresetn)
begin
if s_axi_aresetn = '0' then
databus <= (others => '1');
else
databus <= stat_reg;
end if;
end process;
end beh_axi_data;
|
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for one device
-- Project :
---------------------------------------------------------------
-- File : one_device.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 08/10/17
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
-- exampel for fpga_pkg_2 usage
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: one_device.vhd,v $
-- Revision 1.3 2008/11/21 15:17:01 FWombacher
-- changed name of the fpga_pkg to allow use together with local version
--
-- Revision 1.2 2008/10/24 16:40:02 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:19 FWombacher
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY one_device IS
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END one_device;
ARCHITECTURE one_device_arch OF one_device IS
COMPONENT cyclone_implementation
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
BEGIN
gen_cyc : IF (FPGA_FAMILY = CYCLONE) GENERATE
the_cyclone_implementation : cyclone_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
END one_device_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- Video controller, providing bitmapped display to the system. It uses the SRAM
-- as a video memory, with each pixel occupying 8 bits. This is then taken as an
-- offset into the colour look-up table, or CRAM, and outputted.
--
-- SRAM is organised with each line taking up 1024 bytes, for simpler logic. The
-- addresses are built as row(8..0) | col(9..1). Since the SRAM is 16 bits wide,
-- we only request a read every other pixel.
--
entity VideoController is
PORT (
-- clocks and friends
reset: IN std_logic;
In_Clk_24: IN std_logic;
-- video signals
Out_R: OUT std_logic_vector(3 downto 0);
Out_G: OUT std_logic_vector(3 downto 0);
Out_B: OUT std_logic_vector(3 downto 0);
Out_HSync: OUT std_logic;
Out_VSync: OUT std_logic;
-- SRAM (used to store video datas)
SRAM_Addr: OUT std_logic_vector(17 downto 0);
SRAM_Data: INOUT std_logic_vector(15 downto 0);
SRAM_CE: OUT std_logic;
SRAM_OE: OUT std_logic;
SRAM_WE: OUT std_logic;
SRAM_LB: OUT std_logic;
SRAM_UB: OUT std_logic;
-- Debug status info
debug_state: OUT std_logic_vector(3 downto 0) := (others => '0');
debug_bits: IN std_logic_vector(3 downto 0) := (others => '0');
-- CPU bus
bus_cs: IN std_logic; -- when high, outs is Z
bus_clk: IN std_logic;
bus_address: IN std_logic_vector(18 downto 0);
bus_data: INOUT std_logic_vector(15 downto 0);
bus_rw: IN std_logic;
bus_as: IN std_logic;
bus_dtack: OUT std_logic;
bus_uds: IN std_logic;
bus_lds: IN std_logic
);
end VideoController;
architecture behavioral of VideoController is
signal VidClk: std_logic; -- 25.175 MHz
signal MemClk: std_logic; -- 50.35 MHz
signal ActiveDisplay: std_logic; -- when asserted, colours out
signal col, row: std_logic_vector(9 downto 0);
-- this will *always* hold the last word read from memory
signal pxgen_data: std_logic_vector(15 downto 0) register;
-- CRAM signals
signal cram_read_data: std_logic_vector(23 downto 0);
signal cram_write_data: std_logic_vector(23 downto 0);
signal cram_read_addr: std_logic_vector(7 downto 0) := (others => '0');
signal cram_write_addr: std_logic_vector(7 downto 0) := (others => '0');
signal cram_write_strobe: std_logic := '0';
-- FIFO stuff
signal fifo_read_pend: std_logic register := '0';
signal fifo_rdempty: std_logic := '1';
signal fifo_wrfull: std_logic := '0';
signal fifo_rdreq: std_logic := '0';
signal fifo_wrreq: std_logic := '0';
signal fifo_read_data: std_logic_vector(35 downto 0) := (others => '0');
signal fifo_write_data: std_logic_vector(35 downto 0) := (others => '0');
-- SRAM access state machine
type ram_state_type is (SysReset, CPUSlot0, CPUSlot1, ReadAddrVideo, ReadDataVideo);
signal ram_current_state, ram_next_state: ram_state_type;
begin
-- video clock generator
u_VideoPLL: entity work.VideoPLL(SYN)
port map(
inclk0 => In_Clk_24,
c0 => VidClk,
c1 => MemClk,
areset => reset
);
-- video sync state machine
u_videoSyncer: entity work.VideoSyncGenerator(behavioral)
port map(
reset => reset,
PixelClock => VidClk,
HSync => Out_HSync,
VSync => Out_VSync,
VideoOn => ActiveDisplay,
CurCol => col,
CurRow => row
);
-- Colour RAM
u_cram: entity work.VideoCRAM(SYN)
port map (
data => cram_write_data,
wraddress => cram_write_addr,
wrclock => MemClk,
wren => cram_write_strobe,
q => cram_read_data,
rdaddress => cram_read_addr,
rdclock => MemClk
);
-- CPU Write FIFO
-- Each entry is 36 bits: UDS, LDS, 16 bits of data, and 18 bits of VRAM address.
u_writefifo: entity work.VideoWriteFIFO(SYN)
port map (
data => fifo_write_data,
wrclk => bus_clk,
wrreq => fifo_wrreq,
wrfull => fifo_wrfull,
q => fifo_read_data,
rdclk => MemClk,
rdreq => fifo_rdreq,
rdempty => fifo_rdempty,
aclr => reset
);
-- 68k bus interface. Writes go straight into the FIFO, and will process with
-- no wait states, unless the FIFO is filled. In that case, wait states are
-- inserted until the FIFO is no longer full.
process(bus_clk, reset, bus_cs, bus_rw, fifo_wrfull, bus_uds, bus_lds)
begin
-- in reset state, don't drive the bus
if reset='0' then
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
elsif rising_edge(bus_clk) then
-- is our chip select asserted?
if bus_cs='0' then
-- write cycle
if bus_rw='0' then
if fifo_wrfull='0' then
fifo_write_data <= bus_uds & bus_lds & bus_data & bus_address(18 downto 1);
fifo_wrreq <= '1';
bus_dtack <= '0';
else
-- fifo is full: delay the bus cycle some more
bus_dtack <= '1';
end if;
-- read cycle
else
-- unhandled: lock up machine
bus_dtack <= '1';
end if;
-- not selected: don't drive bus
else
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
-- de-assert FIFO write request
fifo_wrreq <= '0';
end if;
end if;
end process;
-- blank output if active display
process(ActiveDisplay, col, row, cram_read_data, pxgen_data)
begin
if ActiveDisplay='0'
then -- inactivedisplay; render colour 0
cram_read_addr <= (others => '0');
else -- active display; process read pixel data
if col(0)='0'
then cram_read_addr <= pxgen_data(7 downto 0); -- display odd pixel next
else cram_read_addr <= pxgen_data(15 downto 8); -- display even pixel next
end if;
end if;
-- get colour from CRAM
Out_R <= cram_read_data(23 downto 20);
Out_G <= cram_read_data(15 downto 12);
Out_B <= cram_read_data(7 downto 4);
end process;
-- Read/write state machine state advancement
process (MemClk, reset)
begin
if reset='1'
then ram_current_state <= SysReset;
elsif rising_edge(MemClk)
then
ram_current_state <= ram_next_state;
end if;
end process;
-- Read/write state machine
process(reset, ram_current_state, SRAM_Data, row, col, fifo_rdempty)
begin
-- default CRAM and FIFO values
--cram_read_addr <= (others => '0');
fifo_rdreq <= '0';
-- default sram state
SRAM_CE <= '0';
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_UB <= '1';
SRAM_LB <= '1';
SRAM_Addr <= (others => '0');
SRAM_Data <= (others => 'Z');
-- state machine
case ram_current_state is
-- Reset state: the mem system is cleared out
when SysReset =>
SRAM_CE <= '1';
SRAM_OE <= '1';
ram_next_state <= CPUSlot0;
-- CPU access slot 0
when CPUSlot0 => -- pixel 1
-- configure SRAM for write, /WE controlled
SRAM_OE <= '1';
SRAM_WE <= '0';
SRAM_UB <= '0';
SRAM_LB <= '0';
-- put address for write slot on bus
SRAM_Addr <= row(8 downto 0) & col(9 downto 1);
SRAM_Data <= col(8 downto 1) & col(8 downto 1);
-- Was a word read out of the FIFO?
if fifo_read_pend='1'
then
SRAM_Addr <= fifo_read_data(17 downto 0);
SRAM_Data <= fifo_read_data(33 downto 18);
SRAM_UB <= fifo_read_data(35);
SRAM_LB <= fifo_read_data(34);
fifo_read_pend <= '0';
--else
end if;
ram_next_state <= CPUSlot1;
when CPUSlot1 =>
ram_next_state <= ReadAddrVideo;
-- process of reading data for video
when ReadAddrVideo => -- pixel 2
SRAM_UB <= '0';
SRAM_LB <= '0';
--if debug_bits(1 downto 0) = "00" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) + 0;
--elsif debug_bits(1 downto 0) = "01" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) + 1;
--elsif debug_bits(1 downto 0) = "10" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) - 1;
--end if;
SRAM_Addr <= (row(8 downto 0) & col(9 downto 1));
-- Request a readout of the FIFO, if it is not empty. There is a 2-cycle
-- delay between asserting rdreq and getting valid output data.
if fifo_rdempty='0'
then
fifo_rdreq <= '1';
fifo_read_pend <= '1';
end if;
ram_next_state <= ReadDataVideo;
-- Data is ready on SRAM, read it out and restore to idle state.
when ReadDataVideo =>
pxgen_data <= SRAM_Data;
ram_next_state <= CPUSlot0;
end case;
end process;
debug_state(1) <= ActiveDisplay;
end behavioral; |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- MAC sublayer functionality (en-/decapsulation, FCS, IPG)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.framing_common.all;
use work.crc32.all;
use work.utility.all;
entity framing is
port(
tx_reset_i : in std_ulogic;
tx_clock_i : in std_ulogic;
rx_reset_i : in std_ulogic;
rx_clock_i : in std_ulogic;
-- MAC address of this station
-- Must not change after either reset is deasserted
-- Used for
-- * dropping received packets when the destination address differs from both this one and the broadcast address
-- * inserting as source address in transmitted packets when the first byte of the source address in the data stream is all-ones
mac_address_i : in t_mac_address;
-- For details on the signals, see the port list of mii_gmii
-- TX from client logic
-- The length/type field is considered part of the data!
-- It is not interpreted by the framing layer at all.
tx_enable_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
tx_byte_sent_o : out std_ulogic;
-- Do not start new frames while asserted
-- (continuing the previous one is alright)
tx_busy_o : out std_ulogic;
-- RX to client logic
rx_frame_o : out std_ulogic;
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
rx_error_o : out std_ulogic;
-- TX to MII
mii_tx_enable_o : out std_ulogic;
mii_tx_data_o : out t_ethernet_data;
mii_tx_byte_sent_i : in std_ulogic;
mii_tx_gap_o : out std_ulogic;
-- RX from MII
mii_rx_frame_i : in std_ulogic;
mii_rx_data_i : in t_ethernet_data;
mii_rx_byte_received_i : in std_ulogic;
mii_rx_error_i : in std_ulogic
);
end entity;
architecture rtl of framing is
-- Transmission
type t_tx_state is (
TX_IDLE,
-- TX_PREMABLE1 is not needed: first preamble byte is transmitted directly in TX_IDLE when start of transmission
-- is detected.
TX_PREAMBLE2,
TX_PREAMBLE3,
TX_PREAMBLE4,
TX_PREAMBLE5,
TX_PREAMBLE6,
TX_PREAMBLE7,
TX_START_FRAME_DELIMITER,
TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS,
TX_SOURCE_ADDRESS,
TX_CLIENT_DATA,
TX_PAD,
TX_FRAME_CHECK_SEQUENCE2,
TX_FRAME_CHECK_SEQUENCE3,
TX_FRAME_CHECK_SEQUENCE4,
TX_INTERPACKET_GAP
);
signal tx_state : t_tx_state := TX_IDLE;
signal tx_frame_check_sequence : t_crc32;
signal tx_padding_required : natural range 0 to MIN_FRAME_DATA_BYTES + 4 + 1 := 0;
signal tx_interpacket_gap_counter : integer range 0 to INTERPACKET_GAP_BYTES;
signal tx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
-- Reception
type t_rx_state is (
RX_WAIT_START_FRAME_DELIMITER,
RX_DATA,
RX_ERROR,
RX_SKIP_FRAME
);
signal rx_state : t_rx_state := RX_WAIT_START_FRAME_DELIMITER;
signal rx_frame_check_sequence : t_crc32;
subtype t_rx_frame_size is natural range 0 to MAX_FRAME_DATA_BYTES + CRC32_BYTES + 1;
signal rx_frame_size : t_rx_frame_size;
signal rx_is_group_address : std_ulogic;
signal rx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
begin
-- Pass mii_tx_byte_sent_i through directly as long as data is being transmitted
-- to avoid having to prefetch data in the synchronous process
tx_byte_sent_o <= '1' when ((tx_state = TX_CLIENT_DATA or tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS) and mii_tx_byte_sent_i = '1') else '0';
-- Transmission state machine
tx_fsm_sync : process(tx_reset_i, tx_clock_i)
variable update_fcs : boolean;
variable data_out : t_ethernet_data;
begin
if tx_reset_i = '1' then
tx_state <= TX_IDLE;
mii_tx_enable_o <= '0';
tx_busy_o <= '1';
elsif rising_edge(tx_clock_i) then
mii_tx_enable_o <= '0';
tx_busy_o <= '0';
if tx_state = TX_IDLE then
if tx_enable_i = '1' then
-- Jump straight into preamble to save a clock cycle of latency
tx_state <= TX_PREAMBLE2;
mii_tx_data_o <= PREAMBLE_DATA;
mii_tx_enable_o <= '1';
mii_tx_gap_o <= '0';
tx_busy_o <= '1';
end if;
else
-- Keep TX enable and busy asserted at all times
mii_tx_enable_o <= '1';
tx_busy_o <= '1';
-- Use mii_tx_byte_sent_i as clock enable
if mii_tx_byte_sent_i = '1' then
mii_tx_gap_o <= '0';
data_out := (others => '0');
update_fcs := FALSE;
case tx_state is
when TX_IDLE =>
-- Handled above, cannot happen here
null;
when TX_PREAMBLE2 | TX_PREAMBLE3 | TX_PREAMBLE4 | TX_PREAMBLE5 | TX_PREAMBLE6 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := PREAMBLE_DATA;
when TX_PREAMBLE7 =>
tx_state <= TX_START_FRAME_DELIMITER;
data_out := PREAMBLE_DATA;
when TX_START_FRAME_DELIMITER =>
tx_state <= TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS;
data_out := START_FRAME_DELIMITER_DATA;
-- Load padding register
tx_padding_required <= MIN_FRAME_DATA_BYTES;
-- Load FCS
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
tx_frame_check_sequence <= (others => '1');
-- Load MAC address counter
tx_mac_address_byte <= 0;
when TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS =>
data_out := tx_data_i;
update_fcs := TRUE;
-- Skip destination address
if tx_mac_address_byte < MAC_ADDRESS_BYTES then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- All-ones means that we should insert the source address here
if tx_data_i = x"FF" then
tx_state <= TX_SOURCE_ADDRESS;
-- Override client data with first source address byte
data_out := extract_byte(mac_address_i, 0);
-- Second byte is to be sent in next cycle
tx_mac_address_byte <= 1;
else
-- Transmit as usual, skip TX_SOURCE_ADDRESS
tx_state <= TX_CLIENT_DATA;
end if;
end if;
-- Bail out from here if transmission was aborted
-- Note that this should not happen under normal circumstances as the
-- Ethernet frame would be far too short.
if tx_enable_i = '0' then
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
when TX_SOURCE_ADDRESS =>
data_out := extract_byte(mac_address_i, tx_mac_address_byte);
update_fcs := TRUE;
if tx_mac_address_byte < MAC_ADDRESS_BYTES - 1 then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- Address completely sent when tx_mac_address_byte reaches 5
-- Pass on client data again in next cycle
tx_state <= TX_CLIENT_DATA;
end if;
when TX_CLIENT_DATA =>
data_out := tx_data_i;
update_fcs := TRUE;
if tx_enable_i = '0' then
-- No more user data was available, next value has to be sent
-- in this clock cycle already
if tx_padding_required = 0 then
-- Send FCS byte 1 now, byte 2 in next cycle
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
else
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
end if;
when TX_PAD =>
data_out := PADDING_DATA;
update_fcs := TRUE;
if tx_padding_required = 0 then
-- When required=0, previous one was the last one -> send FCS
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
end if;
when TX_FRAME_CHECK_SEQUENCE2 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 1);
when TX_FRAME_CHECK_SEQUENCE3 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 2);
when TX_FRAME_CHECK_SEQUENCE4 =>
tx_state <= TX_INTERPACKET_GAP;
data_out := fcs_output_byte(tx_frame_check_sequence, 3);
-- Load IPG counter with initial value
tx_interpacket_gap_counter <= 0;
when TX_INTERPACKET_GAP =>
-- Only state where the MAC is still busy but no data is actually sent
mii_tx_gap_o <= '1';
if tx_interpacket_gap_counter = INTERPACKET_GAP_BYTES - 1 then
-- Last IPG byte is transmitted in this cycle
tx_state <= TX_IDLE;
else
tx_interpacket_gap_counter <= tx_interpacket_gap_counter + 1;
end if;
end case;
mii_tx_data_o <= data_out;
if update_fcs then
tx_frame_check_sequence <= update_crc32(tx_frame_check_sequence, data_out);
end if;
if tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS or tx_state = TX_CLIENT_DATA or tx_state = TX_PAD then
-- Decrement required padding
if tx_padding_required > 0 then
tx_padding_required <= tx_padding_required - 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- Reception state machine
rx_fsm_sync : process(rx_reset_i, rx_clock_i)
begin
if rx_reset_i = '1' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
elsif rising_edge(rx_clock_i) then
rx_error_o <= '0';
rx_data_o <= mii_rx_data_i;
rx_byte_received_o <= '0';
rx_frame_o <= '0';
case rx_state is
when RX_WAIT_START_FRAME_DELIMITER =>
-- Reset MAC address detection
rx_mac_address_byte <= 0;
rx_is_group_address <= '1';
-- Reset frame size and FCS
rx_frame_size <= 0;
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
rx_frame_check_sequence <= (others => '1');
if mii_rx_frame_i = '1' then
if mii_rx_byte_received_i = '1' then
case mii_rx_data_i is
when START_FRAME_DELIMITER_DATA =>
rx_state <= RX_DATA;
when PREAMBLE_DATA =>
-- Do nothing, wait for end of preamble
null;
when others =>
-- The frame needs to be thrown away, but there is no need to
-- inform the higher layer since nothing of value was actually "received" anyway.
rx_state <= RX_SKIP_FRAME;
end case;
end if;
if mii_rx_error_i = '1' then
-- Same here
rx_state <= RX_SKIP_FRAME;
end if;
end if;
when RX_DATA =>
rx_frame_o <= '1';
rx_byte_received_o <= mii_rx_byte_received_i;
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
-- Remaining FCS after parsing whole packet + FCS needs to be a specific value
if mii_rx_error_i = '1' or rx_frame_check_sequence /= CRC32_POSTINVERT_MAGIC or rx_frame_size < MIN_FRAME_DATA_BYTES + CRC32_BYTES or rx_frame_size > MAX_FRAME_DATA_BYTES + CRC32_BYTES then
rx_error_o <= '1';
end if;
else
if mii_rx_byte_received_i = '1' then
-- Update FCS check
rx_frame_check_sequence <= update_crc32(rx_frame_check_sequence, mii_rx_data_i);
-- Increase frame size
if rx_frame_size < t_rx_frame_size'high then
rx_frame_size <= rx_frame_size + 1;
end if;
-- Check destination MAC address (first 6 bytes of packet)
if rx_mac_address_byte < MAC_ADDRESS_BYTES then
-- First byte determines whether the address is an individual or group address
if rx_mac_address_byte = 0 then
if mii_rx_data_i(0) = '0' then
-- LSB of the address is zero: packet is destined for an individual entity
rx_is_group_address <= '0';
-- Check first address byte
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
-- If not: It is a group address packet -> do not drop it and do not check the address further
elsif rx_is_group_address = '0' then
-- Check other MAC address bytes only if we know it doesn't have a group destination address
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
rx_mac_address_byte <= rx_mac_address_byte + 1;
end if;
end if;
if mii_rx_error_i = '1' then
-- Skip the rest of the frame and tell the higher layer
rx_state <= RX_ERROR;
end if;
end if;
when RX_SKIP_FRAME =>
-- Skip the currently receiving frame without signaling the higher layer
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
when RX_ERROR =>
-- Skip the currently receiving frame and signal the higher layer
rx_frame_o <= '1';
rx_error_o <= '1';
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
end case;
end if;
end process;
end architecture;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(SHMU_ID, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (10 downto 0);
variable faulty_healhty: integer;
variable seed1 :positive ;
variable seed2 :positive ;
variable rand : real ;
begin
uniform(seed1, seed2, rand);
faulty_healhty := integer(rand*100.0);
if faulty_healhty > 50 then
Header_flit := std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(destination, 4)) & Header_type;
else
Header_flit := std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(destination, 4)) & Header_type;
end if;
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (10 downto 0);
begin
Body_flit := std_logic_vector(to_unsigned(Data, 8)) & Body_type;
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (10 downto 0);
begin
Tail_flit := std_logic_vector(to_unsigned(Data, 8)) & Tail_type;
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if credit_in = '1' then
credit_counter := credit_counter + 1;
end if;
if valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(SHMU_ID, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*((2*frame_length/3) - Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
--uniform(seed1, seed2, rand);
--destination_id := integer(rand*3.0);
--while (destination_id = source) loop
-- uniform(seed1, seed2, rand);
-- destination_id := integer(rand*3.0);
--end loop;
destination_id := SHMU_ID;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: "& integer'image(Packet_length));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='1';
--end loop;
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
--valid_out <= '0';
--while credit_counter_in = 0 loop
-- wait until clk'event and clk ='0';
--end loop;
--wait until clk'event and clk ='1';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(2 downto 0) = "001") then
destination_node := to_integer(unsigned(port_in(6 downto 3)));
source_node := to_integer(unsigned(port_in(10 downto 7)));
end if;
if (port_in(2 downto 0) = "100") then
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) ;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) );
writeline(VEC_FILE, LINEVARIABLE);
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end n_register;
architecture arch of n_register is
signal data : std_logic_vector(width-1 downto 0);
begin
output <= data;
latch: process (clk,input,rst)
begin
if (rst = '1') then
data <= (others=>'0');
else if (clk'event and clk = '1') then
data <= input;
end if;
end if;
end process ;
end arch;
|
architecture rtl of fifo is
begin
GEN_LABEL : CASE expression generate
end generate;
GEN_LABEL : CASE expression generate
end generate;
end architecture;
|
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`protect end_protected
|
-- 4-input single-bit multiplexer
-- this circuit takes four single-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_4_single_bit is
port (
-- inputs
in_signal_0 : in std_logic;
in_signal_1 : in std_logic;
in_signal_2 : in std_logic;
in_signal_3 : in std_logic;
-- select signal
input_select : in std_logic_vector(1 downto 0);
-- output
out_signal : out std_logic
);
end entity mux_4_single_bit;
architecture mux_4_single_bit_arch of mux_4_single_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(in_signal_0, in_signal_1, in_signal_2, in_signal_3, input_select)
begin
-- select 00 is input 0
if input_select = "00" then
out_signal <= in_signal_0;
-- select 01 is input 1
elsif input_select = "01" then
out_signal <= in_signal_1;
-- select 10 is input 2
elsif input_select = "10" then
out_signal <= in_signal_2;
-- select 11 is input 3
elsif input_select = "11" then
out_signal <= in_signal_3;
-- otherwise invalid select signal, output 0
else
out_signal <= '0';
end if;
end process mux;
end architecture mux_4_single_bit_arch; |
----------------------------------------
-- ALU : IITB-RISC
-- Author : Sainath
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu16 is
port (
operand1 : in std_logic_vector(15 downto 0); -- 16 std_logic input1
operand2 : in std_logic_vector(15 downto 0); -- 16 std_logic input2
op_code : in std_logic; -- 1 std_logic opcode
result : out std_logic_vector(15 downto 0); -- 16 std_logic ALU result
carry : out std_logic; -- carry flag
zero : out std_logic; -- zero flag
alu_equ : out std_logic -- comparator output
);
end alu16;
--------------------------------Architecture-----------------------------------------------
architecture code of alu16 is
signal result_dummy : std_logic_vector(16 downto 0) := X"0000" & '0';
begin -- behave
result <= result_dummy(15 downto 0);
carry <= result_dummy(16);
ALU : process (operand1, operand2, op_code)
begin
---------- OPCODE for ADDITION operation ---------------------
if(op_code='0') then
result_dummy <= std_logic_vector(unsigned('0' & operand1) + unsigned('0' & operand2));
---------- OPCODE for NAND operation ---------------------
elsif(op_code='1') then
for i in 0 to 15 loop
result_dummy(i) <= operand1(i) nand operand2(i);
end loop;
result_dummy(16) <= '0';
end if;
--------------------------------------------------------------------
end process ALU;
Equality_Check : process(operand1, operand2)
begin
if( operand1 = operand2 ) then -- to set comparator output
alu_equ <= '1';
else
alu_equ <= '0';
end if;
end process Equality_Check;
Zero_Check : process(result_dummy, op_code)
begin
if( result_dummy(15 downto 0) = X"0000" and op_code = '0' ) then -- to set comparator output
zero <= '1';
else
zero <= '0';
end if;
end process Zero_Check;
end code;
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:17 wig Exp $
-- $Date: 2005/07/19 07:13:17 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:17 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_ba : ent_ba
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ba_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00581ent IS
END c03s04b01x00p01n01i00581ent;
ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
type string_file is file of string;
BEGIN
TESTING: PROCESS
file filein : string_file open write_mode is "iofile.21";
BEGIN
for i in 1 to 100 loop
write(filein,"shishir");
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00581arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00581ent IS
END c03s04b01x00p01n01i00581ent;
ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
type string_file is file of string;
BEGIN
TESTING: PROCESS
file filein : string_file open write_mode is "iofile.21";
BEGIN
for i in 1 to 100 loop
write(filein,"shishir");
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00581arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00581ent IS
END c03s04b01x00p01n01i00581ent;
ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
type string_file is file of string;
BEGIN
TESTING: PROCESS
file filein : string_file open write_mode is "iofile.21";
BEGIN
for i in 1 to 100 loop
write(filein,"shishir");
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00581arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mult_gen_0 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mult_gen_0;
ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 0,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_gen_0_arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 5;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
--Burst adapter parameters:
--adapter is mastered by: pcie_compiler_0/Rx_Interface
--adapter masters: avalon64_to_avalon8_0/avalon_slave_0
--asp_debug: 0
--byteaddr_width: 21
--ceil_data_width: 64
--data_width: 64
--dbs_shift: 0
--dbs_upstream_burstcount_width: 10
--downstream_addr_shift: 3
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 64
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 18
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 10
--upstream_max_burstcount: 512
--zero_address_width: 0
entity unici_core_burst_1 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity unici_core_burst_1;
architecture europa of unici_core_burst_1 is
signal address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal downstream_write_reg : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal read_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("00000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= upstream_burstcount;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(upstream_burstdone) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("0000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 10);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("00000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("00000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000") & (data_counter)))), 10);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 9);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 9);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000011"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("0000000000") & ((address_offset & std_logic_vector'("000"))))), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
upstream_readdatavalid <= downstream_readdatavalid;
upstream_readdata <= downstream_readdata;
fifo_empty <= std_logic'('1');
p1_fifo_empty <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
downstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT downstream_write_reg OR NOT downstream_waitrequest)) = '1' then
downstream_write_reg <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND downstream_burstdone))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(downstream_write_reg))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_byteenable <= std_logic_vector'("11111111");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_byteenable <= upstream_byteenable;
end if;
end if;
end process;
internal_downstream_write <= (downstream_write_reg AND upstream_write) AND NOT(internal_downstream_read);
downstream_byteenable <= A_WE_StdLogicVector((std_logic'(downstream_write_reg) = '1'), upstream_byteenable, registered_upstream_byteenable);
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
end europa;
|
--
-- Xilinx ml605 Minimal Transceiver Testbench
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Structural of Top_tb is
constant PERIOD : time := 5 ns;
signal clk, nclk, rst : std_logic;
signal stop : boolean;
signal ready : std_logic;
signal dips : std_logic_vector(7 downto 0):=(others => '0');
begin
nclk <= not(clk);
do_clk: Clock
generic map(PERIOD => PERIOD, RESET_CLKS => 15.0)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: entity work.top
port map(
rst_i => rst,
clk_p_i => clk,
clk_n_i => nclk,
sma_rx_p_i => '0',
sma_rx_n_i => '0',
sma_tx_p_o => open,
sma_tx_n_o => open,
pbc_i => '0',
dips_i => "11000011",
leds_o => open
);
end architecture Structural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2ram
-- File: ddr2ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr2ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
babits: integer range 2 to 3 := 3;
colbits: integer range 9 to 11 := 9;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
-- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C
-- 9:800+ (MT47H-25E)
speedbin: integer range 0 to 9 := 0;
density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip
pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD)
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(babits-1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of ddr2ram is
type moderegs is record
-- Mode register (0)
pd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
rdqsen: std_ulogic;
dqsndis: std_ulogic;
ocdprog: std_logic_vector(2 downto 0);
al: std_logic_vector(2 downto 0);
rtt: std_logic_vector(1 downto 0);
ds: std_ulogic;
dlldis: std_ulogic;
-- Extended mode register 2
srf: std_ulogic;
dccen: std_ulogic;
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
emr3: std_logic_vector(abits-1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
constant tRTP: time := 7.5 ns;
type timetab is array (0 to 9) of time;
-- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E
constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns);
constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(1 to 5) of time;
constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns);
type timetab3 is array(1 to 2) of time;
constant tRRD: timetab3 := (7.5 ns, 10 ns);
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr: integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba(1 downto 0)) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t: time;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning;
-- EMRS EMR2
checkcmd('0','0','0',"10","----------------");
-- EMRS EMR3
checkcmd('0','0','0',"11","----------------");
-- EMRS enable DLL
checkcmd('0','0','0',"01","000---000-------");
-- MRS reset DLL
checkcmd('0','0','0',"00","000----1--------");
cyctr := 0;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
-- 2 x auto refresh
checkcmd('0','0','1',"--","----------------");
checkcmd('0','0','1',"--","----------------");
-- MRS !reset DLL
checkcmd('0','0','0',"00","-------0--------");
-- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal
-- (assume OCD impedance adjust not performed)
checkcmd('0','0','0',"01","------111-------");
assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning;
checkcmd('0','0','0',"01","------000-------");
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if;
if cl<2 or cl>6 then cl:=0; end if;
if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if;
if al>5 then al:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if;
if wrap<2 or wrap>6 then wrap:=0; end if;
-- Checks for all-bank commands
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
-- Get additive latency
i := to_integer(unsigned(vmr.al));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
-- Allow interrupting read in case of middle of BL8 burst only
if (accpipe(3).r and accpipe(2).r and
not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then
accpipe(3).r := false;
accpipe(2).r := false;
end if;
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+blen/2;
else
banks(bank).autopch := cl+al-1+blen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- Reserved (Burst terminate on DDR1)
assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning;
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0
assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank)
report "Precharging bank with access in progress"
severity warning;
end loop;
for x in 0 to (2**babits)-1 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.pd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.rdqsen := a(11);
vmr.dqsndis := a(10);
vmr.ocdprog := a(9 downto 7);
vmr.al := a(5 downto 3);
vmr.rtt := a(6) & a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.srf := a(7);
vmr.dccen := a(3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.emr3 := a;
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then
-- Auto delay auto-precharge to satisfy tRAS/tRC
banks(x).autopch := banks(x).autopch+1;
elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then
-- Auto delay auto-precharge to satisfy tRTP
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP, true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1));
else
read_en <= false;
end if;
-- tRTP is counted from read command + AL for BL4, read command + AL + 2
-- for BL8. This check covers both cases by writing readtime on the next-to-last
-- transfer.
if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then
banks(accpipe(2+al).bank).readtime := now;
end if;
write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w;
if accpipe(3+cl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(3+cl+al).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en;
assert not (read_en and write_en);
if read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
assert to_X01(dqs)=(dqs'range => '0');
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Tue Oct 24 00:00:16 2017
--Host : CHRIS-PC running 64-bit major release (build 9200)
--Command : generate_target DemoConfigDesign_wrapper.bd
--Design : DemoConfigDesign_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoConfigDesign_wrapper is
port (
ULPI_clk : in STD_LOGIC;
ULPI_data_io : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ULPI_dir : in STD_LOGIC;
ULPI_next : in STD_LOGIC;
ULPI_rst : out STD_LOGIC;
ULPI_stop : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_resetn : in STD_LOGIC
);
end DemoConfigDesign_wrapper;
architecture STRUCTURE of DemoConfigDesign_wrapper is
component DemoConfigDesign is
port (
ULPI_clk : in STD_LOGIC;
ULPI_data_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
ULPI_data_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
ULPI_data_t : out STD_LOGIC;
ULPI_dir : in STD_LOGIC;
ULPI_next : in STD_LOGIC;
ULPI_rst : out STD_LOGIC;
ULPI_stop : out STD_LOGIC;
sys_resetn : in STD_LOGIC;
sys_clk : in STD_LOGIC
);
end component DemoConfigDesign;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal ULPI_data_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ULPI_data_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal ULPI_data_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal ULPI_data_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal ULPI_data_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal ULPI_data_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal ULPI_data_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal ULPI_data_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal ULPI_data_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ULPI_data_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal ULPI_data_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal ULPI_data_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal ULPI_data_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal ULPI_data_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal ULPI_data_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal ULPI_data_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal ULPI_data_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal ULPI_data_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal ULPI_data_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal ULPI_data_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal ULPI_data_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal ULPI_data_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal ULPI_data_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal ULPI_data_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal ULPI_data_t : STD_LOGIC;
begin
DemoConfigDesign_i: component DemoConfigDesign
port map (
ULPI_clk => ULPI_clk,
ULPI_data_i(7) => ULPI_data_i_7(7),
ULPI_data_i(6) => ULPI_data_i_6(6),
ULPI_data_i(5) => ULPI_data_i_5(5),
ULPI_data_i(4) => ULPI_data_i_4(4),
ULPI_data_i(3) => ULPI_data_i_3(3),
ULPI_data_i(2) => ULPI_data_i_2(2),
ULPI_data_i(1) => ULPI_data_i_1(1),
ULPI_data_i(0) => ULPI_data_i_0(0),
ULPI_data_o(7) => ULPI_data_o_7(7),
ULPI_data_o(6) => ULPI_data_o_6(6),
ULPI_data_o(5) => ULPI_data_o_5(5),
ULPI_data_o(4) => ULPI_data_o_4(4),
ULPI_data_o(3) => ULPI_data_o_3(3),
ULPI_data_o(2) => ULPI_data_o_2(2),
ULPI_data_o(1) => ULPI_data_o_1(1),
ULPI_data_o(0) => ULPI_data_o_0(0),
ULPI_data_t => ULPI_data_t,
ULPI_dir => ULPI_dir,
ULPI_next => ULPI_next,
ULPI_rst => ULPI_rst,
ULPI_stop => ULPI_stop,
sys_clk => sys_clk,
sys_resetn => sys_resetn
);
ULPI_data_iobuf_0: component IOBUF
port map (
I => ULPI_data_o_0(0),
IO => ULPI_data_io(0),
O => ULPI_data_i_0(0),
T => ULPI_data_t
);
ULPI_data_iobuf_1: component IOBUF
port map (
I => ULPI_data_o_1(1),
IO => ULPI_data_io(1),
O => ULPI_data_i_1(1),
T => ULPI_data_t
);
ULPI_data_iobuf_2: component IOBUF
port map (
I => ULPI_data_o_2(2),
IO => ULPI_data_io(2),
O => ULPI_data_i_2(2),
T => ULPI_data_t
);
ULPI_data_iobuf_3: component IOBUF
port map (
I => ULPI_data_o_3(3),
IO => ULPI_data_io(3),
O => ULPI_data_i_3(3),
T => ULPI_data_t
);
ULPI_data_iobuf_4: component IOBUF
port map (
I => ULPI_data_o_4(4),
IO => ULPI_data_io(4),
O => ULPI_data_i_4(4),
T => ULPI_data_t
);
ULPI_data_iobuf_5: component IOBUF
port map (
I => ULPI_data_o_5(5),
IO => ULPI_data_io(5),
O => ULPI_data_i_5(5),
T => ULPI_data_t
);
ULPI_data_iobuf_6: component IOBUF
port map (
I => ULPI_data_o_6(6),
IO => ULPI_data_io(6),
O => ULPI_data_i_6(6),
T => ULPI_data_t
);
ULPI_data_iobuf_7: component IOBUF
port map (
I => ULPI_data_o_7(7),
IO => ULPI_data_io(7),
O => ULPI_data_i_7(7),
T => ULPI_data_t
);
end STRUCTURE;
|
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cfe40c",
3 => x"3a0b0b80",
4 => x"c7ba0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
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2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002e48",
2965 => x"00002e48",
2966 => x"00002e50",
2967 => x"00002e50",
2968 => x"00002e58",
2969 => x"00002e58",
2970 => x"00002e60",
2971 => x"00002e60",
2972 => x"00002e68",
2973 => x"00002e68",
2974 => x"00002e70",
2975 => x"00002e70",
2976 => x"00002e78",
2977 => x"00002e78",
2978 => x"00002e80",
2979 => x"00002e80",
2980 => x"00002e88",
2981 => x"00002e88",
2982 => x"00002e90",
2983 => x"00002e90",
2984 => x"00002e98",
2985 => x"00002e98",
2986 => x"00002ea0",
2987 => x"00002ea0",
2988 => x"00002ea8",
2989 => x"00002ea8",
2990 => x"00002eb0",
2991 => x"00002eb0",
2992 => x"00002eb8",
2993 => x"00002eb8",
2994 => x"00002ec0",
2995 => x"00002ec0",
2996 => x"00002ec8",
2997 => x"00002ec8",
2998 => x"00002ed0",
2999 => x"00002ed0",
3000 => x"00002ed8",
3001 => x"00002ed8",
3002 => x"00002ee0",
3003 => x"00002ee0",
3004 => x"00002ee8",
3005 => x"00002ee8",
3006 => x"00002ef0",
3007 => x"00002ef0",
3008 => x"00002ef8",
3009 => x"00002ef8",
3010 => x"00002f00",
3011 => x"00002f00",
3012 => x"00002f08",
3013 => x"00002f08",
3014 => x"00002f10",
3015 => x"00002f10",
3016 => x"00002f18",
3017 => x"00002f18",
3018 => x"00002f20",
3019 => x"00002f20",
3020 => x"00002f28",
3021 => x"00002f28",
3022 => x"00002f30",
3023 => x"00002f30",
3024 => x"00002f38",
3025 => x"00002f38",
3026 => x"00002f40",
3027 => x"00002f40",
3028 => x"00002f48",
3029 => x"00002f48",
3030 => x"00002f50",
3031 => x"00002f50",
3032 => x"00002f58",
3033 => x"00002f58",
3034 => x"00002f60",
3035 => x"00002f60",
3036 => x"00002f68",
3037 => x"00002f68",
3038 => x"00002f70",
3039 => x"00002f70",
3040 => x"00002f78",
3041 => x"00002f78",
3042 => x"00002f80",
3043 => x"00002f80",
3044 => x"00002f88",
3045 => x"00002f88",
3046 => x"00002f90",
3047 => x"00002f90",
3048 => x"00002f98",
3049 => x"00002f98",
3050 => x"00002fa0",
3051 => x"00002fa0",
3052 => x"00002fa8",
3053 => x"00002fa8",
3054 => x"000027d4",
3055 => x"ffffffff",
3056 => x"00000000",
3057 => x"ffffffff",
3058 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Garfield is
port(
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLK
-- CLK_I2C_SCL : out std_logic;
-- CLK_I2C_SDA : inout std_logic;
-- FPGA
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- GPIO
GPIO_0 : inout std_logic_vector(35 downto 0);
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic;
-- Key
KEY : in std_logic_vector(1 downto 0);
-- LEDs
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0)
);
end Garfield;
architecture RTL of Garfield is
component Garfield_system is
port (
clk_clk : in std_logic := 'X'; -- clk
clk_1_fpga_clock_clk : in std_logic := 'X'; -- clk
clk_1_fpga_reset_reset_n : in std_logic := 'X'; -- reset_n
drive_pwm_pwm_signal_export : out std_logic; -- export
garfield_general_io_external_connection_export : out std_logic_vector(7 downto 0); -- export
garfield_lighting_led_external_connection_export : out std_logic_vector(3 downto 0); -- export
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_opencores_0_export_sda_pad_in : in std_logic := 'X'; -- sda_pad_in
i2c_opencores_0_export_sda_pad_out : out std_logic; -- sda_pad_out
i2c_opencores_0_export_sda_pad_en : out std_logic; -- sda_pad_en
i2c_opencores_0_export_scl_pad_in : in std_logic := 'X'; -- scl_pad_in
i2c_opencores_0_export_scl_pad_out : out std_logic; -- scl_pad_out
i2c_opencores_0_export_scl_pad_en : out std_logic; -- scl_pad_en
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
onboard_button_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
onboard_dipsw_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
onboard_led_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
rotary_encoder_0_conduit_end_rot_input : in std_logic := 'X'; -- rot_input
spi_0_external_connection_MISO : in std_logic := 'X'; -- MISO
spi_0_external_connection_MOSI : out std_logic; -- MOSI
spi_0_external_connection_SCLK : out std_logic; -- SCLK
spi_0_external_connection_SS_n : out std_logic_vector(2 downto 0); -- SS_n
steering_pwm_pwm_signal_export : out std_logic -- export
);
end component Garfield_system;
component altera_edge_detector is
generic(
PULSE_EXT : natural := 0;
EDGE_TYPE : natural := 0;
IGNORE_RST_WHILE_BUSY : natural := 0
);
port(
clk : in std_logic;
rst_n : in std_logic;
signal_in : in std_logic;
pulse_out : out std_logic
);
end component;
component hps_reset is
port(
probe : in std_logic;
source_clk : in std_logic;
source : out std_logic_vector(2 downto 0)
);
end component;
----------------------------------------------------------------------------
---------------------- signals for top level logic
----------------------------------------------------------------------------
signal hps_fpga_reset_n : std_logic;
signal fpga_debounced_buttons : std_logic_vector(1 downto 0);
signal fpga_led_internal : std_logic_vector(7 downto 0);
signal hps_reset_req : std_logic_vector(2 downto 0);
signal hps_cold_reset : std_logic;
signal hps_warm_reset : std_logic;
signal hps_debug_reset : std_logic;
signal stm_hw_events : std_logic_vector(27 downto 0);
signal fpga_clk_50 : std_logic;
signal spi_0_miso : std_logic;
signal spi_0_mosi : std_logic;
signal spi_0_sclk : std_logic;
signal spi_0_cs_n : std_logic_vector(2 downto 0);
signal i2c0_sda_i : std_logic;
signal i2c0_sda_o : std_logic;
signal i2c0_sda_en : std_logic;
signal i2c0_scl_i : std_logic;
signal i2c0_scl_o : std_logic;
signal i2c0_scl_en : std_logic;
signal garfield_lighting : std_logic_vector(3 downto 0);
signal garfield_gpio : std_logic_vector(7 downto 0);
signal garfield_drive_pwm : std_logic;
signal garfield_steering_pwm : std_logic;
signal speed_rotary : std_logic;
signal status_led : std_logic := '0';
signal status_led_counter : natural := 0;
begin
u0 : component Garfield_system
port map(
clk_clk => FPGA_CLK1_50, -- clk.clk
clk_1_fpga_clock_clk => FPGA_CLK2_50, -- clk_1_fpga_clock.clk
clk_1_fpga_reset_reset_n => hps_fpga_reset_n, -- clk_1_fpga_reset.reset_n
drive_pwm_pwm_signal_export => garfield_drive_pwm, -- drive_pwm_pwm_signal.export
garfield_general_io_external_connection_export => garfield_gpio, -- garfield_general_io_external_connection.export
garfield_lighting_led_external_connection_export => garfield_lighting, -- garfield_lighting_led_external_connection.export
hps_0_f2h_cold_reset_req_reset_n => not hps_cold_reset, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => not hps_debug_reset, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => stm_hw_events, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => not hps_warm_reset, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => hps_fpga_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
onboard_button_external_connection_export => fpga_debounced_buttons, -- onboard_button_external_connection.export
onboard_dipsw_external_connection_export => SW, -- onboard_dipsw_external_connection.export
onboard_led_external_connection_export => fpga_led_internal, -- onboard_led_external_connection.export
reset_reset_n => hps_fpga_reset_n, -- reset.reset_n
rotary_encoder_0_conduit_end_rot_input => speed_rotary, -- rotary_encoder_0_conduit_end.rot_input
spi_0_external_connection_MISO => spi_0_miso, -- spi_0_external_connection.MISO
spi_0_external_connection_MOSI => spi_0_mosi, -- .MOSI
spi_0_external_connection_SCLK => spi_0_sclk, -- .SCLK
spi_0_external_connection_SS_n => spi_0_cs_n, -- .SS_n
steering_pwm_pwm_signal_export => garfield_steering_pwm, -- steering_pwm_pwm_signal.export
i2c_opencores_0_export_sda_pad_in => i2c0_sda_i, -- sda_pad_in
i2c_opencores_0_export_sda_pad_out => i2c0_sda_o, -- sda_pad_out
i2c_opencores_0_export_sda_pad_en => i2c0_sda_en, -- sda_pad_en
i2c_opencores_0_export_scl_pad_in => i2c0_scl_i, -- scl_pad_in
i2c_opencores_0_export_scl_pad_out => i2c0_scl_o, -- scl_pad_out
i2c_opencores_0_export_scl_pad_en => i2c0_scl_en
);
pulse_cold_reset : component altera_edge_detector
generic map(
PULSE_EXT => 6,
EDGE_TYPE => 1,
IGNORE_RST_WHILE_BUSY => 1
)
port map(
clk => fpga_clk_50,
rst_n => hps_fpga_reset_n,
signal_in => hps_reset_req(0),
pulse_out => hps_cold_reset
);
pulse_warm_reset : component altera_edge_detector
generic map(
PULSE_EXT => 2,
EDGE_TYPE => 1,
IGNORE_RST_WHILE_BUSY => 1
)
port map(
clk => fpga_clk_50,
rst_n => hps_fpga_reset_n,
signal_in => hps_reset_req(1),
pulse_out => hps_warm_reset
);
pulse_debug_reset : component altera_edge_detector
generic map(
PULSE_EXT => 32,
EDGE_TYPE => 1,
IGNORE_RST_WHILE_BUSY => 1
)
port map(
clk => fpga_clk_50,
rst_n => hps_fpga_reset_n,
signal_in => hps_reset_req(2),
pulse_out => hps_debug_reset
);
----------------------------------------------------------------------------
-- concurrent statements
----------------------------------------------------------------------------
-- i2c0
GPIO_1(0) <= 'Z' when i2c0_sda_en = '1' else i2c0_sda_o;
GPIO_1(2) <= 'Z' when i2c0_scl_en = '1' else i2c0_scl_o;
i2c0_sda_i <= GPIO_1(0);
i2c0_scl_i <= GPIO_1(2);
-- garfield lighting
GPIO_1(1) <= garfield_lighting(0);
GPIO_1(3) <= garfield_lighting(1);
GPIO_1(5) <= garfield_lighting(2);
GPIO_1(7) <= garfield_lighting(3);
-- spi for display
ARDUINO_IO(13) <= spi_0_sclk;
ARDUINO_IO(12) <= spi_0_miso;
ARDUINO_IO(11) <= spi_0_mosi;
ARDUINO_IO(10) <= spi_0_cs_n(0); -- tft chipselect
ARDUINO_IO(9) <= garfield_gpio(7); -- tft data command switch
ARDUINO_IO(4) <= spi_0_cs_n(1); -- sd card chipselect
-- pwm's and rotary of garfield
GPIO_1(4) <= garfield_drive_pwm;
GPIO_1(6) <= garfield_gpio(0);
GPIO_1(9) <= garfield_steering_pwm;
speed_rotary <= GPIO_1(11);
-- others
stm_hw_events <= (others => '0');
fpga_clk_50 <= FPGA_CLK1_50;
LED(7 downto 1) <= fpga_led_internal(7 downto 1);
LED(0) <= status_led;
----------------------------------------------------------------------------
-- processes
----------------------------------------------------------------------------
status_led_proc : process(fpga_clk_50, hps_fpga_reset_n) is
begin
if (hps_fpga_reset_n = '0') then
status_led_counter <= 0;
elsif (rising_edge(fpga_clk_50)) then
if status_led_counter = 24999999 then
status_led <= not status_led;
status_led_counter <= 0;
else
status_led_counter <= status_led_counter + 1;
end if;
end if;
end process status_led_proc;
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity Mux4_1 is
port(
Data0 : in vl_logic_vector(31 downto 0);
Data1 : in vl_logic_vector(31 downto 0);
Data2 : in vl_logic_vector(31 downto 0);
Data3 : in vl_logic_vector(31 downto 0);
Sel : in vl_logic_vector(1 downto 0);
Data : out vl_logic_vector(31 downto 0)
);
end Mux4_1;
|
library verilog;
use verilog.vl_types.all;
entity Mux4_1 is
port(
Data0 : in vl_logic_vector(31 downto 0);
Data1 : in vl_logic_vector(31 downto 0);
Data2 : in vl_logic_vector(31 downto 0);
Data3 : in vl_logic_vector(31 downto 0);
Sel : in vl_logic_vector(1 downto 0);
Data : out vl_logic_vector(31 downto 0)
);
end Mux4_1;
|
-- SLCD.VHD (a peripheral module for SCOMP)
-- 2009.10.10
--
-- The simple LCD controller displays a single 16 bit register on the top line
-- of the LCD.
-- It sends an initialization string to the LCD, then repeatedly writes a four-
-- digit hex value to a fixed location in the display. The value is latched
-- whenever the device is selected by CS.
-- See datasheets for the HD44780 or equivalent LCD controller.
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY SLCD IS
PORT(
CLOCK_10KHZ : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
CS : IN STD_LOGIC;
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
LCD_D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END SLCD;
ARCHITECTURE a OF SLCD IS
TYPE STATE_TYPE IS (
RESET,
INIT,
INIT_CLOCK,
CURPOS,
CURPOS_CLOCK,
SWRITE,
SWRITE_CLOCK
);
TYPE CSTR15_TYPE IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE CSTR08_TYPE IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE CSTR04_TYPE IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL state : STATE_TYPE;
SIGNAL ascii : CSTR15_TYPE;
SIGNAL cstr : CSTR04_TYPE;
SIGNAL istr : CSTR08_TYPE;
SIGNAL count : INTEGER RANGE 0 TO 1000;
SIGNAL delay : INTEGER RANGE 0 TO 100;
SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
-- LCD initialization string
istr(0) <= x"38"; -- Wakeup
istr(1) <= x"38"; -- Wakeup
istr(2) <= x"38"; -- Wakeup
istr(3) <= x"38"; -- Function set: 2 lines, 5x8 dot font
istr(4) <= x"08"; -- Display off
istr(5) <= x"01"; -- Clear display
istr(6) <= x"0C"; -- Display on
istr(7) <= x"04"; -- Entry mode set (left to right)
ascii( 0) <= x"30"; -- ASCII table values
ascii( 1) <= x"31";
ascii( 2) <= x"32";
ascii( 3) <= x"33";
ascii( 4) <= x"34";
ascii( 5) <= x"35";
ascii( 6) <= x"36";
ascii( 7) <= x"37";
ascii( 8) <= x"38";
ascii( 9) <= x"39";
ascii(10) <= x"41";
ascii(11) <= x"42";
ascii(12) <= x"43";
ascii(13) <= x"44";
ascii(14) <= x"45";
ascii(15) <= x"46";
LCD_RW <= '0';
cstr(0) <= ascii(CONV_INTEGER(data_in( 3 DOWNTO 0)));
cstr(1) <= ascii(CONV_INTEGER(data_in( 7 DOWNTO 4)));
cstr(2) <= ascii(CONV_INTEGER(data_in(11 DOWNTO 8)));
cstr(3) <= ascii(CONV_INTEGER(data_in(15 DOWNTO 12)));
-- This process latches the incoming data value on the rising edge of CS
PROCESS (RESETN, CS)
BEGIN
IF (RESETN = '0') THEN
data_in <= x"0000";
ELSIF (RISING_EDGE(CS)) THEN
data_in <= IO_DATA;
END IF;
END PROCESS;
-- This processes writes the latched data values to the LCD
PROCESS (RESETN, CLOCK_10KHZ)
BEGIN
IF (RESETN = '0') THEN
LCD_D <= x"00";
LCD_RS <= '0';
LCD_E <= '0';
count <= 0;
delay <= 0;
state <= RESET;
ELSIF (RISING_EDGE(CLOCK_10KHZ)) THEN
CASE state IS
WHEN RESET => -- wait about 0.1 sec (exceeds 15 ms requirement)
IF (count > 999) THEN
count <= 0;
state <= INIT;
ELSE
count <= count + 1;
END IF;
WHEN INIT => -- send an init command
LCD_RS <= '0';
LCD_E <= '1';
LCD_D <= istr(count);
count <= count + 1;
delay <= 0;
state <= INIT_CLOCK;
WHEN INIT_CLOCK => -- latch the command and wait
LCD_E <= '0'; -- dropping LCD_E latches
delay <= delay + 1;
IF (delay >= 99) THEN -- wait about 10 ms between init commands
IF (count < 8) THEN
state <= INIT;
ELSE
state <= CURPOS;
END IF;
END IF;
-- all remaining states have no waits. 100 us per state
-- write (enable) states alternate with latching states
WHEN CURPOS => -- Move to 11th character posn on line 1
LCD_RS <= '0';
LCD_E <= '1';
LCD_D <= x"8A";
state <= CURPOS_CLOCK;
WHEN CURPOS_CLOCK =>
LCD_E <= '0';
count <= 0;
state <= SWRITE;
WHEN SWRITE => -- Write (least significant digit first)
LCD_RS <= '1';
LCD_E <= '1';
LCD_D <= cstr(count);
count <= count + 1;
state <= SWRITE_CLOCK;
WHEN SWRITE_CLOCK => -- Finish write (moves left on screen in chosen mode)
LCD_E <= '0';
IF (count >= 4) THEN
state <= CURPOS;
ELSE
state <= SWRITE;
END IF;
END CASE;
END IF;
END PROCESS;
END a;
|
------------------------------------------------------------------------------
-- adau1761_audio.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: adau1761_audio.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library adau1761_audio_v1_00_a;
use adau1761_audio_v1_00_a.user_logic;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity adau1761_audio is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
--AC_SDA : INOUT std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity adau1761_audio;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of adau1761_audio is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal AC_SDA_tmp : std_logic;
signal clk_48_s : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity adau1761_audio_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
clk_48_o <= clk_48_s;
--AC_SDA_tmp <= AC_SDA_I when AC_SDA_T = '0' else 'Z';
--AC_SDA_O <= AC_SDA_tmp;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- adau1761_audio.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: adau1761_audio.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library adau1761_audio_v1_00_a;
use adau1761_audio_v1_00_a.user_logic;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity adau1761_audio is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
--AC_SDA : INOUT std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity adau1761_audio;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of adau1761_audio is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal AC_SDA_tmp : std_logic;
signal clk_48_s : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity adau1761_audio_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
clk_48_o <= clk_48_s;
--AC_SDA_tmp <= AC_SDA_I when AC_SDA_T = '0' else 'Z';
--AC_SDA_O <= AC_SDA_tmp;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp64a
-- File: ddrsp64a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr(0));
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
end case;
end if;
else
case r.waddr(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 4; v.dqm := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 64) := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+96 downto 0+96);
v.cfg.cke := wdata(15+96);
v.cfg.renable := wdata(16+96);
v.cfg.dllrst := wdata(17+96);
v.cfg.command := wdata(20+96 downto 18+96);
v.cfg.csize := wdata(22+96 downto 21+96);
v.cfg.bsize := wdata(25+96 downto 23+96);
v.cfg.trcd := wdata(26+96);
v.cfg.trfc := wdata(29+96 downto 27+96);
v.cfg.trp := wdata(30+96);
v.cfg.refon := wdata(31+96);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp64a
-- File: ddrsp64a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 64-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp64a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr(0));
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
end case;
end if;
else
case r.waddr(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 4; v.dqm := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 64) := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+96 downto 0+96);
v.cfg.cke := wdata(15+96);
v.cfg.renable := wdata(16+96);
v.cfg.dllrst := wdata(17+96);
v.cfg.command := wdata(20+96 downto 18+96);
v.cfg.csize := wdata(22+96 downto 21+96);
v.cfg.bsize := wdata(25+96 downto 23+96);
v.cfg.trcd := wdata(26+96);
v.cfg.trfc := wdata(29+96 downto 27+96);
v.cfg.trp := wdata(30+96);
v.cfg.refon := wdata(31+96);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap
-- File: tap.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: TAP controller technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
library grlib;
use grlib.stdlib.all;
entity tap is
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1;
tcknen: integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
tapo_tckn : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0'
);
end;
architecture rtl of tap is
signal ltck, ltckn, lltckn, llltckn : std_ulogic;
begin
xcv : if tech = virtex generate
u0 : virtex_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc2v : if tech = virtex2 generate
u0 : virtex2_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc4v : if tech = virtex4 generate
u0 : virtex4_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc5v : if tech = virtex5 generate
u0 : virtex5_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc6v : if tech = virtex6 generate
u0 : virtex6_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc7v : if tech = virtex7 generate
u0 : virtex7_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
kc7v : if tech = kintex7 generate
u0 : kintex7_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
ac7v : if tech = artix7 generate
u0 : artix7_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
zynq7v : if tech = zynq7000 generate
u0 : virtex7_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc3s : if (tech = spartan3) or (tech = spartan3e) generate
u0 : spartan3_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
xc6s : if (tech = spartan6) generate
u0 : spartan6_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) or (tech = cyclone3) generate
u0 : altera_tap port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_inst, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
pa3 : if (tech = apa3) generate
u0 : proasic3_tap port map (tck, tms, tdi, trst, tdo,
tapi_tdo1, tapi_tdo2, tapi_en1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_inst);
tdoen <= '0'; tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
pa3e : if (tech = apa3e) generate
u0 : proasic3e_tap port map (tck, tms, tdi, trst, tdo,
tapi_tdo1, tapi_tdo2, tapi_en1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_inst);
tdoen <= '0'; tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
pa3l : if (tech = apa3l) generate
u0 : proasic3l_tap port map (tck, tms, tdi, trst, tdo,
tapi_tdo1, tapi_tdo2, tapi_en1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_inst);
tdoen <= '0'; tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
fus : if (tech = actfus) generate
u0 : fusion_tap port map (tck, tms, tdi, trst, tdo,
tapi_tdo1, tapi_tdo2, tapi_en1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_inst);
tdoen <= '0'; tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
inf : if has_tap(tech) = 0 generate
asic : if is_fpga(tech) = 0 generate
gtn: if tcknen /= 0 generate
llltckn <= '0';
lltckn <= tckn;
end generate;
noscn : if tcknen=0 and scantest = 0 generate
llltckn <= '0';
lltckn <= not tck;
end generate;
gscn : if tcknen=0 and scantest = 1 generate
llltckn <= not tck;
usecmux: if has_clkmux(tech)/=0 generate
cmux0: clkmux generic map (tech) port map (llltckn, tck, testen, lltckn);
end generate;
usegmux: if has_clkmux(tech)=0 generate
gmux2_0 : grmux2 generic map (tech) port map (llltckn, tck, testen, lltckn);
end generate;
end generate;
pclk : techbuf generic map (tech => tech) port map (tck, ltck);
nclk : techbuf generic map (tech => tech) port map (lltckn, ltckn);
end generate;
fpga : if is_fpga(tech) = 1 generate
ltck <= tck; ltckn <= not tck;
end generate;
u0 : tap_gen generic map (irlen => irlen, manf => manf, part => part, ver => ver,
idcode => idcode, scantest => scantest, oepol => oepol)
port map (trst, ltck, ltckn, tms, tdi, tdo, tapi_en1, tapi_tdo1, tapi_tdo2, tapo_tck,
tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1,
tapo_xsel2, tapo_ninst, tapo_iupd, testen, testrst, testoen, tdoen);
tapo_tckn <= ltckn;
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_bus_writer is
end test_bus_writer;
architecture behavioural of test_bus_writer is
component bus_writer is
generic (
bus_length : natural;
bus_index : natural;
value : std_logic_vector(7 downto 0)
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component bus_writer;
signal clock : std_logic;
signal data_bus : std_logic_vector(7 downto 0);
begin
WRITER: bus_writer generic map (
bus_length => 3,
bus_index => 1, --- The middle one
value => "11111111"
)
port map (
clock,
data_bus
);
process
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "11111111"
report "Data should be recieved on tick 1" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 2" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 3" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "11111111"
report "Data should be recieved on tick 4" severity error;
wait;
end process;
end behavioural;
|
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2nySnfl05ePoGD/ZCEM=
`protect end_protected
|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.constants.all;
use IEEE.Numeric_std.all;
entity MemoryController is
port (
CLK : in std_logic;
Address : in word;
Enable : in std_logic;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Reset : in std_logic;
Done : out std_logic;
SRAM_addr : out std_logic_vector(20 downto 0);
SRAM_OE : out std_logic;
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_data : inout std_logic_vector(7 downto 0);
Status_Debug : out std_logic_vector(7 downto 0)
);
end MemoryController;
architecture Behavioral of MemoryController is
constant LoadByteUnsigned : Operator := "000";
constant LoadByteSigned : Operator := "001";
constant LoadHalfWordUnsigned : Operator := "010";
constant LoadHalfWordSigned : Operator := "011";
constant LoadWord : Operator := "100";
constant StoreByte : Operator := "101";
constant StoreHalfWord : Operator := "110";
constant StoreWord : Operator := "111";
-- outputTest (absolute jump)
--constant BootImage : MemoryArray := ("01000001","00000000","00100000","00100100","00000000","00000000","00100001","10110100","00000001","00000000","00000000","11000100","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
-- outputTest (relative jump)
constant BootImage : MemoryArray := ("01000001","00000000","00100000","00100100","00000000","00000000","00100001","10110100","11111111","11111111","11111111","11001011","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
-- ROT13
--constant BootImage : MemoryArray := ("00000000","00000000","10000001","10100100","01000001","00000000","00100100","01110100","00001010","00000000","00100000","11011000","01011011","00000000","00100100","01110100","00001001","00000000","00100000","11011000","01100001","00000000","00100100","01110100","00000110","00000000","00100000","11011000","01111011","00000000","00100100","01110100","00001100","00000000","00100000","11011000","00000011","00000000","00000000","11001000","00000000","00000000","10000001","10110100","11110101","11111111","11111111","11001011","11111110","11111111","11111111","11001011","10111111","11111111","10000100","00100100","00001101","00000000","10000100","00100100","00011010","00000000","00100100","01110100","00000010","00000000","00100000","11011000","11100110","11111111","10000100","00100100","01000001","00000000","10000100","00100100","11110111","11111111","11111111","11001011","10011111","11111111","10000100","00100100","00001101","00000000","10000100","00100100","00011010","00000000","00100100","01110100","00000010","00000000","00100000","11011000","11100110","11111111","10000100","00100100","01100001","00000000","10000100","00100100","11110000","11111111","11111111","11001011","00000000","00000000","00000000");--(others => (others => '0'));
signal FromRead_S : Word := (others => '0');
signal NeedsInit : std_logic := '1';
signal BootImageIndex : Integer := 0;
signal Done_s : std_logic := '0';
signal SRAM_addr_s : std_logic_vector(20 downto 0) := (others => '0');
signal SRAM_data_s : std_logic_vector(7 downto 0); --:= (others => 'Z');
signal SRAM_OE_s : std_logic := '1';
signal SRAM_WE_s : std_logic := '1';
signal SRAM_CE_s : std_logic := '1';
signal AddressOffset : integer := 0;
signal Status_Debug_s : std_logic_vector(7 downto 0) := (others => '0');
begin -- Behavioral
SRAM_addr <= SRAM_addr_s;
SRAM_data <= SRAM_data_s when SRAM_OE_s = '1' else (others => 'Z');
SRAM_OE <= SRAM_OE_s;
SRAM_WE <= SRAM_WE_s;
SRAM_CE <= '0';
FromRead <= FromRead_S;
Done <= Done_s;
Status_Debug <= Status_Debug_S;
process (CLK)--(Enable, Instruction, Address, Reset)
-- procedure initialize is begin
-- Memory(0) <= "00000000";
-- Memory(1) <= "00000000";
-- Memory(2) <= "10000001";
-- Memory(3) <= "10100100";
-- Memory(4) <= "01000001";
-- Memory(5) <= "00000000";
-- Memory(6) <= "00100100";
-- Memory(7) <= "01110100";
-- Memory(8) <= "00001010";
-- Memory(9) <= "00000000";
-- Memory(10) <= "00100000";
-- Memory(11) <= "11011000";
-- Memory(12) <= "01011011";
-- Memory(13) <= "00000000";
-- Memory(14) <= "00100100";
-- Memory(15) <= "01110100";
---- Memory(16) <= "00001001";
---- Memory(17) <= "00000000";
---- Memory(18) <= "00100000";
---- Memory(19) <= "11011000";
---- Memory(20) <= "01100001";
---- Memory(21) <= "00000000";
---- Memory(22) <= "00100100";
---- Memory(23) <= "01110100";
---- Memory(24) <= "00000110";
---- Memory(25) <= "00000000";
---- Memory(26) <= "00100000";
---- Memory(27) <= "11011000";
---- Memory(28) <= "01111011";
---- Memory(29) <= "00000000";
---- Memory(30) <= "00100100";
---- Memory(31) <= "01110100";
---- Memory(32) <= "00001100";
---- Memory(33) <= "00000000";
---- Memory(34) <= "00100000";
---- Memory(35) <= "11011000";
---- Memory(36) <= "00000011";
---- Memory(37) <= "00000000";
---- Memory(38) <= "00000000";
---- Memory(39) <= "11001000";
---- Memory(40) <= "00000000";
---- Memory(41) <= "00000000";
---- Memory(42) <= "10000001";
---- Memory(43) <= "10110100";
---- Memory(44) <= "11110101";
---- Memory(45) <= "11111111";
---- Memory(46) <= "11111111";
---- Memory(47) <= "11001011";
---- Memory(48) <= "11111110";
---- Memory(49) <= "11111111";
---- Memory(50) <= "11111111";
---- Memory(51) <= "11001011";
---- Memory(52) <= "10111111";
---- Memory(53) <= "11111111";
---- Memory(54) <= "10000100";
---- Memory(55) <= "00100100";
---- Memory(56) <= "00001101";
---- Memory(57) <= "00000000";
---- Memory(58) <= "10000100";
---- Memory(59) <= "00100100";
---- Memory(60) <= "00011010";
---- Memory(61) <= "00000000";
---- Memory(62) <= "00100100";
---- Memory(63) <= "01110100";
---- Memory(64) <= "00000010";
---- Memory(65) <= "00000000";
---- Memory(66) <= "00100000";
---- Memory(67) <= "11011000";
---- Memory(68) <= "11100110";
---- Memory(69) <= "11111111";
---- Memory(70) <= "10000100";
---- Memory(71) <= "00100100";
---- Memory(72) <= "01000001";
---- Memory(73) <= "00000000";
---- Memory(74) <= "10000100";
---- Memory(75) <= "00100100";
---- Memory(76) <= "11110111";
---- Memory(77) <= "11111111";
---- Memory(78) <= "11111111";
---- Memory(79) <= "11001011";
---- Memory(80) <= "10011111";
---- Memory(81) <= "11111111";
---- Memory(82) <= "10000100";
---- Memory(83) <= "00100100";
---- Memory(84) <= "00001101";
---- Memory(85) <= "00000000";
---- Memory(86) <= "10000100";
---- Memory(87) <= "00100100";
---- Memory(88) <= "00011010";
---- Memory(89) <= "00000000";
---- Memory(90) <= "00100100";
---- Memory(91) <= "01110100";
---- Memory(92) <= "00000010";
---- Memory(93) <= "00000000";
---- Memory(94) <= "00100000";
---- Memory(95) <= "11011000";
---- Memory(96) <= "11100110";
---- Memory(97) <= "11111111";
---- Memory(98) <= "10000100";
---- Memory(99) <= "00100100";
---- Memory(100) <= "01100001";
---- Memory(101) <= "00000000";
---- Memory(102) <= "10000100";
---- Memory(103) <= "00100100";
---- Memory(104) <= "11110000";
---- Memory(105) <= "11111111";
---- Memory(106) <= "11111111";
---- Memory(107) <= "11001011";
-- --for I in 100 to 4095 loop
-- -- Memory(I) <= "00000000";
-- --end loop;
-- end procedure initialize;
variable current_operator : std_logic_vector(2 downto 0);
begin -- process
if rising_edge(CLK) then
if NeedsInit = '1' then
if BootImageIndex = BootImage'Length then
SRAM_we_s <= '1';
-- SRAM_addr_s <= "000000000000001101011";
-- SRAM_oe_s <= '0';
-- BootImageIndex <= BootImageIndex + 1;
-- elsif BootImageIndex = (BootImage'Length + 1) then
NeedsInit <= '0';
-- Status_Debug_S <= SRAM_data xor "11111111";
SRAM_oe_s <= '1';
else
SRAM_data_s <= BootImage(BootImageIndex);
SRAM_addr_s <= std_logic_vector(to_unsigned(BootImageIndex,21));
SRAM_we_s <= '0';
BootImageIndex <= BootImageIndex + 1;
end if;
--Memory <= (others => (others => '0'));
-- initialize;
elsif Enable = '1' then
current_operator := GetOperator(Instruction);
case current_operator is
when LoadByteUnsigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
Done_s <= '0';
else
FromRead_S <= "000000000000000000000000" & SRAM_data;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadByteSigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
Done_s <= '0';
else
FromRead_S <= std_logic_vector(resize(signed(SRAM_data),32));
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadHalfWordUnsigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 1 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset + 1,20));
AddressOffset <= AddressOffset + 1;
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
FromRead_S(31 downto 16) <= (others => '0');
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadHalfWordSigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 1 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset + 1,20));
AddressOffset <= AddressOffset + 1;
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
if SRAM_data(7) = '1' then
FromRead_S(31 downto 16) <= "1111111111111111";
else
FromRead_S(31 downto 16) <= "0000000000000000";
end if;
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadWord =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 3 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset+1,20));
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
AddressOffset <= AddressOffset + 1;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
Status_Debug_S <= Address(9 downto 2) xor "11111111";
end if;
when StoreByte =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
Done_s <= '1';
when StoreHalfWord =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
-- Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
Done_s <= '1';
when StoreWord =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
-- Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
-- Memory(to_integer(unsigned(Address)) + 2) <= ToWrite(23 downto 16);
-- Memory(to_integer(unsigned(Address)) + 3) <= ToWrite(31 downto 24);
Done_s <= '1';
when others => null;
end case;
else
SRAM_oe_s <= '1';
SRAM_we_s <= '1';
Done_s <= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0);
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0);
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
begin
---- User Signal Assignments ----
--assign address bus and be to openMAC
mac_addr <=
s_address(9 downto 1) & s_address(0) when mac_selfilter = '1' and endian_g = "little" else
s_address(9 downto 1) & not s_address(0) when endian_g = "little" else
s_address(9 downto 1) & s_address(0); -- when endian_g = "big" else
mac_be <=
s_byteenable(0) & s_byteenable(1) when endian_g = "little" else
s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout(15 downto 8) & mac_dout(7 downto 0) when (mac_selram = '1' or mac_selcont = '1') and s_byteenable = "11" and endian_g = "little" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else
smi_dout when smi_sel = '1' else
irqTable when irqTable_sel = '1' else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' else
(others => '0');
--assign writedata to input data
mac_din <=
s_writedata(15 downto 8) & s_writedata(7 downto 0) when s_byteenable = "11" and endian_g = "little" else
s_writedata(7 downto 0) & s_writedata(15 downto 8) when endian_g = "little" else
s_writedata; -- when endian_g = "big" else
smi_din <= s_writedata;
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata,
dout => t_readdata,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <=
dma_dout(7 downto 0) & dma_dout(15 downto 8) when endian_g = "little" else
dma_dout;
dma_din <=
dma_din_s(7 downto 0) & dma_din_s(15 downto 8) when endian_g = "little" else
dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <=
dma_addr(iPktBufSizeLog2_g-1 downto 2) & dma_addr(1) when endian_g = "little" else
dma_addr(iPktBufSizeLog2_g-1 downto 2) & not dma_addr(1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst, dma_ack_rw)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
endian_g => endian_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
|
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lisipif_master
-- Architectures: lisipif_master_rtl
-- Description:
-- The master attachment of the LIS-IPIF may be used by an IP to provide
-- a simplifed interface to the Processor Local Bus (PLB).
-- See the LIS-IPIF specification for details.
--
-- Dependencies:
--
-- Revision:
-- 7.3.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
--------------------------------------------------------------------------------
-- LIS-IPIF Master Entity Declaration
--------------------------------------------------------------------------------
entity lisipif_master is
generic (
C_NUM_WIDTH : integer := 5;
C_ARBITRATION : integer := 0;
C_EN_SRL16 : boolean := true;
C_EN_RECALC_ADDR : boolean := false; -- Not Implemented
C_EN_PIPELINING : boolean := true; -- Not Implemented
C_EN_FAST_ABORT : boolean := false -- Not Implemented
);
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
-- Read Transfer Signals
M_rdReq : in std_logic;
M_rdAccept : out std_logic;
M_rdAddr : in std_logic_vector(31 downto 0);
M_rdNum : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdBE : in std_logic_vector(7 downto 0);
M_rdData : out std_logic_vector(63 downto 0);
M_rdAck : out std_logic;
M_rdComp : out std_logic;
M_rdPriority : in std_logic_vector(1 downto 0);
M_rdType : in std_logic_vector(2 downto 0);
M_rdCompress : in std_logic;
M_rdGuarded : in std_logic;
M_rdLockErr : in std_logic;
M_rdRearb : out std_logic;
M_rdAbort : in std_logic;
M_rdError : out std_logic;
-- Write Transfer Signals
M_wrReq : in std_logic;
M_wrAccept : out std_logic;
M_wrAddr : in std_logic_vector(31 downto 0);
M_wrNum : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrBE : in std_logic_vector(7 downto 0);
M_wrData : in std_logic_vector(63 downto 0);
M_wrRdy : out std_logic;
M_wrAck : out std_logic;
M_wrComp : out std_logic;
M_wrPriority : in std_logic_vector(1 downto 0);
M_wrType : in std_logic_vector(2 downto 0);
M_wrCompress : in std_logic;
M_wrGuarded : in std_logic;
M_wrOrdered : in std_logic;
M_wrLockErr : in std_logic;
M_wrRearb : out std_logic;
M_wrAbort : in std_logic;
M_wrError : out std_logic;
-- Shared Transfer Signals
M_Error : out std_logic;
M_Lock : in std_logic;
-- PLB Signals
PLB_MAddrAck : in std_logic;
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
M_request : out std_logic; -- A
M_priority : out std_logic_vector(0 to 1); -- I
M_busLock : out std_logic; -- I
M_RNW : out std_logic; -- A
M_BE : out std_logic_vector(0 to 7); -- A
M_size : out std_logic_vector(0 to 3); -- A
M_type : out std_logic_vector(0 to 2); -- I
M_MSize : out std_logic_vector(0 to 1); -- C
M_compress : out std_logic; -- I
M_guarded : out std_logic; -- I
M_ordered : out std_logic; -- I
M_lockErr : out std_logic; -- I
M_abort : out std_logic; -- A
M_ABus : out std_logic_vector(0 to 31); -- A
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_wrBurst : out std_logic; -- W
M_wrDBus : out std_logic_vector(0 to 63); -- W
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
M_rdBurst : out std_logic; -- R
PLB_MRdDBus : in std_logic_vector(0 to 63)
);
end lisipif_master;
--------------------------------------------------------------------------------
-- LIS-IPIF Master RT Level Architecture
--------------------------------------------------------------------------------
architecture lisipif_master_rtl of lisipif_master is
-- Control Signals between Arbiter and Read/Write Controller
signal rd_rdy : std_logic; -- To arb: Ready for new transfer
signal rd_init : std_logic; -- From arb: Latch new transfer
signal rd_ack : std_logic; -- From arb: Transfer ack'd by slave
signal rd_rearb : std_logic; -- From arb: Rearbitrate transfer
signal rd_retry : std_logic; -- To arb: Repeat the transfer
signal rd_abort : std_logic; -- To arb: Abort the transfer
signal wr_rdy : std_logic; -- To arb: Ready for new transfer
signal wr_init : std_logic; -- From arb: Latch new transfer
signal wr_ack : std_logic; -- From arb: Transfer ack'd by slave
signal wr_rearb : std_logic; -- From arb: Rearbitrate transfer
signal wr_retry : std_logic; -- To arb: Repeat the transfer
signal wr_abort : std_logic; -- To arb: Abort the transfer
begin
M_MSize <= "01";
-- Arbiter
arbiter_0: entity lisipif_master_v1_00_c.lipif_mst_arbiter
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_ARBITRATION => C_ARBITRATION,
C_EN_SRL16 => C_EN_SRL16
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to Read and Write Controller
rd_rdy_i => rd_rdy,
rd_init_o => rd_init,
rd_ack_o => rd_ack,
rd_rearb_o => rd_rearb,
rd_retry_i => rd_retry,
rd_abort_i => rd_abort,
wr_rdy_i => wr_rdy,
wr_init_o => wr_init,
wr_ack_o => wr_ack,
wr_rearb_o => wr_rearb,
wr_retry_i => wr_retry,
wr_abort_i => wr_abort,
-- LIS-IPIC Read Qualifiers
M_rdReq_i => M_rdReq,
M_rdAccept_o => M_rdAccept,
M_rdAddr_i => M_rdAddr,
M_rdNum_i => M_rdNum,
M_rdBE_i => M_rdBE,
M_rdPriority_i => M_rdPriority,
M_rdType_i => M_rdType,
M_rdCompress_i => M_rdCompress,
M_rdGuarded_i => M_rdGuarded,
M_rdLockErr_i => M_rdLockErr,
-- LIS-IPIC Write Qualifiers
M_wrReq_i => M_wrReq,
M_wrAccept_o => M_wrAccept,
M_wrAddr_i => M_wrAddr,
M_wrNum_i => M_wrNum,
M_wrBE_i => M_wrBE,
M_wrPriority_i => M_wrPriority,
M_wrType_i => M_wrType,
M_wrCompress_i => M_wrCompress,
M_wrGuarded_i => M_wrGuarded,
M_wrOrdered_i => M_wrOrdered,
M_wrLockErr_i => M_wrLockErr,
-- LIS-IPIC Shared Qualifiers
M_Error_o => M_Error,
M_Lock_i => M_Lock,
-- PLB Signals
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MErr => PLB_MErr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus
);
-- Read Controller
read_ctrl_0: entity lisipif_master_v1_00_c.lipif_mst_read
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_EN_SRL16 => C_EN_SRL16,
C_EN_FAST_ABORT => C_EN_FAST_ABORT
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to/from Arbiter
xfer_rdy_o => rd_rdy,
xfer_init_i => rd_init,
xfer_ack_i => rd_ack,
xfer_rearb_i => rd_rearb,
xfer_retry_o => rd_retry,
xfer_abort_o => rd_abort,
-- LIS-IPIC Transfer Signals
M_rdNum_i => M_rdNum,
M_rdRearb_o => M_rdRearb,
M_rdAbort_i => M_rdAbort,
M_rdError_o => M_rdError,
M_rdData_o => M_rdData,
M_rdAck_o => M_rdAck,
M_rdComp_o => M_rdComp,
-- PLB Signals
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdWdAddr => PLB_MRdWdAddr,
M_rdBurst => M_rdBurst,
PLB_MRdDBus => PLB_MRdDBus
);
-- Write Controller
write_ctrl_0: entity lisipif_master_v1_00_c.lipif_mst_write
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_EN_SRL16 => C_EN_SRL16,
C_EN_FAST_ABORT => C_EN_FAST_ABORT
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to/from Arbiter
xfer_rdy_o => wr_rdy,
xfer_init_i => wr_init,
xfer_ack_i => wr_ack,
xfer_rearb_i => wr_rearb,
xfer_retry_o => wr_retry,
xfer_abort_o => wr_abort,
-- LIS-IPIC Transfer Signals
M_wrNum_i => M_wrNum,
M_wrRearb_o => M_wrRearb,
M_wrAbort_i => M_wrAbort,
M_wrError_o => M_wrError,
M_wrData_i => M_wrData,
M_wrRdy_o => M_wrRdy,
M_wrAck_o => M_wrAck,
M_wrComp_o => M_wrComp,
-- PLB Signals
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_wrBurst => M_WrBurst,
M_wrDBus => M_wrDBus
);
end lisipif_master_rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 186656)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg32_tb is
end reg32_tb;
architecture TB of reg32_tb is
component reg32
port(
D : in std_logic_vector(31 downto 0);
clk : in std_logic;
wr : in std_logic;
clr : in std_logic;
Q : out std_logic_vector(31 downto 0));
end component;
signal D : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal wr : std_logic;
signal clr : std_logic;
signal Q : std_logic_vector(31 downto 0);
signal sim_done : std_logic := '0';
begin -- TB
UUT: entity work.reg32
port map(
D => D,
clk => clk,
wr => wr,
clr => clr,
Q => Q);
-- toggle clock
clk <= not clk after 20 ns when sim_done = '0' else clk;
process
begin
-- reset
D <= x"1234ABCD";
wr <= '1';
clr <= '0';
wait until rising_edge(clk);
assert(Q = std_logic_vector(to_unsigned(0, 32))) report "Clear failed" severity warning;
-- load 1
D <= x"1234ABCD";
wr <= '1';
clr <= '1';
for i in 0 to 9 loop
wait until rising_edge(clk);
end loop;
assert(Q = std_logic_vector(to_unsigned(305441741, 32))) report "Clear failed" severity warning;
-- load 2
D <= x"ABCD1234";
wr <= '1';
clr <= '1';
for i in 0 to 2 loop
wait until rising_edge(clk);
end loop;
assert(Q = std_logic_vector(to_unsigned(305441741, 32))) report "Clear failed" severity warning;
clr <= '1';
report "SIMULATION FINISHED!";
sim_done <= '1';
end process;
end TB;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_54d148b4178eb862.vhd when simulating
-- the core, fr_cmplr_v6_3_54d148b4178eb862. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_54d148b4178eb862 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_54d148b4178eb862;
ARCHITECTURE fr_cmplr_v6_3_54d148b4178eb862_a OF fr_cmplr_v6_3_54d148b4178eb862 IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_54d148b4178eb862
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_54d148b4178eb862 USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "42",
c_accum_path_widths => "42",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_54d148b4178eb862.mif",
c_coef_file_lines => 18,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_54d148b4178eb862",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "24",
c_data_width => 24,
c_datapath_memtype => 2,
c_decim_rate => 2,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 1400000,
c_interp_rate => 1,
c_ipbuff_memtype => 2,
c_latency => 18,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 1,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 35,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25",
c_output_rate => 2800000,
c_output_width => 25,
c_oversampling_rate => 9,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 24,
c_s_data_tuser_width => 2,
c_symmetry => 1,
c_xdevicefamily => "virtex6",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_54d148b4178eb862
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_54d148b4178eb862_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end explosion_sound;
architecture content of explosion_sound is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(8 downto 0);
constant TEST: tune :=
(
"001001001",
"010001001",
"001001001",
"010001001",
"001001010",
"010001010",
"001001010",
"010001010",
"001001011",
"010001011",
"001001011",
"010001011",
"001001100",
"010001100",
"001001100",
"010001100",
"001001101",
"010001101",
"001001101",
"010001101",
"001001110",
"010001110",
"001001110",
"010001110",
"001001111",
"010001111",
"001001111",
"010001111",
"001001111",
"000000000",
"000000000",
"000000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity explosion_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end explosion_sound;
architecture content of explosion_sound is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(8 downto 0);
constant TEST: tune :=
(
"001001001",
"010001001",
"001001001",
"010001001",
"001001010",
"010001010",
"001001010",
"010001010",
"001001011",
"010001011",
"001001011",
"010001011",
"001001100",
"010001100",
"001001100",
"010001100",
"001001101",
"010001101",
"001001101",
"010001101",
"001001110",
"010001110",
"001001110",
"010001110",
"001001111",
"010001111",
"001001111",
"010001111",
"001001111",
"000000000",
"000000000",
"000000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
-- File: BitSlicingDemo.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:28:06 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_010.all;
entity BitSlicingDemo is
port (
MSB: in unsigned(4 downto 0);
LSB: in unsigned(4 downto 0);
Res: out signed (15 downto 0)
);
end entity BitSlicingDemo;
-- Demenstration Module for Bit Slicing in myHDL
--
-- Inputs:
-- MSB (5BitVec): Most Signficant Bit Index Must be > LSB,
-- ex: if LSB==0 MSB must range between 1 and 15
-- LSB (5BitVec): Lest Signficant Bit Index Must be < MSB
-- ex: if MSB==15 LSB must range beteen 0 and 15
--
-- Outputs:
-- Res(16BitVec Signed): Result of the slicing operation from
-- Refrance Vales (hard coded in module) -1749 (16BitVec Signed)
--
architecture MyHDL of BitSlicingDemo is
signal RefVal: signed (15 downto 0);
begin
RefVal <= to_signed(-1749, 16);
Res <= signed(unsigned(RefVal(to_integer(MSB)-1 downto to_integer(LSB))));
end architecture MyHDL;
|
entity recsignal1 is
end entity;
architecture test of recsignal1 is
type rec is record
x, y : integer;
end record;
signal p, q : rec;
begin
p1: p <= q;
end architecture;
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- MIIM register definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.miim_types.all;
package miim_registers is
-- Register numbers
constant CONTROL_REG : t_register_address := to_register_address(0);
constant STATUS_REG : t_register_address := to_register_address(1);
constant PHY_ID1_REG : t_register_address := to_register_address(2);
constant PHY_ID2_REG : t_register_address := to_register_address(3);
constant AUTONEG_ADVERTISEMENT_REG : t_register_address := to_register_address(4);
constant AUTONEG_LP_BASEPAGEABILITY_REG : t_register_address := to_register_address(5);
constant AUTONEG_EXPANSION_REG : t_register_address := to_register_address(6);
constant AUTONEG_NEXTPAGETX_REG : t_register_address := to_register_address(7);
constant AUTONEG_LP_NEXTPAGERECV_REG : t_register_address := to_register_address(8);
constant MASTERSLAVE_CTRL_REG : t_register_address := to_register_address(9);
constant MASTERSLAVE_STATUS_REG : t_register_address := to_register_address(10);
constant PSE_CONTROL_REG : t_register_address := to_register_address(11);
constant PSE_STATUS_REG : t_register_address := to_register_address(12);
constant MMD_ACCESSCONTROL_REG : t_register_address := to_register_address(13);
constant MMD_ACCESSADDRESSDATA_REG : t_register_address := to_register_address(14);
constant EXTENDED_STATUS_REG : t_register_address := to_register_address(15);
constant VENDOR_SPECIFIC_REG_BASE : t_register_address := to_register_address(16);
-- Register contents of selected registers
-- See Ethernet specification for the meaning of the fields
type t_control_register is record
reset : std_ulogic;
loopback : std_ulogic;
speed_10_100 : std_ulogic;
speed_1000 : std_ulogic;
auto_negotiation_enable : std_ulogic;
power_down : std_ulogic;
isolate : std_ulogic;
restart_auto_negotiation : std_ulogic;
duplex_mode : std_ulogic;
enable_collision_test : std_ulogic;
unidirectional_enable : std_ulogic;
end record;
type t_status_register is record
can_100base_t4 : std_ulogic;
can_100base_x_fd : std_ulogic;
can_100base_x_hd : std_ulogic;
can_10mbps_fd : std_ulogic;
can_10mbps_hd : std_ulogic;
can_100base_t2_fd : std_ulogic;
can_100base_t2_hd : std_ulogic;
extended_status : std_ulogic;
undirectional_ability : std_ulogic;
mf_preamble_suppression : std_ulogic;
auto_negotiation_complete : std_ulogic;
remote_fault : std_ulogic;
auto_negotiation_ability : std_ulogic;
link_status : std_ulogic;
jabber_detect : std_ulogic;
extended_capability : std_ulogic;
end record;
type t_auto_negotiation_advertisement_register_802_3 is record
next_page : std_ulogic;
remote_fault : std_ulogic;
extended_next_page : std_ulogic;
asymmetric_pause : std_ulogic;
pause : std_ulogic;
advertise_100base_t4 : std_ulogic;
advertise_100base_tx_fd : std_ulogic;
advertise_100base_tx_hd : std_ulogic;
advertise_10base_t_fd : std_ulogic;
advertise_10base_t_hd : std_ulogic;
end record;
type auto_negotiation_lp_base_page_ability_register_802_3_t is record
next_page : std_ulogic;
acknowledge : std_ulogic;
remote_fault : std_ulogic;
extended_next_page : std_ulogic;
asymmetric_pause : std_ulogic;
pause : std_ulogic;
can_100base_t4 : std_ulogic;
can_100base_tx_fd : std_ulogic;
can_100base_tx_hd : std_ulogic;
can_10base_t_fd : std_ulogic;
can_10base_t_hd : std_ulogic;
end record;
type t_master_slave_control_register is record
test_mode_bits : std_ulogic_vector(2 downto 0);
master_slave_manual_config_enable : std_ulogic;
master_slave_manual_config_value : std_ulogic;
port_type_is_multiport : std_ulogic;
advertise_1000base_t_fd : std_ulogic;
advertise_1000base_t_hd : std_ulogic;
end record;
type t_master_slave_status_register is record
master_slave_config_fault : std_ulogic;
master_slave_config_resolution : std_ulogic;
local_receiver_status : std_ulogic;
remote_receiver_status : std_ulogic;
lp_1000base_t_fd : std_ulogic;
lp_1000base_t_hd : std_ulogic;
idle_error_count : unsigned(7 downto 0);
end record;
constant AUTO_NEGOTATION_802_3_SELECTOR : std_ulogic_vector(4 downto 0) := "00001";
-- Selected conversion functions
-- Register records to 16-bit data values
function control_register_to_data(reg : in t_control_register) return t_data;
function auto_negotiation_advertisement_register_802_3_to_data(reg : in t_auto_negotiation_advertisement_register_802_3) return t_data;
function master_slave_control_register_to_data(reg : in t_master_slave_control_register) return t_data;
-- 16-bit data values to registers
function data_to_status_register(data : in t_data) return t_status_register;
function data_to_master_slave_status_register(data : in t_data) return t_master_slave_status_register;
function data_to_auto_negotiation_lp_base_page_ability_register(data : in t_data) return auto_negotiation_lp_base_page_ability_register_802_3_t;
end package;
package body miim_registers is
function control_register_to_data(reg : in t_control_register) return t_data is
variable data : t_data;
begin
data := (
15 => reg.reset,
14 => reg.loopback,
13 => reg.speed_10_100,
12 => reg.auto_negotiation_enable,
11 => reg.power_down,
10 => reg.isolate,
9 => reg.restart_auto_negotiation,
8 => reg.duplex_mode,
7 => reg.enable_collision_test,
6 => reg.speed_1000,
5 => reg.unidirectional_enable,
others => '0'
);
return data;
end function;
function auto_negotiation_advertisement_register_802_3_to_data(reg : in t_auto_negotiation_advertisement_register_802_3) return t_data is
variable data : t_data;
begin
data := (
15 => reg.next_page,
13 => reg.remote_fault,
12 => reg.extended_next_page,
11 => reg.asymmetric_pause,
10 => reg.pause,
9 => reg.advertise_100base_t4,
8 => reg.advertise_100base_tx_fd,
7 => reg.advertise_100base_tx_hd,
6 => reg.advertise_10base_t_fd,
5 => reg.advertise_10base_t_hd,
others => '0'
);
data(4 downto 0) := AUTO_NEGOTATION_802_3_SELECTOR;
return data;
end function;
function master_slave_control_register_to_data(reg : in t_master_slave_control_register) return t_data is
variable data : t_data;
begin
data := (
12 => reg.master_slave_manual_config_enable,
11 => reg.master_slave_manual_config_value,
10 => reg.port_type_is_multiport,
9 => reg.advertise_1000base_t_fd,
8 => reg.advertise_1000base_t_hd,
others => '0'
);
data(15 downto 13) := reg.test_mode_bits;
return data;
end function;
function data_to_status_register(data : in t_data) return t_status_register is
variable status : t_status_register;
begin
status := (
can_100base_t4 => data(15),
can_100base_x_fd => data(14),
can_100base_x_hd => data(13),
can_10mbps_fd => data(12),
can_10mbps_hd => data(11),
can_100base_t2_fd => data(10),
can_100base_t2_hd => data(9),
extended_status => data(8),
undirectional_ability => data(7),
mf_preamble_suppression => data(6),
auto_negotiation_complete => data(5),
remote_fault => data(4),
auto_negotiation_ability => data(3),
link_status => data(2),
jabber_detect => data(1),
extended_capability => data(0)
);
return status;
end function;
function data_to_master_slave_status_register(data : in t_data) return t_master_slave_status_register is
variable status : t_master_slave_status_register;
begin
status := (
master_slave_config_fault => data(15),
master_slave_config_resolution => data(14),
local_receiver_status => data(13),
remote_receiver_status => data(12),
lp_1000base_t_fd => data(11),
lp_1000base_t_hd => data(10),
idle_error_count => unsigned(data(7 downto 0))
);
return status;
end function;
function data_to_auto_negotiation_lp_base_page_ability_register(data : in t_data) return auto_negotiation_lp_base_page_ability_register_802_3_t is
variable ability : auto_negotiation_lp_base_page_ability_register_802_3_t;
begin
ability := (
next_page => data(15),
acknowledge => data(14),
remote_fault => data(13),
extended_next_page => data(12),
asymmetric_pause => data(11),
pause => data(10),
can_100base_t4 => data(9),
can_100base_tx_fd => data(8),
can_100base_tx_hd => data(7),
can_10base_t_fd => data(6),
can_10base_t_hd => data(5)
);
return ability;
end function;
end package body;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 18:52:36
-- Design Name:
-- Module Name: cam_move - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity cam_move is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
hsync_in : in std_logic;
vsync_in : in std_logic;
href_in : in std_logic;
cam_pxdata : in STD_LOGIC_VECTOR(7 downto 0);
-----
cam_clk : out STD_LOGIC;
px_number : out natural range 0 to 1024 := 0;
line_number : out natural range 0 to 1024 := 0;
pixel_data : out std_logic_vector(23 downto 0);
pixel_data_ready : out STD_LOGIC;
sensor_data : out sensor_vector;
sensor_data_ready : out STD_LOGIC
);
end cam_move;
architecture Behavioral of cam_move is
signal tmp_pixel_data_ready : std_logic := '0';
signal tmp_pixel_data : std_logic_vector(23 downto 0);
signal x, y : integer range 0 to 1024 := 0;
signal pclk : STD_LOGIC;
constant pclk_to_clk_rate : integer := 2;
signal outbus_free : STD_LOGIC;
signal tmp_sensor_data_ready : STD_LOGIC_VECTOR(4 downto 0);
component get_mark_points
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
px_data : in STD_LOGIC_VECTOR(7 downto 0);
data_ready : out STD_LOGIC;
px_count_out, line_count_out : out natural;
px_data_out : out STD_LOGIC_VECTOR(23 downto 0));
end component;
component check_sensor is
generic(sensor_position : pixel_position := (130, 50);
sensor_radius : integer range 16 downto 4 := 8);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
pixel_cnt : positive range 1 TO 1023;
line_cnt : positive range 1 TO 1023;
pixel_data : in STD_LOGIC_VECTOR(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : out sensor;
sensor_data_ready : out STD_LOGIC);
end component;
component sensor_gate is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sensor_ready : in STD_LOGIC;
sensor_in : in sensor;
outbus_free : in STD_LOGIC;
sensor_out : out sensor_vector;
sensor_data_ready : out std_logic
);
end component;
begin
cam_clk <= pclk;
---- Ausgabe für wreiter
px_number <= x;
line_number <= y;
pixel_data <= tmp_pixel_data;
pixel_data_ready <= tmp_pixel_data_ready;
cam_to_pixel : get_mark_points
port map(
resetn => resetn,
clk => pclk,
vsync => vsync_in,
href => href_in,
px_data => cam_pxdata,
px_count_out => x,
line_count_out => y,
data_ready => tmp_pixel_data_ready,
px_data_out => tmp_pixel_data
);
generate_sensors : for i in 1 to 5 generate
signal tmp_sensor : sensor;
begin
sensor_inst : component check_sensor
generic map(sensor_position => (i*20, 50))
port map(
resetn => resetn,
clk => clk,
pixel_cnt => x,
line_cnt => y,
pixel_data => tmp_pixel_data,
pixel_data_ready => tmp_pixel_data_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_data_ready(i - 1)
);
sensor_gate_inst : component sensor_gate
port map(
clk => clk,
resetn => resetn,
sensor_ready => tmp_sensor_data_ready(i - 1),
sensor_in => tmp_sensor,
outbus_free => outbus_free,
sensor_out => sensor_data,
sensor_data_ready => sensor_data_ready
);
end generate generate_sensors;
pclk_pr : process(clk) is
variable n : integer := 0;
begin
if rising_edge(clk) then
if resetn = '0' then
n := 0;
pclk <= '0';
else
n := n + 1;
if n > pclk_to_clk_rate then
pclk <= '1';
else
pclk <= '0';
end if;
if n = 2*pclk_to_clk_rate then
n := 0;
end if;
end if;
end if;
end process pclk_pr;
check_bus : process(clk) is -- ist notwendig für clock Verschiebung
begin
if rising_edge(clk) then
if resetn = '0' then
outbus_free <= '0';
else
outbus_free <= not or_reduct(tmp_sensor_data_ready);
end if;
end if;
end process check_bus;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : ddr3ram
generic map (
width => 16, abits => 13, fname => sdramfile,
speedbin => 3,
ldguard => 1
)
port map (
ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt,
rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn,
doload => led(2)
);
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture; |
constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00000100011100001001100100000010000000000000011100000000010100101000000100101000000011000001100000100100001000011100010000001001100010000100000010100000100101000000100100001000001000010000011111100000000000000000000011111100000000000000000000011111100000000000000000000000000000000001000100000000000011100000000000000000001001000011000000100100000000001000000000010100001000000001010000100001000000000011000100000000100100000100001100000000101000001100000000100000000001100000000100100100100001000100000000101000000000100100000100001000100000000101000000000101000101000000000100000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000111111000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000";
|
-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n2 - sim
-- Description: Test bench for sys_tst_serloop2_n2
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop2_n2 is
end tb_tst_serloop2_n2;
architecture sim of tb_tst_serloop2_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_edcl_ahb_mst
-- File: eth_edcl_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet EDCL MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_edcl_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable tretry : std_ulogic;
variable tready : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; tready := '0'; tretry := '0';
terror := '0'; tgrant := '0';
hsize := HSIZE_WORD;
hwdata := tmsti.data;
hbusreq := tmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1' then
tgrant := '1';
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
|
-- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_kernel - Behavioral
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- search : in std_logic;
done : out std_logic;
-- Input Graph Pointers (Represented in Custom CSR)
graph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
p1_rsp_q_wr_en : out std_logic;
p1_rsp_q_din : out std_logic_vector(63 downto 0);
p1_rsp_q_almost_full : in std_logic;
-- Process 2 signals
p2_scc_req_rd_enb : out std_logic;
p2_scc_req_dout : in std_logic_vector(63 downto 0);
p2_scc_req_valid : in std_logic;
p2_scc_req_empty : in std_logic;
p2_scc_req_almost_full : in std_logic;
p2_rinfo_req_rd_enb : out std_logic;
p2_rinfo_req_dout : in std_logic_vector(63 downto 0);
p2_rinfo_req_valid : in std_logic;
p2_rinfo_req_empty : in std_logic;
p2_rinfo_req_almost_full : in std_logic;
p2_scc_rsp_wr_en : out std_logic;
p2_scc_rsp_din : out std_logic_vector(0 downto 0);
p2_scc_rsp_almost_full : in std_logic;
p2_rinfo_rsp_wr_en : out std_logic;
p2_rinfo_rsp_din : out std_logic_vector(0 downto 0);
p2_rinfo_rsp_almost_full : in std_logic;
-- Process 3 signals
p3_done : in std_logic;
p3_scc_addr_rd_enb : out std_logic;
p3_scc_addr_dout : in std_logic_vector(63 downto 0);
p3_scc_addr_valid : in std_logic;
p3_scc_addr_empty : in std_logic;
p3_info_req_rd_enb : out std_logic;
p3_info_req_dout : in std_logic_vector(63 downto 0);
p3_info_req_valid : in std_logic;
p3_info_req_empty : in std_logic;
p3_id_q_rd_enb : out std_logic;
p3_id_q_dout : in std_logic_vector(63 downto 0);
p3_id_q_valid : in std_logic;
p3_id_q_empty : in std_logic;
p3_info_rsp_rd_enb : out std_logic;
p3_info_rsp_dout : in std_logic_vector(63 downto 0);
p3_info_rsp_valid : in std_logic;
p3_info_rsp_empty : in std_logic;
p3_info_rsp_wr_en : out std_logic;
p3_info_rsp_din : out std_logic_vector(63 downto 0);
p3_info_rsp_almost_full : in std_logic;
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end scc_master;
architecture Behavioral of scc_master is
type muxstatetype is (mx_start, mx_stall, mx_p1, mx_p2, mx_p3, mx_p4, mx_p5, mx_p6);
signal mux_state : muxstatetype;
signal done_count : integer range 0 to 3;
signal saved_state : std_logic_vector(7 downto 0);
signal saved_addr : std_logic_vector(63 downto 0);
signal saved_data : std_logic_vector(63 downto 0);
signal count : unsigned (63 downto 0);
signal p2_q_alt : std_logic;
signal p2_scc_rsp_wr_en_temp : std_logic;
signal p2_scc_rsp_din_temp : std_logic_vector(63 downto 0);
signal p2_rinfo_rsp_wr_en_temp : std_logic;
signal p2_rinfo_rsp_din_temp : std_logic_vector(63 downto 0);
begin
-- Requests Multiplexer
-- Read from the processes' request queues with the specific tag
Master : process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
done <= '0';
done_count <= 0;
-- reset master process control signals
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '0';
else
--- MULTIPLEX requests to memory controller
if (enable = '1') then
-- is memory controller asserting rd/wr stall?
if (mc_rd_rq_stall = '1' or mc_wr_rq_stall = '1') then
-- save addr/data
if (p1_req_q_valid = '1') then
-- Read from reach queue at this address
saved_state <= x"01";
saved_addr <= p1_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_scc_req_valid = '1') then
-- Read from SCC color value at this address
saved_state <= x"02";
saved_addr <= p2_scc_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_rinfo_req_valid = '1') then
-- Read rInfo (in CSR)
saved_state <= x"03";
saved_addr <= p2_rinfo_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_scc_addr_valid = '1') then
-- Color node
saved_state <= x"04";
saved_addr <= p3_scc_addr_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_info_req_valid = '1') then
-- Read Info (in CSR)
saved_state <= x"05";
saved_addr <= p3_info_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_id_q_valid = '1' and p3_info_rsp_valid = '1') then
-- Update Info CSR
saved_state <= x"06";
saved_addr <= p3_id_q_dout;
saved_data <= p3_info_rsp_dout;
mux_state <= mx_stall;
else
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mux_state;
end if;
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
-- If not a memory controller rd/wr stall
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0') then
if (mux_state = mx_stall) then
-- Issue a request, if comming from a stall
if (saved_state = x"01") then
-- Request from reach queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"02") then
-- Request SCC[id] Color
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"03") then
-- Request rInfo[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"04") then
-- Color node at SCC[id]
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl <= color;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"05") then
-- Read Info[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl(7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"06") then
-- Update Info[id] in (CSR)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl <= saved_data(63 downto 1) & '0';
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if;
elsif (mux_state = mx_p1 and p1_req_q_valid = '1') then
-- Request from reach queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p1_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"01";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p2 and p2_scc_req_valid = '1') then
-- Request SCC[id] Color
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p2_scc_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"02";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p3 and p2_rinfo_req_valid = '1') then
-- Request rInfo[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p2_rinfo_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"03";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p4 and p3_scc_addr_valid = '1') then
-- Color node at SCC[id]
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= p3_scc_addr_dout(47 downto 0);
mc_req_wrd_rdctl <= color;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p5 and p3_info_req_valid = '1') then
-- Read Info[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p3_info_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"05";
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p6 and p3_id_q_valid = '1' and p3_info_rsp_valid = '1') then
-- Update Info[id] in (CSR) to be unvisited
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= p3_id_q_dout(47 downto 0);
mc_req_wrd_rdctl <= p3_info_rsp_dout(63 downto 1) & '0';
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if; -- End mux states execution
-- Pop from queue if mux is ready
if ((mux_state = mx_start) or (mux_state = mx_stall)
or (mux_state = mx_p1 and p1_req_q_valid = '1')
or (mux_state = mx_p2 and p2_scc_req_valid = '1')
or (mux_state = mx_p3 and p2_rinfo_req_valid = '1')
or (mux_state = mx_p4 and p3_scc_addr_valid = '1')
or (mux_state = mx_p5 and p3_info_req_valid = '1')
or (mux_state = mx_p6 and p3_id_q_valid = '1' and p3_info_rsp_valid = '1')) then
if (p3_id_q_empty = '0' and p3_info_rsp_empty = '0') then
-- If process 3 info/addr queues are not empty, make a write request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '1';
p3_info_rsp_rd_enb <= '1';
mux_state <= mx_p6;
elsif (p3_scc_addr_empty = '0') then
-- If process 3 SCC queue isn't empty, make a write request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '1';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p4;
elsif (p3_info_req_empty = '0') then
-- If process 3 info req queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '1';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p5;
elsif (p2_rinfo_req_empty = '0' and p2_q_alt = '0') then
-- If process 2 rInfo queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '1';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '1'; -- Next time read from SCC queue
mux_state <= mx_p3;
elsif (p2_scc_req_empty = '0' and p2_q_alt = '1') then
-- If process 2 SCC queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '1';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '0'; -- Next time read from rInfo queue
mux_state <= mx_p2;
elsif (p1_req_q_empty = '0') then
-- If process 1 queue isn't empty, make a read request
p1_req_q_rd_enb <= '1';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p1;
else
-- reset
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_start;
end if;
else
-- Keep mux state
mux_state <= mux_state;
-- reset enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end if mux green light!
else
-- weird case, memory controller not ready yet
mux_state <= mux_state;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end check for rd/wr stall
-- if all processes are done and queues ar eempty go done
if (p3_done = '1' and p3_id_q_empty = '1' and p3_info_rsp_empty = '1' and p3_info_req_empty = '1' and p3_scc_addr_empty = '1'
and p2_rinfo_req_empty = '1' and p2_scc_req_empty = '1' and p1_req_q_empty = '1') then
if (done_count < 3) then
done <= '0';
done_count <= done_count + 1;
elsif (done_count = 3) then
done <= '1';
done_count <= 0;
end if;
else
done <= '0';
done_count <= 0;
end if;
else
done <= '0';
done_count <= 0;
-- reset master process control signals
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end if enable
end if; -- end if rst
end if; -- end if clk
end process; -- Master
-- MC Response decoder process
mc_rsp_decoder : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p2_scc_rsp_wr_en <= '0';
p2_scc_rsp_din <= (others => '0');
p2_rinfo_rsp_wr_en <= '0';
p2_rinfo_rsp_din <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
mc_rsp_stall <= '0';
else
if (enable = '1') then
if (mc_rsp_push = '1') then
-- Get process 1 response
if (mc_rsp_rdctl(7 downto 0) = x"01") then
-- push results to p1 response queue
p1_rsp_q_wr_en <= '1';
p1_rsp_q_din <= mc_rsp_data;
-- reset others
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 2 SCC[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"02") then
-- push results to p2 SCC response queue
p2_scc_rsp_wr_en_temp <= '1';
p2_scc_rsp_din_temp <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 2 rInfo[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"03") then
-- push results to p2 rInfo response queue
p2_rinfo_rsp_wr_en_temp <= '1';
p2_rinfo_rsp_din_temp <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 3 Info[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"05") then
-- push results to p3 Info response queue
p3_info_rsp_wr_en <= '1';
p3_info_rsp_din <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
end if;
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
end if;
-- Control mc_rsp_stall signal
if (p1_rsp_q_almost_full = '1' or p2_scc_rsp_almost_full = '1' or p2_rinfo_rsp_almost_full = '1'
or p3_info_rsp_almost_full = '1' or p2_scc_req_almost_full = '1' or p2_rinfo_req_almost_full = '1') then
mc_rsp_stall <= '1';
else
mc_rsp_stall <= '0';
end if;
-- elsif enable = '0'
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
mc_rsp_stall <= '0';
end if; -- end if enable
p2_scc_rsp_wr_en <= p2_scc_rsp_wr_en_temp;
p2_scc_rsp_din(0) <= or_reduce(p2_scc_rsp_din_temp);
p2_rinfo_rsp_wr_en <= p2_rinfo_rsp_wr_en_temp;
p2_rinfo_rsp_din(0) <= p2_rinfo_rsp_din_temp(0);
end if; -- end if rst
end if; -- end if clk
end process; -- end process rsp decoder
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p10n01i01713ent IS
port (signal max : in natural);
type word is array (natural range <>) of bit;
subtype mem_array is word (0 to 7);
END c09s02b00x00p10n01i01713ent;
ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS
signal idx : natural;
signal mem : mem_array;
BEGIN
TESTING: PROCESS(mem_array'(others => '1'))
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p10n01i01713arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p10n01i01713ent IS
port (signal max : in natural);
type word is array (natural range <>) of bit;
subtype mem_array is word (0 to 7);
END c09s02b00x00p10n01i01713ent;
ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS
signal idx : natural;
signal mem : mem_array;
BEGIN
TESTING: PROCESS(mem_array'(others => '1'))
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p10n01i01713arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p10n01i01713ent IS
port (signal max : in natural);
type word is array (natural range <>) of bit;
subtype mem_array is word (0 to 7);
END c09s02b00x00p10n01i01713ent;
ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS
signal idx : natural;
signal mem : mem_array;
BEGIN
TESTING: PROCESS(mem_array'(others => '1'))
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p10n01i01713arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
-- SPI Select (Master is AVR)
AVR_CPLD_EXT_1 : in STD_LOGIC;
-- SPI Pins from Outside World
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD : in STD_LOGIC; -- Active low
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
-- Using this as our SEL pin due to timer issues
AVR_CPLD_EXT_2 : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC := 'Z';
-- NTSC
LUMA : inout STD_LOGIC_VECTOR(3 downto 0);
SYNC : inout STD_LOGIC;
COLORBURST : inout STD_LOGIC;
-- CPLD_GPIO : out STD_LOGIC := '0';
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code for NTSC
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
LUMA : INOUT std_logic_vector(3 downto 0);
SYNC : INOUT std_logic;
COLORBURST : INOUT std_logic;
-- CPLD_GPIO : OUT std_logic;
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and NTSC output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SEL_SPI => AVR_CPLD_EXT_1,
EXT_SCK => EXT_SCK,
EXT_SEL => EXT_SEL_CPLD,
EXT_MOSI => EXT_MOSI,
EXT_MISO => EXT_MISO,
AVR_SCK => AVR_SCK,
AVR_SEL => AVR_CPLD_EXT_2,
AVR_MOSI => AVR_MOSI,
-- AVR_MISO => AVR_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
LUMA => LUMA,
COLORBURST => COLORBURST,
SYNC => SYNC,
-- CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:09:18 09/09/2011
-- Design Name:
-- Module Name: comparadordeentradas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comparador is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
HAB : in STD_LOGIC;
RESP : out STD_LOGIC;
RETRO : out bit);
end comparador;
architecture Behavioral of comparadordeentradas is
begin
RETRO <= (((A XNOR C)and(B XNOR D)and(C XNOR E)) or((A XNOR E)and(B XNOR F)and(C XNOR G)) or((C XNOR E)and(D XNOR F) and( E XNOR G)) );
RESP <= RETRO AND HAB ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:21:45 03/21/2014
-- Design Name:
-- Module Name: header_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity header_display is
Port ( char : out STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
char_we : out STD_LOGIC := '0';
clk : in STD_LOGIC;
ram_clk : out STD_LOGIC := '0';
ram_enable : out STD_LOGIC := '1';
ram_output : in STD_LOGIC_VECTOR(3 downto 0);
start : in STD_LOGIC;
reset : in STD_LOGIC);
end header_display;
architecture Behavioral of header_display is
type state_type is (IDLE, GET_DATA, START_RISING_EDGE, START_FALLING_EDGE);
signal state, next_state : state_type;
signal busy_in : STD_LOGIC := '0';
begin
process (clk)
begin
if rising_edge(clk) then
if reset='1' then
busy_in <= '0';
elsif start = '1' then
busy_in <= '1';
elsif state = IDLE then
busy_in <= '0';
else
busy_in <= busy_in;
end if;
end if;
end process;
SYNC_PROC: process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
OUTPUT_DECODE: process (state, ram_output)
begin
if state = IDLE then
char <= (others=>'0');
char_we <= '0';
ram_clk <= '0';
ram_enable <= '0';
elsif state = GET_DATA then
char <= (others=>'0');
char_we <= '0';
ram_enable <= '1';
ram_clk <= '1'; -- zobaczymy czy zadzia³a, mo¿e byæ za póno
elsif state = START_RISING_EDGE then
ram_clk <= '0';
ram_enable <= '0';
char_we <= '1';
char <= "0000" & ram_output; -- mo¿na? zrobiæ co do przerabiania na ASCII
elsif state = START_FALLING_EDGE then
ram_clk <= '0';
ram_enable <= '0';
char_we <= '0';
char <= "0000" & ram_output;
end if;
end process;
NEXT_STATE_DECODE: process (state, start, clk)
begin
next_state <= state;
case (state) is
when IDLE =>
if start = '1' then
next_state <= GET_DATA;
end if;
when GET_DATA =>
next_state <= START_RISING_EDGE;
when START_RISING_EDGE =>
next_state <= START_FALLING_EDGE;
when START_FALLING_EDGE =>
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
entity e is end entity;
architecture a of e is
signal x, y, z, q, b : bit;
begin
x <= guarded y; -- Error
with b select z <= guarded q when others; -- Error
b1: block (b = '1') is
begin
x <= guarded y; -- OK
with b select z <= guarded q when others; -- OK
assert guard; -- OK
end block;
b2: block is
signal guard : boolean := true; -- OK
signal q : bit;
disconnect q : bit after 0 ns; -- OK (sem failure)
begin
x <= guarded y; -- OK
with b select z <= guarded q when others; -- OK
end block;
end architecture;
|
--*****************************************************************************
-- @Copyright 2008 by guyoubao, All rights reserved.
-- Module name : vhdl_code_demo
-- Call by :
-- Description : this module is the top module of demo.
-- IC : EP1C4F400C8
-- Version : A
-- Note: : this is a demo
-- Author : guyoubao
-- Date : 2003.09.07
-- Update :
-- 2003.10.15 : xxx(who?)
-- add xxxx
-- modify xxxxx
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LED_HANDLE is
port
(
I_26M_clk : in std_logic;
I_reset_n : in std_logic;
I_led_dis : in std_logic_vector(3 downto 0);
I_adc_dis : in std_logic;
I_fifo_full : in std_logic;
O_fpga_led0 : out std_logic;
O_fpga_led1 : out std_logic;
O_fpga_led2 : out std_logic; --CPUд��ָʾ
O_fpga_led3 : out std_logic --FPGA����ָʾ
);
end LED_HANDLE;
architecture ARC_LED_HANDLE of LED_HANDLE is
signal S_case_cnt : std_logic_vector(23 downto 0);--
signal S_case : std_logic_vector(2 downto 0);
signal S_init : std_logic;
signal S_time_tick : std_logic;
signal S_time_tick_buf : std_logic;
signal S_fpga_led0 : std_logic;
signal S_fpga_led1 : std_logic;
signal S_fpga_led2 : std_logic; --CPUд��ָʾ
signal S_fpga_led3 : std_logic; --FPGA����ָʾ
begin
O_fpga_led0 <= S_fpga_led0;
O_fpga_led1 <= S_fpga_led1;
O_fpga_led2 <= S_fpga_led2;
O_fpga_led3 <= S_fpga_led3;
-------------------------------
--The state transfer one time in 1 second
-------------------------------
process(I_26M_clk, I_reset_n)
begin
if I_reset_n = '0' then
S_case <= (others=>'0');
S_case_cnt <= (others=>'0');
S_init <= '0';
S_time_tick <= '0';
elsif rising_edge(I_26M_clk) then
--if S_case_cnt >= x"10111110" then --200MHz
--if S_case_cnt >= x"019B4E81" then --20MHz
S_case_cnt <= S_case_cnt + 1;
if (S_case_cnt = 0)then --20MHz
S_time_tick <= not S_time_tick; --ʱ�ӽ��ģ�1Sһ��
if S_case >= "100" then
S_init <= '1';
S_case <= (others=>'0');
else
S_case <= S_case + 1; -- Increment state on one second
end if;
end if;
else
null;
end if;
end process;
process(I_26M_clk, I_reset_n)
begin
if I_reset_n = '0' then
S_fpga_led2 <= '1';
S_fpga_led3 <= '1';
elsif rising_edge(I_26M_clk) then
if (I_adc_dis = '1') then
if (S_time_tick = '1') then
S_fpga_led2 <= '0';
else
S_fpga_led2 <= '1';
end if;
else
S_fpga_led2 <= '1';
end if;
if (I_fifo_full = '1') then --FIFO is full
if (S_time_tick = '1') then
S_fpga_led3 <= '0';
else
S_fpga_led3 <= '1';
end if;
else
S_fpga_led3 <= '1';
end if;
else
null;
end if;
end process;
-------------------------------
--Output the led signal one second
-------------------------------
process(I_reset_n,I_26M_clk)
begin
if I_reset_n = '0' then
S_fpga_led0 <= '1';
S_fpga_led1 <= '1';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '1';
else
if rising_edge(I_26M_clk) then
-- if (S_init = '0') then
case S_case is
when "001" =>
S_fpga_led0 <= '0';
S_fpga_led1 <= '1';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '1';
when "010" =>
S_fpga_led0 <= '1';
S_fpga_led1 <= '0';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '1';
when "011" =>
S_fpga_led0 <= '1';
S_fpga_led1 <= '1';
-- S_fpga_led2 <= '0';
-- S_fpga_led3 <= '1';
when "100" =>
S_fpga_led0 <= '0';
S_fpga_led1 <= '0';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '0';
-- when "101" =>
-- S_fpga_led0 <= '1';
-- S_fpga_led1 <= '1';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '1';
-- when "110" =>
-- S_fpga_led0 <= '0';
-- S_fpga_led1 <= '0';
-- S_fpga_led2 <= '0';
-- S_fpga_led3 <= '0';
when others =>
S_fpga_led0 <= '1';
S_fpga_led1 <= '1';
-- S_fpga_led2 <= '1';
-- S_fpga_led3 <= '1';
end case;
-- else
-- S_time_tick_buf <= S_time_tick;
-- if(S_time_tick_buf = not S_time_tick)then
-- S_fpga_led3 <= not S_fpga_led3; --FPGA��������ָʾ��
-- end if;
else
null;
end if;
end if;
end process;
end ARC_LED_HANDLE; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity latch is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end latch;
architecture Behavioral of latch is
begin
process(en, clk, reset)
begin
if(reset = '0') then
q <= "00000000";
elsif(rising_edge(clk) AND (en = '1')) then
q <= d;
end if;
end process;
end Behavioral;
|
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro2_1 is
port (
clk : std_logic;
rst : std_logic;
tx : out std_logic_vector(7 downto 0));
end repro2_1;
architecture behav of repro2_1 is
subtype byte_t is std_logic_vector(7 downto 0);
-- Define terminal newline characters (CR+LF)
constant NEWLINE_CR : byte_t := x"0d";
constant NEWLINE_LF : byte_t := x"0a";
-- Create ROM array with all concatenated messages.
type array_t is array(0 to 15) of byte_t;
impure function get_msg_array return array_t is
variable result : array_t := (others => (others => '0'));
variable ridx : integer := 0;
procedure append(constant msg : string) is
begin
-- Append the message to the output array.
for c in 0 to msg'length-1 loop
result(ridx) := x"00";
ridx := ridx + 1;
end loop;
-- Then append the CR+LF characters.
result(ridx+0) := NEWLINE_CR;
result(ridx+1) := NEWLINE_LF;
ridx := ridx + 2;
end procedure;
begin
-- For each fixed message...
append("xx");
return result;
end function;
constant MESSAGE_ROM : array_t := get_msg_array;
begin
process (clk)
variable p : natural;
begin
if rising_edge(clk) then
if rst = '1' then
p := 0;
else
tx <= message_rom (p);
if p = message_rom'right then
p := message_rom'left;
else
p := p + 1;
end if;
end if;
end if;
end process;
end behav;
|
entity pipeline is
generic (width : natural; depth : natural);
port (i : bit_vector (1 to width);
o : out bit_vector (1 to width);
clk : bit);
end pipeline;
architecture behav of pipeline is
type pipe is array (1 to depth) of bit_vector (1 to width);
begin
process (clk) is
variable tmp : pipe;
begin
if clk = '1' then
o <= tmp (1);
tmp (1 to depth - 1) := tmp (2 to depth);
tmp (depth) := i;
end if;
end process;
end behav;
entity tb is
end tb;
architecture behav of tb is
constant width : natural := 4;
signal i : bit_vector (1 to width);
signal o : bit_vector (1 to width);
signal clk : bit;
begin
p : entity work.pipeline
generic map (width => width, depth => 3)
port map (i => i, o => o, clk => clk);
process is
begin
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1010";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1001";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1000";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
wait;
end process;
end behav;
|
entity pipeline is
generic (width : natural; depth : natural);
port (i : bit_vector (1 to width);
o : out bit_vector (1 to width);
clk : bit);
end pipeline;
architecture behav of pipeline is
type pipe is array (1 to depth) of bit_vector (1 to width);
begin
process (clk) is
variable tmp : pipe;
begin
if clk = '1' then
o <= tmp (1);
tmp (1 to depth - 1) := tmp (2 to depth);
tmp (depth) := i;
end if;
end process;
end behav;
entity tb is
end tb;
architecture behav of tb is
constant width : natural := 4;
signal i : bit_vector (1 to width);
signal o : bit_vector (1 to width);
signal clk : bit;
begin
p : entity work.pipeline
generic map (width => width, depth => 3)
port map (i => i, o => o, clk => clk);
process is
begin
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1010";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1001";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1000";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
wait;
end process;
end behav;
|
entity pipeline is
generic (width : natural; depth : natural);
port (i : bit_vector (1 to width);
o : out bit_vector (1 to width);
clk : bit);
end pipeline;
architecture behav of pipeline is
type pipe is array (1 to depth) of bit_vector (1 to width);
begin
process (clk) is
variable tmp : pipe;
begin
if clk = '1' then
o <= tmp (1);
tmp (1 to depth - 1) := tmp (2 to depth);
tmp (depth) := i;
end if;
end process;
end behav;
entity tb is
end tb;
architecture behav of tb is
constant width : natural := 4;
signal i : bit_vector (1 to width);
signal o : bit_vector (1 to width);
signal clk : bit;
begin
p : entity work.pipeline
generic map (width => width, depth => 3)
port map (i => i, o => o, clk => clk);
process is
begin
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1010";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1001";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1000";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
wait;
end process;
end behav;
|
-----------------------------------
-- PROCESSOR --
-- Test bench for now --
-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE WORK.controller_constants.ALL;
ENTITY processor IS
PORT
(
-- Main processor clock
system_clock : IN STD_LOGIC;
-- Debug outputs
--ir : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--mar : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--mdr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--pc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--signal_alu : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ra : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--rb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--status : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
switches : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
hex : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END processor;
ARCHITECTURE behavioral OF processor IS
-- Control signals from the controller
SIGNAL s_controller_mask : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_controller_en : STD_LOGIC_VECTOR(40 DOWNTO 0);
SIGNAL s_controller_fun : STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL s_controller_sel : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- Program counter input/output signals
SIGNAL s_pc_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_pc_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Program counter incrementer unity data output
SIGNAL s_pc_incrementer_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory addres register data output
SIGNAL s_mar_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Ram data output
SIGNAL s_ram_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Instruction register data output
SIGNAL s_ir_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_ram_enable : STD_LOGIC;
SIGNAL s_io_enable : STD_LOGIC;
-- Main bus data
SIGNAL s_bus_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Main bus address
SIGNAL s_bus_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- IO data output
SIGNAL s_io_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Hex display output
SIGNAL s_hex_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory destination register data input
SIGNAL s_mdr_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory destination register data output
SIGNAL s_mdr_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Value masked by the controler data mask
SIGNAL s_mask_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Main data multiplexer
SIGNAL s_main_mux_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank output for register a
SIGNAL s_register_bank_output_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank output for register b
SIGNAL s_register_bank_output_b : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu register a output
SIGNAL s_register_a_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu register b output
SIGNAL s_register_b_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bit shifter data output
SIGNAL s_shifter_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bit shifter status flag output
SIGNAL s_shifter_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
-- Alu register data output
SIGNAL s_alu_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu status flag output
SIGNAL s_alu_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
-- Status multiplexer data output (selects status from alu or bit shifter)
SIGNAL s_mux_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Status register output
SIGNAL s_status_register_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank register signals
SIGNAL s_reg_00 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_01 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_02 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_03 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_04 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_05 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_06 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_07 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_08 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_09 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_10 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_11 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_12 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_13 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_14 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_15 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_16 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_17 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_18 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_19 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_20 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_21 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_22 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_24 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_25 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_26 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_27 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_28 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_29 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_30 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_31 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
-- Debug output hooks
--ir(31 DOWNTO 0) <= s_ir_output(31 DOWNTO 0);
--mar(31 DOWNTO 0) <= s_mar_output(31 DOWNTO 0);
--mdr(31 DOWNTO 0) <= s_mdr_output(31 DOWNTO 0);
--pc(31 DOWNTO 0) <= s_ram_output(31 DOWNTO 0);
--r0(31 DOWNTO 0) <= s_reg_31(31 DOWNTO 0);
--r1(31 DOWNTO 0) <= s_reg_01(31 DOWNTO 0);
--r2(31 DOWNTO 0) <= s_reg_02(31 DOWNTO 0);
--r3(31 DOWNTO 0) <= s_reg_03(31 DOWNTO 0);
--r4(31 DOWNTO 0) <= s_reg_04(31 DOWNTO 0);
--signal_alu(31 DOWNTO 0) <= s_alu_output(31 DOWNTO 0);
--ra(31 DOWNTO 0) <= s_register_a_output(31 DOWNTO 0);
--rb(31 DOWNTO 0) <= s_register_b_output(31 DOWNTO 0);
--status(31 DOWNTO 0) <= s_status_register_output;
hex(31 DOWNTO 0) <= s_hex_output;
-- Main data multiplexer driven by control selection signal
main_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 3
)
PORT MAP
(
in_i(0) => s_shifter_output,
in_i(1) => s_alu_output,
in_i(2) => s_mdr_output,
in_i(3) => s_pc_output,
in_i(4) => s_mask_output,
in_sel(2 DOWNTO 0) => s_controller_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main),
out_o => s_main_mux_output
);
-- Controller unity receives ir, status and negated clock for double speed
controller: ENTITY WORK.controller(behavioral)
PORT MAP
(
in_ir => s_ir_output,
in_st => s_status_register_output,
in_clk => NOT(system_clock),
out_mask => s_controller_mask,
out_en => s_controller_en,
out_fun => s_controller_fun,
out_sel => s_controller_sel
);
-- Program counter register
program_counter: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_pc_input,
s_controller_en(c_clock_program_counter),
system_clock,
s_pc_output
);
-- Program counter incrementer
pc_incrementer: ENTITY WORK.adder(behavioral)
PORT MAP
(
s_pc_output,
STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
'1',
s_pc_incrementer_output,
OPEN
);
-- Program counter data selection multiplexer
pc_incrementer_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 1
)
PORT MAP
(
in_i(0) => s_main_mux_output,
in_i(1) => s_pc_incrementer_output,
in_sel => s_controller_sel(c_select_mux_pc_incrementer DOWNTO c_select_mux_pc_incrementer),
out_o => s_pc_input
);
-- Memory address register
memory_address_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(c_clock_mar),
system_clock,
s_mar_output
);
-- Memory destination register
memory_destination_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_ram_output,
s_controller_en(c_clock_mdr),
system_clock,
s_mdr_output
);
-- Instruction register
instruction_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_ram_output,
s_controller_en(c_clock_instruction_register),
system_clock,
s_ir_output
);
-- Memory mapped IO controller
mem_io: ENTITY WORK.ram_io(behavioral)
PORT MAP
(
s_main_mux_output, -- mem_io data
s_mar_output, -- mem_io addr
buttons, -- board buttons
switches, -- board switches
s_controller_fun(c_function_ram_we), -- mem_io combined write enable
s_controller_en(c_clock_ram),
system_clock,
-------------------------------------------
s_ram_output, -- fans out to registers
s_hex_output
);
-- -- IO/Memory bus controller
-- io_memory_bus: ENTITY WORK.bus_controller(behavioral)
-- PORT MAP
-- (
-- s_mar_output,
-- s_main_mux_output,
-- s_io_output,
-- s_ram_output,
-- s_controller_en(c_clock_ram),
-- s_bus_addr,
-- s_bus_data,
-- s_mdr_input,
-- s_ram_enable,
-- s_io_enable
-- );
-- -- IO controller
-- io_data_controller: ENTITY WORK.io_controller(behavioral)
-- PORT MAP
-- (
-- s_bus_data,
-- s_bus_addr,
-- s_controller_fun(c_function_ram_we),
-- s_io_enable,
-- system_clock,
-- buttons,
-- switches,
-- s_io_output,
-- s_hex_output
-- );
-- -- Ram block
-- ram: ENTITY WORK.ram(behavioral)
-- GENERIC MAP
-- (
-- g_addr_width => 10
-- )
-- PORT MAP
-- (
-- s_bus_data,
-- s_bus_addr(9 DOWNTO 0),
-- s_controller_fun(c_function_ram_we),
-- s_ram_enable,
-- system_clock,
-- s_ram_output
-- );
-- Alu register a
register_a: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_register_bank_output_a,
s_controller_en(c_clock_register_a),
system_clock,
s_register_a_output
);
-- Alu register b
register_b: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_register_bank_output_b,
s_controller_en(c_clock_register_b),
system_clock,
s_register_b_output
);
-- Bit shifter
shifter: ENTITY WORK.shifter(behavioral)
PORT MAP
(
s_register_a_output,
s_controller_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter),
s_shifter_output,
s_shifter_status_output(3 DOWNTO 0)
);
-- Alu
alu: ENTITY WORK.alu(behavioral)
PORT MAP
(
s_register_a_output,
s_register_b_output,
s_controller_fun(c_function_alu_cin),
s_controller_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu),
s_alu_output,
s_alu_status_output(3 DOWNTO 0)
);
-- Status selector multiplexer driven by control selection signal
status_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 1
)
PORT MAP
(
in_i(0) => s_alu_status_output,
in_i(1) => s_shifter_status_output,
in_sel => s_controller_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter),
out_o => s_mux_status_output
);
-- Status register
status_register: ENTITY WORK.parallel_register
PORT MAP
(
s_mux_status_output,
s_controller_en(c_clock_status_register),
system_clock,
s_status_register_output
);
-- Register bank registers
r00: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(0),
system_clock,
s_reg_00
);
r01: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(1),
system_clock,
s_reg_01
);
r02: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(2),
system_clock,
s_reg_02
);
r03: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(3),
system_clock,
s_reg_03
);
r04: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(4),
system_clock,
s_reg_04
);
r05: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(5),
system_clock,
s_reg_05
);
r06: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(6),
system_clock,
s_reg_06
);
r07: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(7),
system_clock,
s_reg_07
);
r08: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(8),
system_clock,
s_reg_08
);
r09: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(9),
system_clock,
s_reg_09
);
r10: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(10),
system_clock,
s_reg_10
);
r11: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(11),
system_clock,
s_reg_11
);
r12: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(12),
system_clock,
s_reg_12
);
r13: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(13),
system_clock,
s_reg_13
);
r14: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(14),
system_clock,
s_reg_14
);
r15: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(15),
system_clock,
s_reg_15
);
r16: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(16),
system_clock,
s_reg_16
);
r17: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(17),
system_clock,
s_reg_17
);
r18: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(18),
system_clock,
s_reg_18
);
r19: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(19),
system_clock,
s_reg_19
);
r20: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(20),
system_clock,
s_reg_20
);
r21: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(21),
system_clock,
s_reg_21
);
r22: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(22),
system_clock,
s_reg_22
);
r23: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(23),
system_clock,
s_reg_23
);
r24: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(24),
system_clock,
s_reg_24
);
r25: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(25),
system_clock,
s_reg_25
);
r26: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(26),
system_clock,
s_reg_26
);
r27: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(27),
system_clock,
s_reg_27
);
r28: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(28),
system_clock,
s_reg_28
);
r29: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(29),
system_clock,
s_reg_29
);
r30: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(30),
system_clock,
s_reg_30
);
r31: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(31),
system_clock,
s_reg_31
);
-- Register bank data output a multiplexer driven by selection signal
m1: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 5
)
PORT MAP
(
in_i(0) => s_reg_00,
in_i(1) => s_reg_01,
in_i(2) => s_reg_02,
in_i(3) => s_reg_03,
in_i(4) => s_reg_04,
in_i(5) => s_reg_05,
in_i(6) => s_reg_06,
in_i(7) => s_reg_07,
in_i(8) => s_reg_08,
in_i(9) => s_reg_09,
in_i(10) => s_reg_10,
in_i(11) => s_reg_11,
in_i(12) => s_reg_12,
in_i(13) => s_reg_13,
in_i(14) => s_reg_14,
in_i(15) => s_reg_15,
in_i(16) => s_reg_16,
in_i(17) => s_reg_17,
in_i(18) => s_reg_18,
in_i(19) => s_reg_19,
in_i(20) => s_reg_20,
in_i(21) => s_reg_21,
in_i(22) => s_reg_22,
in_i(23) => s_reg_23,
in_i(24) => s_reg_24,
in_i(25) => s_reg_25,
in_i(26) => s_reg_26,
in_i(27) => s_reg_27,
in_i(28) => s_reg_28,
in_i(29) => s_reg_29,
in_i(30) => s_reg_30,
in_i(31) => s_reg_31,
in_sel => s_controller_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a),
out_o => s_register_bank_output_a
);
-- Register bank data output b multiplexer driven by selection signal
m2: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 5
)
PORT MAP
(
in_i(0) => s_reg_00,
in_i(1) => s_reg_01,
in_i(2) => s_reg_02,
in_i(3) => s_reg_03,
in_i(4) => s_reg_04,
in_i(5) => s_reg_05,
in_i(6) => s_reg_06,
in_i(7) => s_reg_07,
in_i(8) => s_reg_08,
in_i(9) => s_reg_09,
in_i(10) => s_reg_10,
in_i(11) => s_reg_11,
in_i(12) => s_reg_12,
in_i(13) => s_reg_13,
in_i(14) => s_reg_14,
in_i(15) => s_reg_15,
in_i(16) => s_reg_16,
in_i(17) => s_reg_17,
in_i(18) => s_reg_18,
in_i(19) => s_reg_19,
in_i(20) => s_reg_20,
in_i(21) => s_reg_21,
in_i(22) => s_reg_22,
in_i(23) => s_reg_23,
in_i(24) => s_reg_24,
in_i(25) => s_reg_25,
in_i(26) => s_reg_26,
in_i(27) => s_reg_27,
in_i(28) => s_reg_28,
in_i(29) => s_reg_29,
in_i(30) => s_reg_30,
in_i(31) => s_reg_31,
in_sel => s_controller_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b),
out_o => s_register_bank_output_b
);
-- Data masking
s_mask_output <= s_controller_mask AND s_mdr_output;
END behavioral; |
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