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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p10n01i00778ent_a IS
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
END c01s01b01x02p10n01i00778ent_a;
ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
BEGIN
test : process
begin
wait;
end process test;
END c01s01b01x02p10n01i00778arch_a;
ENTITY c01s01b01x02p10n01i00778ent IS
port (p1 : in integer;
p2 : out integer;
p3 : inout integer;
p4 : buffer integer;
p5 : linkage integer);
END c01s01b01x02p10n01i00778ent;
ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
component c01s01b01x02p10n01i00778ent_b
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
end component;
for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
BEGIN
L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p10n01i00778"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p10n01i00778arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p10n01i00778ent_a IS
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
END c01s01b01x02p10n01i00778ent_a;
ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
BEGIN
test : process
begin
wait;
end process test;
END c01s01b01x02p10n01i00778arch_a;
ENTITY c01s01b01x02p10n01i00778ent IS
port (p1 : in integer;
p2 : out integer;
p3 : inout integer;
p4 : buffer integer;
p5 : linkage integer);
END c01s01b01x02p10n01i00778ent;
ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
component c01s01b01x02p10n01i00778ent_b
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
end component;
for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
BEGIN
L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p10n01i00778"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p10n01i00778arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p10n01i00778ent_a IS
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
END c01s01b01x02p10n01i00778ent_a;
ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
BEGIN
test : process
begin
wait;
end process test;
END c01s01b01x02p10n01i00778arch_a;
ENTITY c01s01b01x02p10n01i00778ent IS
port (p1 : in integer;
p2 : out integer;
p3 : inout integer;
p4 : buffer integer;
p5 : linkage integer);
END c01s01b01x02p10n01i00778ent;
ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
component c01s01b01x02p10n01i00778ent_b
port ( c1 : linkage integer;
c2 : linkage integer;
c3 : linkage integer;
c4 : linkage integer;
c5 : linkage integer);
end component;
for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
BEGIN
L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p10n01i00778"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p10n01i00778arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP1_DOT.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** (for first level of vector multiplier) ***
--*** ***
--*** 27/09/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** ***
--*** Optimizations: ***
--*** 1: Signed Output ***
--*** 2: Unsigned Output, Normalized ***
--*** 3: Unsigned Output, Scaled ***
--*** ***
--*** Optimization = 1,2 ***
--*** Stratix II/III/IV: Latency 4 ***
--*** Stratix V: Latency 3 ***
--*** Optimization = 3 ***
--*** Stratix II/III/IV: Latency 3 ***
--*** Stratix V: Latency 2 ***
--*** ***
--***************************************************
ENTITY hcc_mulfp1_dot IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 2; -- 0,1 = "Stratix II/III/IV", 2 = "Stratix V"
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_mulfp1_dot;
ARCHITECTURE rtl OF hcc_mulfp1_dot IS
type exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal biasvalue : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentff : exponentfftype;
signal aasignff, bbsignff : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aamantissa, bbmantissa : STD_LOGIC_VECTOR (27 DOWNTO 1);
signal multiply : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalize : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal premantissa : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal twos_complement_carry : STD_LOGIC;
signal normalize_bit_older, normalize_bit_newer : STD_LOGIC;
signal scale_bit : STD_LOGIC;
signal aaexponentzero, bbexponentzero : STD_LOGIC;
signal aaexponentmax, bbexponentmax : STD_LOGIC;
signal aamantissabitff, bbmantissabitff : STD_LOGIC;
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal aazero, aainfinity, aanan : STD_LOGIC;
signal bbzero, bbinfinity, bbnan : STD_LOGIC;
signal aaexp, bbexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- SII/III/IV behavioral component
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SII/III/IV synthesizable component
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
-- SV behavioral component = SV synthesizable component
component hcc_mul2727s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
gen_bias_norm: IF (optimization = 1 OR optimization = 2) GENERATE
biasvalue <= conv_std_logic_vector (127,10);
END GENERATE;
gen_bias_scale: IF (optimization = 3) GENERATE
biasvalue <= conv_std_logic_vector (126,10); -- bias is subtract 127, add 1 for scale right shift
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exponentff(k)(j) <= '0';
END LOOP;
END LOOP;
aasignff <= '0';
bbsignff <= '0';
signff <= "000";
FOR k IN 1 TO mantissa LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaexponentff <= aa(31 DOWNTO 24);
bbexponentff <= bb(31 DOWNTO 24);
exponentff(1)(10 DOWNTO 1) <= ("00" & aaexponentff) + ("00" & bbexponentff) - biasvalue;
exponentff(2)(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1) + normalize_bit_newer;
exponentff(3)(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1) + normalize_bit_older;
aasignff <= aa(32);
bbsignff <= bb(32);
signff(1) <= aasignff XOR bbsignff;
signff(2) <= signff(1);
signff(3) <= signff(2);
mantissaff <= premantissa + twos_complement_carry;
END IF;
END IF;
END PROCESS;
gen_twos_one: IF (device < 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(2);
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_two: IF (device = 2 AND optimization = 1) GENERATE
twos_complement_carry <= signff(1);
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_thr: IF (device < 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_newer <= '0';
normalize_bit_older <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_for: IF (device = 2 AND optimization = 2) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= multiply(52);
scale_bit <= '0';
END GENERATE;
gen_twos_other: IF (optimization = 3) GENERATE
twos_complement_carry <= '0';
normalize_bit_older <= '0';
normalize_bit_newer <= '0';
scale_bit <= '1';
END GENERATE;
--**************************
--*** Multiplier Section ***
--**************************
-- multiplier input in this form
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
aamantissa <= "01" & aa(23 DOWNTO 1) & "00";
bbmantissa <= "01" & bb(23 DOWNTO 1) & "00";
gen_mul_one: IF (device < 2 AND synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
gen_mul_two: IF (device < 2 AND synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aamantissa,mulbb=>bbmantissa,
mulcc=>multiply);
END GENERATE;
gen_mul_thr: IF (device = 2) GENERATE
bmult5: hcc_mul2727s
GENERIC MAP (width=>27)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aamantissa,bb=>bbmantissa,
cc=>multiply);
END GENERATE;
-- output will either be "0001XXXX" or "001XXXX", normalize multiplier
normalize(mantissa DOWNTO mantissa-2) <= "000";
gnma: FOR k IN 1 TO mantissa-3 GENERATE
normalize(k) <= (multiply(57-mantissa+k) AND multiply(52)) OR
(multiply(56-mantissa+k) AND NOT(multiply(52)));
END GENERATE;
gpma: FOR k IN 1 TO mantissa GENERATE
premantissa(k) <= normalize(k) XOR twos_complement_carry;
END GENERATE;
--*** EXCEPTIONS ***
-- condition = 1 when true
aaexponentzero <= NOT(aaexponentff(8) OR aaexponentff(7) OR aaexponentff(6) OR aaexponentff(5) OR
aaexponentff(4) OR aaexponentff(3) OR aaexponentff(2) OR aaexponentff(1));
bbexponentzero <= NOT(bbexponentff(8) OR bbexponentff(7) OR bbexponentff(6) OR bbexponentff(5) OR
bbexponentff(4) OR bbexponentff(3) OR bbexponentff(2) OR bbexponentff(1));
aaexponentmax <= aaexponentff(8) AND aaexponentff(7) AND aaexponentff(6) AND aaexponentff(5) AND
aaexponentff(4) AND aaexponentff(3) AND aaexponentff(2) AND aaexponentff(1);
bbexponentmax <= bbexponentff(8) AND bbexponentff(7) AND bbexponentff(6) AND bbexponentff(5) AND
bbexponentff(4) AND bbexponentff(3) AND bbexponentff(2) AND bbexponentff(1);
-- exceptions
-- a x 0 = 0 : if (expaa = 0 OR expbb = 0) AND multiply = 0
-- a x inf = inf : if (expaa = inf OR expbb = inf) AND multiply = 0
-- 0 x inf = nan : if (expaa = inf AND expbb = 0) OR (expaa = 0 AND expbb = inf) AND multiply = 0
-- a x nan = nan : if (expaa = inf OR expbb = inf) AND multiply = !0
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aamantissabitff <= '0';
bbmantissabitff <= '0';
cczipff <= "000";
ccsatff <= "000";
ccnanff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamantissabitff <= aa(23);
bbmantissabitff <= bb(23);
-- a x 0 = 0
cczipff(1) <= (aazero AND NOT(bbexponentmax)) OR (bbexponentzero AND NOT(aaexponentmax));
cczipff(2) <= cczipff(1);
cczipff(3) <= cczipff(2);
-- a x inf = inf
ccsatff(1) <= (NOT(aazero) AND NOT(aaexponentmax) AND bbinfinity) OR
(NOT(bbzero) AND NOT(bbexponentmax) AND aainfinity);
ccsatff(2) <= ccsatff(1);
ccsatff(3) <= ccsatff(2);
-- 0 x inf = nan
-- a x nan = nan
ccnanff(1) <= (aazero AND bbinfinity) OR (bbzero AND aainfinity) OR aanan OR bbnan;
ccnanff(2) <= ccnanff(1);
ccnanff(3) <= ccnanff(2);
END IF;
END IF;
END PROCESS;
aazero <= aaexponentzero;
aainfinity <= aaexponentmax AND NOT(aamantissabitff);
aanan <= aaexponentmax AND aamantissabitff;
bbzero <= bbexponentzero;
bbinfinity <= bbexponentmax AND NOT(bbmantissabitff);
bbnan <= bbexponentmax AND bbmantissabitff;
--***************
--*** OUTPUTS ***
--***************
-- if device = 0,1 (SII,III,IV) and optimization = 1 (signed output)
-- latency = 4
gen_out_older_one: IF (device < 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 2 (unsigned output, normalized)
-- latency = 4
gen_out_older_two: IF (device < 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(3); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(3)(10 DOWNTO 1);
ccsat <= ccsatff(3);
cczip <= cczipff(3);
ccnan <= ccnanff(3);
END GENERATE;
-- if device = 0,1 (SII,III,IV) and optimization = 3 (unsigned output, scaled)
-- latency = 3
gen_out_older_thr: IF (device < 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_one: IF (device = 2 AND optimization = 1) GENERATE
cc(mantissa+10 DOWNTO 11) <= mantissaff;
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_two: IF (device = 2 AND optimization = 2) GENERATE
cc(mantissa+10) <= signff(2); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= mantissaff(mantissa-1 DOWNTO 1);
cc(10 DOWNTO 1) <= exponentff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
ccnan <= ccnanff(2);
END GENERATE;
gen_out_newer_thr: IF (device = 2 AND optimization = 3) GENERATE
cc(mantissa+10) <= signff(1); -- sign bit packed into MSB
cc(mantissa+9 DOWNTO 11) <= "00" & multiply(54 DOWNTO 58-mantissa); -- right shifted
cc(10 DOWNTO 1) <= exponentff(1)(10 DOWNTO 1);
ccsat <= ccsatff(1);
cczip <= cczipff(1);
ccnan <= ccnanff(1);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(31 DOWNTO 24);
bbexp <= bb(31 DOWNTO 24);
gen_debug_older: IF (device < 2) GENERATE
ccexp <= exponentff(3)(10 DOWNTO 1);
END GENERATE;
gen_debug_newer: IF (device = 2) GENERATE
ccexp <= exponentff(2)(10 DOWNTO 1);
END GENERATE;
aaman <= aa(23 DOWNTO 1);
bbman <= bb(23 DOWNTO 1);
ccman <= mantissaff;
END rtl;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Convert the push button to a 1PPS that can be used to restart
-- camera initialisation
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce is
port (
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end debounce;
architecture behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if i = '1' then
if c = x"ffffff" then
o <= '1';
else
o <= '0';
end if;
c <= c+1;
else
c <= (others => '0');
o <= '0';
end if;
end if;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split6;
architecture augh of output_split6 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split6;
architecture augh of output_split6 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
------------------------------------------------------------------------------
-- simple_timebase.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: simple_timebase.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Feb 17 10:01:45 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library simple_timebase_v1_00_a;
use simple_timebase_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity simple_timebase is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity simple_timebase;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of simple_timebase is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity issue2 is
port(
a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(2 downto 0)
);
end issue2;
architecture behavior of issue2 is
begin
b <= a;
end behavior;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_data_queue_pkg is
-- Declaration of storage
subtype t_data_buffer is std_logic_vector(C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1 downto 0);
shared variable shared_data_buffer : t_data_buffer;
type t_buffer_natural_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of natural;
type t_buffer_boolean_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of boolean;
type t_data_queue is protected
------------------------------------------
-- init_queue
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the queue.
--
-- - Parameters:
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
-- - Returns: The index of the initiated queue (natural).
-- Returns 0 on error.
--
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural;
------------------------------------------
-- init_queue
------------------------------------------
-- This procedure allocates space in the buffer at the given queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be initialized.
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
);
------------------------------------------
-- flush
------------------------------------------
-- This procedure empties the queue given
-- by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be flushed.
--
procedure flush(
queue_idx : natural
);
------------------------------------------
-- push_back
------------------------------------------
-- This procedure pushes data to the end of a queue.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the queue size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure push_back(
queue_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- peek_front
------------------------------------------
-- This function returns the data from the front
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- peek_back
------------------------------------------
-- This function returns the data from the back
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_back
------------------------------------------
-- This function returns the data from the back
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_front
------------------------------------------
-- This function returns the data from the front
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The number of elements occupying the queue (natural).
--
--
impure function get_count(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_count_max
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the queue (natural).
--
--
impure function get_queue_count_max(
queue_idx : natural
) return natural;
------------------------------------------
-- deallocate_buffer
------------------------------------------
-- This procedure resets the entire std_logic_vector and all
-- variable arrays related to the buffer, effectively removing all queues.
--
-- - Parameters:
-- - dummy - VOID
--
procedure deallocate_buffer(
dummy : t_void
);
end protected;
end package ti_data_queue_pkg;
package body ti_data_queue_pkg is
type t_data_queue is protected body
-- Internal variables for the data queue
-- The buffer is one large std_logic_vector of size C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER.
-- There are several queues that can be instantiated in the slv.
-- There is one set of variables per queue.
variable v_queue_initialized : t_buffer_boolean_array := (others => false);
variable v_queue_size_in_bits : t_buffer_natural_array := (others => 0);
variable v_count : t_buffer_natural_array := (others => 0);
-- min_idx/max idx: These variables set the upper and lower limit of each queue in the buffer.
-- This is how the large slv buffer is divided into several smaller queues.
-- After a queue has been instantiated, all queue operations in the buffer
-- for a given idx will happen within the v_min_idx and v_max_idx boundary.
-- These variables will be set when a queue is instantiated, and will not
-- change afterwards.
variable v_min_idx : t_buffer_natural_array := (others => 0);
variable v_max_idx : t_buffer_natural_array := (others => 0);
variable v_next_available_idx : natural := 0; -- Where the v_min_idx of the next queue initialized shall be set.
-- first_idx/last_idx: These variables set the current indices within a queue, i.e., within
-- the min_idx/max_idx boundary. These variables will change every time
-- a given queue has data pushed or popped.
variable v_first_idx : t_buffer_natural_array := (others => 0);
variable v_last_idx : t_buffer_natural_array := (others => 0);
type t_string_pointer is access string;
variable v_scope : t_string_pointer := NULL;
------------------------------------------
-- init_queue
------------------------------------------
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural is
variable vr_queue_idx : natural;
variable vr_queue_idx_found : boolean := false;
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not check_value(v_next_available_idx < C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER, TB_ERROR,
"init_queue called, but no more space in buffer!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Find first available queue
-- and tag as initialized
for i in t_buffer_boolean_array'range loop
if not v_queue_initialized(i) then
-- Save queue idx
vr_queue_idx := i;
vr_queue_idx_found := true;
-- Tag this queue as initialized
v_queue_initialized(vr_queue_idx) := true;
exit; -- exit loop
end if;
end loop;
-- Verify that an available queue idx was found, else trigger alert and return 0
if not check_value(vr_queue_idx_found, TB_ERROR,
"init_queue called, but all queues have already been initialized!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(vr_queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(vr_queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(vr_queue_idx) := v_next_available_idx;
v_max_idx(vr_queue_idx) := v_min_idx(vr_queue_idx) + v_queue_size_in_bits(vr_queue_idx) - 1;
v_first_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_last_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_next_available_idx := v_max_idx(vr_queue_idx) + 1;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(vr_queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(vr_queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(vr_queue_idx);
-- Return the index of the buffer
return vr_queue_idx;
end function;
------------------------------------------
-- init_queue
------------------------------------------
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
) is
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not v_queue_initialized(queue_idx) then
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(queue_idx) := v_next_available_idx;
v_max_idx(queue_idx) := v_min_idx(queue_idx) + v_queue_size_in_bits(queue_idx) - 1;
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_next_available_idx := v_max_idx(queue_idx) + 1;
-- Tag this buffer as initialized
v_queue_initialized(queue_idx) := true;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(queue_idx);
else
alert(TB_ERROR, "init_queue called, but the desired buffer index is already in use! No action taken.", v_scope.all);
return;
end if;
end procedure;
------------------------------------------
-- push_back
------------------------------------------
procedure push_back(
queue_idx : natural;
data : std_logic_vector
) is
alias a_data : std_logic_vector(data'length - 1 downto 0) is data;
begin
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"push_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
for i in a_data'right to a_data'left loop -- From right to left since LSB shall be first in the queue.
shared_data_buffer(v_last_idx(queue_idx)) := a_data(i);
if v_last_idx(queue_idx) /= v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_last_idx(queue_idx) + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) + 1;
end loop;
log(ID_UVVM_DATA_QUEUE, "Data " & to_string(data, HEX) & " pushed to back of queue " & to_string(queue_idx) & " (index " & to_string(v_last_idx(queue_idx)) & "). Fill level is " & to_string(v_count(queue_idx)) & "/" & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
end if;
end procedure;
------------------------------------------
-- flush
------------------------------------------
procedure flush(
queue_idx : natural
) is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "flush called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
shared_data_buffer(v_max_idx(queue_idx) downto v_min_idx(queue_idx)) := (others => '0');
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_count(queue_idx) := 0;
end procedure;
------------------------------------------
-- peek_front
------------------------------------------
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_front() called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_front() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
v_current_idx := v_first_idx(queue_idx);
-- Generate return value
for i in 0 to v_return_entry'length - 1 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- peek_back
------------------------------------------
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_back called, but queue not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_back() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_last_idx(queue_idx) > 0 then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Generate return value
for i in v_return_entry'length - 1 downto 0 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- pop_back
------------------------------------------
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "pop_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_queue_initialized(queue_idx) then
v_return_entry := peek_back(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
if v_last_idx(queue_idx) > v_min_idx(queue_idx) then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
-- Set last idx
if v_current_idx < v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_current_idx + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
end if;
end if;
return v_return_entry;
end function;
------------------------------------------
-- pop_front
------------------------------------------
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural := v_first_idx(queue_idx);
begin
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"pop_front called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
v_return_entry := peek_front(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
-- v_first_idx points to the idx PREVIOUS to the first element in the buffer.
-- Therefore must correct if at max_idx.
v_current_idx := v_first_idx(queue_idx);
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
v_first_idx(queue_idx) := v_current_idx;
end if;
return v_return_entry;
end if;
v_return_entry := (others => '0');
return v_return_entry;
end function;
------------------------------------------
-- get_count
------------------------------------------
impure function get_count(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_count called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_count(queue_idx);
end function;
------------------------------------------
-- get_queue_count_max
------------------------------------------
impure function get_queue_count_max(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_count_max called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_queue_size_in_bits(queue_idx);
end function;
------------------------------------------
-- deallocate_buffer
------------------------------------------
procedure deallocate_buffer(
dummy : t_void
) is
begin
shared_data_buffer := (others => '0');
v_queue_initialized := (others => false);
v_queue_size_in_bits := (others => 0);
v_count := (others => 0);
v_min_idx := (others => 0);
v_max_idx := (others => 0);
v_first_idx := (others => 0);
v_last_idx := (others => 0);
v_next_available_idx := 0;
log(ID_UVVM_DATA_QUEUE, "Buffer has been deallocated, i.e., all queues removed.", v_scope.all);
end procedure;
end protected body;
end package body ti_data_queue_pkg;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_rnd;
architecture behaviour of ex1_rnd is
constant s1: std_logic_vector(4 downto 0) := "11101";
constant s2: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "11011";
constant s3: std_logic_vector(4 downto 0) := "11110";
constant s5: std_logic_vector(4 downto 0) := "11111";
constant s6: std_logic_vector(4 downto 0) := "10001";
constant s7: std_logic_vector(4 downto 0) := "10110";
constant s8: std_logic_vector(4 downto 0) := "01011";
constant s9: std_logic_vector(4 downto 0) := "01111";
constant s10: std_logic_vector(4 downto 0) := "00001";
constant s11: std_logic_vector(4 downto 0) := "10000";
constant s12: std_logic_vector(4 downto 0) := "11010";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s14: std_logic_vector(4 downto 0) := "01000";
constant s15: std_logic_vector(4 downto 0) := "00100";
constant s16: std_logic_vector(4 downto 0) := "01001";
constant s17: std_logic_vector(4 downto 0) := "00110";
constant s18: std_logic_vector(4 downto 0) := "11100";
constant s19: std_logic_vector(4 downto 0) := "00011";
constant s20: std_logic_vector(4 downto 0) := "10111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_10a is
end entity inline_10a;
architecture test of inline_10a is
constant R : real := 10_000.0;
constant R1 : real := 10_000.0;
constant R2 : real := 10_000.0;
-- code from book
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
-- end code from book
begin
block_1 : block is
-- code from book
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
-- end code from book
begin
-- code from book
bus_v == bus_i * R;
-- end code from book
end block block_1;
block_2 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
bus_v.databus(1) == bus_i.databus(1) * R;
-- ...
-- not in book
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
-- end not in book
bus_v.databus(7) == bus_i.databus(7) * R;
-- end code from book
end block block_2;
block_3 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R;
-- end code from book
end block block_3;
block_4 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v / R == i;
-- end code from book
end block block_4;
block_5 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
-- end code from book
bus_v.databus(1) == bus_i.databus(1) * R;
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
bus_v.databus(7) == bus_i.databus(7) * R;
end block block_5;
block_6 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2; -- illegal
-- end code from book
end block block_6;
block_7 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance "current_tolerance";
-- end code from book
end block block_7;
block_8 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance i2'tolerance;
-- end code from book
end block block_8;
block_9 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R tolerance i'tolerance;
-- end code from book
end block block_9;
end architecture test;
|
component ghrd_10as066n2_ocm_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(7 downto 0); -- readdata
writedata : in std_logic_vector(7 downto 0) := (others => 'X') -- writedata
);
end component ghrd_10as066n2_ocm_0;
u0 : component ghrd_10as066n2_ocm_0
port map (
clk => CONNECTED_TO_clk, -- clk1.clk
reset => CONNECTED_TO_reset, -- reset1.reset
reset_req => CONNECTED_TO_reset_req, -- .reset_req
address => CONNECTED_TO_address, -- s1.address
clken => CONNECTED_TO_clken, -- .clken
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write => CONNECTED_TO_write, -- .write
readdata => CONNECTED_TO_readdata, -- .readdata
writedata => CONNECTED_TO_writedata -- .writedata
);
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY memory_dp_48x4096 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END memory_dp_48x4096;
ARCHITECTURE memory_dp_48x4096_arch OF memory_dp_48x4096 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF memory_dp_48x4096_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF memory_dp_48x4096_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF memory_dp_48x4096_arch : ARCHITECTURE IS "memory_dp_48x4096,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF memory_dp_48x4096_arch: ARCHITECTURE IS "memory_dp_48x4096,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=0,C_PRIM_TYPE=3,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=memory_dp_48x4096.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=6,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=48,C_READ_WIDTH_A=48,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=6,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=48,C_READ_WIDTH_B=48,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=6,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 27.3621 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 8,
C_ALGORITHM => 0,
C_PRIM_TYPE => 3,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "memory_dp_48x4096.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 6,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 48,
C_READ_WIDTH_A => 48,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 6,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 48,
C_READ_WIDTH_B => 48,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "6",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 27.3621 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 48)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 48)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END memory_dp_48x4096_arch;
|
-- $Id: tbcore_rlink_dcm.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink_dcm - sim
-- Description: DCM aware core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core_dcm->tbcore_rlink_dcm; rbv3 names
-- 2010-11-13 338 1.1 First DCM aware version, cloned from rritb_core
-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.rlink_cext_vhpi.all;
entity tbcore_rlink_dcm is -- dcm aware core of rlink_cext based tb
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink_dcm;
architecture sim of tbcore_rlink_dcm is
signal CLK_STOP : slbit := '0';
begin
CLKGEN : simclk
generic map (
PERIOD => CLKOSC_PERIOD,
OFFSET => CLKOSC_OFFSET)
port map (
CLK => CLKOSC,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt
port map (
CLK => CLKSYS,
CLK_CYCLE => SB_CLKCYCLE
);
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 0 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 0 ns;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable t_lastclksys : time := 0 ns;
variable clksys_period : time := 0 ns;
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
-- just wait for 10 CLKSYS cycles
for i in 1 to 10 loop
wait until rising_edge(CLKSYS);
clksys_period := now - t_lastclksys;
t_lastclksys := now;
end loop; -- i
stim_loop: loop
wait until rising_edge(CLKSYS);
clksys_period := now - t_lastclksys;
t_lastclksys := now;
wait for clksys_period-SETUP_TIME;
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
icycle := to_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
if RX_HOLD = '0' then
irxint := rlink_cext_getbyte(icycle);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= '1';
wait for 0 ns;
SB_VAL <= 'Z';
wait for 0 ns;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if;
end if;
SB_CNTL <= r_sb_cntl;
end loop;
-- just wait for 50 CLKSYS cycles
for i in 1 to 50 loop
wait until rising_edge(CLKSYS);
end loop; -- i
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable itxdata : integer := 0;
variable itxrc : integer := 0;
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for C2OUT_TIME;
if TX_ENA = '1' then
itxdata := to_integer(unsigned(TX_DATA));
itxrc := rlink_cext_putbyte(itxdata);
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end loop;
end process proc_moni;
end sim;
|
entity repro is
end entity;
architecture A of repro is
signal S1 : bit := '0';
signal S2_transport : bit;
signal S2_delayed : bit;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
process (S1) is
begin
assert false report "S1 = " & bit'image(S1) severity note;
end process;
process (S2_delayed) is
begin
assert false report "S1'delayed = " & bit'image(S2_delayed) severity note;
end process;
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 2,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 1,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_tx_udp.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_tx_udp IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END fifo_tx_udp;
ARCHITECTURE SYN OF fifo_tx_udp IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_one_hot is
constant assert_name : string := "OVL_ONE_HOT";
constant path : string := rtl'path_name;
constant all_ones : std_logic_vector(width - 1 downto 0) := (others => '1');
constant all_zeros : std_logic_vector(width - 1 downto 0) := (others => '0');
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY);
constant cover_corner : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_CORNER);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
signal prev_test_expr : std_logic_vector(width - 1 downto 0);
signal one_hots_checked : std_logic_vector(width - 1 downto 0);
signal prev_one_hots_checked : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
function check_one_hot (v : std_logic_vector) return boolean is
variable v_1 : std_logic_vector((v'length - 1) downto 0);
begin
case ovl_is_x(v) is
when false => v_1 := std_logic_vector(unsigned(v) - 1);
when others => v_1 := (others => '0');
end case;
if ((v and v_1) = all_zeros) then
return true;
else
return false;
end if;
end function check_one_hot;
begin
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif (not ovl_is_x(test_expr_x01)) then
if ((test_expr_x01 = all_zeros) or (not check_one_hot(test_expr_x01))) then
fire(0) <= '1';
ovl_error_proc("Test expression contains more or less than 1 asserted bits", severity_level,
property_type, assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif (ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_sanity or cover_corner)) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
prev_one_hots_checked <= one_hots_checked;
prev_test_expr <= test_expr_x01;
if (reset_n = '0') then
fire(2) <= '0';
one_hots_checked <= (others => '0');
else
fire(2) <= '0';
if ((not ovl_is_x(test_expr_x01)) and check_one_hot(test_expr_x01)) then
one_hots_checked <= one_hots_checked or test_expr_x01;
end if;
if (cover_sanity and (test_expr_x01 /= prev_test_expr) and not ovl_is_x(test_expr_x01) and
not ovl_is_x(prev_test_expr)) then
ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
if (cover_corner and (one_hots_checked /= prev_one_hots_checked) and (one_hots_checked = all_ones) and
not ovl_is_x(one_hots_checked)) then
ovl_cover_proc("all_one_hots_checked covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not(cover_sanity) and not(cover_corner))) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sevenseg is
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
segs_out : out std_logic_vector(6 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end sevenseg;
architecture behavioural of sevenseg is
-- Refresh rate 50M/2^18 ~ 190Hz
-- Refresh rate 8M/2^16 ~ 122Hz
constant COUNTER_WIDTH : natural := 18;
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anode_select : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
begin
count_next <= count + 1;
anode_select <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Update counter, drive anodes_out and select bits to display for each 7-seg
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
case anode_select is
when "00" =>
anodes_out <= "0111";
nibble <= data_in(15 downto 12);
when "01" =>
anodes_out <= "1011";
nibble <= data_in(11 downto 8);
when "10" =>
anodes_out <= "1101";
nibble <= data_in(7 downto 4);
when others =>
anodes_out <= "1110";
nibble <= data_in(3 downto 0);
end case;
end if;
end process;
-- Decode selected nibble
with nibble select
segs_out <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add32 is
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
sum : out std_logic_vector(31 downto 0)
);
end add32;
architecture arch of add32 is
signal temp_c : std_logic_vector(32 downto 0);
begin
add: for i in 0 to 31 generate --generate 32 1-bit adders for add32 entity
add32: entity work.add1
port map(
in1 => in1(i),
in0 => in0(i),
cin => temp_c(i), -- Cin will be previous value temp signal
cout => temp_c(i+1), -- cout will feed into cin
sum => sum(i)
);
end generate;
temp_c(0) <= '0'; -- Set cin to first adder to 0. Leaving it blank will result in an 'X' for sum(0)
end arch;
|
-- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
package Utility_Package is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant c_word_length : integer := 32;
constant c_vhpi_max_string_length : integer := 1024;
-----------------------------------------------------------------------------
-- types
-----------------------------------------------------------------------------
subtype VhpiString is string(1 to c_vhpi_max_string_length);
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer; -- returns minimum
function Pack_String_To_Vhpi_String(x: string) return VhpiString; -- converts x to null terminated string
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString; -- converts slv x to null terminated string
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector; -- convert null term string to slv
function To_Std_Logic(x: VhpiString) return std_logic; -- string to sl
function To_String(x: std_logic) return VhpiString; -- string to sl
function Convert_To_String(val : natural) return STRING; -- convert val to string.
function Convert_SLV_To_String(val : std_logic_vector) return STRING; -- convert val to string.
function To_Hex_Char (constant val: std_logic_vector) return character;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING; -- convert val to string.
end package Utility_Package;
package body Utility_Package is
-----------------------------------------------------------------------------
-- utility functions
-----------------------------------------------------------------------------
function Minimum(x,y: integer) return integer is
begin
if( x < y) then return x; else return y; end if;
end Minimum;
function Ceiling(x,y: integer) return integer is
variable ret_var : integer;
begin
assert x /= 0 report "divide by zero in ceiling function" severity failure;
ret_var := x/y;
if(ret_var*y < x) then ret_var := ret_var + 1; end if;
return(ret_var);
end Ceiling;
function Pack_String_To_Vhpi_String(x: string) return VhpiString is
alias lx: string(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
ret_var(I) := lx(I);
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_String_To_Vhpi_String;
function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString is
alias lx : std_logic_vector(1 to x'length) is x;
variable strlen: integer;
variable ret_var : VhpiString;
begin
strlen := Minimum(c_vhpi_max_string_length-1,x'length);
for I in 1 to strlen loop
if(lx(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
ret_var(strlen+1) := nul;
return(ret_var);
end Pack_SLV_To_Vhpi_String;
function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector is
variable ret_var : std_logic_vector(1 to lgth);
variable strlen: integer;
begin
strlen := Minimum(c_vhpi_max_string_length-1,lgth);
for I in 1 to strlen loop
if(x(I) = '1') then
ret_var(I) := '1';
else
ret_var(I) := '0';
end if;
end loop;
return(ret_var);
end Unpack_String;
function To_Std_Logic(x: VhpiString) return std_logic is
variable s: std_logic_vector(0 downto 0);
begin
s := Unpack_String(x,1);
return(s(0));
end To_Std_Logic;
function To_String(x: std_logic) return VhpiString is
variable s: std_logic_vector(0 downto 0);
begin
s(0) := x;
return(Pack_SLV_To_Vhpi_String(s));
end To_String;
-- Thanks to: D. Calvet [email protected]
function Convert_To_String(val : NATURAL) return STRING is
variable result : STRING(10 downto 1) := (others => '0'); -- smallest natural, longest string
variable pos : NATURAL := 1;
variable tmp, digit : NATURAL;
begin
tmp := val;
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
return result((pos-1) downto 1);
end Convert_To_String;
function Convert_SLV_To_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(1 to val'length) is val;
variable ret_var: string( 1 to lval'length);
begin
for I in lval'range loop
if(lval(I) = '1') then
ret_var(I) := '1';
elsif (lval(I) = '0') then
ret_var(I) := '0';
else
ret_var(I) := 'X';
end if;
end loop;
return(ret_var);
end Convert_SLV_To_String;
function To_Hex_Char (constant val: std_logic_vector) return character is
alias lval: std_logic_vector(1 to val'length) is val;
variable tvar : std_logic_vector(1 to 4);
variable ret_val : character;
begin
if(lval'length >= 4) then
tvar := lval(1 to 4);
else
tvar := (others => '0');
tvar(1 to lval'length) := lval;
end if;
case tvar is
when "0000" => ret_val := '0';
when "0001" => ret_val := '1';
when "0010" => ret_val := '2';
when "0011" => ret_val := '3';
when "0100" => ret_val := '4';
when "0101" => ret_val := '5';
when "0110" => ret_val := '6';
when "0111" => ret_val := '7';
when "1000" => ret_val := '8';
when "1001" => ret_val := '9';
when "1010" => ret_val := 'a';
when "1011" => ret_val := 'b';
when "1100" => ret_val := 'c';
when "1101" => ret_val := 'd';
when "1110" => ret_val := 'e';
when "1111" => ret_val := 'f';
when others => ret_val := 'f';
end case;
return(ret_val);
end To_Hex_Char;
function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING is
alias lval: std_logic_vector(val'length downto 1) is val;
variable ret_var: string( 1 to Ceiling(lval'length,4));
variable hstr : std_logic_vector(4 downto 1);
variable I : integer;
begin
I := 0;
while I < (lval'length/4) loop
hstr := lval(4*(I+1) downto (4*I)+1);
ret_var(ret_var'length - I) := To_Hex_Char(hstr);
I := (I + 1);
end loop; -- I
hstr := (others => '0');
if(ret_var'length > (lval'length/4)) then
hstr((lval'length-((lval'length/4)*4)) downto 1) := lval(lval'length downto (4*(lval'length/4))+1);
ret_var(1) := To_Hex_Char(hstr);
end if;
return(ret_var);
end Convert_SLV_To_Hex_String;
end Utility_Package;
|
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0;
use dist_mem_gen_v8_0.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0
-- component declaration for dist_mem_gen_v8_0
component dist_mem_gen_v8_0
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0.dist_mem_gen_v8_0";
--xcc include
end comp_defs;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity filesystem_encrypt_buffer_V_m_axi;
architecture behave of filesystem_encrypt_buffer_V_m_axi is
component filesystem_encrypt_buffer_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_write;
component filesystem_encrypt_buffer_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_read;
component filesystem_encrypt_buffer_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component filesystem_encrypt_buffer_V_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : filesystem_encrypt_buffer_V_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : filesystem_encrypt_buffer_V_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : filesystem_encrypt_buffer_V_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : filesystem_encrypt_buffer_V_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity filesystem_encrypt_buffer_V_m_axi_reg_slice;
architecture behave of filesystem_encrypt_buffer_V_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity filesystem_encrypt_buffer_V_m_axi_fifo;
architecture behave of filesystem_encrypt_buffer_V_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of filesystem_encrypt_buffer_V_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity filesystem_encrypt_buffer_V_m_axi_decoder;
architecture behav of filesystem_encrypt_buffer_V_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity filesystem_encrypt_buffer_V_m_axi_throttl;
architecture behav of filesystem_encrypt_buffer_V_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity filesystem_encrypt_buffer_V_m_axi_read;
architecture behave of filesystem_encrypt_buffer_V_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component filesystem_encrypt_buffer_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_fifo;
component filesystem_encrypt_buffer_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component filesystem_encrypt_buffer_V_m_axi_reg_slice;
component filesystem_encrypt_buffer_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : filesystem_encrypt_buffer_V_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : filesystem_encrypt_buffer_V_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : filesystem_encrypt_buffer_V_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity filesystem_encrypt_buffer_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity filesystem_encrypt_buffer_V_m_axi_write;
architecture behave of filesystem_encrypt_buffer_V_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component filesystem_encrypt_buffer_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_fifo;
component filesystem_encrypt_buffer_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component filesystem_encrypt_buffer_V_m_axi_reg_slice;
component filesystem_encrypt_buffer_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : filesystem_encrypt_buffer_V_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : filesystem_encrypt_buffer_V_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component filesystem_encrypt_buffer_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component filesystem_encrypt_buffer_V_m_axi_decoder;
begin
-- Instantiation
fifo_burst : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : filesystem_encrypt_buffer_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : filesystem_encrypt_buffer_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : filesystem_encrypt_buffer_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file FIFO.vhd when simulating
-- the core, FIFO. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIFO IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END FIFO;
ARCHITECTURE FIFO_a OF FIFO IS
-- synthesis translate_off
component wrapped_FIFO
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_FIFO use entity XilinxCoreLib.fifo_generator_v5_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIFO
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on
END FIFO_a;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_downstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_downstream_adapter;
architecture europa of pipeline_bridge_0_downstream_adapter is
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
s1_endofpacket <= m1_endofpacket;
s1_readdata <= m1_readdata;
s1_readdatavalid <= m1_readdatavalid;
s1_waitrequest <= m1_waitrequest;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_address <= std_logic_vector'("000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_address <= s1_address;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_arbiterlock <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_arbiterlock <= s1_arbiterlock;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_arbiterlock2 <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_arbiterlock2 <= s1_arbiterlock2;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_burstcount <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_burstcount <= s1_burstcount;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_byteenable <= std_logic_vector'("00000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_byteenable <= s1_byteenable;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_chipselect <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_chipselect <= s1_chipselect;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_debugaccess <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_debugaccess <= s1_debugaccess;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_nativeaddress <= std_logic_vector'("000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_nativeaddress <= s1_nativeaddress;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_read <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_read <= s1_read;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_write <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_write <= s1_write;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_writedata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_writedata <= s1_writedata;
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_upstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_clk : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_flush : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_reset_n : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_upstream_adapter;
architecture europa of pipeline_bridge_0_upstream_adapter is
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
process (s1_clk, s1_reset_n)
begin
if s1_reset_n = '0' then
s1_readdatavalid <= std_logic'('0');
elsif s1_clk'event and s1_clk = '1' then
if std_logic'(s1_flush) = '1' then
s1_readdatavalid <= std_logic'('0');
else
s1_readdatavalid <= m1_readdatavalid;
end if;
end if;
end process;
s1_waitrequest <= m1_waitrequest;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
s1_endofpacket <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(m1_readdatavalid) = '1' then
s1_endofpacket <= m1_endofpacket;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
s1_readdata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(m1_readdatavalid) = '1' then
s1_readdata <= m1_readdata;
end if;
end if;
end process;
m1_address <= s1_address;
m1_arbiterlock <= s1_arbiterlock;
m1_arbiterlock2 <= s1_arbiterlock2;
m1_burstcount <= s1_burstcount;
m1_byteenable <= s1_byteenable;
m1_chipselect <= s1_chipselect;
m1_debugaccess <= s1_debugaccess;
m1_nativeaddress <= s1_nativeaddress;
m1_read <= s1_read;
m1_write <= s1_write;
m1_writedata <= s1_writedata;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_waitrequest_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_waitrequest_adapter;
architecture europa of pipeline_bridge_0_waitrequest_adapter is
signal d1_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal d1_s1_arbiterlock : STD_LOGIC;
signal d1_s1_arbiterlock2 : STD_LOGIC;
signal d1_s1_burstcount : STD_LOGIC;
signal d1_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal d1_s1_chipselect : STD_LOGIC;
signal d1_s1_debugaccess : STD_LOGIC;
signal d1_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal d1_s1_read : STD_LOGIC;
signal d1_s1_write : STD_LOGIC;
signal d1_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_s1_waitrequest : STD_LOGIC;
signal set_use_registered : STD_LOGIC;
signal use_registered : STD_LOGIC;
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
internal_s1_waitrequest <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
internal_s1_waitrequest <= m1_waitrequest;
end if;
end process;
s1_endofpacket <= m1_endofpacket;
s1_readdata <= m1_readdata;
s1_readdatavalid <= m1_readdatavalid;
--set use registered, which is an e_assign
set_use_registered <= m1_waitrequest AND NOT internal_s1_waitrequest;
--use registered, which is an e_register
process (m1_clk, reset_n)
begin
if reset_n = '0' then
use_registered <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'((NOT m1_waitrequest AND internal_s1_waitrequest)) = '1' then
use_registered <= std_logic'('0');
elsif std_logic'(set_use_registered) = '1' then
use_registered <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_address <= std_logic_vector'("000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_address <= s1_address;
end if;
end if;
end process;
m1_address <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_address, s1_address);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_arbiterlock <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_arbiterlock <= s1_arbiterlock;
end if;
end if;
end process;
m1_arbiterlock <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_arbiterlock, s1_arbiterlock);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_arbiterlock2 <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_arbiterlock2 <= s1_arbiterlock2;
end if;
end if;
end process;
m1_arbiterlock2 <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_arbiterlock2, s1_arbiterlock2);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_burstcount <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_burstcount <= s1_burstcount;
end if;
end if;
end process;
m1_burstcount <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_burstcount, s1_burstcount);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_byteenable <= std_logic_vector'("00000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_byteenable <= s1_byteenable;
end if;
end if;
end process;
m1_byteenable <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_byteenable, s1_byteenable);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_chipselect <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_chipselect <= s1_chipselect;
end if;
end if;
end process;
m1_chipselect <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_chipselect, s1_chipselect);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_debugaccess <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_debugaccess <= s1_debugaccess;
end if;
end if;
end process;
m1_debugaccess <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_debugaccess, s1_debugaccess);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_nativeaddress <= std_logic_vector'("000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_nativeaddress <= s1_nativeaddress;
end if;
end if;
end process;
m1_nativeaddress <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_nativeaddress, s1_nativeaddress);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_read <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_read <= s1_read;
end if;
end if;
end process;
m1_read <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_read, s1_read);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_write <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_write <= s1_write;
end if;
end if;
end process;
m1_write <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_write, s1_write);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_writedata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_writedata <= s1_writedata;
end if;
end if;
end process;
m1_writedata <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_writedata, s1_writedata);
--vhdl renameroo for output signals
s1_waitrequest <= internal_s1_waitrequest;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0;
architecture europa of pipeline_bridge_0 is
component pipeline_bridge_0_downstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_downstream_adapter;
component pipeline_bridge_0_upstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_clk : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_flush : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_reset_n : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_upstream_adapter;
component pipeline_bridge_0_waitrequest_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_waitrequest_adapter;
signal downstream_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_m1_arbiterlock : STD_LOGIC;
signal downstream_m1_arbiterlock2 : STD_LOGIC;
signal downstream_m1_burstcount : STD_LOGIC;
signal downstream_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_m1_chipselect : STD_LOGIC;
signal downstream_m1_debugaccess : STD_LOGIC;
signal downstream_m1_endofpacket : STD_LOGIC;
signal downstream_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal downstream_m1_read : STD_LOGIC;
signal downstream_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_m1_readdatavalid : STD_LOGIC;
signal downstream_m1_waitrequest : STD_LOGIC;
signal downstream_m1_write : STD_LOGIC;
signal downstream_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_s1_arbiterlock : STD_LOGIC;
signal downstream_s1_arbiterlock2 : STD_LOGIC;
signal downstream_s1_burstcount : STD_LOGIC;
signal downstream_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_s1_chipselect : STD_LOGIC;
signal downstream_s1_debugaccess : STD_LOGIC;
signal downstream_s1_endofpacket : STD_LOGIC;
signal downstream_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal downstream_s1_read : STD_LOGIC;
signal downstream_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_s1_readdatavalid : STD_LOGIC;
signal downstream_s1_waitrequest : STD_LOGIC;
signal downstream_s1_write : STD_LOGIC;
signal downstream_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_arbiterlock : STD_LOGIC;
signal m1_arbiterlock2 : STD_LOGIC;
signal m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal module_input : STD_LOGIC;
signal upstream_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_m1_arbiterlock : STD_LOGIC;
signal upstream_m1_arbiterlock2 : STD_LOGIC;
signal upstream_m1_burstcount : STD_LOGIC;
signal upstream_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_m1_chipselect : STD_LOGIC;
signal upstream_m1_debugaccess : STD_LOGIC;
signal upstream_m1_endofpacket : STD_LOGIC;
signal upstream_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal upstream_m1_read : STD_LOGIC;
signal upstream_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_m1_readdatavalid : STD_LOGIC;
signal upstream_m1_waitrequest : STD_LOGIC;
signal upstream_m1_write : STD_LOGIC;
signal upstream_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_s1_arbiterlock : STD_LOGIC;
signal upstream_s1_arbiterlock2 : STD_LOGIC;
signal upstream_s1_burstcount : STD_LOGIC;
signal upstream_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_s1_chipselect : STD_LOGIC;
signal upstream_s1_debugaccess : STD_LOGIC;
signal upstream_s1_endofpacket : STD_LOGIC;
signal upstream_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal upstream_s1_read : STD_LOGIC;
signal upstream_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_s1_readdatavalid : STD_LOGIC;
signal upstream_s1_waitrequest : STD_LOGIC;
signal upstream_s1_write : STD_LOGIC;
signal upstream_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal waitrequest_m1_arbiterlock : STD_LOGIC;
signal waitrequest_m1_arbiterlock2 : STD_LOGIC;
signal waitrequest_m1_burstcount : STD_LOGIC;
signal waitrequest_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal waitrequest_m1_chipselect : STD_LOGIC;
signal waitrequest_m1_debugaccess : STD_LOGIC;
signal waitrequest_m1_endofpacket : STD_LOGIC;
signal waitrequest_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal waitrequest_m1_read : STD_LOGIC;
signal waitrequest_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_m1_readdatavalid : STD_LOGIC;
signal waitrequest_m1_waitrequest : STD_LOGIC;
signal waitrequest_m1_write : STD_LOGIC;
signal waitrequest_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal waitrequest_s1_arbiterlock : STD_LOGIC;
signal waitrequest_s1_arbiterlock2 : STD_LOGIC;
signal waitrequest_s1_burstcount : STD_LOGIC;
signal waitrequest_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal waitrequest_s1_chipselect : STD_LOGIC;
signal waitrequest_s1_debugaccess : STD_LOGIC;
signal waitrequest_s1_endofpacket : STD_LOGIC;
signal waitrequest_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal waitrequest_s1_read : STD_LOGIC;
signal waitrequest_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_s1_readdatavalid : STD_LOGIC;
signal waitrequest_s1_waitrequest : STD_LOGIC;
signal waitrequest_s1_write : STD_LOGIC;
signal waitrequest_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
begin
--the_pipeline_bridge_0_downstream_adapter, which is an e_instance
the_pipeline_bridge_0_downstream_adapter : pipeline_bridge_0_downstream_adapter
port map(
m1_address => downstream_m1_address,
m1_arbiterlock => downstream_m1_arbiterlock,
m1_arbiterlock2 => downstream_m1_arbiterlock2,
m1_burstcount => downstream_m1_burstcount,
m1_byteenable => downstream_m1_byteenable,
m1_chipselect => downstream_m1_chipselect,
m1_debugaccess => downstream_m1_debugaccess,
m1_nativeaddress => downstream_m1_nativeaddress,
m1_read => downstream_m1_read,
m1_write => downstream_m1_write,
m1_writedata => downstream_m1_writedata,
s1_endofpacket => downstream_s1_endofpacket,
s1_readdata => downstream_s1_readdata,
s1_readdatavalid => downstream_s1_readdatavalid,
s1_waitrequest => downstream_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => downstream_m1_endofpacket,
m1_readdata => downstream_m1_readdata,
m1_readdatavalid => downstream_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => downstream_m1_waitrequest,
s1_address => downstream_s1_address,
s1_arbiterlock => downstream_s1_arbiterlock,
s1_arbiterlock2 => downstream_s1_arbiterlock2,
s1_burstcount => downstream_s1_burstcount,
s1_byteenable => downstream_s1_byteenable,
s1_chipselect => downstream_s1_chipselect,
s1_debugaccess => downstream_s1_debugaccess,
s1_nativeaddress => downstream_s1_nativeaddress,
s1_read => downstream_s1_read,
s1_write => downstream_s1_write,
s1_writedata => downstream_s1_writedata
);
--the_pipeline_bridge_0_upstream_adapter, which is an e_instance
the_pipeline_bridge_0_upstream_adapter : pipeline_bridge_0_upstream_adapter
port map(
m1_address => upstream_m1_address,
m1_arbiterlock => upstream_m1_arbiterlock,
m1_arbiterlock2 => upstream_m1_arbiterlock2,
m1_burstcount => upstream_m1_burstcount,
m1_byteenable => upstream_m1_byteenable,
m1_chipselect => upstream_m1_chipselect,
m1_debugaccess => upstream_m1_debugaccess,
m1_nativeaddress => upstream_m1_nativeaddress,
m1_read => upstream_m1_read,
m1_write => upstream_m1_write,
m1_writedata => upstream_m1_writedata,
s1_endofpacket => upstream_s1_endofpacket,
s1_readdata => upstream_s1_readdata,
s1_readdatavalid => upstream_s1_readdatavalid,
s1_waitrequest => upstream_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => upstream_m1_endofpacket,
m1_readdata => upstream_m1_readdata,
m1_readdatavalid => upstream_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => upstream_m1_waitrequest,
s1_address => upstream_s1_address,
s1_arbiterlock => upstream_s1_arbiterlock,
s1_arbiterlock2 => upstream_s1_arbiterlock2,
s1_burstcount => upstream_s1_burstcount,
s1_byteenable => upstream_s1_byteenable,
s1_chipselect => upstream_s1_chipselect,
s1_clk => clk,
s1_debugaccess => upstream_s1_debugaccess,
s1_flush => module_input,
s1_nativeaddress => upstream_s1_nativeaddress,
s1_read => upstream_s1_read,
s1_reset_n => reset_n,
s1_write => upstream_s1_write,
s1_writedata => upstream_s1_writedata
);
module_input <= std_logic'('0');
--the_pipeline_bridge_0_waitrequest_adapter, which is an e_instance
the_pipeline_bridge_0_waitrequest_adapter : pipeline_bridge_0_waitrequest_adapter
port map(
m1_address => waitrequest_m1_address,
m1_arbiterlock => waitrequest_m1_arbiterlock,
m1_arbiterlock2 => waitrequest_m1_arbiterlock2,
m1_burstcount => waitrequest_m1_burstcount,
m1_byteenable => waitrequest_m1_byteenable,
m1_chipselect => waitrequest_m1_chipselect,
m1_debugaccess => waitrequest_m1_debugaccess,
m1_nativeaddress => waitrequest_m1_nativeaddress,
m1_read => waitrequest_m1_read,
m1_write => waitrequest_m1_write,
m1_writedata => waitrequest_m1_writedata,
s1_endofpacket => waitrequest_s1_endofpacket,
s1_readdata => waitrequest_s1_readdata,
s1_readdatavalid => waitrequest_s1_readdatavalid,
s1_waitrequest => waitrequest_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => waitrequest_m1_endofpacket,
m1_readdata => waitrequest_m1_readdata,
m1_readdatavalid => waitrequest_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => waitrequest_m1_waitrequest,
reset_n => reset_n,
s1_address => waitrequest_s1_address,
s1_arbiterlock => waitrequest_s1_arbiterlock,
s1_arbiterlock2 => waitrequest_s1_arbiterlock2,
s1_burstcount => waitrequest_s1_burstcount,
s1_byteenable => waitrequest_s1_byteenable,
s1_chipselect => waitrequest_s1_chipselect,
s1_debugaccess => waitrequest_s1_debugaccess,
s1_nativeaddress => waitrequest_s1_nativeaddress,
s1_read => waitrequest_s1_read,
s1_write => waitrequest_s1_write,
s1_writedata => waitrequest_s1_writedata
);
m1_nativeaddress <= downstream_m1_nativeaddress;
downstream_s1_nativeaddress <= upstream_m1_nativeaddress;
upstream_s1_nativeaddress <= waitrequest_m1_nativeaddress;
waitrequest_s1_nativeaddress <= s1_nativeaddress;
m1_debugaccess <= downstream_m1_debugaccess;
downstream_s1_debugaccess <= upstream_m1_debugaccess;
upstream_s1_debugaccess <= waitrequest_m1_debugaccess;
waitrequest_s1_debugaccess <= s1_debugaccess;
m1_arbiterlock <= downstream_m1_arbiterlock;
downstream_s1_arbiterlock <= upstream_m1_arbiterlock;
upstream_s1_arbiterlock <= waitrequest_m1_arbiterlock;
waitrequest_s1_arbiterlock <= s1_arbiterlock;
m1_writedata <= downstream_m1_writedata;
downstream_s1_writedata <= upstream_m1_writedata;
upstream_s1_writedata <= waitrequest_m1_writedata;
waitrequest_s1_writedata <= s1_writedata;
m1_chipselect <= downstream_m1_chipselect;
downstream_s1_chipselect <= upstream_m1_chipselect;
upstream_s1_chipselect <= waitrequest_m1_chipselect;
waitrequest_s1_chipselect <= s1_chipselect;
m1_burstcount <= downstream_m1_burstcount;
downstream_s1_burstcount <= upstream_m1_burstcount;
upstream_s1_burstcount <= waitrequest_m1_burstcount;
waitrequest_s1_burstcount <= s1_burstcount;
m1_byteenable <= downstream_m1_byteenable;
downstream_s1_byteenable <= upstream_m1_byteenable;
upstream_s1_byteenable <= waitrequest_m1_byteenable;
waitrequest_s1_byteenable <= s1_byteenable;
m1_arbiterlock2 <= downstream_m1_arbiterlock2;
downstream_s1_arbiterlock2 <= upstream_m1_arbiterlock2;
upstream_s1_arbiterlock2 <= waitrequest_m1_arbiterlock2;
waitrequest_s1_arbiterlock2 <= s1_arbiterlock2;
m1_read <= downstream_m1_read;
downstream_s1_read <= upstream_m1_read;
upstream_s1_read <= waitrequest_m1_read;
waitrequest_s1_read <= s1_read;
m1_write <= downstream_m1_write;
downstream_s1_write <= upstream_m1_write;
upstream_s1_write <= waitrequest_m1_write;
waitrequest_s1_write <= s1_write;
waitrequest_s1_address <= s1_address & std_logic_vector'("000");
upstream_s1_address <= waitrequest_m1_address;
downstream_s1_address <= upstream_m1_address;
m1_address <= downstream_m1_address;
downstream_m1_readdatavalid <= m1_readdatavalid;
upstream_m1_readdatavalid <= downstream_s1_readdatavalid;
waitrequest_m1_readdatavalid <= upstream_s1_readdatavalid;
s1_readdatavalid <= waitrequest_s1_readdatavalid;
downstream_m1_waitrequest <= m1_waitrequest;
upstream_m1_waitrequest <= downstream_s1_waitrequest;
waitrequest_m1_waitrequest <= upstream_s1_waitrequest;
s1_waitrequest <= waitrequest_s1_waitrequest;
downstream_m1_endofpacket <= m1_endofpacket;
upstream_m1_endofpacket <= downstream_s1_endofpacket;
waitrequest_m1_endofpacket <= upstream_s1_endofpacket;
s1_endofpacket <= waitrequest_s1_endofpacket;
downstream_m1_readdata <= m1_readdata;
upstream_m1_readdata <= downstream_s1_readdata;
waitrequest_m1_readdata <= upstream_s1_readdata;
s1_readdata <= waitrequest_s1_readdata;
--s1, which is an e_avalon_slave
--m1, which is an e_avalon_master
end europa;
|
-------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
-- Copyright 2011 - 2012
--
-- Email: [email protected]
--
-- License: LGPL
--
-- If you would like a version with a different license for use
-- in commercial projects please contact the above email address
-- for more details.
-------------------------------------------------------------------
--
-- Copyright (C) 2011 - 2012 Ultra-Embedded.com
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package peripherals is
-------------------------------------------------------------------
-- Components:
-------------------------------------------------------------------
component mpx
generic
(
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
);
port
(
-- General
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
intr_i : in std_logic;
step_done_o : out std_logic;
fault_o : out std_logic;
-- Data Memory
mem_addr_o : out std_logic_vector(31 downto 0);
mem_data_out_o : out std_logic_vector(31 downto 0);
mem_data_in_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic_vector(3 downto 0);
mem_rd_o : out std_logic;
mem_pause_i : in std_logic;
-- Debug Register Access
dbg_reg_addr_i : in std_logic_vector(8 downto 0);
dbg_reg_out_o : out std_logic_vector(31 downto 0);
dbg_pc_o : out std_logic_vector(31 downto 0)
);
end component;
component mpx_soc
generic
(
CLK_KHZ : integer := 12288;
UART_BAUD : integer := 115200;
EXTERNAL_INTERRUPTS : integer := 1;
CORE_ID : std_logic_vector := X"00000000";
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
);
port
(
-- General - clocking & rst_i
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
ext_intr_i : in std_logic_vector(EXTERNAL_INTERRUPTS-1 downto 0);
fault_o : out std_logic;
-- UART
uart_tx_o : out std_logic;
uart_rx_i : in std_logic;
-- BootRAM
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
-- External Memory
ext_mem_addr_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_i : in std_logic_vector(32-1 downto 0);
ext_mem_wr_o : out std_logic_vector(3 downto 0);
ext_mem_rd_o : out std_logic;
ext_mem_pause_i : in std_logic;
-- External IO
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
-- External Shared / DP-RAM
ext_dpram_addr_o : out std_logic_vector(32-1 downto 0);
ext_dpram_data_o : out std_logic_vector(32-1 downto 0);
ext_dpram_data_i : in std_logic_vector(32-1 downto 0);
ext_dpram_wr_o : out std_logic_vector(3 downto 0);
ext_dpram_rd_o : out std_logic;
ext_dpram_pause_i : in std_logic;
-- SPI Flash
flash_cs_o : out std_logic;
flash_si_o : out std_logic;
flash_so_i : in std_logic;
flash_sck_o : out std_logic;
-- Debug Register Access
dbg_reg_addr_i : in std_logic_vector(8 downto 0);
dbg_reg_out_o : out std_logic_vector(31 downto 0);
dbg_pc_o : out std_logic_vector(31 downto 0);
-- Debug UART Output
dbg_uart_data_o : out std_logic_vector(7 downto 0);
dbg_uart_wr_o : out std_logic
);
end component;
component asram16_if
generic
(
EXT_ADDR_WIDTH : integer := 17
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
timing_ctrl_i : in std_logic_vector(32-1 downto 0);
-- Asynchronous SRAM interface
sram_address_o: out std_logic_vector(EXT_ADDR_WIDTH-1 downto 0);
sram_data_o : out std_logic_vector(16-1 downto 0);
sram_data_i : in std_logic_vector(16-1 downto 0);
sram_oe_o : out std_logic;
sram_cs_o : out std_logic;
sram_be_o : out std_logic_vector(2-1 downto 0);
sram_we_o : out std_logic;
sram_dir_out_o: out std_logic;
-- Internal access
address_i : in std_logic_vector(32-1 downto 0);
data_i : in std_logic_vector(32-1 downto 0);
data_o : out std_logic_vector(32-1 downto 0);
rd_i : in std_logic;
wr_i : in std_logic_vector(4-1 downto 0);
ack_o : out std_logic;
busy_o : out std_logic
);
end component;
component uart
generic
(
DIVISOR : integer := 278
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
--
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
tx_avail_o : out std_logic;
tx_busy_o : out std_logic;
rx_avail_o : out std_logic;
rx_full_o : out std_logic;
rx_error_o : out std_logic;
--
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end component;
component spi_master
generic
(
-- Clock Divider
CLK_DIV : integer := 32;
-- Transfer Width
TRANSFER_WIDTH : integer := 8
);
port
(
-- Clocking / Reset
clk_i : in std_logic;
rst_i : in std_logic;
-- Control & Status
start_i : in std_logic;
done_o : out std_logic;
busy_o : out std_logic;
-- Data
data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
-- SPI interface
spi_clk_o : out std_logic;
spi_ss_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component;
component spi_ctrl
generic
(
MEM_ADDR_WIDTH : natural := 18;
XFER_COUNT_WIDTH : natural := 32;
TRANSFER_WIDTH : natural := 8
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
-- Memory interface
mem_address_o: out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
mem_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_rd_o : out std_logic;
mem_wr_o : out std_logic;
-- SPI Access
spi_start_o : out std_logic;
spi_done_i : in std_logic;
spi_busy_i : in std_logic;
spi_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
spi_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
-- Control
xfer_count_i : in std_logic_vector(XFER_COUNT_WIDTH-1 downto 0);
xfer_address_i: in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
xfer_start_i : in std_logic;
xfer_rx_only_i: in std_logic;
xfer_done_o : out std_logic;
xfer_busy_o : out std_logic
);
end component;
component spi_dma_ext
generic
(
MEM_ADDR_WIDTH : natural := 18;
XFER_COUNT_WIDTH : natural := 32;
SPI_CLK_DIV : natural := 4;
TRANSFER_WIDTH : natural := 8
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
-- SPI Interface
spi_clk_o : out std_logic;
spi_ss_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- Memory interface
mem_address_o: out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
mem_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_rd_o : out std_logic;
mem_wr_o : out std_logic;
-- Control
xfer_count_i : in std_logic_vector(XFER_COUNT_WIDTH-1 downto 0);
xfer_address_i: in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
xfer_start_i : in std_logic;
xfer_rx_only_i: in std_logic;
xfer_done_o : out std_logic;
xfer_busy_o : out std_logic
);
end component;
component i2s
generic
(
CLK_DIVISOR : integer := 6
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- Audio PCM input (2x16-bit LE signed data)
pcm_data_i : in std_logic_vector(32-1 downto 0);
pcm_fifo_empty_i: in std_logic;
pcm_fifo_rd_o : out std_logic;
pcm_fifo_ur_o : out std_logic;
-- I2S output
bclk_o : out std_logic;
ws_o : out std_logic;
data_o : out std_logic
);
end component;
end peripherals;
package body peripherals is
end; --package body
|
library verilog;
use verilog.vl_types.all;
entity View_output is
port(
clk : in vl_logic;
reset : in vl_logic;
hex0_out : out vl_logic_vector(7 downto 0);
hex1_out : out vl_logic_vector(7 downto 0);
hex2_out : out vl_logic_vector(7 downto 0)
);
end View_output;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev28 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev28 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RX4 : std_logic_vector(2 downto 0) is IR4(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RY3 : std_logic_vector(2 downto 0) is IR3(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
signal tmpxx: std_logic_vector(19 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDMD2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
--constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal rcount : std_logic_vector(31 downto 0);
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
signal lcount: std_logic_vector(31 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=LDMD) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when ((Opcode3=RETI or Opcode3=LDMD) and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2 = LDMD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI or Opcode3=LDMD) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
rcount <= x"00000000";
lcount <= x"00000000";
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM or Opcode2 = LDMD) then
MAR <= x"000" & M2;
tmpxx <= std_logic_vector((unsigned(M2) + 1));
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
end if;
if (to_integer(unsigned(rcount)) < 16) then
wout <= std_logic_vector(mvect(to_integer(unsigned(rcount))));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(wva) + unsigned(h0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(wva) + unsigned(h0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(wvb) + unsigned(h1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(wvb) + unsigned(h1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(wvc) + unsigned(h2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(wvc) + unsigned(h2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(wvd) + unsigned(h3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(wvd) + unsigned(h3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(wve) + unsigned(h4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(wve) + unsigned(h4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(wvf) + unsigned(h5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(wvf) + unsigned(h5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(wvg) + unsigned(h6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(wvg) + unsigned(h6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(wvh) + unsigned(h7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(wvh) + unsigned(h7))(31 downto 0);
-- elsif (Opcode2 = FIN) then
-- dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
-- dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
-- dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
-- dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
-- dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
-- dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
-- dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
-- dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX or Opcode2 = LDMD) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(rcount)))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=LDMD) then
mvect(to_integer(unsigned(lcount)))(63 downto 32) <= MDR_in;
MAR <= x"000" & tmpxx;
register_file(to_integer(unsigned(RX3))) <= std_logic_vector(lcount);
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (to_integer(unsigned(rcount)) < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= std_logic_vector((unsigned(rcount)+1));
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= std_logic_vector((unsigned(rcount)+1));
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif(Opcode3 = LDMD) then
MDR_in <= MEM_in;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
mvect(to_integer(unsigned(lcount)))(31 downto 0) <= MDR_in;
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
lcount <= std_logic_vector(unsigned(lcount)+1);
end if;
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity FSM is
PORT(
clock,reset,nivel, abierto, cerrado: IN std_logic;
piso,boton: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
boton_memoria: out STD_LOGIC_VECTOR (1 DOWNTO 0);
accionador_puerta: out STD_LOGIC;
accionador_subir, accionador_bajar: out STD_LOGIC
);
end FSM;
architecture Behavioral of FSM is
TYPE estado IS (inicial,parado,cerrando,marcha,abriendo);
SIGNAL presente: estado:=inicial;
SIGNAL bot: std_logic_vector(1 DOWNTO 0); -- Almacena botón pulsado
SIGNAL piso_ini: std_logic_vector(1 DOWNTO 0); -- Piso de partida
begin
estados:
PROCESS(reset,clock)
BEGIN
IF reset='1' THEN presente<=inicial;
ELSIF clock='1' AND clock'event THEN
CASE presente IS
WHEN inicial=> -- Estado inicial para que se nivele
IF nivel='1' then presente<=parado;
END IF;
WHEN parado=> -- Espera la pulsación de un botón
IF (bot/="00") AND (bot/=piso) THEN presente<=cerrando;
END IF;
WHEN cerrando=> -- Cierra la puerta
IF cerrado='1' THEN presente<=marcha;
END IF;
WHEN marcha=> -- Lleva el ascensor a su piso
IF (bot=piso) AND (nivel='1') THEN presente<=abriendo;
END IF;
WHEN abriendo=> -- Abre las puertas
IF abierto='1' THEN presente<=parado;
END IF;
END CASE;
END IF;
END PROCESS estados;
salida:
PROCESS(clock)
BEGIN
if rising_edge(clock) then
boton_memoria<=bot;
CASE presente IS
WHEN inicial=> -- Al encender puede que este entre dos pisos
IF piso/="01" THEN
accionador_subir<='0'; -- Bajamos
accionador_bajar<='1';
END IF;
accionador_puerta<='0'; -- Cerrada
WHEN parado=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='1'; -- Abierta
WHEN cerrando=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='0';
WHEN marcha=>
IF bot<piso_ini THEN
accionador_subir<='0'; -- Bajamos
accionador_bajar<='1';
ELSE
accionador_subir<='1'; -- Subimos
accionador_bajar<='0';
END IF;
accionador_puerta<='0'; -- Cerrada
WHEN abriendo=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='1'; -- Abrir
END CASE;
end if;
END PROCESS salida;
memoria:
PROCESS(reset,clock,piso) -- Captura la pulsación del botón
BEGIN -- y el piso donde se encuentra
IF reset='1' THEN
bot<="00";
piso_ini<=piso;
ELSIF clock='1' AND clock'event THEN
IF presente=parado THEN
IF (boton="01") OR (boton="10") OR (boton="11") THEN bot<=boton;
ELSE bot<="00"; -- Cualquier otra combinación no vale
END IF;
piso_ini<=piso;
END IF;
END IF;
END PROCESS memoria;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity putchar_testbench is
generic (
output_file : string := "putchar.out");
port (
-- inputs:
signal address : in std_logic_vector (1 downto 0);
signal chipselect : in std_logic;
signal clk : in std_logic;
signal reset : in std_logic;
signal write_i : in std_logic;
signal writedata : in std_logic_vector (31 downto 0);
signal waitrequest : out std_logic);
end entity putchar_testbench;
architecture rtl of putchar_testbench is
begin
waitrequest <= '0';
process(clk)
variable uart_byte :std_logic_vector(7 downto 0);
file outfile : text;
variable f_status: FILE_OPEN_STATUS;
variable outline : line;
variable out_chr : character;
variable out_str : string(1 downto 1);
begin
if rising_edge(clk) then
if write_i = '1' and chipselect = '1' then
uart_byte := writedata(uart_byte'range);
file_open(f_status,outfile, OUTPUT_FILE,append_mode);
out_chr := character'val(to_integer(unsigned(uart_byte)));
out_str(1) := out_chr;
write(outfile,out_str);
file_close(outfile);
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logic;
start: in std_logic;
result: inout std_logic_vector(31 downto 0);
outAB : out std_logic_vector(31 downto 0);
ready : out std_logic_vector(7 downto 0)
);
end multiplier;
architecture synt of multiplier is
signal romAOut : std_logic_vector (31 downto 0);
signal romBOut : std_logic_vector (31 downto 0);
component graph_driver
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end component;
signal outAB_graph_s: std_logic_vector(31 downto 0);
signal result_graph_s: std_logic_vector(31 downto 0);
component romMemOpA
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component romMemOpB
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component device
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end component;
signal en_mul:std_logic;
signal rst_mul:std_logic;
signal result_graph_ss: std_logic_vector(31 downto 0);
signal res: std_logic_vector(31 downto 0);
signal done_mult: std_logic;
signal graph: std_logic_vector(31 downto 0);
type state is (initial, multiply, view_result);
signal CurrentState, NextState : state;
begin
process(CurrentState) begin
NextState<=initial;
result_graph_s<=(others=>'0');
case CurrentState is
when initial =>
en_mul<='0';
rst_mul<='0';
-----result<="11110000010000000010010011110001";
if(start='0') then
NextState<=multiply;
else
NextState<=initial;
end if;
when multiply =>
en_mul<='1';
rst_mul<='1';
if(done_mult='1') then
NextState<=view_result;
else
NextState<=multiply;
end if;
when view_result =>
--en_mul<='1';
--if(reset='0') then
--NextState<=initial;
--else
--NextState<=view_result;
--end if;
NextState<=multiply;
end case;
end process;
transitions:process (clk, reset) begin
if reset='0'then
CurrentState <= initial;
elsif (clk'event and clk='1')then
CurrentState <= NextState;
end if;
end process;
uOpA: romMemOpA
port map (
addr => addrA,
dataOut => romAOut
);
uOpB: romMemOpB
port map (
addr => addrB,
dataOut => romBOut
);
uMult: device
port map (
a => romAOut,
b => romBOut,
clk=>clk ,
en=> en_mul,
rst=> rst_mul,
c => result_graph_ss,
done=>done_mult
);
outtAB_graph: graph_driver port map(in_graph=>outAB_graph_s,out_graph=>outAB);
result_graph: graph_driver port map(in_graph=>result_graph_ss,out_graph=>res);
with currentState select
result<="11110000010000000010010011110001" when initial,
res when others ;
-- When the button assoiciated to outAB is pushed romAOut is displayed
outAB_graph_s<= romAOut when showAB = '0'
else romBOut;
ready(7 downto 0) <= (others => done_mult);
end synt;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
siw : in std_logic_vector (7 downto 0) := "00000000";
led : out std_logic_vector (7 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
led(0) <= (not siw(0));
led(1) <= siw(1) and (not siw(2));
led(2) <= siw(1) or siw(3);
led(3) <= siw(2) and siw(3);
led(4) <= siw(4);
led(5) <= siw(5);
led(6) <= siw(6);
led(7) <= siw(7);
end Behavioral; |
-- ###################################################################################
--
-- #### #### #####
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ### ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- ###################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
generic (FilterSize : positive := 10);
port(
clk : in std_logic;
reset : in std_logic;
PS2_Clk : in std_logic;
PS2_Data : in std_logic;
Key_Data : out std_logic_vector(7 downto 0) );
end keyboard;
architecture Behavioral of keyboard is
signal PS2_Datr : std_logic;
signal DoRead : std_logic; -- From outside when reading the scan code
signal Scan_Err : std_logic; -- To outside : Parity or Overflow error
signal Scan_Code : std_logic_vector(7 downto 0); -- Eight bits Data Out
signal Filter : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t0 : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t1 : std_logic_vector(FilterSize-1 downto 0);
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Parity : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic; signal Code_Readed : std_logic;
signal Key_Released : std_logic;
signal Extend_Key : std_logic;
signal Matrix : std_logic_vector(7 downto 0);
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Filter_t0 <= (others=>'0');
Filter_t1 <= (others=>'1');
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t1 then
PS2_Clk_f <= '1';
elsif Filter = Filter_t0 then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Err <= '0';
Code_Readed <= '0';
elsif rising_edge (Clk) then
Code_Readed <= '0';
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr);
Scan_Code <= S_Reg(7 downto 0);
Code_Readed <= '1';
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
end if;
end process;
process(Clk,Reset)
variable aaa : std_logic_vector(7 downto 0);
begin
if Reset='1' then
Matrix <= (others => '0');
Key_Released <= '0';
Extend_Key <= '0';
elsif rising_edge (Clk) then
if Code_Readed = '1' then -- ScanCode is Readed
if Scan_Code = x"F0" then -- Key is Released
Key_Released <= '1';
elsif Scan_Code = x"E0" then -- Extended Key Pressed
Extend_Key <= '1';
else -- Analyse
aaa := (others=>'0');
case Scan_Code is
when x"76" => aaa := "00000001"; -- ESC
when x"5A" => aaa := "00000010"; -- ENTER
when x"75" =>
if Extend_Key = '1' then
aaa := "00000100"; -- UP
end if;
when x"6B" =>
if Extend_Key = '1' then
aaa := "00001000"; -- LEFT
end if;
when x"72" =>
if Extend_Key = '1' then
aaa := "00010000"; -- DOWN
end if;
when x"74" =>
if Extend_Key = '1' then
aaa := "00100000"; -- RIGHT
end if;
when others => null;
end case;
if Key_Released = '0' then
Matrix <= Matrix or aaa;
else
Matrix <= Matrix and not aaa;
end if;
Key_Released <= '0';
Extend_Key <= '0';
end if;
end if;
end if;
end process;
Key_Data <= Matrix;
end Behavioral;
|
-- NEED RESULT: ARCH00090.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090.P2: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090.P3: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00090
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00090)
-- ENT00090_Test_Bench(ARCH00090_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00090 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00090.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00090" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00090.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00090" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00090.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00090" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00090" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00090 ;
--
entity ENT00090_Test_Bench is
end ENT00090_Test_Bench ;
--
architecture ARCH00090_Test_Bench of ENT00090_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00090 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00090_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : boolean := true;
g_boot_rom : boolean := false;
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
break_o : out std_logic;
error : out std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end cpu_wrapper_zpu;
architecture logical of cpu_wrapper_zpu is
signal cpu_address : std_logic_vector(26 downto 0);
signal cpu_size : std_logic_vector(1 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_instr : std_logic;
signal cpu_req : std_logic;
signal cpu_rack : std_logic;
signal cpu_dack : std_logic;
signal ram_rack : std_logic := '0';
signal ram_dack : std_logic := '0';
signal ram_claimed : std_logic := '0';
signal ram_rdata : std_logic_vector(7 downto 0) := X"FF";
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal break_o_i : std_logic;
signal reset_cpu : std_logic;
type t_state is (idle, busy);
signal state : t_state;
type t_crash_state is (all_ok, flash_on, flash_off);
signal crash_state : t_crash_state := all_ok;
signal delay : integer range 0 to 8388607 := 0;
begin
break_o <= break_o_i;
core: entity work.zpu
generic map (
g_addr_size => cpu_address'length,
g_stack_size => 12,
g_prog_size => 20, -- Program size
g_dont_care => '-') -- Value used to fill the unused bits, can be '-' or '0'
port map (
clock => clock,
reset => reset_cpu,
interrupt_i => io_resp.irq,
break_o => break_o_i,
mem_address => cpu_address,
mem_instr => cpu_instr,
mem_size => cpu_size,
mem_req => cpu_req,
mem_write => cpu_write,
mem_rack => cpu_rack,
mem_dack => cpu_dack,
mem_wdata => cpu_wdata,
mem_rdata => cpu_rdata );
r_int_ram: if g_internal_prg generate
r_boot: if g_boot_rom generate
i_zpuram: entity work.mem32k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
r_noboot: if not g_boot_rom generate
i_zpuram: entity work.mem4k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
end generate;
cpu_rdata <= io_resp.data when io_resp.ack='1'
else mem_resp.data when mem_dack='1'
else ram_rdata;
cpu_rack <= io_resp.ack or mem_rack or ram_rack;
cpu_dack <= (io_resp.ack and not cpu_write) or mem_dack or ram_dack;
mem_req.request <= '1' when cpu_req='1' and cpu_address(26)='0' and ram_claimed='0'
else '0';
mem_req.tag <= g_mem_tag;
mem_req.address <= unsigned(cpu_address(25 downto 0));
mem_req.read_writen <= not cpu_write;
mem_req.data <= cpu_wdata;
mem_req.size <= "00"; -- to be optimized
mem_rack <= '1' when mem_resp.rack_tag = g_mem_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_mem_tag else '0';
io_req.address(19 downto 2) <= unsigned(cpu_address(19 downto 2));
with cpu_address(24) select
io_req.address( 1 downto 0) <=
unsigned(cpu_address(1 downto 0) xor cpu_size) when '0',
unsigned(cpu_address(1 downto 0)) when others;
io_req.data <= cpu_wdata;
p_io: process(clock)
begin
if rising_edge(clock) then
io_req.read <= '0';
io_req.write <= '0';
case state is
when idle =>
if cpu_req='1' and cpu_address(26)='1' then
io_req.read <= not cpu_write;
io_req.write <= cpu_write;
state <= busy;
end if;
when busy =>
if io_resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
p_crash: process(clock)
begin
if rising_edge(clock) then
case crash_state is
when all_ok =>
reset_cpu <= '0';
error <= '0';
delay <= 6_250_000;
if break_o_i='1' then
reset_cpu <= '1';
crash_state <= flash_on;
end if;
when flash_on =>
reset_cpu <= '1';
error <= '1';
if delay = 0 then
crash_state <= flash_off;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when flash_off =>
reset_cpu <= '1';
error <= '0';
if delay = 0 then
crash_state <= flash_on;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when others =>
crash_state <= flash_on;
end case;
if reset='1' then
error <= '0';
reset_cpu <= '1';
crash_state <= all_ok;
end if;
end if;
end process;
end logical;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : boolean := true;
g_boot_rom : boolean := false;
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
break_o : out std_logic;
error : out std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end cpu_wrapper_zpu;
architecture logical of cpu_wrapper_zpu is
signal cpu_address : std_logic_vector(26 downto 0);
signal cpu_size : std_logic_vector(1 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_instr : std_logic;
signal cpu_req : std_logic;
signal cpu_rack : std_logic;
signal cpu_dack : std_logic;
signal ram_rack : std_logic := '0';
signal ram_dack : std_logic := '0';
signal ram_claimed : std_logic := '0';
signal ram_rdata : std_logic_vector(7 downto 0) := X"FF";
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal break_o_i : std_logic;
signal reset_cpu : std_logic;
type t_state is (idle, busy);
signal state : t_state;
type t_crash_state is (all_ok, flash_on, flash_off);
signal crash_state : t_crash_state := all_ok;
signal delay : integer range 0 to 8388607 := 0;
begin
break_o <= break_o_i;
core: entity work.zpu
generic map (
g_addr_size => cpu_address'length,
g_stack_size => 12,
g_prog_size => 20, -- Program size
g_dont_care => '-') -- Value used to fill the unused bits, can be '-' or '0'
port map (
clock => clock,
reset => reset_cpu,
interrupt_i => io_resp.irq,
break_o => break_o_i,
mem_address => cpu_address,
mem_instr => cpu_instr,
mem_size => cpu_size,
mem_req => cpu_req,
mem_write => cpu_write,
mem_rack => cpu_rack,
mem_dack => cpu_dack,
mem_wdata => cpu_wdata,
mem_rdata => cpu_rdata );
r_int_ram: if g_internal_prg generate
r_boot: if g_boot_rom generate
i_zpuram: entity work.mem32k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
r_noboot: if not g_boot_rom generate
i_zpuram: entity work.mem4k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
end generate;
cpu_rdata <= io_resp.data when io_resp.ack='1'
else mem_resp.data when mem_dack='1'
else ram_rdata;
cpu_rack <= io_resp.ack or mem_rack or ram_rack;
cpu_dack <= (io_resp.ack and not cpu_write) or mem_dack or ram_dack;
mem_req.request <= '1' when cpu_req='1' and cpu_address(26)='0' and ram_claimed='0'
else '0';
mem_req.tag <= g_mem_tag;
mem_req.address <= unsigned(cpu_address(25 downto 0));
mem_req.read_writen <= not cpu_write;
mem_req.data <= cpu_wdata;
mem_req.size <= "00"; -- to be optimized
mem_rack <= '1' when mem_resp.rack_tag = g_mem_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_mem_tag else '0';
io_req.address(19 downto 2) <= unsigned(cpu_address(19 downto 2));
with cpu_address(24) select
io_req.address( 1 downto 0) <=
unsigned(cpu_address(1 downto 0) xor cpu_size) when '0',
unsigned(cpu_address(1 downto 0)) when others;
io_req.data <= cpu_wdata;
p_io: process(clock)
begin
if rising_edge(clock) then
io_req.read <= '0';
io_req.write <= '0';
case state is
when idle =>
if cpu_req='1' and cpu_address(26)='1' then
io_req.read <= not cpu_write;
io_req.write <= cpu_write;
state <= busy;
end if;
when busy =>
if io_resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
p_crash: process(clock)
begin
if rising_edge(clock) then
case crash_state is
when all_ok =>
reset_cpu <= '0';
error <= '0';
delay <= 6_250_000;
if break_o_i='1' then
reset_cpu <= '1';
crash_state <= flash_on;
end if;
when flash_on =>
reset_cpu <= '1';
error <= '1';
if delay = 0 then
crash_state <= flash_off;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when flash_off =>
reset_cpu <= '1';
error <= '0';
if delay = 0 then
crash_state <= flash_on;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when others =>
crash_state <= flash_on;
end case;
if reset='1' then
error <= '0';
reset_cpu <= '1';
crash_state <= all_ok;
end if;
end if;
end process;
end logical;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : boolean := true;
g_boot_rom : boolean := false;
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
break_o : out std_logic;
error : out std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end cpu_wrapper_zpu;
architecture logical of cpu_wrapper_zpu is
signal cpu_address : std_logic_vector(26 downto 0);
signal cpu_size : std_logic_vector(1 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_instr : std_logic;
signal cpu_req : std_logic;
signal cpu_rack : std_logic;
signal cpu_dack : std_logic;
signal ram_rack : std_logic := '0';
signal ram_dack : std_logic := '0';
signal ram_claimed : std_logic := '0';
signal ram_rdata : std_logic_vector(7 downto 0) := X"FF";
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal break_o_i : std_logic;
signal reset_cpu : std_logic;
type t_state is (idle, busy);
signal state : t_state;
type t_crash_state is (all_ok, flash_on, flash_off);
signal crash_state : t_crash_state := all_ok;
signal delay : integer range 0 to 8388607 := 0;
begin
break_o <= break_o_i;
core: entity work.zpu
generic map (
g_addr_size => cpu_address'length,
g_stack_size => 12,
g_prog_size => 20, -- Program size
g_dont_care => '-') -- Value used to fill the unused bits, can be '-' or '0'
port map (
clock => clock,
reset => reset_cpu,
interrupt_i => io_resp.irq,
break_o => break_o_i,
mem_address => cpu_address,
mem_instr => cpu_instr,
mem_size => cpu_size,
mem_req => cpu_req,
mem_write => cpu_write,
mem_rack => cpu_rack,
mem_dack => cpu_dack,
mem_wdata => cpu_wdata,
mem_rdata => cpu_rdata );
r_int_ram: if g_internal_prg generate
r_boot: if g_boot_rom generate
i_zpuram: entity work.mem32k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
r_noboot: if not g_boot_rom generate
i_zpuram: entity work.mem4k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
end generate;
cpu_rdata <= io_resp.data when io_resp.ack='1'
else mem_resp.data when mem_dack='1'
else ram_rdata;
cpu_rack <= io_resp.ack or mem_rack or ram_rack;
cpu_dack <= (io_resp.ack and not cpu_write) or mem_dack or ram_dack;
mem_req.request <= '1' when cpu_req='1' and cpu_address(26)='0' and ram_claimed='0'
else '0';
mem_req.tag <= g_mem_tag;
mem_req.address <= unsigned(cpu_address(25 downto 0));
mem_req.read_writen <= not cpu_write;
mem_req.data <= cpu_wdata;
mem_req.size <= "00"; -- to be optimized
mem_rack <= '1' when mem_resp.rack_tag = g_mem_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_mem_tag else '0';
io_req.address(19 downto 2) <= unsigned(cpu_address(19 downto 2));
with cpu_address(24) select
io_req.address( 1 downto 0) <=
unsigned(cpu_address(1 downto 0) xor cpu_size) when '0',
unsigned(cpu_address(1 downto 0)) when others;
io_req.data <= cpu_wdata;
p_io: process(clock)
begin
if rising_edge(clock) then
io_req.read <= '0';
io_req.write <= '0';
case state is
when idle =>
if cpu_req='1' and cpu_address(26)='1' then
io_req.read <= not cpu_write;
io_req.write <= cpu_write;
state <= busy;
end if;
when busy =>
if io_resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
p_crash: process(clock)
begin
if rising_edge(clock) then
case crash_state is
when all_ok =>
reset_cpu <= '0';
error <= '0';
delay <= 6_250_000;
if break_o_i='1' then
reset_cpu <= '1';
crash_state <= flash_on;
end if;
when flash_on =>
reset_cpu <= '1';
error <= '1';
if delay = 0 then
crash_state <= flash_off;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when flash_off =>
reset_cpu <= '1';
error <= '0';
if delay = 0 then
crash_state <= flash_on;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when others =>
crash_state <= flash_on;
end case;
if reset='1' then
error <= '0';
reset_cpu <= '1';
crash_state <= all_ok;
end if;
end if;
end process;
end logical;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "Step Down";
impulse_width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
result : out std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_single_pulse_GN2XGKTRR3 is
Begin
SinglePulsei : alt_dspbuilder_sStepAltr Generic map (
StepDelay => 1,
direction => 0 )
port map (
clock => clock,
ena => ena,
q => result,
sclr => sclr,
user_aclr => '0',
aclr => aclr);
end architecture;
|
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal enc : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal block_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
key => key,
block_in => block_in,
block_out => block_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- ==============================================
-- T_0: Test encryption and subsequent decryption
-- ==============================================
-- SIMON 64/128 test vectors
block_in <= X"656b696c20646e75";
key <= X"1b1a1918131211100b0a090803020100";
-- Test encryption
enc <= '0';
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Wait for registers
wait for 44*clk_period;
assert block_out = X"44c8fc20b9dfa07a"
report "ENCRYPT ERROR (e_0)" severity FAILURE;
-- Use output of encryption as input for decryption
block_in <= block_out;
-- Test decryption
enc <= '1';
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Wait for registers
wait for 44*clk_period;
assert block_out = X"656b696c20646e75"
report "DECRYPT ERROR (d_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity counter is
port(Clock: in std_logic;
Count5: out std_logic;
Count7: out std_logic);
end counter;
architecture Behavioral of counter is
signal temp: std_logic_vector(0 to 2) := "000";
begin process(Clock)
begin
if(Clock'event and Clock='0') then
if temp = "000" or temp = "111"
then
Count7 <= '1';
else
Count7 <= '0';
end if;
end if;
if(Clock'event and Clock='1') then
Count7 <= '0';
if temp="101" or temp="110" then
Count5 <= '1';
else
Count5 <= '0';
end if;
if temp="111" then
temp<="001";
else
temp <= temp + 1;
end if;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_codec_gen
-- File: grspw_codec_gen.vhd
-- Author: Marko Isomaki - Aeroflex Gaisler
-- Description: Generic wrapper for SpaceWire encoder-decoder
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 3 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end entity;
architecture rtl of grspw_codec_gen is
constant fabits : integer := log2(fifosize/4)+2;
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(9 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(9 downto 0);
signal rxerror : std_logic_vector(1 downto 0);
signal rxaccess : std_ulogic;
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(8 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(8 downto 0);
signal txerror : std_logic_vector(1 downto 0);
signal txaccess : std_ulogic;
signal testin : std_logic_vector(3 downto 0);
begin
testin <= testen & "000";
core : grspw_codec_core
generic map(
ports => ports,
input_type => input_type,
output_type => output_type,
rxtx_sameclk => rxtx_sameclk,
fifosize => fifosize,
tech => tech,
scantest => scantest
)
port map(
rst => rst,
clk => clk,
rxclk0 => rxclk0,
rxclk1 => rxclk1,
txclk => txclk,
txclkn => txclkn,
testen => testen,
testrst => testrst,
--spw in
d => d,
dv => dv,
dconnect => dconnect,
--spw out
do => do,
so => so,
--link fsm
linkdisabled => linkdisabled,
linkstart => linkstart,
autostart => autostart,
portsel => portsel,
noportforce => noportforce,
rdivisor => rdivisor,
idivisor => idivisor,
state => state,
actport => actport,
dconnecterr => dconnecterr,
crederr => crederr,
escerr => escerr,
parerr => parerr,
--rx fifo signals
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
rxaccess => rxaccess,
--rx iface
rxicharav => rxicharav,
rxicharcnt => rxicharcnt,
rxichar => rxichar,
rxiread => rxiread,
rxififorst => rxififorst,
--tx fifo signals
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
txaccess => txaccess,
--tx iface
txicharcnt => txicharcnt,
txifull => txifull,
txiempty => txiempty,
txiwrite => txiwrite,
txichar => txichar,
txififorst => txififorst,
txififorstact => txififorstact,
--time iface
tickin => tickin,
timein => timein,
tickin_done => tickin_done,
tickout => tickout,
timeout => timeout
);
ft0 : if ft = 0 generate
merror <= '0';
end generate;
ft1 : if ft /= 0 generate
merror <= (orv(rxerror) and rxaccess) or (orv(txerror) and txaccess);
end generate;
--receiver nchar FIFO
rx_ram : syncram_2pft generic map(tech*techfifo, fabits, 10, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk, rxwrite,
rxwaddress(fabits-1 downto 0), rxwdata, rxerror, testin);
--transmitter nchar FIFO
tx_ram : syncram_2pft generic map(tech*techfifo, fabits, 9, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk, txwrite,
txwaddress(fabits-1 downto 0), txwdata, txerror, testin);
end architecture;
|
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: gcpad_ctrl-c.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $
--
-------------------------------------------------------------------------------
configuration gcpad_ctrl_rtl_c0 of gcpad_ctrl is
for rtl
end for;
end gcpad_ctrl_rtl_c0;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_b_0 : in std_logic_vector(14 downto 0);
i_b_1 : in std_logic_vector(14 downto 0);
i_b_2 : in std_logic_vector(14 downto 0);
i_b_3 : in std_logic_vector(14 downto 0);
i_a_1 : in std_logic_vector(14 downto 0);
i_a_2 : in std_logic_vector(14 downto 0);
i_a_3 : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(11 downto 0);
-- filtered data
o_data : out std_logic_vector(11 downto 0));
end iir;
architecture Behavioral of iir is
type t_data_pipe is array (0 to 3) of signed(11 downto 0);
type t_fdata_pipe is array (0 to 3) of signed(11 downto 0);
type t_bcoeff is array (0 to 3) of signed(14 downto 0);
type t_acoeff is array (0 to 3) of signed(14 downto 0);
type t_mult is array (0 to 3) of signed(26 downto 0);
type t_fmult is array (0 to 3) of signed(26 downto 0);
type t_add_st0 is array (0 to 1) of signed(26+1 downto 0);
type t_fadd_st0 is array (0 to 1) of signed(26+1 downto 0);
signal r_bcoeff : t_bcoeff;
signal r_acoeff : t_acoeff;
signal p_data : t_data_pipe;
signal p_fdata : t_fdata_pipe;
signal r_mult : t_mult;
signal r_fmult : t_fmult;
signal r_add_st0 : t_add_st0;
signal r_fadd_st0 : t_fadd_st0;
signal r_add_st1 : signed(26+2 downto 0);
signal r_fadd_st1 : signed(26+2 downto 0);
signal r_final_sum : signed(26+2 downto 0);
signal out_buf : signed(11 downto 0);
begin
--- Data input ---
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
p_fdata <= (others=>(others=>'0'));
r_bcoeff <= (others=>(others=>'0'));
r_acoeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
p_fdata <= out_buf & p_fdata(0 to p_fdata'length-2);
r_bcoeff(0) <= signed(i_b_0);
r_bcoeff(1) <= signed(i_b_1);
r_bcoeff(2) <= signed(i_b_2);
r_bcoeff(3) <= signed(i_b_3);
r_acoeff(0) <= signed(i_a_1);
r_acoeff(1) <= signed(i_a_2);
r_acoeff(2) <= signed(i_a_3);
-- r_acoeff(3) <= signed('0');
end if;
end process p_input;
--- Feedforward ---
p_mult : process (i_rstb,i_clk,p_data,r_bcoeff,p_fdata,r_acoeff)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
r_fmult <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_bcoeff(k);
r_fmult(k) <= p_fdata(k) * r_acoeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk,r_mult,r_fmult)
begin
if(i_rstb='1') then
r_add_st0 <= (others=>(others=>'0'));
r_fadd_st0 <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),28) + resize(r_mult(2*k+1),28);
r_fadd_st0(k) <= resize(r_fmult(2*k),28) + resize(r_fmult(2*k+1),28);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk,r_add_st0,r_fadd_st0)
begin
if(i_rstb='1') then
r_add_st1 <= (others=>'0');
r_fadd_st1 <= (others=>'0');
elsif(i_clk='1') then
r_add_st1 <= resize(r_add_st0(0),29) + resize(r_add_st0(1),29);
r_fadd_st1 <= resize(r_fadd_st0(0),29) + resize(r_fadd_st0(1),29);
end if;
end process p_add_st1;
--- Feedback ---
-- p_fmult : process (i_rstb,i_clk,p_fdata,r_acoeff)
-- begin
-- if(i_rstb='1') then
-- r_fmult <= (others=>(others=>'0'));
-- elsif(i_clk='1') then
-- for k in 0 to 3 loop
-- r_fmult(k) <= p_fdata(k) * r_acoeff(k);
-- end loop;
-- end if;
-- end process p_fmult;
-- p_fadd_st0 : process (i_rstb,i_clk,r_fmult)
-- begin
-- if(i_rstb='1') then
-- r_fadd_st0 <= (others=>(others=>'0'));
-- elsif(i_clk='1') then
-- for k in 0 to 1 loop
-- r_fadd_st0(k) <= resize(r_fmult(2*k),28) + resize(r_fmult(2*k+1),28);
-- end loop;
-- end if;
-- end process p_fadd_st0;
-- p_fadd_st1 : process (i_rstb,i_clk,r_fadd_st0)
-- begin
-- if(i_rstb='1') then
-- r_fadd_st1 <= (others=>'0');
-- elsif(i_clk='1') then
-- r_fadd_st1 <= resize(r_fadd_st0(0),29) + resize(r_fadd_st0(1),29);
-- end if;
-- end process p_fadd_st1;
p_final_sum : process (i_rstb,i_clk,r_add_st1,r_fadd_st1)
begin
if(i_rstb='1') then
r_final_sum <= (others=>'0');
elsif(i_clk='1') then
r_final_sum <= r_add_st1 - r_fadd_st1;
end if;
end process p_final_sum;
p_output : process (i_rstb,i_clk,r_final_sum,p_fdata,out_buf)
begin
done <= '0';
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
elsif(i_clk='1') then
done <= '1';
out_buf <= r_final_sum(26 downto 15);
o_data <= std_logic_vector(out_buf);
end if;
end process p_output;
-- p_done : process (i_rstb, i_clk)
-- begin
-- if(i_rstb='0') then
-- done <= '0';
-- elsif(rising_edge(i_clk)) then
-- done <= '1';
-- end if;
-- end process p_done;
end Behavioral;
|
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`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
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B1r0wD6tkTlV3Q==
`protect end_protected
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter4 is
port( clk : in std_logic;
reset : in std_logic;
enable: in std_logic;
count : out std_logic_vector(1 downto 0));
end Counter4;
-- Contador de 0 a 3.
architecture Behavioral of Counter4 is
signal s_count : unsigned (1 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(not(s_count(0)='0') and not(s_count(0)='1')) then
s_count <= (others => '0');
elsif(reset='1') then
s_count <= (others => '0');
elsif (enable = '0') then
s_count <= s_count;
else
s_count <= s_count + 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral; |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-16 V0.01 zelenkaj First version
-- 2010-10-11 V0.02 zelenkaj Bugfix: PCP can't be producer in any case => added generic
-- 2010-10-25 V0.03 zelenkaj Use one Address Adder per DPR port side (reduces LE usage)
-- 2011-04-26 V0.04 zelenkaj generic for clock domain selection
-- 2011-12-13 V0.05 zelenkaj Added constants for one hot code
-- Reduced clkXing to two signals (one hot -> bin -> one hot)
------------------------------------------------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the appropriate address offset
-- The output address offset has to be added to the input address.
-- The trigger signal switches to the next available buffer. The switch mechanism is implemented in the
-- PCP's clock domain. Thus the switch over on the PCP side is performed without delay. An AP switch over crosses
-- from AP to PCP clock domain (2x pcpClk) and back from PCP to AP (2x apClk).
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
|
architecture test of test2 is
constant foo : bar := "hel"lo";
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_804;
architecture augh of cmp_804 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_804;
architecture augh of cmp_804 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
|
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
|
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
--write(l, 50 ns, field => 20, justified => right, unit => us);
--writeline(output, l);
wait;
end process;
end architecture;
|
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
--write(l, 50 ns, field => 20, justified => right, unit => us);
--writeline(output, l);
wait;
end process;
end architecture;
|
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
--write(l, 50 ns, field => 20, justified => right, unit => us);
--writeline(output, l);
wait;
end process;
end architecture;
|
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
--write(l, 50 ns, field => 20, justified => right, unit => us);
--writeline(output, l);
wait;
end process;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SX9KW8s1cjgHNPaHacV8JxqNOFYndCzeHmeDOgBNBPCNmhgbTkYoEYuZQZngTJO3IMifpv3/8doM
NnihbQmbUw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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XI8ZjEPgh6S3If1NfNo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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85fAEm3i3JXK5Sw/K+Nf0IDUFWpUG8mSfPwJAQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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pt9OevHfBhm/yqr8Ds0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62080)
`protect data_block
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`protect end_protected
|
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00616
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00616(ARCH00616)
-- ENT00616_Test_Bench(ARCH00616_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00616 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
end ENT00616 ;
--
--
architecture ARCH00616 of ENT00616 is
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
procedure P1
(signal s_st_boolean_vector : in st_boolean_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_boolean_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_severity_level_vector : in st_severity_level_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_severity_level_vector_cnt + 1 ;
--
end ;
--
procedure P3
(signal s_st_string : in st_string ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_string_cnt + 1 ;
--
end ;
--
procedure P4
(signal s_st_enum1_vector : in st_enum1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_enum1_vector_cnt + 1 ;
--
end ;
--
procedure P5
(signal s_st_integer_vector : in st_integer_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_integer_vector_cnt + 1 ;
--
end ;
--
procedure P6
(signal s_st_time_vector : in st_time_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_time_vector_cnt + 1 ;
--
end ;
--
procedure P7
(signal s_st_real_vector : in st_real_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_real_vector_cnt + 1 ;
--
end ;
--
procedure P8
(signal s_st_rec1_vector : in st_rec1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec1_vector_cnt + 1 ;
--
end ;
--
procedure P9
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00616" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00616" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_boolean_vector ,
st_boolean_vector_select ,
s_st_boolean_vector_savt ,
chk_st_boolean_vector ,
s_st_boolean_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb to highb-1) <= transport
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_severity_level_vector ,
st_severity_level_vector_select ,
s_st_severity_level_vector_savt ,
chk_st_severity_level_vector ,
s_st_severity_level_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb to highb-1) <= transport
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG3 :
P3(
s_st_string ,
st_string_select ,
s_st_string_savt ,
chk_st_string ,
s_st_string_cnt ) ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb-1 to highb-1) <= transport
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG4 :
P4(
s_st_enum1_vector ,
st_enum1_vector_select ,
s_st_enum1_vector_savt ,
chk_st_enum1_vector ,
s_st_enum1_vector_cnt ) ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb-1 to highb-1) <= transport
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG5 :
P5(
s_st_integer_vector ,
st_integer_vector_select ,
s_st_integer_vector_savt ,
chk_st_integer_vector ,
s_st_integer_vector_cnt ) ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb to highb-1) <= transport
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG6 :
P6(
s_st_time_vector ,
st_time_vector_select ,
s_st_time_vector_savt ,
chk_st_time_vector ,
s_st_time_vector_cnt ) ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb to highb-1) <= transport
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG7 :
P7(
s_st_real_vector ,
st_real_vector_select ,
s_st_real_vector_savt ,
chk_st_real_vector ,
s_st_real_vector_cnt ) ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb-1 to highb-1) <= transport
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG8 :
P8(
s_st_rec1_vector ,
st_rec1_vector_select ,
s_st_rec1_vector_savt ,
chk_st_rec1_vector ,
s_st_rec1_vector_cnt ) ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb-1 to highb-1) <= transport
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG9 :
P9(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb to highb-1) <= transport
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00616 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00616_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
end ENT00616_Test_Bench ;
--
--
architecture ARCH00616_Test_Bench of ENT00616_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00616 ( ARCH00616 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_time_vector
, s_st_real_vector
, s_st_rec1_vector
, s_st_arr2_vector
)
;
end block L1 ;
end ARCH00616_Test_Bench ;
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