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---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ASCII_BUFFER is
port(
ASCII_DATA : in STD_LOGIC_VECTOR(7 downto 0);
ASCII_RD: in STD_LOGIC;
ASCII_WE: in STD_LOGIC;
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
ASCII_BUFF: out STD_LOGIC_VECTOR(19 downto 0)
);
end ASCII_BUFFER;
architecture dataflow of ASCII_BUFFER is
type StateType is (init, idle, VALID_KEY, SPECIAL_KEY, BACKSPACE, FLUSH);
signal STATE : StateType := init;
type ram_type is array (0 to 5) of STD_LOGIC_VECTOR(3 downto 0);
signal ram_addr : integer range 0 to 5;
signal ram : ram_type;
signal KEY : STD_LOGIC_VECTOR(3 downto 0);
signal INST: STD_LOGIC_VECTOR(19 downto 0) := (OTHERS => '0');
begin
with ASCII_DATA select
KEY <=
x"f" when x"66",
x"e" when x"65",
x"d" when x"64",
x"c" when x"63",
x"b" when x"62",
x"a" when x"61",
x"F" when x"46",
x"E" when x"45",
x"D" when x"44",
x"C" when x"43",
x"B" when x"42",
x"A" when x"41",
x"9" when x"39",
x"8" when x"38",
x"7" when x"37",
x"6" when x"36",
x"5" when x"35",
x"4" when x"34",
x"3" when x"33",
x"2" when x"32",
x"1" when x"31",
x"0" when x"30",
x"0" when OTHERS; -- Null
PROCESS(CLK,RST)
BEGIN
if(RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '1' ) then
case STATE is
when init =>
ASCII_BUFF <= (OTHERS => '0');
ram(0) <= x"0";
ram(1) <= x"0";
ram(2) <= x"0";
ram(3) <= x"0";
ram(4) <= x"0";
ram_addr <= 0;
state <= idle;
when idle =>
ASCII_BUFF <= INST;
if ASCII_RD = '1' and ASCII_WE = '1' then
state <= VALID_KEY;
-- A Valid key was pressed
elsif ASCII_RD = '1' and ASCII_WE = '0' then
state <= SPECIAL_KEY;
--Special key was pressed
else
state <= idle;
end if;
when VALID_KEY =>
if ram_addr < 5 then
ram(ram_addr) <= key;
ram_addr <= ram_addr + 1;
else
ram_addr <= 5;
end if;
state <= idle;
when SPECIAL_KEY =>
if ASCII_DATA = x"0D" then --0D = enterkey
state <= FLUSH;
elsif ASCII_DATA = x"08" then -- 08 = backspace
state <= BACKSPACE;
else
state <= idle;
end if;
when BACKSPACE =>
if ram_addr > 0 then
ram_addr <= ram_addr - 1;
end if;
ram(ram_addr) <= x"0";
state <= idle;
when FLUSH =>
INST <= ram(0) & ram(1) & ram(2) & ram(3) & ram(4);
state <= init;
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
architecture RTL of ENTITY1 is
function FUNC1 (A : in natural) return natural is
variable temp : natural;
begin
temp := A;
while (temp /= 10) loop
temp := temp + 1;
end loop;
while (temp /= 20) loop
temp := temp + 1;
end loop;
while (temp /= 30) loop
temp := temp + 1;
end loop;
return temp;
end function FUNC1;
begin
end architecture RTL;
|
package vunit2 is
type int_ptr is access integer;
type array_of_access is array (natural range <>) of int_ptr;
impure function get_one (idx : natural) return int_ptr;
end package;
package body vunit2 is
shared variable a : array_of_access(1 to 5);
impure function get_one (idx : natural) return int_ptr is
begin
return a(idx);
end function;
end package body;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 04:17:04 AM
-- Design Name:
-- Module Name: spi_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_slave is
Generic (
N : positive := 8;
CPOL : std_logic := '0';
CPHA : std_logic := '0'
);
Port ( clk : in STD_LOGIC;
-- External SPI signals
spi_ss_n : in STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_mosi : in STD_LOGIC;
spi_miso : out STD_LOGIC;
-- Internal data signals
di : out STD_LOGIC_VECTOR (N-1 downto 0); -- Data received from SPI
do : in STD_LOGIC_VECTOR (N-1 downto 0); -- Data to be transmitted over SPI
di_valid : out std_logic; -- High for one clock cycle to indicate a new word is present
do_wren : in std_logic; -- Write a data word to the transmit register
do_wrack : out std_logic); -- High for one clock cycle when the transmission starts.
-- The next data word can be written as soon as this signal goes low.
end spi_slave;
architecture Behavioral of spi_slave is
-- constants to control FlipFlop synthesis
constant CAPTURE_EDGE : std_logic := (CPOL xnor CPHA);
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA);
type spi_state_t is (
IDLE,
INIT_TRANSACTION,
SHIFTING_DATA,
WORD_COMPLETE
);
signal spi_state : spi_state_t := IDLE;
signal spi_state_next : spi_state_t;
signal spi_clk_buf : std_logic := CPOL;
signal spi_capture_edge : std_logic;
signal spi_change_edge : std_logic;
signal di_buf : std_logic;
signal di_reg : std_logic_vector(N-1 downto 0);
signal do_reg : std_logic_vector(N-1 downto 0);
signal do_i : std_logic_vector(N-1 downto 0);
signal bit_counter : integer range 0 to N-1 := 0;
begin
-- state register
process
begin
wait until rising_edge (clk);
if spi_ss_n='1' then
spi_state <= IDLE;
else
spi_state <= spi_state_next;
end if;
end process;
-- Next state logic
process (
spi_state,
spi_ss_n,
bit_counter)
begin
spi_state_next <= spi_state;
case (spi_state) is
when IDLE =>
if spi_ss_n='0' then
spi_state_next <= INIT_TRANSACTION;
end if;
when INIT_TRANSACTION =>
spi_state_next <= SHIFTING_DATA;
when SHIFTING_DATA =>
if bit_counter=N-1 then
spi_state_next <= WORD_COMPLETE;
end if;
when WORD_COMPLETE =>
if bit_counter = 0 then
spi_state_next <= INIT_TRANSACTION;
end if;
when others =>
spi_state_next <= IDLE;
end case;
end process;
-- SPI clock edge detector
process
begin
wait until rising_edge(clk);
spi_clk_buf <= spi_clk;
if (spi_clk_buf= not spi_clk) and spi_clk=CAPTURE_EDGE then
spi_capture_edge <= '1';
else
spi_capture_edge <= '0';
end if;
if (spi_clk_buf= not spi_clk) and spi_clk=CHANGE_EDGE then
spi_change_edge <= '1';
else
spi_change_edge <= '0';
end if;
end process;
-- Input shift register
process
begin
wait until rising_edge(clk);
di_buf <= spi_mosi;
if spi_capture_edge='1' then
di_reg <= di_reg(N-2 downto 0) & di_buf;
bit_counter <= bit_counter + 1;
end if;
end process;
-- output received data word
process
begin
wait until rising_edge(clk);
di_valid <= '0';
if spi_state=WORD_COMPLETE and bit_counter=0 then
di <= di_reg;
di_valid <= '1';
end if;
end process;
-- get data word for tx
process
begin
wait until rising_edge(clk);
if do_wren='1' then
do_i <= do;
end if;
end process;
-- output shift register
process
begin
wait until rising_edge(clk);
do_wrack <= '0';
if spi_state = IDLE then
do_reg <= X"00";
elsif spi_state = INIT_TRANSACTION then
do_reg <= do_i;
do_wrack <= '1';
elsif spi_change_edge='1' and bit_counter /= 0 then
do_reg <= do_reg(N-2 downto 0) & '0';
end if;
end process;
spi_miso <= do_reg(7);
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY noise_tb IS
END noise_tb;
ARCHITECTURE behavior OF noise_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noise
GENERIC(
NOISE : NOISE_TYPE := WHITE
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
--Outputs
signal data : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noise PORT MAP (
clk => clk,
rst => rst,
ce => ce,
data => data
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll50.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.2 Build 602 07/19/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll50 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll50;
ARCHITECTURE SYN OF pll50 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire7 <= sub_wire3(3);
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
c3 <= sub_wire7;
locked <= sub_wire8;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "5000",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 3,
clk2_phase_shift => "0",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 3,
clk3_phase_shift => "4167",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone 10 LP",
lpm_hint => "CBX_MODULE_PREFIX=pll50",
lpm_type => "altpll",
operation_mode => "SOURCE_SYNCHRONOUS",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire8
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "200.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "225.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll50.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "4167"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.cmp TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01200_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of process label: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01200_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_01200_good;
architecture Behavioral of CNE_01200_good is
signal Q : std_logic; -- D Flip-Flop output
begin
--CODE
-- D FlipFlop process
P_FlipFlop:process(i_Clock, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
--CODE
o_Q <= Q;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compar_fsm_tb is
end entity;
architecture behav of compar_fsm_tb is
component compar_fsm is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector(1 downto 0);
--this is pair of bits of two numbers, a0b0, a1b1, etc.., easier to process
o: out std_logic_vector(1 downto 0)
-- 00 is equal, 10 a is bigger, 01 b is bigger
);
end component;
signal clk : std_logic :='1';
signal reset : std_logic :='0';
signal ab, o : std_logic_vector(1 downto 0) :="00";
constant period : time := 20 ns;
begin
mapping: compar_fsm port map (clk=>clk, reset=>reset, ab=>ab, o=>o);
clk_proc: process
begin
clk<=not clk;
wait for period/4;
end process;
stim_proc: process
begin
ab<="00";
wait for period;
ab<="00";
wait for period;
ab<="10";
wait for period;
ab<="01";
wait for period;
ab<="10";
wait for period;
ab<="10";
wait for period;
ab<="10";
wait for period;
ab<="01";
wait for period;
ab<="00";
wait for period;
ab<="00";
wait for period;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Mult_GF_2_M
-- Module Name: Tb_Mult_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests multiplier circuit implementation for a field GF(2^m).
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity tb_mult_gf_2_m is
Generic(
PERIOD : time := 10 ns;
gf_2_m : integer range 1 to 20 := 20;
-- Software --
test_memory_file_gf_2_1 : string := "mceliece/finite_field_tests/mult_gf_2_1.dat";
test_memory_file_gf_2_2 : string := "mceliece/finite_field_tests/mult_gf_2_2_x2_x1_1.dat";
test_memory_file_gf_2_3 : string := "mceliece/finite_field_tests/mult_gf_2_3_x3_x1_1.dat";
test_memory_file_gf_2_4 : string := "mceliece/finite_field_tests/mult_gf_2_4_x4_x1_1.dat";
test_memory_file_gf_2_5 : string := "mceliece/finite_field_tests/mult_gf_2_5_x5_x2_1.dat";
test_memory_file_gf_2_6 : string := "mceliece/finite_field_tests/mult_gf_2_6_x6_x1_1.dat";
test_memory_file_gf_2_7 : string := "mceliece/finite_field_tests/mult_gf_2_7_x7_x1_1.dat";
test_memory_file_gf_2_8 : string := "mceliece/finite_field_tests/mult_gf_2_8_x8_x4_x3_x2_1.dat";
test_memory_file_gf_2_9 : string := "mceliece/finite_field_tests/mult_gf_2_9_x9_x4_1.dat";
test_memory_file_gf_2_10 : string := "mceliece/finite_field_tests/mult_gf_2_10_x10_x3_1.dat";
test_memory_file_gf_2_11 : string := "mceliece/finite_field_tests/mult_gf_2_11_x11_x2_1.dat";
test_memory_file_gf_2_12 : string := "mceliece/finite_field_tests/mult_gf_2_12_x12_x6_x4_x1_1.dat";
test_memory_file_gf_2_13 : string := "mceliece/finite_field_tests/mult_gf_2_13_x13_x4_x3_x1_1.dat";
test_memory_file_gf_2_14 : string := "mceliece/finite_field_tests/mult_gf_2_14_x14_x5_x3_x1_1.dat";
test_memory_file_gf_2_15 : string := "mceliece/finite_field_tests/mult_gf_2_15_x15_x1_1.dat";
test_memory_file_gf_2_16 : string := "mceliece/finite_field_tests/mult_gf_2_16_x16_x5_x3_x2_1.dat";
test_memory_file_gf_2_17 : string := "mceliece/finite_field_tests/mult_gf_2_17_x17_x3_1.dat";
test_memory_file_gf_2_18 : string := "mceliece/finite_field_tests/mult_gf_2_18_x18_x7_1.dat";
test_memory_file_gf_2_19 : string := "mceliece/finite_field_tests/mult_gf_2_19_x19_x5_x2_x1_1.dat";
test_memory_file_gf_2_20 : string := "mceliece/finite_field_tests/mult_gf_2_20_x20_x3_1.dat"
-- IEEE --
-- test_memory_file_gf_2_1 : string := "mceliece/finite_field_tests/mult_gf_2_1.dat";
-- test_memory_file_gf_2_2 : string := "mceliece/finite_field_tests/mult_gf_2_2_x2_x1_1.dat";
-- test_memory_file_gf_2_3 : string := "mceliece/finite_field_tests/mult_gf_2_3_x3_x1_1.dat";
-- test_memory_file_gf_2_4 : string := "mceliece/finite_field_tests/mult_gf_2_4_x4_x1_1.dat";
-- test_memory_file_gf_2_5 : string := "mceliece/finite_field_tests/mult_gf_2_5_x5_x2_1.dat";
-- test_memory_file_gf_2_6 : string := "mceliece/finite_field_tests/mult_gf_2_6_x6_x1_1.dat";
-- test_memory_file_gf_2_7 : string := "mceliece/finite_field_tests/mult_gf_2_7_x7_x1_1.dat";
-- test_memory_file_gf_2_8 : string := "mceliece/finite_field_tests/mult_gf_2_8_x8_x4_x3_x1_1.dat";
-- test_memory_file_gf_2_9 : string := "mceliece/finite_field_tests/mult_gf_2_9_x9_x1_1.dat";
-- test_memory_file_gf_2_10 : string := "mceliece/finite_field_tests/mult_gf_2_10_x10_x3_1.dat";
-- test_memory_file_gf_2_11 : string := "mceliece/finite_field_tests/mult_gf_2_11_x11_x2_1.dat";
-- test_memory_file_gf_2_12 : string := "mceliece/finite_field_tests/mult_gf_2_12_x12_x3_1.dat";
-- test_memory_file_gf_2_13 : string := "mceliece/finite_field_tests/mult_gf_2_13_x13_x4_x3_x1_1.dat";
-- test_memory_file_gf_2_14 : string := "mceliece/finite_field_tests/mult_gf_2_14_x14_x5_1.dat";
-- test_memory_file_gf_2_15 : string := "mceliece/finite_field_tests/mult_gf_2_15_x15_x1_1.dat";
-- test_memory_file_gf_2_16 : string := "mceliece/finite_field_tests/mult_gf_2_16_x16_x5_x3_x1_1.dat";
-- test_memory_file_gf_2_17 : string := "mceliece/finite_field_tests/mult_gf_2_17_x17_x3_1.dat";
-- test_memory_file_gf_2_18 : string := "mceliece/finite_field_tests/mult_gf_2_18_x18_x3_1.dat";
-- test_memory_file_gf_2_19 : string := "mceliece/finite_field_tests/mult_gf_2_19_x19_x5_x2_x1_1.dat";
-- test_memory_file_gf_2_20 : string := "mceliece/finite_field_tests/mult_gf_2_20_x20_x3_1.dat"
);
end tb_mult_gf_2_m;
architecture Behavioral of tb_mult_gf_2_m is
component mult_gf_2_m is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal test_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal error : STD_LOGIC := '0';
signal clk : STD_LOGIC := '1';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : mult_gf_2_m
Generic Map(gf_2_m => gf_2_m)
Port Map(
a => test_a,
b => test_b,
o => test_o
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
FILE ram_file : text;
variable line_n : line;
variable number_of_tests : integer;
variable read_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
variable read_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
variable read_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
case gf_2_m is
when 1 => file_open(ram_file, test_memory_file_gf_2_1, READ_MODE);
when 2 => file_open(ram_file, test_memory_file_gf_2_2, READ_MODE);
when 3 => file_open(ram_file, test_memory_file_gf_2_3, READ_MODE);
when 4 => file_open(ram_file, test_memory_file_gf_2_4, READ_MODE);
when 5 => file_open(ram_file, test_memory_file_gf_2_5, READ_MODE);
when 6 => file_open(ram_file, test_memory_file_gf_2_6, READ_MODE);
when 7 => file_open(ram_file, test_memory_file_gf_2_7, READ_MODE);
when 8 => file_open(ram_file, test_memory_file_gf_2_8, READ_MODE);
when 9 => file_open(ram_file, test_memory_file_gf_2_9, READ_MODE);
when 10 => file_open(ram_file, test_memory_file_gf_2_10, READ_MODE);
when 11 => file_open(ram_file, test_memory_file_gf_2_11, READ_MODE);
when 12 => file_open(ram_file, test_memory_file_gf_2_12, READ_MODE);
when 13 => file_open(ram_file, test_memory_file_gf_2_13, READ_MODE);
when 14 => file_open(ram_file, test_memory_file_gf_2_14, READ_MODE);
when 15 => file_open(ram_file, test_memory_file_gf_2_15, READ_MODE);
when 16 => file_open(ram_file, test_memory_file_gf_2_16, READ_MODE);
when 17 => file_open(ram_file, test_memory_file_gf_2_17, READ_MODE);
when 18 => file_open(ram_file, test_memory_file_gf_2_18, READ_MODE);
when 19 => file_open(ram_file, test_memory_file_gf_2_19, READ_MODE);
when 20 => file_open(ram_file, test_memory_file_gf_2_20, READ_MODE);
end case;
readline (ram_file, line_n);
read (line_n, number_of_tests);
wait for PERIOD;
for I in 1 to number_of_tests loop
error <= '0';
readline (ram_file, line_n);
read (line_n, read_a);
readline (ram_file, line_n);
read (line_n, read_b);
readline (ram_file, line_n);
read (line_n, read_o);
test_a <= read_a;
test_b <= read_b;
true_o <= read_o;
wait for PERIOD;
if (true_o = test_o) then
error <= '0';
else
error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error <= '0';
wait for PERIOD;
end loop;
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic--;
----debug
-- state_out : out std_logic_vector(7 downto 0);
-- input_sample_0 : out std_logic_vector(7 downto 0);
-- input_sample_1 : out std_logic_vector(7 downto 0);
-- input_sample_2 : out std_logic_vector(7 downto 0);
-- input_sample_3 : out std_logic_vector(7 downto 0);
-- input_sample_4 : out std_logic_vector(7 downto 0);
-- input_sample_5 : out std_logic_vector(7 downto 0);
-- input_sample_6 : out std_logic_vector(7 downto 0);
-- input_sample_7 : out std_logic_vector(7 downto 0);
-- input_sample_8 : out std_logic_vector(7 downto 0);
-- input_sample_9 : out std_logic_vector(7 downto 0);
-- input_sample_A : out std_logic_vector(7 downto 0);
-- input_sample_B : out std_logic_vector(7 downto 0);
-- input_sample_C : out std_logic_vector(7 downto 0);
-- input_sample_D : out std_logic_vector(7 downto 0);
-- input_sample_E : out std_logic_vector(7 downto 0);
-- input_sample_F : out std_logic_vector(7 downto 0);
-- qp_out : out std_logic_vector(7 downto 0);
-- zigzag_0 : out std_logic_vector(7 downto 0);
-- zigzag_1 : out std_logic_vector(7 downto 0);
-- zigzag_2 : out std_logic_vector(7 downto 0);
-- zigzag_3 : out std_logic_vector(7 downto 0);
-- zigzag_4 : out std_logic_vector(7 downto 0);
-- zigzag_5 : out std_logic_vector(7 downto 0);
-- zigzag_6 : out std_logic_vector(7 downto 0);
-- zigzag_7 : out std_logic_vector(7 downto 0);
-- zigzag_8 : out std_logic_vector(7 downto 0);
-- zigzag_9 : out std_logic_vector(7 downto 0);
-- zigzag_A : out std_logic_vector(7 downto 0);
-- zigzag_B : out std_logic_vector(7 downto 0);
-- zigzag_C : out std_logic_vector(7 downto 0);
-- zigzag_D : out std_logic_vector(7 downto 0);
-- zigzag_E : out std_logic_vector(7 downto 0);
-- zigzag_F : out std_logic_vector(7 downto 0);
-- dequant_0 : out std_logic_vector(15 downto 0);
-- dequant_1 : out std_logic_vector(15 downto 0);
-- dequant_2 : out std_logic_vector(15 downto 0);
-- dequant_3 : out std_logic_vector(15 downto 0);
-- dequant_4 : out std_logic_vector(15 downto 0);
-- dequant_5 : out std_logic_vector(15 downto 0);
-- dequant_6 : out std_logic_vector(15 downto 0);
-- dequant_7 : out std_logic_vector(15 downto 0);
-- dequant_8 : out std_logic_vector(15 downto 0);
-- dequant_9 : out std_logic_vector(15 downto 0);
-- dequant_A : out std_logic_vector(15 downto 0);
-- dequant_B : out std_logic_vector(15 downto 0);
-- dequant_C : out std_logic_vector(15 downto 0);
-- dequant_D : out std_logic_vector(15 downto 0);
-- dequant_E : out std_logic_vector(15 downto 0);
-- dequant_F : out std_logic_vector(15 downto 0);
-- result_0 : out std_logic_vector(7 downto 0);
-- result_1 : out std_logic_vector(7 downto 0);
-- result_2 : out std_logic_vector(7 downto 0);
-- result_3 : out std_logic_vector(7 downto 0);
-- result_4 : out std_logic_vector(7 downto 0);
-- result_5 : out std_logic_vector(7 downto 0);
-- result_6 : out std_logic_vector(7 downto 0);
-- result_7 : out std_logic_vector(7 downto 0);
-- result_8 : out std_logic_vector(7 downto 0);
-- result_9 : out std_logic_vector(7 downto 0);
-- result_A : out std_logic_vector(7 downto 0);
-- result_B : out std_logic_vector(7 downto 0);
-- result_C : out std_logic_vector(7 downto 0);
-- result_D : out std_logic_vector(7 downto 0);
-- result_E : out std_logic_vector(7 downto 0);
-- result_F : out std_logic_vector(7 downto 0)
);
end entity iqit_node;
architecture fsmd of iqit_node is
--- COMPONENTS ------------------------------------------------------------
component zigzag is
generic(
sample_width : integer := 8
);
port(
x : in std_logic_vector((16*sample_width)-1 downto 0);
y : out std_logic_vector((16*sample_width)-1 downto 0)
);
end component zigzag;
component inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end component inverse_quant;
component inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto 0);
inv_transform_block : out std_logic_vector((16*out_sample_width)-1 downto 0);
sign_mask : out std_logic_vector(15 downto 0)
);
end component inverse_transform;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- TYPES -----------------------------------------------------------------
type iqit_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_row_4_3,
rx_row_4_3,
dequeue_row_4_3,
wait_row_2_1,
rx_row_2_1,
dequeue_row_2_1,
wait_tx_header,
tx_header,
wait_tx_row_4_3,
tx_row_4_3,
wait_tx_row_2_1,
tx_row_2_1
);
--- SIGNALS ---------------------------------------------------------------
signal state : iqit_states;
signal next_state : iqit_states;
signal quant_param_d : std_logic_vector(qp_width-1 downto 0);
signal quant_param_q : std_logic_vector(qp_width-1 downto 0);
signal without_dc_d : std_logic_vector(wo_dc_width-1 downto 0);
signal without_dc_q : std_logic_vector(wo_dc_width-1 downto 0);
signal identifier_d : std_logic_vector(7 downto 0);
signal identifier_q : std_logic_vector(7 downto 0);
signal input_samples_d : std_logic_vector((16*sample_width)-1 downto 0);
signal input_samples_q : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_zigzag : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_inv_q : std_logic_vector((16*2*sample_width)-1 downto 0);
signal inv_t_input : std_logic_vector((16*2*sample_width)-1 downto 0);
signal result_samples : std_logic_vector((16*sample_width)-1 downto 0);
signal tx_header_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_4_3_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_2_1_data : std_logic_vector(data_width-1 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal dc_high_byte_q : std_logic_vector(7 downto 0);
signal dc_high_byte_d : std_logic_vector(7 downto 0);
signal sign_mask : std_logic_vector(15 downto 0);
signal x_pass_thru_d : std_logic_vector(10 downto 0);
signal y_pass_thru_d : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_d : std_logic_vector(1 downto 0);
signal x_pass_thru_q : std_logic_vector(10 downto 0);
signal y_pass_thru_q : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_q : std_logic_vector(1 downto 0);
constant do_iqit_cmd : std_logic_vector(7 downto 0) := x"03";
begin
--- DATAPATH --------------------------------------------------------------
u0: component zigzag
generic map(
sample_width => sample_width
)
port map(
x => input_samples_q,
y => samples_after_zigzag
);
u1: component inverse_quant
generic map(
in_sample_width => sample_width,
out_sample_width => 2*sample_width,
qp_width => qp_width,
wo_dc_width => wo_dc_width
)
port map(
quantized_samples => samples_after_zigzag,
quant_param => quant_param_q,
without_dc => without_dc_q,
dequant_samples => samples_after_inv_q
);
u2: component inverse_transform
generic map(
in_sample_width => 2*sample_width,
out_sample_width => sample_width
)
port map(
transform_block => inv_t_input,
inv_transform_block => result_samples,
sign_mask => sign_mask
);
u3: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--register process
process(clk, rst) begin
if rst = '1' then
state <= idle;
quant_param_q <= (others => '0');
without_dc_q <= (others => '0');
identifier_q <= (others => '0');
input_samples_q <= (others => '0');
sel_vc_q <= (others => '0');
dc_high_byte_q <= (others => '0');
x_pass_thru_q <= (others => '0');
y_pass_thru_q <= (others => '0');
LCbCr_pass_thru_q <= (others => '0');
elsif rising_edge(clk) then
state <= next_state;
quant_param_q <= quant_param_d;
without_dc_q <= without_dc_d;
identifier_q <= identifier_d;
input_samples_q <= input_samples_d;
sel_vc_q <= sel_vc_d;
dc_high_byte_q <= dc_high_byte_d;
x_pass_thru_q <= x_pass_thru_d;
y_pass_thru_q <= y_pass_thru_d;
LCbCr_pass_thru_q <= LCbCr_pass_thru_d;
end if;
end process;
--insert high byte of dc into signal if non-zero
inv_t_input <= samples_after_inv_q(16*2*sample_width-1 downto sample_width*2) & dc_high_byte_q & samples_after_inv_q(sample_width-1 downto 0) when or_reduce(dc_high_byte_q) = '1' else
samples_after_inv_q;
--parse packet
quant_param_d <= recv_data(47 downto 40) when state = rx_header else quant_param_q;
without_dc_d <= recv_data(39 downto 32) when state = rx_header else without_dc_q;
identifier_d <= recv_data(7 downto 0) when state = rx_header else identifier_q;
dc_high_byte_d <= recv_data(55 downto 48) when state = rx_header else dc_high_byte_q;
x_pass_thru_d <= recv_data(18 downto 8) when state = rx_header else x_pass_thru_q;
y_pass_thru_d <= recv_data(29 downto 19) when state = rx_header else y_pass_thru_q;
LCbCr_pass_thru_d <= recv_data(31 downto 30) when state = rx_header else LCbCr_pass_thru_q;
input_samples_d((16*sample_width)-1 downto (8*sample_width)) <= recv_data when state = rx_row_4_3 else
input_samples_q((16*sample_width)-1 downto (8*sample_width));
input_samples_d((8*sample_width)-1 downto 0) <= recv_data when state = rx_row_2_1 else
input_samples_q((8*sample_width)-1 downto 0);
-- format repsonse packet
tx_header_data <= x_pass_thru_q & "00000" &sign_mask& "000" & LCbCr_pass_thru_q & y_pass_thru_q &do_iqit_cmd&identifier_q;
tx_row_4_3_data <= result_samples((16*sample_width)-1 downto (8*sample_width));
tx_row_2_1_data <= result_samples((8*sample_width)-1 downto 0) ;
-- channel selection logic
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_header or state = dequeue_row_4_3 or state = dequeue_row_2_1 else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
--packet generation
send_data <= tx_header_data when state = wait_tx_header or state = tx_header else
tx_row_4_3_data when state = wait_tx_row_4_3 or state = tx_row_4_3 else
tx_row_2_1_data when state = wait_tx_row_2_1 or state = tx_row_2_1 else
std_logic_vector(to_unsigned(0, data_width));
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_row_2_1 or state = tx_row_2_1 else '0';
send_flit <= '1' when state = tx_header or state = tx_row_4_3 or state = tx_row_2_1 else '0';
-- STATE MACHINE ----------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state; --default behaviour
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_row_4_3;
end if;
if state = wait_row_4_3 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_4_3;
end if;
if state = rx_row_4_3 then
next_state <= dequeue_row_4_3;
end if;
if state = dequeue_row_4_3 then
next_state <= wait_row_2_1;
end if;
if state = wait_row_2_1 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_2_1;
end if;
if state = rx_row_2_1 then
next_state <= dequeue_row_2_1;
end if;
if state = dequeue_row_2_1 then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_row_4_3;
end if;
if state = wait_tx_row_4_3 and ready_to_send = '1' then
next_state <= tx_row_4_3;
end if;
if state = tx_row_4_3 then
next_state <= wait_tx_row_2_1;
end if;
if state = wait_tx_row_2_1 and ready_to_send = '1' then
next_state <= tx_row_2_1;
end if;
if state = tx_row_2_1 then
next_state <= idle;
end if;
end process;
end architecture fsmd; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSCTANS.ALL;
entity KITT is
port (
CLK : in std_logic;
RESET : in std_logic;
LEDS : out std_logic_vector (7 downto 0)
);
end KITT;
architecture KITT_BODY of KITT is
signal CNT_OUT : std_logic_vector (OUTPUT_WIDTH - 1 downto 0);
signal UP, TOP, BOTTOM : std_logic;
component CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end component;
component COUNTER is
port (
CLK : in std_logic;
RESET : in std_logic;
UP : in std_logic;
CNT_OUT : out std_logic_vector (OUTPUT_WIDTH - 1 downto 0);
TOP : out std_logic;
BOTTOM : out std_logic
);
end component;
component DECODER is
port (
BIN_VALUE : in std_logic_vector (2 downto 0);
ONE_HOT : out std_logic_vector (7 downto 0)
);
end component;
begin
RADIC : CONTROLLER port map ( CLK => CLK, RESET => RESET, UP => UP, TOP => TOP, BOTTOM => BOTTOM );
CITAC : COUNTER port map ( CLK => CLK, RESET => RESET, UP => UP, CNT_OUT => CNT_OUT, TOP => TOP, BOTTOM => BOTTOM );
DEKODER : DECODER port map ( BIN_VALUE => CNT_OUT, ONE_HOT => LEDS);
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.2 2004/11/10 09:54:10 wig Exp $
-- $Date: 2004/11/10 09:54:10 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.2 2004/11/10 09:54:10 wig
-- testcase extended
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.46 2004/08/18 10:45:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_ab_e
width : integer := 8
-- End of Generated Generics for Entity inst_ab_e
);
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ab_e
y_p0_i : in std_ulogic_vector(width - 1 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_k3_k4_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_shadow_k3_k4_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_k3_k4_e
--
entity inst_shadow_k3_k4_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_k3_k4_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_k3_k4_e
end inst_shadow_k3_k4_e;
--
-- End of Generated Entity inst_shadow_k3_k4_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
-- $Id: tb_nexys3_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.1 use simbididly
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
-- Alias of enum in another package
--
package pack1 is
type t is (foo, bar, baz);
end package;
use work.pack1.all;
package pack2 is
alias t is work.pack1.t; -- OK
end package;
use work.pack2.all;
package pack3 is
constant c1 : t := foo; -- OK
end package;
use work.pack1.all;
use work.pack2.all;
package pack4 is
constant c2 : t := bar; -- OK
constant c3 : integer := foo; -- Error
end package;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_wait_2.c
-- reg2 = * mutex
-- reg3 = * cond
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
-- hthread_mutex_lock( data->mutex );
when STATE_4 =>
reg6_next <= intrfc2thrd_value;
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread, NULL, data->function, (void *) data );
when STATE_6 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- retVal = hthread_cond_wait( data->cond, data->mutex );
when STATE_11 =>
-- Puth data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- Puth data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_cond_wait
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_14 =>
retVal_next <= intrfc2thrd_value;
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_16;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_16 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
when STATE_20 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net5
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net6
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net7
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net9
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net10,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net10
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
|
-- #################################################################################################
-- # << NEO430 - 32-bit Wishbone Bus Interface Adapter >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_wb_interface is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- wishbone interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic -- transfer acknowledge
);
end neo430_wb_interface;
architecture neo430_wb_interface_rtl of neo430_wb_interface is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(wb32_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_byte_en0_c : natural := 0; -- -/w: wishbone data byte enable bit 0
constant ctrl_byte_en1_c : natural := 1; -- -/w: wishbone data byte enable bit 1
constant ctrl_byte_en2_c : natural := 2; -- -/w: wishbone data byte enable bit 2
constant ctrl_byte_en3_c : natural := 3; -- -/w: wishbone data byte enable bit 3
constant ctrl_pending_c : natural := 15; -- r/-: pending wb transfer
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic;
-- accessible regs --
signal wb_addr : std_ulogic_vector(31 downto 0);
signal wb_rdata : std_ulogic_vector(31 downto 0);
signal wb_wdata : std_ulogic_vector(31 downto 0);
signal pending : std_ulogic; -- pending transfer?
signal byte_en : std_ulogic_vector(03 downto 0);
-- misc --
signal enable : std_ulogic;
begin
-- Access control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wb32_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= wb32_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then -- valid word write
if (addr = wb32_rd_adr_lo_addr_c) then
wb_addr(15 downto 0) <= data_i;
wb_we_o <= '0';
end if;
if (addr = wb32_rd_adr_hi_addr_c) then
wb_addr(31 downto 16) <= data_i;
wb_we_o <= '0';
end if;
if (addr = wb32_wr_adr_lo_addr_c) then
wb_addr(15 downto 0) <= data_i;
wb_we_o <= '1';
end if;
if (addr = wb32_wr_adr_hi_addr_c) then
wb_addr(31 downto 16) <= data_i;
wb_we_o <= '1';
end if;
if (addr = wb32_data_lo_addr_c) then
wb_wdata(15 downto 0) <= data_i;
end if;
if (addr = wb32_data_hi_addr_c) then
wb_wdata(31 downto 16) <= data_i;
end if;
if (addr = wb32_ctrl_addr_c) then
byte_en(0) <= data_i(ctrl_byte_en0_c);
byte_en(1) <= data_i(ctrl_byte_en1_c);
byte_en(2) <= data_i(ctrl_byte_en2_c);
byte_en(3) <= data_i(ctrl_byte_en3_c);
end if;
end if;
end if;
end process wr_access;
-- direct output --
wb_adr_o <= wb_addr; -- address
wb_dat_o <= wb_wdata; -- write data
wb_sel_o <= byte_en; -- byte enable
-- Access arbiter -------------------------------------------------------------
-- -----------------------------------------------------------------------------
arbiter: process(clk_i)
begin
if rising_edge(clk_i) then
-- trigger transfer --
if (pending = '0') or (enable = '0') then
wb_stb_o <= '0';
pending <= '0';
if (wr_en = '1') and (enable = '1') and ((addr_i = wb32_rd_adr_hi_addr_c) or (addr_i = wb32_wr_adr_hi_addr_c)) then
wb_stb_o <= '1';
pending <= '1';
end if;
else -- transfer in progress
wb_stb_o <= '0'; -- use ONLY standard/classic cycle with single-cycle STB assertion!!
-- waiting for ACK
if (wb_ack_i = '1') then
wb_rdata <= wb_dat_i; -- sample input data
wb_stb_o <= '0';
pending <= '0';
end if;
end if;
end if;
end process arbiter;
-- device actually in use? --
enable <= or_all_f(byte_en);
-- valid cycle signal --
wb_cyc_o <= pending;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden_i = '1') and (acc_en = '1') then
if (addr = wb32_data_lo_addr_c) then
data_o <= wb_rdata(15 downto 00);
elsif (addr = wb32_data_hi_addr_c) then
data_o <= wb_rdata(31 downto 16);
else -- when wb32_ctrl_addr_c =>
data_o(ctrl_pending_c) <= pending;
end if;
end if;
end if;
end process rd_access;
end neo430_wb_interface_rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00525ent IS
END c03s03b00x00p03n04i00525ent;
ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
BEGIN
TESTING : PROCESS
type bit_ptr is access bit;
variable v_bit_ptr1: bit_ptr := new bit'('1');
variable v_bit_ptr2: bit_ptr;
variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
variable v_bit_ptr4: bit_ptr := new bit'('0');
variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bit_ptr1.all = '1';
if (v_bit_ptr1.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr2 = null;
if (v_bit_ptr2 = null) then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr3.all = '1';
if (v_bit_ptr3.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr4.all = '0';
if (v_bit_ptr4.all = '0') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr5.all = '0';
if (v_bit_ptr5.all = '0') then
OKtest := OKtest + 1;
end if;
v_bit_ptr2 := new bit'('0');
assert v_bit_ptr2.all = '0';
if (v_bit_ptr2.all = '0') then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
OKtest := OKtest + 1;
end if;
deallocate(v_bit_ptr1);
deallocate(v_bit_ptr2);
deallocate(v_bit_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00525"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00525arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00525ent IS
END c03s03b00x00p03n04i00525ent;
ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
BEGIN
TESTING : PROCESS
type bit_ptr is access bit;
variable v_bit_ptr1: bit_ptr := new bit'('1');
variable v_bit_ptr2: bit_ptr;
variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
variable v_bit_ptr4: bit_ptr := new bit'('0');
variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bit_ptr1.all = '1';
if (v_bit_ptr1.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr2 = null;
if (v_bit_ptr2 = null) then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr3.all = '1';
if (v_bit_ptr3.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr4.all = '0';
if (v_bit_ptr4.all = '0') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr5.all = '0';
if (v_bit_ptr5.all = '0') then
OKtest := OKtest + 1;
end if;
v_bit_ptr2 := new bit'('0');
assert v_bit_ptr2.all = '0';
if (v_bit_ptr2.all = '0') then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
OKtest := OKtest + 1;
end if;
deallocate(v_bit_ptr1);
deallocate(v_bit_ptr2);
deallocate(v_bit_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00525"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00525arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00525ent IS
END c03s03b00x00p03n04i00525ent;
ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
BEGIN
TESTING : PROCESS
type bit_ptr is access bit;
variable v_bit_ptr1: bit_ptr := new bit'('1');
variable v_bit_ptr2: bit_ptr;
variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
variable v_bit_ptr4: bit_ptr := new bit'('0');
variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bit_ptr1.all = '1';
if (v_bit_ptr1.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr2 = null;
if (v_bit_ptr2 = null) then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr3.all = '1';
if (v_bit_ptr3.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr4.all = '0';
if (v_bit_ptr4.all = '0') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr5.all = '0';
if (v_bit_ptr5.all = '0') then
OKtest := OKtest + 1;
end if;
v_bit_ptr2 := new bit'('0');
assert v_bit_ptr2.all = '0';
if (v_bit_ptr2.all = '0') then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
OKtest := OKtest + 1;
end if;
deallocate(v_bit_ptr1);
deallocate(v_bit_ptr2);
deallocate(v_bit_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00525"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00525arch;
|
entity hello_world is
end ;
architecture hello_world of hello_world is
begin
stimulus : PROCESS
begin
assert false report "Hello, world!"
severity note ;
wait ;
end PROCESS stimulus ;
end hello_world ;
|
entity hello_world is
end ;
architecture hello_world of hello_world is
begin
stimulus : PROCESS
begin
assert false report "Hello, world!"
severity note ;
wait ;
end PROCESS stimulus ;
end hello_world ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Mq15Uxvq8TpovK0VHOjVIqcterdGjGw0vXf5/CcRbJy8DxHeaX/7+OLue1eHm86CijvgGESbBACz
JkIFLWfF6A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
nlGlmlWgx2dcArT+YjNR03+AI8xDpAJqs3PUH0dGTVPNy+2me3I6K3/Y+0PUOBmo6ENPSimUygAZ
ksy+UgkArErykALj4Yj+1tAP4lzB6LHa6T1YjcCqfl+YO4Vtv7pKTgHSvlFceVOmrabtv0zQJ3EP
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6144)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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2rFmwuNLMhiGCfqe/aSSSir0MA5TrcQj7WKMfg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6144)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
icc: out STD_LOGIC_VECTOR(3 downto 0);
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
--signal PSRegister: std_logic_vector(4 downto 0):=(others=>'0');
begin
process(NZVC,nCWP,CLK,rst)
begin
if rst='1' then
--PSRegister<=(others=>'0');
C<='0';
CWP<='0';
icc<=(others=>'0');
elsif rising_edge(CLK) then
--if not(NZVC="1111") then
--PSRegister(4 downto 1)<=NZVC;
--end if;
--PSRegister(0)<=nCWP;
--CWP<=PSRegister(0);
CWP<=nCWP;
--C<=PSRegister(1);
C<=NZVC(0);
--icc<=PSRegister(4 downto 1);
icc<=NZVC;
end if;
end process;
end Behavioral;
|
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
-- Violations below
architecture RTL of FIFO is
begin
process
begin
a := b;
a := b;
x := z when b = 0 else y;
x := z when b = 0 else y;
with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: testmem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY testmem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END testmem_exdes;
ARCHITECTURE xilinx OF testmem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT testmem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : testmem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_sound2 is
generic(
ADDR_WIDTH: integer := 4
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(5 downto 0)
);
end test_sound2;
architecture content of test_sound2 is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(5 downto 0);
constant TEST: tune :=
(
"111001",
"001001",
"110001",
"001001",
"101001",
"001001",
"100001",
"001001",
"011001",
"001001",
"010001",
"001001",
"001001",
"001001",
"000000",
"000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity GPIO is
generic (BitWidth: integer);
port ( IO_sel: in std_logic;
IO: inout std_logic_vector (BitWidth-1 downto 0);
WrtData: in std_logic_vector (BitWidth-1 downto 0);
RdData: out std_logic_vector (BitWidth-1 downto 0)
);
end GPIO;
architecture behavioral of GPIO is
begin
process(IO_sel, IO, WrtData)begin
if IO_sel = '0' then
IO <= (others => 'Z');
RdData <= IO;
else
IO <= WrtData;
end if;
end process;
end behavioral;
|
--------------------------------------------------------------------------------------------------
-- Multi-channel FIR Filter Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.dsp_pkg.all;
use work.tb_write_csv_pkg.all;
use work.multichannel_fir_filter_pkg.all;
--This module is a test-bench for simulating the multichannel fir filter
entity tb_multichannel_fir_filter is
end tb_multichannel_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_multichannel_fir_filter is
constant INPUT_FILE1 : string
:= "X:\Education\Masters Thesis\matlab\multichannel\chirp_s2f.csv";
constant TEST_FILTER1 : coefficient_array := LOW_PASS_101;
constant OUTPUT_FILE1 : string
:= "X:\Education\Masters Thesis\matlab\multichannel\chirp_lowpass101.csv";
constant INPUT_FILE2 : string
:= "X:\Education\Masters Thesis\matlab\multichannel\chirp_f2s.csv";
constant TEST_FILTER2 : coefficient_array := HIGH_PASS_101;
constant OUTPUT_FILE2 : string
:= "X:\Education\Masters Thesis\matlab\multichannel\chirp_highpass101.csv";
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal clk_2x : std_logic := '0';
signal sig1 : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0');
signal sig2 : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0');
signal filtered1 : fir_sig := (others => '0');
signal filtered2 : fir_sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Instantiate 2x clock generator
clk2 : tb_clockgen
generic map(PERIOD => 5ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_2x);
--Instantiate file reader
reader1 : tb_read_csv
generic map(FILENAME => INPUT_FILE1)
port map( clk => clk,
data => sig1);
--Instantiate file reader
reader2 : tb_read_csv
generic map(FILENAME => INPUT_FILE2)
port map( clk => clk,
data => sig2);
--Instantiate unit under test
uut : entity work.multichannel_fir_filter(behave)
generic map(h0 => TEST_FILTER1,
h1 => TEST_FILTER2)
port map( clk => clk,
clk_2x => clk_2x,
rst => rst,
x1 => signed(sig1),
x2 => signed(sig2),
y1 => filtered1,
y2 => filtered2);
--Instantiate a file writer
writer1 : tb_write_csv
generic map(FILENAME => OUTPUT_FILE1)
port map( clk => clk,
data => std_logic_vector(filtered1(30 downto 15)));
--Instantiate a file writer
writer2 : tb_write_csv
generic map(FILENAME => OUTPUT_FILE2)
port map( clk => clk,
data => std_logic_vector(filtered2(30 downto 15)));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 12ns;
rst <= '0';
wait;
end process;
end sim;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:42 03/05/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet/rx_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SMI_RXTX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY rx_test IS
END rx_test;
ARCHITECTURE behavior OF rx_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SMI_RXTX
PORT(
data_in : IN std_logic_vector(15 downto 0);
data_out : OUT std_logic_vector(15 downto 0);
phy_addr : IN std_logic_vector(4 downto 0);
reg_addr : IN std_logic_vector(4 downto 0);
write_read : IN std_logic;
strt : IN std_logic;
busy : OUT std_logic;
reset : IN std_logic;
clk : IN std_logic;
clk_div : IN std_logic;
MDC : OUT std_logic;
MDIO : INOUT std_logic
);
END COMPONENT;
--Inputs
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal phy_addr : std_logic_vector(4 downto 0) := (others => '0');
signal reg_addr : std_logic_vector(4 downto 0) := (others => '0');
signal write_read : std_logic := '0';
signal strt : std_logic := '0';
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal clk_div : std_logic := '0';
--BiDirs
signal MDIO : std_logic;
--Outputs
signal data_out : std_logic_vector(15 downto 0);
signal busy : std_logic;
signal MDC : std_logic;
-- Clock period definitions
constant clk_period : time := 40 ns;
constant clk_div_period : time := 400 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SMI_RXTX PORT MAP (
data_in => data_in,
data_out => data_out,
phy_addr => phy_addr,
reg_addr => reg_addr,
write_read => write_read,
strt => strt,
busy => busy,
reset => reset,
clk => clk,
clk_div => clk_div,
MDC => MDC,
MDIO => MDIO
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
clk_div_process :process
begin
clk_div <= '0';
wait for clk_div_period/2;
clk_div <= '1';
wait for clk_div_period/2;
end process;
-- write_read <= '1' after 35 ns;
-- phy_addr <= "11001" after 35 ns;
-- reg_addr <= "11001" after 35 ns;
-- data_in <= "1111000011110000" after 35 ns;
-- strt <= '1' after 67 ns, '0' after 107 ns;
write_read <= '0' after 35 ns;
phy_addr <= "11001" after 35 ns;
reg_addr <= "11001" after 35 ns;
strt <= '1' after 67 ns, '0' after 107 ns;
MDIO <= 'Z', '1' after 19710 ns, '0' after 21310 ns, '1' after 22910 ns, '0' after 24510 ns, 'Z' after 26110 ns;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:09:11 09/11/2011
-- Design Name:
-- Module Name: deconcat3b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity deconcat3b is
Port ( sig : in STD_LOGIC_VECTOR (2 downto 0);
A2 : out STD_LOGIC;
A1 : out STD_LOGIC;
A0 : out STD_LOGIC);
end deconcat3b;
architecture Behavioral of deconcat3b is
begin
A0 <= sig(0);
A1 <= sig(1);
A2 <= sig(2);
end Behavioral;
|
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPTimeCodeControl is
port (
clock : in std_logic;
reset : in std_logic;
receiveClock : in std_logic;
gotTimeCode : in std_logic;
receiveTimeCodeOut : in std_logic_vector(7 downto 0);
timeOut : out std_logic_vector(5 downto 0);
controlFlagsOut : out std_logic_vector(1 downto 0);
tickOut : out std_logic
);
end SpaceWireCODECIPTimeCodeControl;
architecture Behavioral of SpaceWireCODECIPTimeCodeControl is
component SpaceWireCODECIPSynchronizeOnePulse is
port (
clock : in std_logic;
asynchronousClock : in std_logic;
reset : in std_logic;
asynchronousIn : in std_logic;
synchronizedOut : out std_logic
);
end component;
signal iReceiveTimeCodeOutRegister : std_logic_vector (7 downto 0);
signal iControlFlags : std_logic_vector(1 downto 0);
signal iReceiveTimeCode : std_logic_vector(5 downto 0);
signal iReceiveTimeCodePlus1 : std_logic_vector(5 downto 0);
signal iTickOutSignal : std_logic;
signal gotTimeCodeSynchronized : std_logic;
begin
timeOut <= iReceiveTimeCode;
controlFlagsOut <= iControlFlags;
tickOut <= iTickOutSignal;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.12 System time distribution (normative)
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes
-- The new time should be one more than the time-counter's previous
-- time-value.
----------------------------------------------------------------------
process (clock, reset)
begin
if (reset = '1') then
iReceiveTimeCode <= (others => '0');
iReceiveTimeCodePlus1 <= "000001";
iTickOutSignal <= '0';
iControlFlags <= "00";
iReceiveTimeCodeOutRegister <= (others => '0');
else
if (clock'event and clock = '1') then
if (gotTimeCodeSynchronized = '1') then
iControlFlags <= iReceiveTimeCodeOutRegister (7 downto 6);
iReceiveTimeCode <= iReceiveTimeCodeOutRegister (5 downto 0);
iReceiveTimeCodePlus1 <= iReceiveTimeCodeOutRegister (5 downto 0) + 1;
if (iReceiveTimeCodePlus1 = iReceiveTimeCodeOutRegister (5 downto 0)) then
iTickOutSignal <= '1';
end if;
else
iTickOutSignal <= '0';
end if;
iReceiveTimeCodeOutRegister <= receiveTimeCodeOut;
end if;
end if;
end process;
timeCodePulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotTimeCode,
synchronizedOut => gotTimeCodeSynchronized
);
end Behavioral;
|
library ieee;
--library vunit_lib;
--context vunit_lib.vunit_context;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_counter is
generic (runner_cfg : string);
end tb_counter;
architecture arch_tb_counter of tb_counter is
component counter is
port (
key0: in std_logic;
key3: in std_logic;
counter_out: out std_logic_vector(3 downto 0)
);
end component;
signal key0, key3: std_logic;
signal counter_out: std_logic_vector(3 downto 0);
function trigger_rising() return std_logic_vector is
begin
key0 <= '0';
wait for 1 ns;
key0 <= '1';
wait for 1 ns;
end;
begin
uut: counter port map(
key0 => key0,
key3 => key3,
counter_out => counter_out
);
main: process
begin
test_runner_setup(runner, runner_cfg);
for j in 0 to 8 loop
trigger_rising();
check_match(counter_out, (std_logic_vector(to_unsigned(j + 1, 4))));
end loop;
check_match(counter_out, ())))
test_runner_cleanup(runner); -- Simulation ends here
end process;
end arch_tb_counter ; -- arch_tb_counter
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1609.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01609ent IS
END c08s11b00x00p04n01i01609ent;
ARCHITECTURE c08s11b00x00p04n01i01609arch OF c08s11b00x00p04n01i01609ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when 1.0;
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01609 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01609arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1609.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01609ent IS
END c08s11b00x00p04n01i01609ent;
ARCHITECTURE c08s11b00x00p04n01i01609arch OF c08s11b00x00p04n01i01609ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when 1.0;
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01609 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01609arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1609.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01609ent IS
END c08s11b00x00p04n01i01609ent;
ARCHITECTURE c08s11b00x00p04n01i01609arch OF c08s11b00x00p04n01i01609ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when 1.0;
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01609 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01609arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hex2seg is
Port ( clk : in STD_LOGIC; -- Clock of the display (30-100Hz?)
en : in STD_LOGIC;
hex : in STD_LOGIC_VECTOR (3 downto 0); -- HEX number you want to display 0-F
seg : out STD_LOGIC_VECTOR (6 downto 0)); -- 7-Segment output, bit0=segment a, .. ,bit 6=segment g. Output is modulated with clock!
end hex2seg;
architecture Behavioral of hex2seg is
signal segments : STD_LOGIC_VECTOR(6 downto 0); -- '1' for every segment that should be switched on (not modulated)
signal clockvec : STD_LOGIC_VECTOR(6 downto 0); -- just "clk" on every bit of the vector
begin
clockvec <= (others => clk); -- "Copy" clock to every bit of the vector
-- Switch on the hex char, and decide which segments should be on
with hex select
segments <= "0111111" when "0000", --Ziffer 0
"0000110" when "0001", --Ziffer 1
"1011011" when "0010", --Ziffer 2
"1001111" when "0011", --Ziffer 3
"1100110" when "0100", --Ziffer 4
"1101101" when "0101", --Ziffer 5
"1111101" when "0110", --Ziffer 6
"0000111" when "0111", --Ziffer 7
"1111111" when "1000", --Ziffer 8
"1101111" when "1001", --Ziffer 9
"1110111" when "1010", --Ziffer A
"1111100" when "1011", --Ziffer B
"0111001" when "1100", --Ziffer C
"1011110" when "1101", --Ziffer D
"1111001" when "1110", --Ziffer E
"1110001" when "1111", --Ziffer F
"0000000" when others;
-- Assign seg (modulated).
-- All segments which must be on, will have the inverse polarity of the clock. The others go with the clock. We can use xor for that.
seg <= clockvec xor segments when en = '1' else clockvec;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
sgn : signed(7 downto 0) := x"f8";
uns : unsigned(7 downto 0) := x"07";
nat : natural := 15;
int : integer := -3;
mul_int_int : out integer;
mul_uns_uns : out unsigned(15 downto 0);
mul_uns_nat : out unsigned(15 downto 0);
mul_nat_uns : out unsigned(15 downto 0);
mul_sgn_sgn : out signed(15 downto 0);
mul_sgn_int : out signed(15 downto 0);
mul_int_sgn : out signed(15 downto 0);
div_int_int : out integer;
div_uns_uns : out unsigned(7 downto 0);
div_uns_nat : out unsigned(7 downto 0);
div_nat_uns : out unsigned(7 downto 0);
div_sgn_sgn : out signed(7 downto 0);
div_sgn_int : out signed(7 downto 0);
div_int_sgn : out signed(7 downto 0);
rem_int_int : out integer;
rem_uns_uns : out unsigned(7 downto 0);
rem_uns_nat : out unsigned(7 downto 0);
rem_nat_uns : out unsigned(7 downto 0);
rem_sgn_sgn : out signed(7 downto 0);
rem_sgn_int : out signed(7 downto 0);
rem_int_sgn : out signed(7 downto 0);
mod_int_int : out integer;
mod_uns_uns : out unsigned(7 downto 0);
mod_uns_nat : out unsigned(7 downto 0);
mod_nat_uns : out unsigned(7 downto 0);
mod_sgn_sgn : out signed(7 downto 0);
mod_sgn_int : out signed(7 downto 0);
mod_int_sgn : out signed(7 downto 0)
);
end;
architecture a of ent is
begin
mul_int_int <= int * int;
mul_uns_uns <= uns * uns;
mul_uns_nat <= uns * nat;
mul_nat_uns <= nat * uns;
mul_sgn_sgn <= sgn * sgn;
mul_sgn_int <= sgn * int;
mul_int_sgn <= int * sgn;
div_int_int <= int / int;
div_uns_uns <= uns / uns;
div_uns_nat <= uns / nat;
div_nat_uns <= nat / uns;
div_sgn_sgn <= sgn / sgn;
div_sgn_int <= sgn / int;
div_int_sgn <= int / sgn;
rem_int_int <= int rem int;
rem_uns_uns <= uns rem uns;
rem_uns_nat <= uns rem nat;
rem_nat_uns <= nat rem uns;
rem_sgn_sgn <= sgn rem sgn;
rem_sgn_int <= sgn rem int;
rem_int_sgn <= int rem sgn;
mod_int_int <= int mod int;
mod_uns_uns <= uns mod uns;
mod_uns_nat <= uns mod nat;
mod_nat_uns <= nat mod uns;
mod_sgn_sgn <= sgn mod sgn;
mod_sgn_int <= sgn mod int;
mod_int_sgn <= int mod sgn;
end;
|
------------------------------------------------------------------------------
-- ZIPPY global architecture declarations
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/28
-- Last changed: $LastChangedDate: 2005-04-07 11:17:51 +0200 (Thu, 07 Apr 2005) $
------------------------------------------------------------------------------
-- The zippy architecture is widely parameterized. The parameters that define
-- the architecture are declared in this package, e.g. data-width, size of
-- array, number of contexts, FIFO sizes etc.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-08 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.AuxPkg.all;
package ZArchPkg is
-- The user configurable architecture parameter have been moved to
-- archConfigPkg
constant IFWIDTH : integer := 32; -- interface width
constant CCNTWIDTH : integer := IFWIDTH; -- cycle counter width
constant PARTWIDTH : integer := IFWIDTH; -- cfg. partition width
constant N_CELLINPS : integer := 3; -- no. of inputs of a cell
constant N_LOCALCON : integer := 8; -- no. local interconnect inputs
-----------------------------------------------------------------------------
-- FIXME: N_IOP must be set to 2, not fully configurable, since FIFO
-- instantiation and decoder are hardcoded.
-----------------------------------------------------------------------------
constant N_IOP : integer := 2; -- no. of input/output ports
constant SIW_WRDWIDTH : integer := IFWIDTH; -- sched. instr. word width
constant SIW_CONWIDTH : integer := CNTXTWIDTH; -- context field width
constant SIW_CYCWIDTH : integer := 20; -- cycle field width
constant SIW_ADRWIDTH : integer := 7; -- next addr. field width
-- native data type of the zippy architecture, all data operations occur on
-- signals of this data type
subtype data_word is std_logic_vector(DATAWIDTH-1 downto 0);
type data_vector is array (natural range<>) of data_word;
constant SL0 : std_logic := '0'; -- '0' constant in std_logic type
constant SL1 : std_logic := '1'; -- '1' constant in std_logic type
----------------------------------------------------------------------------
-- ZUnit Register Mapping and Functions:
-- 0 Reset W
-- 1 FIFO0 R/W
-- 2 FIFO0 Level R
-- 3 FIFO1 R/W
-- 4 FIFO1 Level R
-- 5 Run Cycle Counter R/W
-- 6 CfgMemory0 W
-- 7 CfgMemory0 Pointer W
-- 8 CfgMemory1 W
-- 9 CfgMemory1 Pointer W
-- 10 CfgMemory2 W
-- 11 CfgMemory2 Pointer W
-- 12 CfgMemory3 W
-- 13 CfgMemory3 Pointer W
-- 14 CfgMemory4 W
-- 15 CfgMemory4 Pointer W
-- 16 CfgMemory5 W
-- 17 CfgMemory5 Pointer W
-- 18 CfgMemory6 W
-- 19 CfgMemory6 Pointer W
-- 20 CfgMemory7 W
-- 21 CfgMemory7 Pointer W
-- 22 Context SelReg wo/ clear W
-- 23 Context SelReg w/ clear W
-- 50 VirtualizationContextNo W
-- set number of virtualization contexts (used by TemporalPartitioning
-- scheduler)
-- 51 ContextSchedulerSelect W
-- select which context scheduler type is used
-- 125 Context Schedule Start W
-- 126 Context Schedule Status R
-- 127 Context Schedule Program W
-- 128 ""
-- ... ""
-- 134 ""
----------------------------------------------------------------------------
constant ZREG_RST : integer := 0;
constant ZREG_FIFO0 : integer := 1;
constant ZREG_FIFO0LEV : integer := 2;
constant ZREG_FIFO1 : integer := 3;
constant ZREG_FIFO1LEV : integer := 4;
constant ZREG_CYCLECNT : integer := 5;
constant ZREG_CFGMEM0 : integer := 6;
constant ZREG_CFGMEM0PTR : integer := 7;
constant ZREG_CFGMEM1 : integer := 8;
constant ZREG_CFGMEM1PTR : integer := 9;
constant ZREG_CFGMEM2 : integer := 10;
constant ZREG_CFGMEM2PTR : integer := 11;
constant ZREG_CFGMEM3 : integer := 12;
constant ZREG_CFGMEM3PTR : integer := 13;
constant ZREG_CFGMEM4 : integer := 14;
constant ZREG_CFGMEM4PTR : integer := 15;
constant ZREG_CFGMEM5 : integer := 16;
constant ZREG_CFGMEM5PTR : integer := 17;
constant ZREG_CFGMEM6 : integer := 18;
constant ZREG_CFGMEM6PTR : integer := 19;
constant ZREG_CFGMEM7 : integer := 20;
constant ZREG_CFGMEM7PTR : integer := 21;
constant ZREG_CONTEXTSEL : integer := 22;
constant ZREG_CONTEXTSELCLR : integer := 23;
-- set number of contexts, used for cyclic context activation with
-- temporal partitioning.
constant ZREG_VIRTCONTEXTNO : integer := 50;
constant ZREG_CONTEXTSCHEDSEL : integer := 51;
-- 0: context sequencer and cycle counter
-- 1: temporal paritioning scheduler
constant ZREG_SCHEDSTART : integer := 125; -- data: 0 store, 1 clr (context)
constant ZREG_SCHEDSTATUS : integer := 126;
constant ZREG_SCHEDIWORD00 : integer := 127;
constant ZREG_SCHEDIWORD01 : integer := 128;
constant ZREG_SCHEDIWORD02 : integer := 129;
constant ZREG_SCHEDIWORD03 : integer := 130;
constant ZREG_SCHEDIWORD04 : integer := 131;
constant ZREG_SCHEDIWORD05 : integer := 132;
constant ZREG_SCHEDIWORD06 : integer := 133;
constant ZREG_SCHEDIWORD07 : integer := 134;
-- (8 will do for the moment ...)
-- tstbitat0(a,b) out = ~0 if all 1bits of 'b' are 0 in word 'a', else 0
-- tstbitat1(a,b) out = ~0 if all 1bits of 'b' are 1 in word 'a' else 0
-- mux(a,b,c) out = 'a' if 'c(0)=0', else 'b'
-- rom(a) out = romdata[a]
constant ALUOPWIDTH : integer := 6; -- need to know for configuration
subtype aluop_type is integer range 0 to 2**ALUOPWIDTH-1;
-- FIXME: the following instructions are unnecessary
-- ALU_PASS1
-- ALU_NEG1 (even NEG0, since can be implemeted as const(0)-input
-- ALU_SUBU
-- ALU_ADDU
-- ALU_OP_MULTULO
-- ALU_OP_MULTUHI
-- ALU_NOT1 (even NOT0, since can be implemented as xor with 111..1)
constant ALU_OP_PASS0 : aluop_type := 0;
constant ALU_OP_PASS1 : aluop_type := 1;
constant ALU_OP_NEG0 : aluop_type := 2;
constant ALU_OP_NEG1 : aluop_type := 3;
constant ALU_OP_ADD : aluop_type := 4;
constant ALU_OP_SUB : aluop_type := 5;
constant ALU_OP_ADDU : aluop_type := 6;
constant ALU_OP_SUBU : aluop_type := 7;
constant ALU_OP_MULTHI : aluop_type := 8;
constant ALU_OP_MULTLO : aluop_type := 9;
constant ALU_OP_MULTUHI : aluop_type := 10;
constant ALU_OP_MULTULO : aluop_type := 11;
constant ALU_OP_AND : aluop_type := 12;
constant ALU_OP_NAND : aluop_type := 13;
constant ALU_OP_OR : aluop_type := 14;
constant ALU_OP_NOR : aluop_type := 15;
constant ALU_OP_XOR : aluop_type := 16;
constant ALU_OP_XNOR : aluop_type := 17;
constant ALU_OP_NOT0 : aluop_type := 18;
constant ALU_OP_NOT1 : aluop_type := 19;
constant ALU_OP_SLL : aluop_type := 20;
constant ALU_OP_SRL : aluop_type := 21;
constant ALU_OP_ROL : aluop_type := 22;
constant ALU_OP_ROR : aluop_type := 23;
constant ALU_OP_TSTBITAT0 : aluop_type := 24;
constant ALU_OP_TSTBITAT1 : aluop_type := 25;
constant ALU_OP_MUX : aluop_type := 26;
constant ALU_OP_ROM : aluop_type := 27;
constant ALU_OP_EQ : aluop_type := 28;
constant ALU_OP_NEQ : aluop_type := 29;
constant ALU_OP_LT : aluop_type := 30;
constant ALU_OP_GT : aluop_type := 31;
constant ALU_OP_LTE : aluop_type := 32;
constant ALU_OP_GTE : aluop_type := 33;
type opcodename_array is array (0 to 33) of string(1 to 9);
constant opcode_name : opcodename_array := (
0 => "pass0 ",
1 => "pass1 ",
2 => "neg0 ",
3 => "neg1 ",
4 => "add ",
5 => "sub ",
6 => "addu ",
7 => "subu ",
8 => "multhi ",
9 => "multlo ",
10 => "multuhi ",
11 => "multulo ",
12 => "and ",
13 => "nand ",
14 => "or ",
15 => "nor ",
16 => "xor ",
17 => "xnor ",
18 => "not0 ",
19 => "not1 ",
20 => "sll ",
21 => "srl ",
22 => "rol ",
23 => "ror ",
24 => "tstbitat0",
25 => "tstbitat1",
26 => "mux ",
27 => "rom ",
28 => "eq ",
29 => "neq ",
30 => "lt ",
31 => "gt ",
32 => "lte ",
33 => "gte "
);
----------------------------------------------------------------------------
-- Configuration
----------------------------------------------------------------------------
type procInputMuxArray is array (N_CELLINPS-1 downto 0) of
std_logic_vector(2 downto 0);
type procInputCtxRegSelectArray is array (N_CELLINPS-1 downto 0) of
std_logic_vector(CNTXTWIDTH-1 downto 0);
subtype procOutputMux is std_logic_vector(1 downto 0);
subtype procOutputCtxRegSelect is std_logic_vector(CNTXTWIDTH-1 downto 0);
-- FIXME find better names for record elements.
-- for instance
-- InputMuxS instead of OpMuxS
-- InputContextRegxS instead of OpCtxRegSelxS
-- etc.
type procConfigRec is
record
OpMuxS : procInputMuxArray;
OpCtxRegSelxS : procInputCtxRegSelectArray;
OutMuxS : procOutputMux;
OutCtxRegSelxS : procOutputCtxRegSelect;
AluOpxS : aluop_type;
ConstOpxD : data_word;
end record;
type cellInputRec is
record
LocalxDI : data_vector(N_LOCALCON-1 downto 0);
HBusNxDI : data_vector(N_HBUSN-1 downto 0);
HBusSxDI : data_vector(N_HBUSS-1 downto 0);
VBusExDI : data_vector(N_VBUSE-1 downto 0);
end record;
type cellOutputRec is
record
LocalxDO : data_word;
HBusNxDZ : data_vector(N_HBUSN-1 downto 0);
HBusSxDZ : data_vector(N_HBUSS-1 downto 0);
VBusExDZ : data_vector(N_VBUSE-1 downto 0);
end record;
type cellRoutingInputConfigRec is
record
LocalxE : std_logic_vector(N_LOCALCON-1 downto 0);
HBusNxE : std_logic_vector(N_HBUSN-1 downto 0);
HBusSxE : std_logic_vector(N_HBUSS-1 downto 0);
VBusExE : std_logic_vector(N_VBUSE-1 downto 0);
end record;
type cellRoutingInputConfigRecArr is array (N_CELLINPS-1 downto 0) of
cellRoutingInputConfigRec;
type cellRoutingOutputConfigRec is
record
HBusNxE : std_logic_vector(N_HBUSN-1 downto 0);
HBusSxE : std_logic_vector(N_HBUSS-1 downto 0);
VBusExE : std_logic_vector(N_VBUSE-1 downto 0);
end record;
type routConfigRec is
record
i : cellRoutingInputConfigRecArr; -- one cfg per input
o : cellRoutingOutputConfigRec;
end record;
type cellConfigRec is
record
procConf : procConfigRec;
routConf : routConfigRec;
end record;
type procelInputArray is array (N_CELLINPS-1 downto 0) of data_word;
type engineInoutDataType is array (N_IOP-1 downto 0) of data_word;
type engineHBusNorthArray is array (N_ROWS-1 downto 0) of
data_vector(N_HBUSN-1 downto 0);
type engineHBusSouthArray is array (N_ROWS-1 downto 0) of
data_vector(N_HBUSS-1 downto 0);
type engineVBusEastArray is array (N_COLS-1 downto 0) of
data_vector(N_VBUSE-1 downto 0);
-- hbdr(row)(hbus_n nr) enables driving input bus to horizontal
-- north bus
type HBusNorthDriverArray is array (N_ROWS-1 downto 0) of
std_logic_vector(N_HBUSN-1 downto 0);
type engineHBusNorthInputDriverArray is array (N_IOP-1 downto 0) of
HBusNorthDriverArray;
type engineHBusNorthOutputDriverArray is array (N_IOP-1 downto 0) of
HBusNorthDriverArray;
type rowConfigArray is array (N_COLS-1 downto 0) of cellConfigRec;
type rowInputArray is array (N_COLS-1 downto 0) of cellInputRec;
type rowOutputArray is array (N_COLS-1 downto 0) of cellOutputRec;
type gridConfigArray is array (N_ROWS-1 downto 0) of rowConfigArray;
type gridInputArray is array (N_ROWS-1 downto 0) of rowInputArray;
type gridOutputArray is array (N_ROWS-1 downto 0) of rowOutputArray;
type ioportConfigRec is
record
Cmp0MuxS : std_logic;
Cmp0ModusxS : std_logic;
Cmp0ConstxD : std_logic_vector(CCNTWIDTH-1 downto 0);
Cmp1MuxS : std_logic;
Cmp1ModusxS : std_logic;
Cmp1ConstxD : std_logic_vector(CCNTWIDTH-1 downto 0);
LUT4FunctxD : std_logic_vector(15 downto 0);
end record;
type engineInportConfigArray is array (N_IOP-1 downto 0) of ioportConfigRec;
type engineOutportConfigArray is array (N_IOP-1 downto 0) of ioportConfigRec;
type engineMemoryConfigArray is array (N_ROWS-1 downto 0) of
data_vector(N_MEMDEPTH-1 downto 0);
-------------------------------------------------------------------------------
-- HELPER constants and functions for configuration specification
-------------------------------------------------------------------------------
-- convert a (singed) integer to a std_logic_vector, for specification of the
-- constant operator ConstOpxD in the configuration file
function i2cfgconst (i : integer) return data_word;
-- convert an unsigned integer to a std_logic_vector, for
-- specification of the input operand context registerselection
-- OpCtxRegSelxS
function i2ctx (i : natural) return std_logic_vector;
-- select which cycle counter to use for comparison
constant CFG_IOPORT_MUX_CYCLEUP : std_logic := '0'; -- cycle up counter
constant CFG_IOPORT_MUX_CYCLEDOWN : std_logic := '1'; -- cycle down counter
-- select comparison mode
constant CFG_IOPORT_MODUS_LARGER : std_logic := '0'; -- test larger
constant CFG_IOPORT_MODUS_EQUAL : std_logic := '1'; -- test equality
-- select LUT function
constant CFG_IOPORT_CMP1 : std_logic_vector(15 downto 0) := X"FF00";
constant CFG_IOPORT_CMP0 : std_logic_vector(15 downto 0) := X"F0F0";
constant CFG_IOPORT_ON : std_logic_vector(15 downto 0) := X"FFFF";
constant CFG_IOPORT_OFF : std_logic_vector(15 downto 0) := X"0000";
-- constants for selecting local inputs from neighbors
constant LOCAL_N : natural := 0;
constant LOCAL_NE : natural := 1;
constant LOCAL_E : natural := 2;
constant LOCAL_SE : natural := 3;
constant LOCAL_S : natural := 4;
constant LOCAL_SW : natural := 5;
constant LOCAL_W : natural := 6;
constant LOCAL_NW : natural := 7;
-- cell input / output configuration
constant I_NOREG : std_logic_vector(2 downto 0) := "000";
constant I_CONST : std_logic_vector(2 downto 0) := "010";
constant I_REG : std_logic_vector(2 downto 0) := "001";
constant I_REG_CTX_THIS : std_logic_vector(2 downto 0) := "001";
constant I_REG_CTX_OTHER : std_logic_vector(2 downto 0) := "011";
constant I_REG_FEEDBACK : std_logic_vector(2 downto 0) := "100";
constant O_NOREG : std_logic_vector(1 downto 0) := "00";
constant O_REG : std_logic_vector(1 downto 0) := "01";
constant O_REG_CTX_THIS : std_logic_vector(1 downto 0) := "01";
constant O_REG_CTX_OTHER : std_logic_vector(1 downto 0) := "11";
type engineConfigRec is
record
gridConf : gridConfigArray;
inputDriverConf : engineHBusNorthInputDriverArray;
outputDriverConf : engineHBusNorthOutputDriverArray;
inportConf : engineInportConfigArray;
outportConf : engineOutportConfigArray;
memoryConf : engineMemoryConfigArray;
end record;
-----------------------------------------------------------------------------
-- Context Scheduler
-----------------------------------------------------------------------------
type EngineScheduleControlType is
record
CExE : std_logic;
ClrContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxE : std_logic;
ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
end record;
----------------------------------------------------------------------------
-- Subprograms
----------------------------------------------------------------------------
-- determines the length of a procConfig record
function procConfig_length return integer;
-- determines the length of a routConfig record
function routConfig_length return integer;
-- determines the length of a cellConfig record
function cellConfig_length return integer;
-- determines the length of a rowConfig array
function rowConfig_length return integer;
-- determines the length of a gridConfig array
function gridConfig_length return integer;
-- determines the length of a InputDriverConf array
function inputDriverConfig_length return integer;
-- determines the length of a OutputDriverConf array
function outputDriverConfig_length return integer;
-- determines the length of a InportConfig array
function inportConfig_length return integer;
-- determines the length of a InportConfig array
function outportConfig_length return integer;
-- determines the length of an ioportConfig record
function ioportConfig_length return integer;
-- determines the lenth of a MemoryConfig arrya
function memoryConfig_length return integer;
-- determines the length of an engineConfig record
function engineConfig_length return integer;
-- calculates the no. of partitions the configuration is partitioned into.
function num_partitions (cfglen : integer; partwidth : integer)
return integer;
end ZArchPkg;
package body ZArchPkg is
function i2cfgconst (i : integer) return data_word is
variable CfgxD : data_word;
begin
CfgxD := std_logic_vector(to_signed(i, CfgxD'length));
return CfgxD;
end function i2cfgconst;
function i2ctx (i : natural) return std_logic_vector is
variable CtxxD : std_logic_vector(CNTXTWIDTH-1 downto 0);
begin
CtxxD := std_logic_vector(to_unsigned(i, CtxxD'length));
return CtxxD;
end function i2ctx;
-- determines the length of a procConfig record
function procConfig_length return integer is
variable Cfg : procConfigRec;
begin
return (Cfg.OpMuxS'length*Cfg.OpMuxS(0)'length +
Cfg.OpCtxRegSelxS'length*Cfg.OpCtxRegSelxS(0)'length +
Cfg.OutMuxS'length + Cfg.OutCtxRegSelxS'length +
ALUOPWIDTH +
Cfg.ConstOpxD'length);
end procConfig_length;
-- determines the length of a routConfig record
function routConfig_length return integer is
variable Cfg : routConfigRec;
begin
return (Cfg.i'length * (Cfg.i(0).LocalxE'length + Cfg.i(0).HBusNxE'length +
Cfg.i(0).HBusSxE'length + Cfg.i(0).VBusExE'length) +
Cfg.o.HBusNxE'length + Cfg.o.HBusSxE'length + Cfg.o.VBusExE'length);
end routConfig_length;
-- determines the length of a cellConfig record
function cellConfig_length return integer is
begin
return (procConfig_length + routConfig_length);
end cellConfig_length;
-- determines the length of a rowConfig array
function rowConfig_length return integer is
begin
return (N_COLS * cellConfig_length);
end rowConfig_length;
-- determines the length of a gridConfig array
function gridConfig_length return integer is
begin
return (N_ROWS * rowConfig_length);
end gridConfig_length;
-- determines the length of an ioportConfig record
function ioportConfig_length return integer is
variable Cfg : ioportConfigRec;
begin
return (4 + Cfg.Cmp0ConstxD'length + Cfg.Cmp1ConstxD'length +
Cfg.LUT4FunctxD'length);
end ioportConfig_length;
-- determines the length of a inputDriverConf array
function inputDriverConfig_length return integer is
begin
return (N_IOP * N_ROWS * N_HBUSN);
end inputDriverConfig_length;
-- determines the length of a outputDriverConf array
function outputDriverConfig_length return integer is
begin
return (N_IOP * N_ROWS * N_HBUSN);
end outputDriverConfig_length;
-- determines the length of a inportConfig array
function inportConfig_length return integer is
begin
return (N_IOP * ioportConfig_length);
end inportConfig_length;
-- determines the length of a inportConfig array
function outportConfig_length return integer is
begin
return (N_IOP * ioportConfig_length);
end outportConfig_length;
-- determines the length of an engine memory config array
function memoryConfig_length return integer is
variable arr : engineMemoryConfigArray;
begin
return (arr'length*arr(0)'length*DATAWIDTH);
end memoryConfig_length;
-- determines the length of an engineConfig record
function engineConfig_length return integer is
variable Cfg : engineConfigRec;
begin
return (gridConfig_length +
inputDriverConfig_length + outputDriverConfig_length +
inportConfig_length + outportConfig_length +
memoryConfig_length
);
end engineConfig_length;
-- calculates the no. of partitions the configuration is partitioned into.
function num_partitions (cfglen : integer; partwidth : integer)
return integer
is
begin
return (cfglen-1)/partwidth+1;
end num_partitions;
end ZArchPkg;
|
entity test is
package a is new b generic map(c => foo'subtype range 0 to 2);
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_inputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_inputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_inputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_inputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_inputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:58:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_sim_netlist.vhdl
-- Design : mul16_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul16_16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul16_16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul16_16_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul16_16_mult_gen_v12_0_12 : entity is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul16_16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul16_16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul16_16_mult_gen_v12_0_12 : entity is "yes";
end mul16_16_mult_gen_v12_0_12;
architecture STRUCTURE of mul16_16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 16;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 31;
attribute C_OUT_LOW of i_mult : label is 16;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul16_16_mult_gen_v12_0_12_viv
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul16_16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul16_16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul16_16 : entity is "mul16_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul16_16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul16_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul16_16;
architecture STRUCTURE of mul16_16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 16;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul16_16_mult_gen_v12_0_12
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
entity tb_fsm_6s is
end tb_fsm_6s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_6s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_6s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"100101_100101_110001";
constant res : std_logic_vector := b"000001_000001_000000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:53
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY PC IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END PC;
ARCHITECTURE ARC_PC OF PC IS
BEGIN
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
OUT_A <= X"00400000"; --Para utilizar com o MARS
ELSIF CLK'EVENT AND CLK = '1' THEN
OUT_A <= IN_A;
END IF;
END PROCESS;
END ARC_PC;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:53
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY PC IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END PC;
ARCHITECTURE ARC_PC OF PC IS
BEGIN
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
OUT_A <= X"00400000"; --Para utilizar com o MARS
ELSIF CLK'EVENT AND CLK = '1' THEN
OUT_A <= IN_A;
END IF;
END PROCESS;
END ARC_PC;
|
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_acf.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_acf.v,v $
-- Revision 1.10 2005/04/08 13:03:07 igorm
-- In "Extended mode" when dual filter was used and standard frame received,
-- upper nibble of the data was not filtered ok.
--
-- Revision 1.9 2004/05/31 14:46:11 igorm
-- Bit acceptance_filter_mode was inverted.
--
-- Revision 1.8 2004/02/08 14:16:44 mohor
-- Header changed.
--
-- Revision 1.7 2003/07/16 13:41:34 mohor
-- Fixed according to the linter.
--
-- Revision 1.6 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.5 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.4 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.3 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.2 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.1 2003/01/08 02:13:15 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_acf IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END ENTITY can_acf;
ARCHITECTURE RTL OF can_acf IS
SIGNAL match : std_logic;
SIGNAL match_sf_std : std_logic;
SIGNAL match_sf_ext : std_logic;
SIGNAL match_df_std : std_logic;
SIGNAL match_df_ext : std_logic;
SIGNAL id_ok_xhdl1 : std_logic;
BEGIN
id_ok <= id_ok_xhdl1;
-- Working in basic mode. ID match for standard format (11-bit ID).
match <= (((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1)) OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3)) OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5)) OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7)) OR acceptance_mask_0(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
match_sf_std <= (((((((((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_2(0)) OR acceptance_mask_2(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_2(1))
OR acceptance_mask_2(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_2(2)) OR acceptance_mask_2(2)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_2(3)) OR acceptance_mask_2(3) OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_2(4))
OR acceptance_mask_2(4) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_2(5)) OR acceptance_mask_2(5) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_2(6))
OR acceptance_mask_2(6) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_2(7)) OR acceptance_mask_2(7) OR no_byte0)) AND (CONV_STD_LOGIC(data1(0) = acceptance_code_3(0))
OR acceptance_mask_3(0) OR no_byte1)) AND (CONV_STD_LOGIC(data1(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte1)) AND (CONV_STD_LOGIC(data1(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte1)) AND (CONV_STD_LOGIC(data1(3) = acceptance_code_3(3)) OR acceptance_mask_3(3) OR no_byte1)) AND (CONV_STD_LOGIC(data1(4) = acceptance_code_3(4))
OR acceptance_mask_3(4) OR no_byte1)) AND (CONV_STD_LOGIC(data1(5) = acceptance_code_3(5)) OR acceptance_mask_3(5) OR no_byte1)) AND (CONV_STD_LOGIC(data1(6) = acceptance_code_3(6))
OR acceptance_mask_3(6) OR no_byte1)) AND (CONV_STD_LOGIC(data1(7) = acceptance_code_3(7)) OR acceptance_mask_3(7) OR no_byte1) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
match_sf_ext <= (((((((((((((((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(0)) OR acceptance_mask_2(0))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(11) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(12) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr2 = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(3) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(4) = acceptance_code_3(7))
OR acceptance_mask_3(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
match_df_std <= ((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_3(0)) OR acceptance_mask_3(0)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_3(3)) OR acceptance_mask_3(3)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_1(0)) OR acceptance_mask_1(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_1(1))
OR acceptance_mask_1(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_1(2))
OR acceptance_mask_1(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_1(3)) OR acceptance_mask_1(3) OR no_byte0))
OR ((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
match_df_ext <= ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) OR ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_3(0)) OR acceptance_mask_3(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_3(1))
OR acceptance_mask_3(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- ID ok signal generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id_ok_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_rx_crc_lim = '1') THEN
-- sample_point is already included in go_rx_crc_lim
IF (extended_mode = '1') THEN
IF (NOT acceptance_filter_mode = '1') THEN
-- dual filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_df_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_df_std ;
END IF;
ELSE
-- single filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_sf_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_sf_std ;
END IF;
END IF;
ELSE
id_ok_xhdl1 <= match ;
END IF;
ELSE
IF ((reset_mode OR go_rx_inter OR go_error_frame) = '1') THEN
-- sample_point is already included in go_rx_inter
id_ok_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl;
ARCHITECTURE RTL OF can_btl IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
resync_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg1 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
quant_cnt <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delay <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sample <= "11";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') THEN
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_next_sp <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync_blocked <= '1' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_fifo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_fifo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- Rev 1.28 rd_info_pointer fix from opencores merged. /Kristoffer
--
-- $Log: can_fifo.v,v $
-- Revision 1.27 2004/11/18 12:39:34 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.26 2004/02/08 14:30:57 mohor
-- Header changed.
--
-- Revision 1.25 2003/10/23 16:52:17 mohor
-- Active high/low problem when Altera devices are used. Bug fixed by
-- Rojhalat Ibrahim.
--
-- Revision 1.24 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.23 2003/09/05 12:46:41 mohor
-- ALTERA_RAM supported.
--
-- Revision 1.22 2003/08/20 09:59:16 mohor
-- Artisan RAM fixed (when not using BIST).
--
-- Revision 1.21 2003/08/14 16:04:52 simons
-- Artisan ram instances added.
--
-- Revision 1.20 2003/07/16 14:00:45 mohor
-- Fixed according to the linter.
--
-- Revision 1.19 2003/07/03 09:30:44 mohor
-- PCI_BIST replaced with CAN_BIST.
--
-- Revision 1.18 2003/06/27 22:14:23 simons
-- Overrun fifo implemented with FFs, because it is not possible to create such a memory.
--
-- Revision 1.17 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16 2003/06/18 23:03:44 mohor
-- Typo fixed.
--
-- Revision 1.15 2003/06/11 09:37:05 mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14 2003/03/05 15:02:30 mohor
-- Xilinx RAM added.
--
-- Revision 1.13 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.12 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.9 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.7 2003/01/17 17:44:31 mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.3 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.1 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_fifo IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
--------------------------------------------------
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_fifo;
ARCHITECTURE RTL OF can_fifo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
--------------------------------------------------
SIGNAL fifo : xhdl_15;
SIGNAL length_fifo : xhdl_16;
SIGNAL overrun_info : xhdl_17;
SIGNAL rd_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL read_address : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_q : std_logic;
SIGNAL len_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL fifo_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL latch_overrun : std_logic;
SIGNAL initialize_memories : std_logic;
SIGNAL length_info : std_logic_vector(3 DOWNTO 0);
SIGNAL write_length_info : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL info_full : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL overrun_xhdl2 : std_logic;
SIGNAL info_empty_xhdl3 : std_logic;
SIGNAL info_cnt_xhdl4 : std_logic_vector(6 DOWNTO 0);
SIGNAL data_64x8_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl6 : std_logic;
SIGNAL rden_64x8_xhdl7 : std_logic;
SIGNAL wraddress_64x8_xhdl8 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl9 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl10 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl11 : std_logic;
SIGNAL wraddress_64x4x1_xhdl12 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl13 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl14 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
overrun <= overrun_xhdl2;
info_empty <= info_empty_xhdl3;
info_cnt <= info_cnt_xhdl4;
data_64x8 <= data_64x8_xhdl5;
wren_64x8 <= wren_64x8_xhdl6;
rden_64x8 <= rden_64x8_xhdl7;
wraddress_64x8 <= wraddress_64x8_xhdl8;
rdaddress_64x8 <= rdaddress_64x8_xhdl9;
data_64x4 <= data_64x4_xhdl10;
wren_64x4x1 <= wren_64x4x1_xhdl11;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
data_64x1 <= data_64x1_xhdl14;
write_length_info <= (NOT wr) AND wr_q ;
-- Delayed write signal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_q <= '0' ;
ELSE
wr_q <= wr ;
END IF;
END IF;
END PROCESS;
-- length counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
len_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
len_cnt <= "0000" ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
len_cnt <= len_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- wr_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
wr_info_pointer <= wr_info_pointer + "000001" ;
ELSE
IF (reset_mode = '1') THEN
wr_info_pointer <= rd_info_pointer ;
END IF;
END IF;
END IF;
END PROCESS;
-- rd_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
-- Fix from opencores rev 1.28
-- IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_info_pointer <= rd_info_pointer + "000001" ;
END IF;
END IF;
END PROCESS;
-- rd_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_pointer <= rd_pointer + ("00" & length_info) ;
END IF;
END IF;
END PROCESS;
-- wr_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_pointer <= rd_pointer ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
wr_pointer <= wr_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- latch_overrun
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
latch_overrun <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
latch_overrun <= '0' ;
ELSE
IF ((wr AND fifo_full) = '1') THEN
latch_overrun <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Counting data in fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
fifo_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
fifo_cnt <= "0000000" ;
ELSE
IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
fifo_cnt <= fifo_cnt + "0000001" ;
ELSE
IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) ;
ELSE
IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;
-- Counting data in length_fifo and overrun_info fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSE
IF ((write_length_info XOR release_buffer) = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;
ELSE
IF ((write_length_info AND (NOT info_full)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;
-- Selecting which address will be used for reading data from rx fifo
PROCESS (extended_mode, rd_pointer, addr)
VARIABLE read_address_xhdl18 : std_logic_vector(5 DOWNTO 0);
BEGIN
IF (extended_mode = '1') THEN
-- extended mode
read_address_xhdl18 := rd_pointer + (addr - "010000");
ELSE
-- normal mode
read_address_xhdl18 := rd_pointer + (addr - "010100");
END IF;
read_address <= read_address_xhdl18;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
initialize_memories <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (andv(wr_info_pointer) = '1') THEN
initialize_memories <= '0' ;
END IF;
END IF;
END PROCESS;
-- port connections for Ram
--64x8
data_out_xhdl1 <= q_dp_64x8 ;
data_64x8_xhdl5 <= data_in ;
wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
rden_64x8_xhdl7 <= fifo_selected ;
wraddress_64x8_xhdl8 <= wr_pointer ;
rdaddress_64x8_xhdl9 <= read_address ;
--64x4
length_info <= q_dp_64x4 ;
data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
--64x1
overrun_xhdl2 <= q_dp_64x1 ;
data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
-- `ifdef ALTERA_RAM
-- // altera_ram_64x8_sync fifo
-- lpm_ram_dp fifo
-- (
-- .q (data_out),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (data_in),
-- .wren (wr & (~fifo_full)),
-- .rden (fifo_selected),
-- .wraddress (wr_pointer),
-- .rdaddress (read_address)
-- );
-- defparam fifo.lpm_width = 8;
-- defparam fifo.lpm_widthad = 6;
-- defparam fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x4_sync info_fifo
-- lpm_ram_dp info_fifo
-- (
-- .q (length_info),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (len_cnt & {4{~initialize_memories}}),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam info_fifo.lpm_width = 4;
-- defparam info_fifo.lpm_widthad = 6;
-- defparam info_fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x1_sync overrun_fifo
-- lpm_ram_dp overrun_fifo
-- (
-- .q (overrun),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam overrun_fifo.lpm_width = 1;
-- defparam overrun_fifo.lpm_widthad = 6;
-- defparam overrun_fifo.lpm_numwords = 64;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc;
ARCHITECTURE RTL OF can_crc IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_ibo IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo;
ARCHITECTURE RTL OF can_ibo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : IN std_logic;
-- Tx Error Counter register
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers -- Tx signal
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
-- Bist -- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_bsp;
ARCHITECTURE RTL OF can_bsp IS
COMPONENT can_acf
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END COMPONENT;
COMPONENT can_crc
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_fifo
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_ibo
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL set_reset_mode_xhdl12 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL error_status_xhdl14 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL info_empty_xhdl22 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL rx_message_counter_xhdl28: std_logic_vector(6 DOWNTO 0);
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL bus_off_on_xhdl31 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
SIGNAL data_64x8_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl37 : std_logic;
SIGNAL rden_64x8_xhdl38 : std_logic;
SIGNAL wraddress_64x8_xhdl39 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl40 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl41 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl42 : std_logic;
SIGNAL wraddress_64x4x1_xhdl43 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl44 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl45 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
set_reset_mode <= set_reset_mode_xhdl12;
node_bus_off <= node_bus_off_xhdl13;
error_status <= error_status_xhdl14;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
info_empty <= info_empty_xhdl22;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
rx_message_counter <= rx_message_counter_xhdl28;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
bus_off_on <= bus_off_on_xhdl31;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
data_64x8 <= data_64x8_xhdl36;
wren_64x8 <= wren_64x8_xhdl37;
rden_64x8 <= rden_64x8_xhdl38;
wraddress_64x8 <= wraddress_64x8_xhdl39;
rdaddress_64x8 <= rdaddress_64x8_xhdl40;
data_64x4 <= data_64x4_xhdl41;
wren_64x4x1 <= wren_64x4x1_xhdl42;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl43;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl44;
data_64x1 <= data_64x1_xhdl45;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl36 <= w_data_64x8 ;
wren_64x8_xhdl37 <= w_wren_64x8 ;
rden_64x8_xhdl38 <= w_rden_64x8 ;
wraddress_64x8_xhdl39 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl40 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl41 <= w_data_64x4 ;
wren_64x4x1_xhdl42 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl43 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl44 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl45 <= w_data_64x1 ;
-- ----------------------
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r0 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_dlc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_data <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_eof <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_len <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tmp_data <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
byte_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
IF ((sample_point AND go_rx_crc_lim) = '1') THEN
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write_data_to_tmp_fifo = '1') THEN
tmp_fifo(conv_integer(byte_cnt)) <= tmp_data ;
END IF;
END IF;
END PROCESS;
-- CRC
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_in <= "000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_cnt <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
eof_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_enable <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_err <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ack_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
stuff_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
form_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_rx : can_crc
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
port_xhdl73 <= tmp_fifo(0);
port_xhdl74 <= tmp_fifo(1);
i_can_acf : can_acf
PORT MAP (
clk => clk,
rst => rst,
id => id,
reset_mode => reset_mode,
acceptance_filter_mode => acceptance_filter_mode,
extended_mode => extended_mode,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
go_rx_crc_lim => go_rx_crc_lim,
go_rx_inter => go_rx_inter_xhdl9,
go_error_frame => go_error_frame_xhdl33,
data0 => port_xhdl73,
data1 => port_xhdl74,
rtr1 => rtr1,
rtr2 => rtr2,
ide => ide,
no_byte0 => no_byte0,
no_byte1 => no_byte1,
id_ok => id_ok);
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
header_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
PROCESS (extended_mode, ide, data_cnt, header_cnt, header_len, storing_header, id, rtr1, rtr2, data_len, tmp_fifo)
VARIABLE data_for_fifo_xhdl79 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl80 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl80 := storing_header & extended_mode & ide & header_cnt;
IF (std_match(temp_xhdl80, "111000")) THEN
data_for_fifo_xhdl79 := '1' & rtr2 & "00" & data_len; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111001")) THEN
data_for_fifo_xhdl79 := id(28 DOWNTO 21); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111010")) THEN
data_for_fifo_xhdl79 := id(20 DOWNTO 13); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111011")) THEN
data_for_fifo_xhdl79 := id(12 DOWNTO 5); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111100")) THEN
data_for_fifo_xhdl79 := id(4 DOWNTO 0) & rtr2 & "00"; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "110000")) THEN
data_for_fifo_xhdl79 := '0' & rtr1 & "00" & data_len; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110001")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110010")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & "0000"; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "10-000")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- normal mode header
ELSIF (std_match(temp_xhdl80, "10-001")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & data_len; -- normal mode header
ELSE
data_for_fifo_xhdl79 := tmp_fifo(conv_integer(data_cnt - ('0' & header_len)) mod 8); -- data
END IF;
data_for_fifo <= data_for_fifo_xhdl79;
END PROCESS;
-- Instantiation of the RX fifo module
-- port connections for Ram
--64x8
--64x4
--64x1
i_can_fifo : can_fifo
PORT MAP (
clk => clk,
rst => rst,
wr => wr_fifo,
data_in => data_for_fifo,
addr => addr(5 DOWNTO 0),
data_out => data_out_xhdl1,
fifo_selected => fifo_selected,
reset_mode => reset_mode,
release_buffer => release_buffer,
extended_mode => extended_mode,
overrun => overrun_xhdl21,
info_empty => info_empty_xhdl22,
info_cnt => rx_message_counter_xhdl28,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_frame <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_flag_over_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
passive_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
first_compare_bit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_request_cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_xhdl29 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
go_early_tx_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
suspend <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
finish_msg <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((we_rx_err_cnt AND (NOT node_bus_off_xhdl13)) = '1') THEN
rx_err_cnt_xhdl15 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
ELSE
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we_tx_err_cnt = '1') THEN
tx_err_cnt_xhdl16 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in < "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in = "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bus_off_on_xhdl31 <= NOT node_bus_off_xhdl13 ;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ;
temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit))) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000"));
error_status_xhdl14 <= CONV_STD_LOGIC(temp_xhdl110) ;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register.v,v $
-- Revision 1.7 2004/02/08 14:32:31 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_register IS
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END ENTITY can_register;
ARCHITECTURE RTL OF can_register IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn.v,v $
-- Revision 1.7 2004/02/08 14:33:19 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END ENTITY can_register_asyn;
ARCHITECTURE RTL OF can_register_asyn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
-- asynchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn_syn.v,v $
-- Revision 1.7 2004/02/08 14:33:59 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:52:43 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_asyn_syn;
ARCHITECTURE RTL OF can_register_asyn_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_syn.v,v $
-- Revision 1.5 2004/02/08 14:34:40 mohor
-- Header changed.
--
-- Revision 1.4 2003/03/11 16:31:58 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_syn;
ARCHITECTURE RTL OF can_register_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, 8);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_registers
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_registers.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
-- Revision 1.36 2005/03/18 15:04:05 igorm
-- Wake-up interrupt was generated in some cases.
--
-- Revision 1.35 2004/11/30 15:08:26 igorm
-- irq is cleared after the release_buffer command. This bug was entered with
-- changes for the edge triggered interrupts.
--
-- Revision 1.34 2004/11/18 12:39:43 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.33 2004/10/25 11:44:38 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.32 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.31 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.30 2003/07/16 15:19:34 mohor
-- Fixed according to the linter.
-- Case statement for data_out joined.
--
-- Revision 1.29 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.28 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.27 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.26 2003/06/22 01:33:14 mohor
-- clkout is clk/2 after the reset.
--
-- Revision 1.25 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.24 2003/06/09 11:22:54 mohor
-- data_out is already registered in the can_top.v file.
--
-- Revision 1.23 2003/04/15 15:31:24 mohor
-- Some features are supported in extended mode only (listen_only_mode...).
--
-- Revision 1.22 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.20 2003/03/11 16:31:05 mohor
-- Mux used for clkout to avoid "gated clocks warning".
--
-- Revision 1.19 2003/03/10 17:34:25 mohor
-- Doubled declarations removed.
--
-- Revision 1.18 2003/03/01 22:52:11 mohor
-- Data is latched on read.
--
-- Revision 1.17 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.16 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.15 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.14 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.13 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.12 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.11 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.6 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.5 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.4 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_registers IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
-- Mode register
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
-- Command register
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: OUT std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
-- Error Warning Limit register
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : OUT std_logic;
-- Tx Error Counter register
we_tx_err_cnt : OUT std_logic;
-- Clock Divider register
extended_mode : OUT std_logic;
clkout : OUT std_logic;
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_registers;
ARCHITECTURE RTL OF can_registers IS
CONSTANT xhdl_timescale : time := 1 ns;
COMPONENT can_register
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn_syn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END COMPONENT;
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
signal read_irq_reg_q : std_logic;
signal reset_irq_reg : std_logic;
SIGNAL tx_successful_q : std_logic;
SIGNAL overrun_q : std_logic;
SIGNAL overrun_status : std_logic;
SIGNAL transmission_complete : std_logic;
SIGNAL transmit_buffer_status_q : std_logic;
SIGNAL receive_buffer_status : std_logic;
SIGNAL error_status_q : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL node_error_passive_q : std_logic;
SIGNAL transmit_buffer_status : std_logic;
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL data_overrun_irq_en : std_logic;
SIGNAL error_warning_irq_en : std_logic;
SIGNAL transmit_irq_en : std_logic;
SIGNAL receive_irq_en : std_logic;
SIGNAL irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL irq : std_logic;
SIGNAL we_mode : std_logic;
SIGNAL we_command : std_logic;
SIGNAL we_bus_timing_0 : std_logic;
SIGNAL we_bus_timing_1 : std_logic;
SIGNAL we_clock_divider_low : std_logic;
SIGNAL we_clock_divider_hi : std_logic;
SIGNAL read : std_logic;
SIGNAL read_irq_reg : std_logic;
-- This section is for BASIC and EXTENDED mode
SIGNAL we_acceptance_code_0 : std_logic;
SIGNAL we_acceptance_mask_0 : std_logic;
SIGNAL we_tx_data_0 : std_logic;
SIGNAL we_tx_data_1 : std_logic;
SIGNAL we_tx_data_2 : std_logic;
SIGNAL we_tx_data_3 : std_logic;
SIGNAL we_tx_data_4 : std_logic;
SIGNAL we_tx_data_5 : std_logic;
SIGNAL we_tx_data_6 : std_logic;
SIGNAL we_tx_data_7 : std_logic;
SIGNAL we_tx_data_8 : std_logic;
SIGNAL we_tx_data_9 : std_logic;
SIGNAL we_tx_data_10 : std_logic;
SIGNAL we_tx_data_11 : std_logic;
SIGNAL we_tx_data_12 : std_logic;
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
SIGNAL we_interrupt_enable : std_logic;
SIGNAL we_error_warning_limit : std_logic;
SIGNAL we_acceptance_code_1 : std_logic;
SIGNAL we_acceptance_code_2 : std_logic;
SIGNAL we_acceptance_code_3 : std_logic;
SIGNAL we_acceptance_mask_1 : std_logic;
SIGNAL we_acceptance_mask_2 : std_logic;
SIGNAL we_acceptance_mask_3 : std_logic;
-- Mode register
SIGNAL mode : std_logic;
SIGNAL mode_basic : std_logic_vector(4 DOWNTO 1);
SIGNAL mode_ext : std_logic_vector(3 DOWNTO 1);
SIGNAL receive_irq_en_basic : std_logic;
SIGNAL transmit_irq_en_basic : std_logic;
SIGNAL error_irq_en_basic : std_logic;
SIGNAL overrun_irq_en_basic : std_logic;
SIGNAL port_xhdl52 : std_logic;
SIGNAL xhdl_61 : std_logic;
-- End Mode register
-- Command register
SIGNAL command : std_logic_vector(4 DOWNTO 0);
SIGNAL xhdl_69 : std_logic;
SIGNAL port_xhdl70 : std_logic;
SIGNAL port_xhdl71 : std_logic;
SIGNAL xhdl_77 : std_logic;
SIGNAL port_xhdl78 : std_logic;
SIGNAL port_xhdl79 : std_logic;
SIGNAL xhdl_85 : std_logic;
SIGNAL xhdl_91 : std_logic;
SIGNAL port_xhdl92 : std_logic;
SIGNAL port_xhdl93 : std_logic;
-- End Command register
-- Status register
SIGNAL status : std_logic_vector(7 DOWNTO 0);
-- End Status register
-- Interrupt Enable register (extended mode)
SIGNAL irq_en_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL bus_error_irq_en : std_logic;
SIGNAL arbitration_lost_irq_en : std_logic;
SIGNAL error_passive_irq_en : std_logic;
SIGNAL data_overrun_irq_en_ext : std_logic;
SIGNAL error_warning_irq_en_ext : std_logic;
SIGNAL transmit_irq_en_ext : std_logic;
SIGNAL receive_irq_en_ext : std_logic;
-- End Bus Timing 0 register
-- Bus Timing 0 register
SIGNAL bus_timing_0 : std_logic_vector(7 DOWNTO 0);
-- End Bus Timing 0 register
-- Bus Timing 1 register
SIGNAL bus_timing_1 : std_logic_vector(7 DOWNTO 0);
-- End Error Warning Limit register
-- Clock Divider register
SIGNAL clock_divider : std_logic_vector(7 DOWNTO 0);
SIGNAL clock_off : std_logic;
SIGNAL cd : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_div : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_tmp : std_logic;
SIGNAL port_xhdl116 : std_logic;
SIGNAL port_xhdl117 : std_logic;
SIGNAL port_xhdl123 : std_logic;
SIGNAL port_xhdl124 : std_logic;
SIGNAL temp_xhdl131 : std_logic;
SIGNAL temp_xhdl132 : std_logic;
SIGNAL temp_xhdl218 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl219 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl220 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl221 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl222 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl223 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl224 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl225 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl226 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl227 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl228 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl229 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl230 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl231 : std_logic_vector(7 DOWNTO 0); -- basic mode
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL temp_xhdl233 : std_logic;
SIGNAL temp_xhdl234 : std_logic;
SIGNAL temp_xhdl235 : std_logic;
SIGNAL temp_xhdl236 : std_logic;
SIGNAL data_overrun_irq : std_logic;
SIGNAL transmit_irq : std_logic;
SIGNAL receive_irq : std_logic;
SIGNAL error_irq : std_logic;
SIGNAL bus_error_irq : std_logic;
SIGNAL arbitration_lost_irq : std_logic;
SIGNAL error_passive_irq : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL irq_n_xhdl2 : std_logic;
SIGNAL reset_mode_xhdl3 : std_logic;
SIGNAL listen_only_mode_xhdl4 : std_logic;
SIGNAL acceptance_filter_mode_xhdl5 : std_logic;
SIGNAL self_test_mode_xhdl6 : std_logic;
SIGNAL clear_data_overrun_xhdl7 : std_logic;
SIGNAL release_buffer_xhdl8 : std_logic;
SIGNAL abort_tx_xhdl9 : std_logic;
SIGNAL tx_request_xhdl10 : std_logic;
SIGNAL self_rx_request_xhdl11 : std_logic;
SIGNAL single_shot_transmission_xhdl12 : std_logic;
SIGNAL overload_request_xhdl13 : std_logic;
SIGNAL read_arbitration_lost_capture_reg_xhdl14: std_logic;
SIGNAL read_error_code_capture_reg_xhdl15: std_logic;
SIGNAL baud_r_presc_xhdl16 : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width_xhdl17 : std_logic_vector(1 DOWNTO 0);
SIGNAL time_segment1_xhdl18 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2_xhdl19 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling_xhdl20 : std_logic;
SIGNAL error_warning_limit_xhdl21 : std_logic_vector(7 DOWNTO 0);
SIGNAL we_rx_err_cnt_xhdl22 : std_logic;
SIGNAL we_tx_err_cnt_xhdl23 : std_logic;
SIGNAL extended_mode_xhdl24 : std_logic;
SIGNAL clkout_xhdl25 : std_logic;
SIGNAL acceptance_code_0_xhdl26 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_0_xhdl27 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_1_xhdl28 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2_xhdl29 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3_xhdl30 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_1_xhdl31 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2_xhdl32 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3_xhdl33 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_0_xhdl34 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1_xhdl35 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3_xhdl37 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4_xhdl38 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5_xhdl39 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6_xhdl40 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7_xhdl41 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8_xhdl42 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_xhdl43 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10_xhdl44 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11_xhdl45 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12_xhdl46 : std_logic_vector(7 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
irq_n <= irq_n_xhdl2;
reset_mode <= reset_mode_xhdl3;
listen_only_mode <= listen_only_mode_xhdl4;
acceptance_filter_mode <= acceptance_filter_mode_xhdl5;
self_test_mode <= self_test_mode_xhdl6;
clear_data_overrun <= clear_data_overrun_xhdl7;
release_buffer <= release_buffer_xhdl8;
abort_tx <= abort_tx_xhdl9;
tx_request <= tx_request_xhdl10;
self_rx_request <= self_rx_request_xhdl11;
single_shot_transmission <= single_shot_transmission_xhdl12;
overload_request <= overload_request_xhdl13;
read_arbitration_lost_capture_reg <= read_arbitration_lost_capture_reg_xhdl14;
read_error_code_capture_reg <= read_error_code_capture_reg_xhdl15;
baud_r_presc <= baud_r_presc_xhdl16;
sync_jump_width <= sync_jump_width_xhdl17;
time_segment1 <= time_segment1_xhdl18;
time_segment2 <= time_segment2_xhdl19;
triple_sampling <= triple_sampling_xhdl20;
error_warning_limit <= error_warning_limit_xhdl21;
we_rx_err_cnt <= we_rx_err_cnt_xhdl22;
we_tx_err_cnt <= we_tx_err_cnt_xhdl23;
extended_mode <= extended_mode_xhdl24;
clkout <= clkout_xhdl25;
acceptance_code_0 <= acceptance_code_0_xhdl26;
acceptance_mask_0 <= acceptance_mask_0_xhdl27;
acceptance_code_1 <= acceptance_code_1_xhdl28;
acceptance_code_2 <= acceptance_code_2_xhdl29;
acceptance_code_3 <= acceptance_code_3_xhdl30;
acceptance_mask_1 <= acceptance_mask_1_xhdl31;
acceptance_mask_2 <= acceptance_mask_2_xhdl32;
acceptance_mask_3 <= acceptance_mask_3_xhdl33;
tx_data_0 <= tx_data_0_xhdl34;
tx_data_1 <= tx_data_1_xhdl35;
tx_data_2 <= tx_data_2_xhdl36;
tx_data_3 <= tx_data_3_xhdl37;
tx_data_4 <= tx_data_4_xhdl38;
tx_data_5 <= tx_data_5_xhdl39;
tx_data_6 <= tx_data_6_xhdl40;
tx_data_7 <= tx_data_7_xhdl41;
tx_data_8 <= tx_data_8_xhdl42;
tx_data_9 <= tx_data_9_xhdl43;
tx_data_10 <= tx_data_10_xhdl44;
tx_data_11 <= tx_data_11_xhdl45;
tx_data_12 <= tx_data_12_xhdl46;
we_mode <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000000") ;
we_command <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000001") ;
we_bus_timing_0 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000110")) AND reset_mode_xhdl3 ;
we_bus_timing_1 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000111")) AND reset_mode_xhdl3 ;
we_clock_divider_low <= (cs AND we) AND CONV_STD_LOGIC(addr = "00011111") ;
we_clock_divider_hi <= we_clock_divider_low AND reset_mode_xhdl3 ;
read <= cs AND (NOT we) ;
read_irq_reg <= read AND CONV_STD_LOGIC(addr = "00000011") ;
reset_irq_reg <= read_irq_reg_q and not read_irq_reg;
read_arbitration_lost_capture_reg_xhdl14 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011") ;
read_error_code_capture_reg_xhdl15 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100") ;
we_acceptance_code_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000"))) ;
we_acceptance_mask_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100"))) ;
we_tx_data_0 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000")))) AND transmit_buffer_status ;
we_tx_data_1 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010001")))) AND transmit_buffer_status ;
we_tx_data_2 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010010")))) AND transmit_buffer_status ;
we_tx_data_3 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010011")))) AND transmit_buffer_status ;
we_tx_data_4 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001110")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100")))) AND transmit_buffer_status ;
we_tx_data_5 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001111")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010101")))) AND transmit_buffer_status ;
we_tx_data_6 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010000")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010110")))) AND transmit_buffer_status ;
we_tx_data_7 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010001")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010111")))) AND transmit_buffer_status ;
we_tx_data_8 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011000")))) AND transmit_buffer_status ;
we_tx_data_9 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011001")))) AND transmit_buffer_status ;
we_tx_data_10 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011010"))) AND transmit_buffer_status ;
we_tx_data_11 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011011"))) AND transmit_buffer_status ;
we_tx_data_12 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011100"))) AND transmit_buffer_status ;
we_interrupt_enable <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000100")) AND extended_mode_xhdl24 ;
we_error_warning_limit <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_rx_err_cnt_xhdl22 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_tx_err_cnt_xhdl23 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010001")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010010")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010011")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
-- End: This section is for EXTENDED mode
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
read_irq_reg_q <= read_irq_reg;
tx_successful_q <= tx_successful ;
overrun_q <= overrun ;
transmit_buffer_status_q <= transmit_buffer_status ;
error_status_q <= error_status ;
node_bus_off_q <= node_bus_off ;
node_error_passive_q <= node_error_passive ;
END IF;
END PROCESS;
port_xhdl52 <= data_in(0);
MODE_REG0 : can_register_asyn_syn
GENERIC MAP (1, 1)
PORT MAP (
data_in(0) => port_xhdl52,
data_out(0) => mode,
we => we_mode,
clk => clk,
rst => rst,
rst_sync => set_reset_mode);
MODE_REG_BASIC : can_register_asyn
GENERIC MAP (4, 0)
PORT MAP (
data_in => data_in(4 DOWNTO 1),
data_out => mode_basic(4 DOWNTO 1),
we => we_mode,
clk => clk,
rst => rst);
xhdl_61 <= (we_mode AND reset_mode_xhdl3);
MODE_REG_EXT : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 1),
data_out => mode_ext(3 DOWNTO 1),
we => xhdl_61,
clk => clk,
rst => rst);
reset_mode_xhdl3 <= mode ;
listen_only_mode_xhdl4 <= extended_mode_xhdl24 AND mode_ext(1) ;
self_test_mode_xhdl6 <= extended_mode_xhdl24 AND mode_ext(2) ;
acceptance_filter_mode_xhdl5 <= extended_mode_xhdl24 AND mode_ext(3) ;
receive_irq_en_basic <= mode_basic(1) ;
transmit_irq_en_basic <= mode_basic(2) ;
error_irq_en_basic <= mode_basic(3) ;
overrun_irq_en_basic <= mode_basic(4) ;
xhdl_69 <= (command(0) AND sample_point) OR reset_mode_xhdl3;
port_xhdl70 <= data_in(0);
command(0) <= port_xhdl71;
COMMAND_REG0 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl70,
data_out(0) => port_xhdl71,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_69);
xhdl_77 <= (sample_point AND (tx_request_xhdl10 OR (abort_tx_xhdl9 AND NOT transmitting))) OR reset_mode_xhdl3;
port_xhdl78 <= data_in(1);
command(1) <= port_xhdl79;
COMMAND_REG1 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl78,
data_out(0) => port_xhdl79,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_77);
xhdl_85 <= orv(command(3 DOWNTO 2)) OR reset_mode_xhdl3;
COMMAND_REG : can_register_asyn_syn
GENERIC MAP (2, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 2),
data_out => command(3 DOWNTO 2),
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_85);
xhdl_91 <= (command(4) AND sample_point) OR reset_mode_xhdl3;
port_xhdl92 <= data_in(4);
command(4) <= port_xhdl93;
COMMAND_REG4 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl92,
data_out(0) => port_xhdl93,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_91);
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
self_rx_request_xhdl11 <= '0';
ELSif clk'event and clk = '1' then
IF ((command(4) AND (NOT command(0))) = '1') THEN
self_rx_request_xhdl11 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
self_rx_request_xhdl11 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
clear_data_overrun_xhdl7 <= command(3) ;
release_buffer_xhdl8 <= command(2) ;
tx_request_xhdl10 <= command(0) OR command(4) ;
abort_tx_xhdl9 <= command(1) AND (NOT tx_request_xhdl10) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
single_shot_transmission_xhdl12 <= '0';
ELSif clk'event and clk = '1' then
IF (((tx_request_xhdl10 AND command(1)) AND sample_point) = '1') THEN
single_shot_transmission_xhdl12 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
single_shot_transmission_xhdl12 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
--
-- can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
-- ( .data_in(data_in[5]),
-- .data_out(overload_request),
-- .we(we_command),
-- .clk(clk),
-- .rst(rst),
-- .rst_sync(overload_frame & ~overload_frame_q)
-- );
-- reg overload_frame_q;
-- always @ (posedge clk or posedge rst)
-- begin
-- if (rst)
-- overload_frame_q <= 1'b0;
-- else
-- overload_frame_q <=#Tp overload_frame;
-- end
--
overload_request_xhdl13 <= '0' ;
status(7) <= node_bus_off ;
status(6) <= error_status ;
status(5) <= transmit_status ;
status(4) <= receive_status ;
status(3) <= transmission_complete ;
status(2) <= transmit_buffer_status ;
status(1) <= overrun_status ;
status(0) <= receive_buffer_status ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmission_complete <= '1';
ELSif clk'event and clk = '1' then
IF ((tx_successful AND ((NOT tx_successful_q) OR abort_tx_xhdl9)) = '1') THEN
-- transmission_complete was always set when abort_tx=1
-- Original code:
-- IF (((tx_successful AND (NOT tx_successful_q)) OR abort_tx_xhdl9) = '1') THEN
transmission_complete <= '1' ;
ELSE
IF (tx_request_xhdl10 = '1') THEN
transmission_complete <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_buffer_status <= '1';
ELSif clk'event and clk = '1' then
IF (tx_request_xhdl10 = '1') THEN
transmit_buffer_status <= '0' ;
ELSE
IF ((reset_mode_xhdl3 OR NOT need_to_tx) = '1') THEN
transmit_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overrun_status <= '0';
ELSif clk'event and clk = '1' then
IF ((overrun AND (NOT overrun_q)) = '1') THEN
overrun_status <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR clear_data_overrun_xhdl7) = '1') THEN
overrun_status <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_buffer_status <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_buffer_status <= '0' ;
ELSE
IF (NOT info_empty = '1') THEN
receive_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
IRQ_EN_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => irq_en_ext,
we => we_interrupt_enable,
clk => clk);
bus_error_irq_en <= irq_en_ext(7) ;
arbitration_lost_irq_en <= irq_en_ext(6) ;
error_passive_irq_en <= irq_en_ext(5) ;
data_overrun_irq_en_ext <= irq_en_ext(3) ;
error_warning_irq_en_ext <= irq_en_ext(2) ;
transmit_irq_en_ext <= irq_en_ext(1) ;
receive_irq_en_ext <= irq_en_ext(0) ;
BUS_TIMING_0_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_0,
we => we_bus_timing_0,
clk => clk);
baud_r_presc_xhdl16 <= bus_timing_0(5 DOWNTO 0) ;
sync_jump_width_xhdl17 <= bus_timing_0(7 DOWNTO 6) ;
BUS_TIMING_1_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_1,
we => we_bus_timing_1,
clk => clk);
time_segment1_xhdl18 <= bus_timing_1(3 DOWNTO 0) ;
time_segment2_xhdl19 <= bus_timing_1(6 DOWNTO 4) ;
triple_sampling_xhdl20 <= bus_timing_1(7) ;
-- End Bus Timing 1 register -- Error Warning Limit register
ERROR_WARNING_REG : can_register_asyn
GENERIC MAP (8, 96)
PORT MAP (
data_in => data_in,
data_out => error_warning_limit_xhdl21,
we => we_error_warning_limit,
clk => clk,
rst => rst);
port_xhdl116 <= data_in(7);
clock_divider(7) <= port_xhdl117;
CLOCK_DIVIDER_REG_7 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl116,
data_out(0) => port_xhdl117,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
clock_divider(6 DOWNTO 4) <= "000" ;
port_xhdl123 <= data_in(3);
clock_divider(3) <= port_xhdl124;
CLOCK_DIVIDER_REG_3 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl123,
data_out(0) => port_xhdl124,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
CLOCK_DIVIDER_REG_LOW : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(2 DOWNTO 0),
data_out => clock_divider(2 DOWNTO 0),
we => we_clock_divider_low,
clk => clk,
rst => rst);
extended_mode_xhdl24 <= clock_divider(7) ;
clock_off <= clock_divider(3) ;
cd(2 DOWNTO 0) <= clock_divider(2 DOWNTO 0) ;
PROCESS (cd)
VARIABLE clkout_div_xhdl130 : std_logic_vector(2 DOWNTO 0);
BEGIN
CASE cd IS
-- synthesis full_case parallel_case
WHEN "000" =>
clkout_div_xhdl130 := "000";
WHEN "001" =>
clkout_div_xhdl130 := "001";
WHEN "010" =>
clkout_div_xhdl130 := "010";
WHEN "011" =>
clkout_div_xhdl130 := "011";
WHEN "100" =>
clkout_div_xhdl130 := "100";
WHEN "101" =>
clkout_div_xhdl130 := "101";
WHEN "110" =>
clkout_div_xhdl130 := "110";
WHEN "111" =>
clkout_div_xhdl130 := "000";
WHEN OTHERS =>
NULL;
END CASE;
clkout_div <= clkout_div_xhdl130;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_cnt <= "000";
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_cnt <= "000" ;
ELSE
clkout_cnt <= clkout_cnt + "001";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_tmp <= '0';
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_tmp <= NOT clkout_tmp ;
END IF;
END IF;
END PROCESS;
temp_xhdl131 <= clk WHEN (andv(cd)) = '1' ELSE clkout_tmp;
temp_xhdl132 <= '1' WHEN clock_off = '1' ELSE (temp_xhdl131);
clkout_xhdl25 <= temp_xhdl132 ;
-- End Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register
ACCEPTANCE_CODE_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_0_xhdl26,
we => we_acceptance_code_0,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register
ACCEPTANCE_MASK_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_0_xhdl27,
we => we_acceptance_mask_0,
clk => clk);
-- End: Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- Tx data 0 register.
TX_DATA_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_0_xhdl34,
we => we_tx_data_0,
clk => clk);
-- End: Tx data 0 register. -- Tx data 1 register.
TX_DATA_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_1_xhdl35,
we => we_tx_data_1,
clk => clk);
-- End: Tx data 1 register. -- Tx data 2 register.
TX_DATA_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_2_xhdl36,
we => we_tx_data_2,
clk => clk);
-- End: Tx data 2 register. -- Tx data 3 register.
TX_DATA_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_3_xhdl37,
we => we_tx_data_3,
clk => clk);
-- End: Tx data 3 register. -- Tx data 4 register.
TX_DATA_REG4 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_4_xhdl38,
we => we_tx_data_4,
clk => clk);
-- End: Tx data 4 register. -- Tx data 5 register.
TX_DATA_REG5 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_5_xhdl39,
we => we_tx_data_5,
clk => clk);
-- End: Tx data 5 register. -- Tx data 6 register.
TX_DATA_REG6 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_6_xhdl40,
we => we_tx_data_6,
clk => clk);
-- End: Tx data 6 register. -- Tx data 7 register.
TX_DATA_REG7 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_7_xhdl41,
we => we_tx_data_7,
clk => clk);
-- End: Tx data 7 register. -- Tx data 8 register.
TX_DATA_REG8 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_8_xhdl42,
we => we_tx_data_8,
clk => clk);
-- End: Tx data 8 register. -- Tx data 9 register.
TX_DATA_REG9 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_9_xhdl43,
we => we_tx_data_9,
clk => clk);
-- End: Tx data 9 register. -- Tx data 10 register.
TX_DATA_REG10 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_10_xhdl44,
we => we_tx_data_10,
clk => clk);
-- End: Tx data 10 register. -- Tx data 11 register.
TX_DATA_REG11 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_11_xhdl45,
we => we_tx_data_11,
clk => clk);
-- End: Tx data 11 register. -- Tx data 12 register.
TX_DATA_REG12 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_12_xhdl46,
we => we_tx_data_12,
clk => clk);
-- End: Tx data 12 register. -- This section is for EXTENDED mode -- Acceptance code register 1
ACCEPTANCE_CODE_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_1_xhdl28,
we => we_acceptance_code_1,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 2
ACCEPTANCE_CODE_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_2_xhdl29,
we => we_acceptance_code_2,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 3
ACCEPTANCE_CODE_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_3_xhdl30,
we => we_acceptance_code_3,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 1
ACCEPTANCE_MASK_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_1_xhdl31,
we => we_acceptance_mask_1,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 2
ACCEPTANCE_MASK_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_2_xhdl32,
we => we_acceptance_mask_2,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 3
ACCEPTANCE_MASK_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_3_xhdl33,
we => we_acceptance_mask_3,
clk => clk);
temp_xhdl218 <= acceptance_code_0_xhdl26 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl219 <= acceptance_mask_0_xhdl27 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl220 <= bus_timing_0 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl221 <= bus_timing_1 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl222 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_0_xhdl34;
temp_xhdl223 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_1_xhdl35;
temp_xhdl224 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_2_xhdl36;
temp_xhdl225 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_3_xhdl37;
temp_xhdl226 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_4_xhdl38;
temp_xhdl227 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_5_xhdl39;
temp_xhdl228 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_6_xhdl40;
temp_xhdl229 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_7_xhdl41;
temp_xhdl230 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_8_xhdl42;
temp_xhdl231 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_9_xhdl43;
-- End: Acceptance code register -- End: This section is for EXTENDED mode -- Reading data from registers
PROCESS (addr, extended_mode_xhdl24, mode, bus_timing_0, bus_timing_1, clock_divider,
acceptance_code_0_xhdl26, acceptance_code_1_xhdl28, acceptance_code_2_xhdl29,
acceptance_code_3_xhdl30, acceptance_mask_0_xhdl27, acceptance_mask_1_xhdl31,
acceptance_mask_2_xhdl32, acceptance_mask_3_xhdl33, status,
error_warning_limit_xhdl21, rx_err_cnt, tx_err_cnt, irq_en_ext, irq_reg, mode_ext,
arbitration_lost_capture, rx_message_counter, mode_basic, error_capture_code,
temp_xhdl218, temp_xhdl219, temp_xhdl220, temp_xhdl221, temp_xhdl222, temp_xhdl223,
temp_xhdl224, temp_xhdl225, temp_xhdl226, temp_xhdl227, temp_xhdl228, temp_xhdl229,
temp_xhdl230, temp_xhdl231
)
VARIABLE data_out_xhdl1_xhdl217 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl232 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl232 := extended_mode_xhdl24 & addr(4 DOWNTO 0);
CASE temp_xhdl232 IS
WHEN "100000" =>
data_out_xhdl1_xhdl217 := "0000" & mode_ext(3 DOWNTO 1) & mode; -- extended mode
WHEN "100001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "100010" =>
data_out_xhdl1_xhdl217 := status; -- extended mode
WHEN "100011" =>
data_out_xhdl1_xhdl217 := irq_reg; -- extended mode
WHEN "100100" =>
data_out_xhdl1_xhdl217 := irq_en_ext; -- extended mode
WHEN "100110" =>
data_out_xhdl1_xhdl217 := bus_timing_0; -- extended mode
WHEN "100111" =>
data_out_xhdl1_xhdl217 := bus_timing_1; -- extended mode
WHEN "101011" =>
data_out_xhdl1_xhdl217 := "000" & arbitration_lost_capture(4 DOWNTO 0); -- extended mode
WHEN "101100" =>
data_out_xhdl1_xhdl217 := error_capture_code; -- extended mode
WHEN "101101" =>
data_out_xhdl1_xhdl217 := error_warning_limit_xhdl21; -- extended mode
WHEN "101110" =>
data_out_xhdl1_xhdl217 := rx_err_cnt; -- extended mode
WHEN "101111" =>
data_out_xhdl1_xhdl217 := tx_err_cnt; -- extended mode
WHEN "110000" =>
data_out_xhdl1_xhdl217 := acceptance_code_0_xhdl26; -- extended mode
WHEN "110001" =>
data_out_xhdl1_xhdl217 := acceptance_code_1_xhdl28; -- extended mode
WHEN "110010" =>
data_out_xhdl1_xhdl217 := acceptance_code_2_xhdl29; -- extended mode
WHEN "110011" =>
data_out_xhdl1_xhdl217 := acceptance_code_3_xhdl30; -- extended mode
WHEN "110100" =>
data_out_xhdl1_xhdl217 := acceptance_mask_0_xhdl27; -- extended mode
WHEN "110101" =>
data_out_xhdl1_xhdl217 := acceptance_mask_1_xhdl31; -- extended mode
WHEN "110110" =>
data_out_xhdl1_xhdl217 := acceptance_mask_2_xhdl32; -- extended mode
WHEN "110111" =>
data_out_xhdl1_xhdl217 := acceptance_mask_3_xhdl33; -- extended mode
WHEN "111000" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111010" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111011" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111100" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111101" =>
data_out_xhdl1_xhdl217 := '0' & rx_message_counter; -- extended mode
WHEN "111111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- extended mode
WHEN "000000" =>
data_out_xhdl1_xhdl217 := "001" & mode_basic(4 DOWNTO 1) & mode; -- basic mode
WHEN "000001" =>
data_out_xhdl1_xhdl217 := "11111111"; -- basic mode
WHEN "000010" =>
data_out_xhdl1_xhdl217 := status; -- basic mode
WHEN "000011" =>
data_out_xhdl1_xhdl217 := "1110" & irq_reg(3 DOWNTO 0); -- basic mode
WHEN "000100" =>
data_out_xhdl1_xhdl217 := temp_xhdl218;
WHEN "000101" =>
data_out_xhdl1_xhdl217 := temp_xhdl219;
WHEN "000110" =>
data_out_xhdl1_xhdl217 := temp_xhdl220;
WHEN "000111" =>
data_out_xhdl1_xhdl217 := temp_xhdl221;
WHEN "001010" =>
data_out_xhdl1_xhdl217 := temp_xhdl222;
WHEN "001011" =>
data_out_xhdl1_xhdl217 := temp_xhdl223;
WHEN "001100" =>
data_out_xhdl1_xhdl217 := temp_xhdl224;
WHEN "001101" =>
data_out_xhdl1_xhdl217 := temp_xhdl225;
WHEN "001110" =>
data_out_xhdl1_xhdl217 := temp_xhdl226;
WHEN "001111" =>
data_out_xhdl1_xhdl217 := temp_xhdl227;
WHEN "010000" =>
data_out_xhdl1_xhdl217 := temp_xhdl228;
WHEN "010001" =>
data_out_xhdl1_xhdl217 := temp_xhdl229;
WHEN "010010" =>
data_out_xhdl1_xhdl217 := temp_xhdl230;
WHEN "010011" =>
data_out_xhdl1_xhdl217 := temp_xhdl231;
WHEN "011111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- basic mode
WHEN OTHERS =>
data_out_xhdl1_xhdl217 := "00000000"; -- the rest is read as 0
END CASE;
data_out_xhdl1 <= data_out_xhdl1_xhdl217;
END PROCESS;
temp_xhdl233 <= data_overrun_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE overrun_irq_en_basic;
data_overrun_irq_en <= temp_xhdl233 ;
temp_xhdl234 <= error_warning_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE error_irq_en_basic;
error_warning_irq_en <= temp_xhdl234 ;
temp_xhdl235 <= transmit_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE transmit_irq_en_basic;
transmit_irq_en <= temp_xhdl235 ;
temp_xhdl236 <= receive_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE receive_irq_en_basic;
receive_irq_en <= temp_xhdl236 ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_overrun_irq <= '0';
ELSif clk'event and clk = '1' then
IF (((overrun AND (NOT overrun_q)) AND data_overrun_irq_en) = '1') THEN
data_overrun_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
data_overrun_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
transmit_irq <= '0' ;
ELSE
IF (((transmit_buffer_status AND (NOT transmit_buffer_status_q)) AND transmit_irq_en) = '1') THEN
transmit_irq <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((NOT info_empty) AND (NOT receive_irq)) AND receive_irq_en) = '1') THEN
receive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((error_status XOR error_status_q) OR (node_bus_off XOR node_bus_off_q)) AND error_warning_irq_en) = '1') THEN
error_irq <= '1' ;
ELSE
IF (reset_irq_reg = '1') THEN
error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_bus_error_irq AND bus_error_irq_en) = '1') THEN
bus_error_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
bus_error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_arbitration_lost_irq AND arbitration_lost_irq_en) = '1') THEN
arbitration_lost_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
arbitration_lost_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_passive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((node_error_passive AND (NOT node_error_passive_q)) OR (((NOT node_error_passive) AND node_error_passive_q) AND node_error_active)) AND error_passive_irq_en) = '1') THEN
error_passive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
error_passive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
irq_reg <= bus_error_irq & arbitration_lost_irq & error_passive_irq & '0' & data_overrun_irq & error_irq & transmit_irq & receive_irq ;
irq <= data_overrun_irq OR transmit_irq OR receive_irq OR error_irq OR bus_error_irq OR arbitration_lost_irq OR error_passive_irq ;
-- irq_o reset change /Kristoffer 2006-02-23 PROCESS (clk, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSif clk'event and clk = '1' then
-- IF (reset_irq_reg = '1' or release_buffer_xhdl8='1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSE
-- IF (irq = '1') THEN
-- irq_n_xhdl2 <= '0' ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1' or release_buffer_xhdl8 = '1') THEN
irq_n_xhdl2 <= '1';
ELSif clk'event and clk = '1' then
irq_n_xhdl2 <= not irq;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top IS
PORT (
-- wb_clk_i : IN std_logic;
-- wb_rst_i : IN std_logic;
-- wb_dat_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_dat_o : OUT std_logic_vector(7 DOWNTO 0);
-- wb_cyc_i : IN std_logic;
-- wb_stb_i : IN std_logic;
-- wb_we_i : IN std_logic;
-- wb_adr_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_ack_o : OUT std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
cs : IN std_logic;
we : IN std_logic;
clk_i : IN std_logic;
rx_i : IN std_logic;
tx_o : OUT std_logic;
bus_off_on : OUT std_logic;
irq_on : OUT std_logic;
clkout_o : OUT std_logic;
-- Bist
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_top;
ARCHITECTURE RTL OF can_top IS
COMPONENT can_bsp
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : IN std_logic;
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_btl
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
COMPONENT can_registers
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
read_arbitration_lost_capture_reg: OUT std_logic;
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : OUT std_logic;
we_tx_err_cnt : OUT std_logic;
extended_mode : OUT std_logic;
clkout : OUT std_logic;
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
-- SIGNAL cs_sync1 : std_logic;
-- SIGNAL cs_sync2 : std_logic;
-- SIGNAL cs_sync3 : std_logic;
-- SIGNAL cs_ack1 : std_logic;
-- SIGNAL cs_ack2 : std_logic;
-- SIGNAL cs_ack3 : std_logic;
-- SIGNAL cs_sync_rst1 : std_logic;
-- SIGNAL cs_sync_rst2 : std_logic;
-- SIGNAL cs_can_i : std_logic;
---------------------------------
SIGNAL data_out_fifo_selected : std_logic;
SIGNAL data_out_fifo : std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_regs : std_logic_vector(7 DOWNTO 0);
-- Mode register
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL acceptance_filter_mode : std_logic;
SIGNAL self_test_mode : std_logic;
-- Command register
SIGNAL release_buffer : std_logic;
SIGNAL tx_request : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
-- Arbitration Lost Capture Register
SIGNAL read_arbitration_lost_capture_reg: std_logic;
-- Error Code Capture Register
SIGNAL read_error_code_capture_reg : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
SIGNAL baud_r_presc : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width : std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
SIGNAL time_segment1 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling : std_logic;
-- Error Warning Limit register
SIGNAL error_warning_limit : std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
SIGNAL we_rx_err_cnt : std_logic;
-- Tx Error Counter register
SIGNAL we_tx_err_cnt : std_logic;
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_0 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_0 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
-- SIGNAL cs : std_logic;
-- Output signals from can_btl module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL set_reset_mode : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL error_status : std_logic;
SIGNAL rx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL tx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL info_empty : std_logic;
SIGNAL set_bus_error_irq : std_logic;
SIGNAL set_arbitration_lost_irq : std_logic;
SIGNAL arbitration_lost_capture : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL rx_message_counter : std_logic_vector(6 DOWNTO 0);
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
-- SIGNAL we : std_logic;
-- SIGNAL addr : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_in : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
-- From btl module
-- Mode register
-- Command register
-- Arbitration Lost Capture Register
-- Error Code Capture Register
-- Error Warning Limit register
-- Rx Error Counter register
-- Tx Error Counter register
-- Clock Divider register
-- output from can_bsp module
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
-- SIGNAL wb_dat_o_xhdl1 : std_logic_vector(7 DOWNTO 0);
-- SIGNAL wb_ack_o_xhdl2 : std_logic;
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL bus_off_on_xhdl4 : std_logic;
SIGNAL irq_on_xhdl5 : std_logic;
SIGNAL clkout_o_xhdl6 : std_logic;
SIGNAL data_64x8_xhdl7 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl8 : std_logic;
SIGNAL rden_64x8_xhdl9 : std_logic;
SIGNAL wraddress_64x8_xhdl10 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl11 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl12 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl13 : std_logic;
SIGNAL wraddress_64x4x1_xhdl14 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl15 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl16 : std_logic;
SIGNAL rx_inter : std_logic;
BEGIN
-- wb_dat_o <= wb_dat_o_xhdl1;
-- wb_ack_o <= wb_ack_o_xhdl2;
tx_o <= tx_o_xhdl3;
bus_off_on <= bus_off_on_xhdl4;
irq_on <= irq_on_xhdl5;
clkout_o <= clkout_o_xhdl6;
data_64x8 <= data_64x8_xhdl7;
wren_64x8 <= wren_64x8_xhdl8;
rden_64x8 <= rden_64x8_xhdl9;
wraddress_64x8 <= wraddress_64x8_xhdl10;
rdaddress_64x8 <= rdaddress_64x8_xhdl11;
data_64x4 <= data_64x4_xhdl12;
wren_64x4x1 <= wren_64x4x1_xhdl13;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl14;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl15;
data_64x1 <= data_64x1_xhdl16;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl7 <= w_data_64x8 ;
wren_64x8_xhdl8 <= w_wren_64x8 ;
rden_64x8_xhdl9 <= w_rden_64x8 ;
wraddress_64x8_xhdl10 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl11 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl12 <= w_data_64x4 ;
wren_64x4x1_xhdl13 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl14 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl15 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl16 <= w_data_64x1 ;
-- Connecting can_registers module -- Mode register -- Command register -- Arbitration Lost Capture Register -- Error Code Capture Register -- Bus Timing 0 register -- Bus Timing 1 register -- Error Warning Limit register -- Rx Error Counter register -- Tx Error Counter register -- Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers
i_can_registers : can_registers
PORT MAP (
clk => clk_i,
rst => rst,
cs => cs,
we => we,
addr => addr,
data_in => data_in,
data_out => data_out_regs,
irq_n => irq_on_xhdl5,
sample_point => sample_point,
transmitting => transmitting,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => rx_err_cnt,
tx_err_cnt => tx_err_cnt,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
clear_data_overrun => open,
release_buffer => release_buffer,
abort_tx => abort_tx,
tx_request => tx_request,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
clkout => clkout_o_xhdl6,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12);
-- Connecting can_btl module -- Bus Timing 0 register -- Bus Timing 1 register -- Output signals from this module -- output from can_bsp module
i_can_btl : can_btl
PORT MAP (
clk => clk_i,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- xhdl_148 <= rx_err_cnt_dummy & rx_err_cnt(7 DOWNTO 0);
rx_err_cnt_dummy <= xhdl_148(8);
rx_err_cnt(7 DOWNTO 0) <= xhdl_148(7 DOWNTO 0);
-- xhdl_150 <= tx_err_cnt_dummy & tx_err_cnt(7 DOWNTO 0);
tx_err_cnt_dummy <= xhdl_150(8);
tx_err_cnt(7 DOWNTO 0) <= xhdl_150(7 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
-- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers -- Tx signal -- port connections for Ram
--64x8
--64x4
--64x1
i_can_bsp : can_bsp
PORT MAP (
clk => clk_i,
rst => rst,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
addr => addr,
data_in => data_in,
data_out => data_out_fifo,
fifo_selected => data_out_fifo_selected,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
release_buffer => release_buffer,
tx_request => tx_request,
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
tx => tx_o_xhdl3,
tx_next => tx_next,
bus_off_on => bus_off_on_xhdl4,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Multiplexing wb_dat_o from registers and rx fifo
PROCESS (extended_mode, addr, reset_mode)
VARIABLE data_out_fifo_selected_xhdl203 : std_logic;
BEGIN
IF ((((extended_mode AND (NOT reset_mode)) AND CONV_STD_LOGIC((addr >= "00010000") AND (addr<="00011100"))) OR ((NOT extended_mode) AND CONV_STD_LOGIC((addr >= "00010100") AND (addr<="00011101")))) = '1') THEN
data_out_fifo_selected_xhdl203 := '1';
ELSE
data_out_fifo_selected_xhdl203 := '0';
END IF;
data_out_fifo_selected <= data_out_fifo_selected_xhdl203;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cs AND (NOT we)) = '1') THEN
IF (data_out_fifo_selected = '1') THEN
data_out <= data_out_fifo ;
ELSE
data_out <= data_out_regs ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i, rst)
BEGIN
IF (rst = '1') THEN
rx_sync_tmp <= '1';
rx_sync <= '1';
ELSIF (clk_i'EVENT AND clk_i = '1') THEN
rx_sync_tmp <= rx_i ;
rx_sync <= rx_sync_tmp ;
END IF;
END PROCESS;
-- cs_can_i <= '1' ;
-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
-- PROCESS (clk_i, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- cs_sync1 <= '0';
-- cs_sync2 <= '0';
-- cs_sync3 <= '0';
-- cs_sync_rst1 <= '0';
-- cs_sync_rst2 <= '0';
-- ELSIF (clk_i'EVENT AND clk_i = '1') THEN
-- cs_sync1 <= ((wb_cyc_i AND wb_stb_i) AND (NOT cs_sync_rst2)) AND cs_can_i ;
-- cs_sync2 <= cs_sync1 AND (NOT cs_sync_rst2) ;
-- cs_sync3 <= cs_sync2 AND (NOT cs_sync_rst2) ;
-- cs_sync_rst1 <= cs_ack3 ;
-- cs_sync_rst2 <= cs_sync_rst1 ;
-- END IF;
-- END PROCESS;
-- cs <= cs_sync2 AND (NOT cs_sync3) ;
--
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- cs_ack1 <= cs_sync3 ;
-- cs_ack2 <= cs_ack1 ;
-- cs_ack3 <= cs_ack2 ;
-- END IF;
-- END PROCESS;
-- Generating acknowledge signal
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- wb_ack_o_xhdl2 <= cs_ack2 AND (NOT cs_ack3) ;
-- END IF;
-- END PROCESS;
-- rst <= wb_rst_i ;
-- we <= wb_we_i ;
-- addr <= wb_adr_i ;
-- data_in <= wb_dat_i ;
-- wb_dat_o_xhdl1 <= data_out ;
END ARCHITECTURE RTL;
|
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_acf.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_acf.v,v $
-- Revision 1.10 2005/04/08 13:03:07 igorm
-- In "Extended mode" when dual filter was used and standard frame received,
-- upper nibble of the data was not filtered ok.
--
-- Revision 1.9 2004/05/31 14:46:11 igorm
-- Bit acceptance_filter_mode was inverted.
--
-- Revision 1.8 2004/02/08 14:16:44 mohor
-- Header changed.
--
-- Revision 1.7 2003/07/16 13:41:34 mohor
-- Fixed according to the linter.
--
-- Revision 1.6 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.5 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.4 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.3 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.2 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.1 2003/01/08 02:13:15 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_acf IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END ENTITY can_acf;
ARCHITECTURE RTL OF can_acf IS
SIGNAL match : std_logic;
SIGNAL match_sf_std : std_logic;
SIGNAL match_sf_ext : std_logic;
SIGNAL match_df_std : std_logic;
SIGNAL match_df_ext : std_logic;
SIGNAL id_ok_xhdl1 : std_logic;
BEGIN
id_ok <= id_ok_xhdl1;
-- Working in basic mode. ID match for standard format (11-bit ID).
match <= (((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1)) OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3)) OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5)) OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7)) OR acceptance_mask_0(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
match_sf_std <= (((((((((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_2(0)) OR acceptance_mask_2(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_2(1))
OR acceptance_mask_2(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_2(2)) OR acceptance_mask_2(2)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_2(3)) OR acceptance_mask_2(3) OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_2(4))
OR acceptance_mask_2(4) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_2(5)) OR acceptance_mask_2(5) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_2(6))
OR acceptance_mask_2(6) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_2(7)) OR acceptance_mask_2(7) OR no_byte0)) AND (CONV_STD_LOGIC(data1(0) = acceptance_code_3(0))
OR acceptance_mask_3(0) OR no_byte1)) AND (CONV_STD_LOGIC(data1(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte1)) AND (CONV_STD_LOGIC(data1(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte1)) AND (CONV_STD_LOGIC(data1(3) = acceptance_code_3(3)) OR acceptance_mask_3(3) OR no_byte1)) AND (CONV_STD_LOGIC(data1(4) = acceptance_code_3(4))
OR acceptance_mask_3(4) OR no_byte1)) AND (CONV_STD_LOGIC(data1(5) = acceptance_code_3(5)) OR acceptance_mask_3(5) OR no_byte1)) AND (CONV_STD_LOGIC(data1(6) = acceptance_code_3(6))
OR acceptance_mask_3(6) OR no_byte1)) AND (CONV_STD_LOGIC(data1(7) = acceptance_code_3(7)) OR acceptance_mask_3(7) OR no_byte1) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
match_sf_ext <= (((((((((((((((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(0)) OR acceptance_mask_2(0))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(11) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(12) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr2 = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(3) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(4) = acceptance_code_3(7))
OR acceptance_mask_3(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
match_df_std <= ((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_3(0)) OR acceptance_mask_3(0)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_3(3)) OR acceptance_mask_3(3)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_1(0)) OR acceptance_mask_1(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_1(1))
OR acceptance_mask_1(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_1(2))
OR acceptance_mask_1(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_1(3)) OR acceptance_mask_1(3) OR no_byte0))
OR ((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
match_df_ext <= ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) OR ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_3(0)) OR acceptance_mask_3(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_3(1))
OR acceptance_mask_3(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- ID ok signal generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id_ok_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_rx_crc_lim = '1') THEN
-- sample_point is already included in go_rx_crc_lim
IF (extended_mode = '1') THEN
IF (NOT acceptance_filter_mode = '1') THEN
-- dual filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_df_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_df_std ;
END IF;
ELSE
-- single filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_sf_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_sf_std ;
END IF;
END IF;
ELSE
id_ok_xhdl1 <= match ;
END IF;
ELSE
IF ((reset_mode OR go_rx_inter OR go_error_frame) = '1') THEN
-- sample_point is already included in go_rx_inter
id_ok_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl;
ARCHITECTURE RTL OF can_btl IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
resync_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg1 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
quant_cnt <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delay <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sample <= "11";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') THEN
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_next_sp <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync_blocked <= '1' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_fifo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_fifo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- Rev 1.28 rd_info_pointer fix from opencores merged. /Kristoffer
--
-- $Log: can_fifo.v,v $
-- Revision 1.27 2004/11/18 12:39:34 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.26 2004/02/08 14:30:57 mohor
-- Header changed.
--
-- Revision 1.25 2003/10/23 16:52:17 mohor
-- Active high/low problem when Altera devices are used. Bug fixed by
-- Rojhalat Ibrahim.
--
-- Revision 1.24 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.23 2003/09/05 12:46:41 mohor
-- ALTERA_RAM supported.
--
-- Revision 1.22 2003/08/20 09:59:16 mohor
-- Artisan RAM fixed (when not using BIST).
--
-- Revision 1.21 2003/08/14 16:04:52 simons
-- Artisan ram instances added.
--
-- Revision 1.20 2003/07/16 14:00:45 mohor
-- Fixed according to the linter.
--
-- Revision 1.19 2003/07/03 09:30:44 mohor
-- PCI_BIST replaced with CAN_BIST.
--
-- Revision 1.18 2003/06/27 22:14:23 simons
-- Overrun fifo implemented with FFs, because it is not possible to create such a memory.
--
-- Revision 1.17 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16 2003/06/18 23:03:44 mohor
-- Typo fixed.
--
-- Revision 1.15 2003/06/11 09:37:05 mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14 2003/03/05 15:02:30 mohor
-- Xilinx RAM added.
--
-- Revision 1.13 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.12 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.9 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.7 2003/01/17 17:44:31 mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.3 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.1 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_fifo IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
--------------------------------------------------
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_fifo;
ARCHITECTURE RTL OF can_fifo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
--------------------------------------------------
SIGNAL fifo : xhdl_15;
SIGNAL length_fifo : xhdl_16;
SIGNAL overrun_info : xhdl_17;
SIGNAL rd_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL read_address : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_q : std_logic;
SIGNAL len_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL fifo_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL latch_overrun : std_logic;
SIGNAL initialize_memories : std_logic;
SIGNAL length_info : std_logic_vector(3 DOWNTO 0);
SIGNAL write_length_info : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL info_full : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL overrun_xhdl2 : std_logic;
SIGNAL info_empty_xhdl3 : std_logic;
SIGNAL info_cnt_xhdl4 : std_logic_vector(6 DOWNTO 0);
SIGNAL data_64x8_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl6 : std_logic;
SIGNAL rden_64x8_xhdl7 : std_logic;
SIGNAL wraddress_64x8_xhdl8 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl9 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl10 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl11 : std_logic;
SIGNAL wraddress_64x4x1_xhdl12 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl13 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl14 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
overrun <= overrun_xhdl2;
info_empty <= info_empty_xhdl3;
info_cnt <= info_cnt_xhdl4;
data_64x8 <= data_64x8_xhdl5;
wren_64x8 <= wren_64x8_xhdl6;
rden_64x8 <= rden_64x8_xhdl7;
wraddress_64x8 <= wraddress_64x8_xhdl8;
rdaddress_64x8 <= rdaddress_64x8_xhdl9;
data_64x4 <= data_64x4_xhdl10;
wren_64x4x1 <= wren_64x4x1_xhdl11;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
data_64x1 <= data_64x1_xhdl14;
write_length_info <= (NOT wr) AND wr_q ;
-- Delayed write signal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_q <= '0' ;
ELSE
wr_q <= wr ;
END IF;
END IF;
END PROCESS;
-- length counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
len_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
len_cnt <= "0000" ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
len_cnt <= len_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- wr_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
wr_info_pointer <= wr_info_pointer + "000001" ;
ELSE
IF (reset_mode = '1') THEN
wr_info_pointer <= rd_info_pointer ;
END IF;
END IF;
END IF;
END PROCESS;
-- rd_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
-- Fix from opencores rev 1.28
-- IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_info_pointer <= rd_info_pointer + "000001" ;
END IF;
END IF;
END PROCESS;
-- rd_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_pointer <= rd_pointer + ("00" & length_info) ;
END IF;
END IF;
END PROCESS;
-- wr_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_pointer <= rd_pointer ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
wr_pointer <= wr_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- latch_overrun
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
latch_overrun <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
latch_overrun <= '0' ;
ELSE
IF ((wr AND fifo_full) = '1') THEN
latch_overrun <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Counting data in fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
fifo_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
fifo_cnt <= "0000000" ;
ELSE
IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
fifo_cnt <= fifo_cnt + "0000001" ;
ELSE
IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) ;
ELSE
IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;
-- Counting data in length_fifo and overrun_info fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSE
IF ((write_length_info XOR release_buffer) = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;
ELSE
IF ((write_length_info AND (NOT info_full)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;
-- Selecting which address will be used for reading data from rx fifo
PROCESS (extended_mode, rd_pointer, addr)
VARIABLE read_address_xhdl18 : std_logic_vector(5 DOWNTO 0);
BEGIN
IF (extended_mode = '1') THEN
-- extended mode
read_address_xhdl18 := rd_pointer + (addr - "010000");
ELSE
-- normal mode
read_address_xhdl18 := rd_pointer + (addr - "010100");
END IF;
read_address <= read_address_xhdl18;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
initialize_memories <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (andv(wr_info_pointer) = '1') THEN
initialize_memories <= '0' ;
END IF;
END IF;
END PROCESS;
-- port connections for Ram
--64x8
data_out_xhdl1 <= q_dp_64x8 ;
data_64x8_xhdl5 <= data_in ;
wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
rden_64x8_xhdl7 <= fifo_selected ;
wraddress_64x8_xhdl8 <= wr_pointer ;
rdaddress_64x8_xhdl9 <= read_address ;
--64x4
length_info <= q_dp_64x4 ;
data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
--64x1
overrun_xhdl2 <= q_dp_64x1 ;
data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
-- `ifdef ALTERA_RAM
-- // altera_ram_64x8_sync fifo
-- lpm_ram_dp fifo
-- (
-- .q (data_out),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (data_in),
-- .wren (wr & (~fifo_full)),
-- .rden (fifo_selected),
-- .wraddress (wr_pointer),
-- .rdaddress (read_address)
-- );
-- defparam fifo.lpm_width = 8;
-- defparam fifo.lpm_widthad = 6;
-- defparam fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x4_sync info_fifo
-- lpm_ram_dp info_fifo
-- (
-- .q (length_info),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (len_cnt & {4{~initialize_memories}}),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam info_fifo.lpm_width = 4;
-- defparam info_fifo.lpm_widthad = 6;
-- defparam info_fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x1_sync overrun_fifo
-- lpm_ram_dp overrun_fifo
-- (
-- .q (overrun),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam overrun_fifo.lpm_width = 1;
-- defparam overrun_fifo.lpm_widthad = 6;
-- defparam overrun_fifo.lpm_numwords = 64;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc;
ARCHITECTURE RTL OF can_crc IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_ibo IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo;
ARCHITECTURE RTL OF can_ibo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : IN std_logic;
-- Tx Error Counter register
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers -- Tx signal
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
-- Bist -- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_bsp;
ARCHITECTURE RTL OF can_bsp IS
COMPONENT can_acf
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END COMPONENT;
COMPONENT can_crc
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_fifo
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_ibo
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL set_reset_mode_xhdl12 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL error_status_xhdl14 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL info_empty_xhdl22 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL rx_message_counter_xhdl28: std_logic_vector(6 DOWNTO 0);
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL bus_off_on_xhdl31 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
SIGNAL data_64x8_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl37 : std_logic;
SIGNAL rden_64x8_xhdl38 : std_logic;
SIGNAL wraddress_64x8_xhdl39 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl40 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl41 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl42 : std_logic;
SIGNAL wraddress_64x4x1_xhdl43 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl44 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl45 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
set_reset_mode <= set_reset_mode_xhdl12;
node_bus_off <= node_bus_off_xhdl13;
error_status <= error_status_xhdl14;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
info_empty <= info_empty_xhdl22;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
rx_message_counter <= rx_message_counter_xhdl28;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
bus_off_on <= bus_off_on_xhdl31;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
data_64x8 <= data_64x8_xhdl36;
wren_64x8 <= wren_64x8_xhdl37;
rden_64x8 <= rden_64x8_xhdl38;
wraddress_64x8 <= wraddress_64x8_xhdl39;
rdaddress_64x8 <= rdaddress_64x8_xhdl40;
data_64x4 <= data_64x4_xhdl41;
wren_64x4x1 <= wren_64x4x1_xhdl42;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl43;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl44;
data_64x1 <= data_64x1_xhdl45;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl36 <= w_data_64x8 ;
wren_64x8_xhdl37 <= w_wren_64x8 ;
rden_64x8_xhdl38 <= w_rden_64x8 ;
wraddress_64x8_xhdl39 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl40 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl41 <= w_data_64x4 ;
wren_64x4x1_xhdl42 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl43 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl44 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl45 <= w_data_64x1 ;
-- ----------------------
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r0 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_dlc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_data <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_eof <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_len <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tmp_data <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
byte_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
IF ((sample_point AND go_rx_crc_lim) = '1') THEN
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write_data_to_tmp_fifo = '1') THEN
tmp_fifo(conv_integer(byte_cnt)) <= tmp_data ;
END IF;
END IF;
END PROCESS;
-- CRC
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_in <= "000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_cnt <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
eof_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_enable <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_err <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ack_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
stuff_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
form_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_rx : can_crc
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
port_xhdl73 <= tmp_fifo(0);
port_xhdl74 <= tmp_fifo(1);
i_can_acf : can_acf
PORT MAP (
clk => clk,
rst => rst,
id => id,
reset_mode => reset_mode,
acceptance_filter_mode => acceptance_filter_mode,
extended_mode => extended_mode,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
go_rx_crc_lim => go_rx_crc_lim,
go_rx_inter => go_rx_inter_xhdl9,
go_error_frame => go_error_frame_xhdl33,
data0 => port_xhdl73,
data1 => port_xhdl74,
rtr1 => rtr1,
rtr2 => rtr2,
ide => ide,
no_byte0 => no_byte0,
no_byte1 => no_byte1,
id_ok => id_ok);
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
header_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
PROCESS (extended_mode, ide, data_cnt, header_cnt, header_len, storing_header, id, rtr1, rtr2, data_len, tmp_fifo)
VARIABLE data_for_fifo_xhdl79 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl80 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl80 := storing_header & extended_mode & ide & header_cnt;
IF (std_match(temp_xhdl80, "111000")) THEN
data_for_fifo_xhdl79 := '1' & rtr2 & "00" & data_len; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111001")) THEN
data_for_fifo_xhdl79 := id(28 DOWNTO 21); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111010")) THEN
data_for_fifo_xhdl79 := id(20 DOWNTO 13); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111011")) THEN
data_for_fifo_xhdl79 := id(12 DOWNTO 5); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111100")) THEN
data_for_fifo_xhdl79 := id(4 DOWNTO 0) & rtr2 & "00"; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "110000")) THEN
data_for_fifo_xhdl79 := '0' & rtr1 & "00" & data_len; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110001")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110010")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & "0000"; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "10-000")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- normal mode header
ELSIF (std_match(temp_xhdl80, "10-001")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & data_len; -- normal mode header
ELSE
data_for_fifo_xhdl79 := tmp_fifo(conv_integer(data_cnt - ('0' & header_len)) mod 8); -- data
END IF;
data_for_fifo <= data_for_fifo_xhdl79;
END PROCESS;
-- Instantiation of the RX fifo module
-- port connections for Ram
--64x8
--64x4
--64x1
i_can_fifo : can_fifo
PORT MAP (
clk => clk,
rst => rst,
wr => wr_fifo,
data_in => data_for_fifo,
addr => addr(5 DOWNTO 0),
data_out => data_out_xhdl1,
fifo_selected => fifo_selected,
reset_mode => reset_mode,
release_buffer => release_buffer,
extended_mode => extended_mode,
overrun => overrun_xhdl21,
info_empty => info_empty_xhdl22,
info_cnt => rx_message_counter_xhdl28,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_frame <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_flag_over_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
passive_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
first_compare_bit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_request_cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_xhdl29 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
go_early_tx_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
suspend <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
finish_msg <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((we_rx_err_cnt AND (NOT node_bus_off_xhdl13)) = '1') THEN
rx_err_cnt_xhdl15 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
ELSE
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we_tx_err_cnt = '1') THEN
tx_err_cnt_xhdl16 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in < "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in = "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bus_off_on_xhdl31 <= NOT node_bus_off_xhdl13 ;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ;
temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit))) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000"));
error_status_xhdl14 <= CONV_STD_LOGIC(temp_xhdl110) ;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register.v,v $
-- Revision 1.7 2004/02/08 14:32:31 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_register IS
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END ENTITY can_register;
ARCHITECTURE RTL OF can_register IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn.v,v $
-- Revision 1.7 2004/02/08 14:33:19 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END ENTITY can_register_asyn;
ARCHITECTURE RTL OF can_register_asyn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
-- asynchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn_syn.v,v $
-- Revision 1.7 2004/02/08 14:33:59 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:52:43 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_asyn_syn;
ARCHITECTURE RTL OF can_register_asyn_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_syn.v,v $
-- Revision 1.5 2004/02/08 14:34:40 mohor
-- Header changed.
--
-- Revision 1.4 2003/03/11 16:31:58 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_syn;
ARCHITECTURE RTL OF can_register_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, 8);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_registers
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_registers.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
-- Revision 1.36 2005/03/18 15:04:05 igorm
-- Wake-up interrupt was generated in some cases.
--
-- Revision 1.35 2004/11/30 15:08:26 igorm
-- irq is cleared after the release_buffer command. This bug was entered with
-- changes for the edge triggered interrupts.
--
-- Revision 1.34 2004/11/18 12:39:43 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.33 2004/10/25 11:44:38 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.32 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.31 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.30 2003/07/16 15:19:34 mohor
-- Fixed according to the linter.
-- Case statement for data_out joined.
--
-- Revision 1.29 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.28 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.27 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.26 2003/06/22 01:33:14 mohor
-- clkout is clk/2 after the reset.
--
-- Revision 1.25 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.24 2003/06/09 11:22:54 mohor
-- data_out is already registered in the can_top.v file.
--
-- Revision 1.23 2003/04/15 15:31:24 mohor
-- Some features are supported in extended mode only (listen_only_mode...).
--
-- Revision 1.22 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.20 2003/03/11 16:31:05 mohor
-- Mux used for clkout to avoid "gated clocks warning".
--
-- Revision 1.19 2003/03/10 17:34:25 mohor
-- Doubled declarations removed.
--
-- Revision 1.18 2003/03/01 22:52:11 mohor
-- Data is latched on read.
--
-- Revision 1.17 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.16 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.15 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.14 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.13 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.12 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.11 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.6 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.5 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.4 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_registers IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
-- Mode register
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
-- Command register
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: OUT std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
-- Error Warning Limit register
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : OUT std_logic;
-- Tx Error Counter register
we_tx_err_cnt : OUT std_logic;
-- Clock Divider register
extended_mode : OUT std_logic;
clkout : OUT std_logic;
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_registers;
ARCHITECTURE RTL OF can_registers IS
CONSTANT xhdl_timescale : time := 1 ns;
COMPONENT can_register
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn_syn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END COMPONENT;
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
signal read_irq_reg_q : std_logic;
signal reset_irq_reg : std_logic;
SIGNAL tx_successful_q : std_logic;
SIGNAL overrun_q : std_logic;
SIGNAL overrun_status : std_logic;
SIGNAL transmission_complete : std_logic;
SIGNAL transmit_buffer_status_q : std_logic;
SIGNAL receive_buffer_status : std_logic;
SIGNAL error_status_q : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL node_error_passive_q : std_logic;
SIGNAL transmit_buffer_status : std_logic;
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL data_overrun_irq_en : std_logic;
SIGNAL error_warning_irq_en : std_logic;
SIGNAL transmit_irq_en : std_logic;
SIGNAL receive_irq_en : std_logic;
SIGNAL irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL irq : std_logic;
SIGNAL we_mode : std_logic;
SIGNAL we_command : std_logic;
SIGNAL we_bus_timing_0 : std_logic;
SIGNAL we_bus_timing_1 : std_logic;
SIGNAL we_clock_divider_low : std_logic;
SIGNAL we_clock_divider_hi : std_logic;
SIGNAL read : std_logic;
SIGNAL read_irq_reg : std_logic;
-- This section is for BASIC and EXTENDED mode
SIGNAL we_acceptance_code_0 : std_logic;
SIGNAL we_acceptance_mask_0 : std_logic;
SIGNAL we_tx_data_0 : std_logic;
SIGNAL we_tx_data_1 : std_logic;
SIGNAL we_tx_data_2 : std_logic;
SIGNAL we_tx_data_3 : std_logic;
SIGNAL we_tx_data_4 : std_logic;
SIGNAL we_tx_data_5 : std_logic;
SIGNAL we_tx_data_6 : std_logic;
SIGNAL we_tx_data_7 : std_logic;
SIGNAL we_tx_data_8 : std_logic;
SIGNAL we_tx_data_9 : std_logic;
SIGNAL we_tx_data_10 : std_logic;
SIGNAL we_tx_data_11 : std_logic;
SIGNAL we_tx_data_12 : std_logic;
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
SIGNAL we_interrupt_enable : std_logic;
SIGNAL we_error_warning_limit : std_logic;
SIGNAL we_acceptance_code_1 : std_logic;
SIGNAL we_acceptance_code_2 : std_logic;
SIGNAL we_acceptance_code_3 : std_logic;
SIGNAL we_acceptance_mask_1 : std_logic;
SIGNAL we_acceptance_mask_2 : std_logic;
SIGNAL we_acceptance_mask_3 : std_logic;
-- Mode register
SIGNAL mode : std_logic;
SIGNAL mode_basic : std_logic_vector(4 DOWNTO 1);
SIGNAL mode_ext : std_logic_vector(3 DOWNTO 1);
SIGNAL receive_irq_en_basic : std_logic;
SIGNAL transmit_irq_en_basic : std_logic;
SIGNAL error_irq_en_basic : std_logic;
SIGNAL overrun_irq_en_basic : std_logic;
SIGNAL port_xhdl52 : std_logic;
SIGNAL xhdl_61 : std_logic;
-- End Mode register
-- Command register
SIGNAL command : std_logic_vector(4 DOWNTO 0);
SIGNAL xhdl_69 : std_logic;
SIGNAL port_xhdl70 : std_logic;
SIGNAL port_xhdl71 : std_logic;
SIGNAL xhdl_77 : std_logic;
SIGNAL port_xhdl78 : std_logic;
SIGNAL port_xhdl79 : std_logic;
SIGNAL xhdl_85 : std_logic;
SIGNAL xhdl_91 : std_logic;
SIGNAL port_xhdl92 : std_logic;
SIGNAL port_xhdl93 : std_logic;
-- End Command register
-- Status register
SIGNAL status : std_logic_vector(7 DOWNTO 0);
-- End Status register
-- Interrupt Enable register (extended mode)
SIGNAL irq_en_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL bus_error_irq_en : std_logic;
SIGNAL arbitration_lost_irq_en : std_logic;
SIGNAL error_passive_irq_en : std_logic;
SIGNAL data_overrun_irq_en_ext : std_logic;
SIGNAL error_warning_irq_en_ext : std_logic;
SIGNAL transmit_irq_en_ext : std_logic;
SIGNAL receive_irq_en_ext : std_logic;
-- End Bus Timing 0 register
-- Bus Timing 0 register
SIGNAL bus_timing_0 : std_logic_vector(7 DOWNTO 0);
-- End Bus Timing 0 register
-- Bus Timing 1 register
SIGNAL bus_timing_1 : std_logic_vector(7 DOWNTO 0);
-- End Error Warning Limit register
-- Clock Divider register
SIGNAL clock_divider : std_logic_vector(7 DOWNTO 0);
SIGNAL clock_off : std_logic;
SIGNAL cd : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_div : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_tmp : std_logic;
SIGNAL port_xhdl116 : std_logic;
SIGNAL port_xhdl117 : std_logic;
SIGNAL port_xhdl123 : std_logic;
SIGNAL port_xhdl124 : std_logic;
SIGNAL temp_xhdl131 : std_logic;
SIGNAL temp_xhdl132 : std_logic;
SIGNAL temp_xhdl218 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl219 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl220 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl221 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl222 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl223 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl224 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl225 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl226 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl227 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl228 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl229 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl230 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl231 : std_logic_vector(7 DOWNTO 0); -- basic mode
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL temp_xhdl233 : std_logic;
SIGNAL temp_xhdl234 : std_logic;
SIGNAL temp_xhdl235 : std_logic;
SIGNAL temp_xhdl236 : std_logic;
SIGNAL data_overrun_irq : std_logic;
SIGNAL transmit_irq : std_logic;
SIGNAL receive_irq : std_logic;
SIGNAL error_irq : std_logic;
SIGNAL bus_error_irq : std_logic;
SIGNAL arbitration_lost_irq : std_logic;
SIGNAL error_passive_irq : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL irq_n_xhdl2 : std_logic;
SIGNAL reset_mode_xhdl3 : std_logic;
SIGNAL listen_only_mode_xhdl4 : std_logic;
SIGNAL acceptance_filter_mode_xhdl5 : std_logic;
SIGNAL self_test_mode_xhdl6 : std_logic;
SIGNAL clear_data_overrun_xhdl7 : std_logic;
SIGNAL release_buffer_xhdl8 : std_logic;
SIGNAL abort_tx_xhdl9 : std_logic;
SIGNAL tx_request_xhdl10 : std_logic;
SIGNAL self_rx_request_xhdl11 : std_logic;
SIGNAL single_shot_transmission_xhdl12 : std_logic;
SIGNAL overload_request_xhdl13 : std_logic;
SIGNAL read_arbitration_lost_capture_reg_xhdl14: std_logic;
SIGNAL read_error_code_capture_reg_xhdl15: std_logic;
SIGNAL baud_r_presc_xhdl16 : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width_xhdl17 : std_logic_vector(1 DOWNTO 0);
SIGNAL time_segment1_xhdl18 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2_xhdl19 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling_xhdl20 : std_logic;
SIGNAL error_warning_limit_xhdl21 : std_logic_vector(7 DOWNTO 0);
SIGNAL we_rx_err_cnt_xhdl22 : std_logic;
SIGNAL we_tx_err_cnt_xhdl23 : std_logic;
SIGNAL extended_mode_xhdl24 : std_logic;
SIGNAL clkout_xhdl25 : std_logic;
SIGNAL acceptance_code_0_xhdl26 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_0_xhdl27 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_1_xhdl28 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2_xhdl29 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3_xhdl30 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_1_xhdl31 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2_xhdl32 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3_xhdl33 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_0_xhdl34 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1_xhdl35 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3_xhdl37 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4_xhdl38 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5_xhdl39 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6_xhdl40 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7_xhdl41 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8_xhdl42 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_xhdl43 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10_xhdl44 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11_xhdl45 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12_xhdl46 : std_logic_vector(7 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
irq_n <= irq_n_xhdl2;
reset_mode <= reset_mode_xhdl3;
listen_only_mode <= listen_only_mode_xhdl4;
acceptance_filter_mode <= acceptance_filter_mode_xhdl5;
self_test_mode <= self_test_mode_xhdl6;
clear_data_overrun <= clear_data_overrun_xhdl7;
release_buffer <= release_buffer_xhdl8;
abort_tx <= abort_tx_xhdl9;
tx_request <= tx_request_xhdl10;
self_rx_request <= self_rx_request_xhdl11;
single_shot_transmission <= single_shot_transmission_xhdl12;
overload_request <= overload_request_xhdl13;
read_arbitration_lost_capture_reg <= read_arbitration_lost_capture_reg_xhdl14;
read_error_code_capture_reg <= read_error_code_capture_reg_xhdl15;
baud_r_presc <= baud_r_presc_xhdl16;
sync_jump_width <= sync_jump_width_xhdl17;
time_segment1 <= time_segment1_xhdl18;
time_segment2 <= time_segment2_xhdl19;
triple_sampling <= triple_sampling_xhdl20;
error_warning_limit <= error_warning_limit_xhdl21;
we_rx_err_cnt <= we_rx_err_cnt_xhdl22;
we_tx_err_cnt <= we_tx_err_cnt_xhdl23;
extended_mode <= extended_mode_xhdl24;
clkout <= clkout_xhdl25;
acceptance_code_0 <= acceptance_code_0_xhdl26;
acceptance_mask_0 <= acceptance_mask_0_xhdl27;
acceptance_code_1 <= acceptance_code_1_xhdl28;
acceptance_code_2 <= acceptance_code_2_xhdl29;
acceptance_code_3 <= acceptance_code_3_xhdl30;
acceptance_mask_1 <= acceptance_mask_1_xhdl31;
acceptance_mask_2 <= acceptance_mask_2_xhdl32;
acceptance_mask_3 <= acceptance_mask_3_xhdl33;
tx_data_0 <= tx_data_0_xhdl34;
tx_data_1 <= tx_data_1_xhdl35;
tx_data_2 <= tx_data_2_xhdl36;
tx_data_3 <= tx_data_3_xhdl37;
tx_data_4 <= tx_data_4_xhdl38;
tx_data_5 <= tx_data_5_xhdl39;
tx_data_6 <= tx_data_6_xhdl40;
tx_data_7 <= tx_data_7_xhdl41;
tx_data_8 <= tx_data_8_xhdl42;
tx_data_9 <= tx_data_9_xhdl43;
tx_data_10 <= tx_data_10_xhdl44;
tx_data_11 <= tx_data_11_xhdl45;
tx_data_12 <= tx_data_12_xhdl46;
we_mode <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000000") ;
we_command <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000001") ;
we_bus_timing_0 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000110")) AND reset_mode_xhdl3 ;
we_bus_timing_1 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000111")) AND reset_mode_xhdl3 ;
we_clock_divider_low <= (cs AND we) AND CONV_STD_LOGIC(addr = "00011111") ;
we_clock_divider_hi <= we_clock_divider_low AND reset_mode_xhdl3 ;
read <= cs AND (NOT we) ;
read_irq_reg <= read AND CONV_STD_LOGIC(addr = "00000011") ;
reset_irq_reg <= read_irq_reg_q and not read_irq_reg;
read_arbitration_lost_capture_reg_xhdl14 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011") ;
read_error_code_capture_reg_xhdl15 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100") ;
we_acceptance_code_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000"))) ;
we_acceptance_mask_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100"))) ;
we_tx_data_0 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000")))) AND transmit_buffer_status ;
we_tx_data_1 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010001")))) AND transmit_buffer_status ;
we_tx_data_2 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010010")))) AND transmit_buffer_status ;
we_tx_data_3 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010011")))) AND transmit_buffer_status ;
we_tx_data_4 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001110")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100")))) AND transmit_buffer_status ;
we_tx_data_5 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001111")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010101")))) AND transmit_buffer_status ;
we_tx_data_6 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010000")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010110")))) AND transmit_buffer_status ;
we_tx_data_7 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010001")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010111")))) AND transmit_buffer_status ;
we_tx_data_8 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011000")))) AND transmit_buffer_status ;
we_tx_data_9 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011001")))) AND transmit_buffer_status ;
we_tx_data_10 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011010"))) AND transmit_buffer_status ;
we_tx_data_11 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011011"))) AND transmit_buffer_status ;
we_tx_data_12 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011100"))) AND transmit_buffer_status ;
we_interrupt_enable <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000100")) AND extended_mode_xhdl24 ;
we_error_warning_limit <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_rx_err_cnt_xhdl22 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_tx_err_cnt_xhdl23 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010001")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010010")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010011")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
-- End: This section is for EXTENDED mode
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
read_irq_reg_q <= read_irq_reg;
tx_successful_q <= tx_successful ;
overrun_q <= overrun ;
transmit_buffer_status_q <= transmit_buffer_status ;
error_status_q <= error_status ;
node_bus_off_q <= node_bus_off ;
node_error_passive_q <= node_error_passive ;
END IF;
END PROCESS;
port_xhdl52 <= data_in(0);
MODE_REG0 : can_register_asyn_syn
GENERIC MAP (1, 1)
PORT MAP (
data_in(0) => port_xhdl52,
data_out(0) => mode,
we => we_mode,
clk => clk,
rst => rst,
rst_sync => set_reset_mode);
MODE_REG_BASIC : can_register_asyn
GENERIC MAP (4, 0)
PORT MAP (
data_in => data_in(4 DOWNTO 1),
data_out => mode_basic(4 DOWNTO 1),
we => we_mode,
clk => clk,
rst => rst);
xhdl_61 <= (we_mode AND reset_mode_xhdl3);
MODE_REG_EXT : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 1),
data_out => mode_ext(3 DOWNTO 1),
we => xhdl_61,
clk => clk,
rst => rst);
reset_mode_xhdl3 <= mode ;
listen_only_mode_xhdl4 <= extended_mode_xhdl24 AND mode_ext(1) ;
self_test_mode_xhdl6 <= extended_mode_xhdl24 AND mode_ext(2) ;
acceptance_filter_mode_xhdl5 <= extended_mode_xhdl24 AND mode_ext(3) ;
receive_irq_en_basic <= mode_basic(1) ;
transmit_irq_en_basic <= mode_basic(2) ;
error_irq_en_basic <= mode_basic(3) ;
overrun_irq_en_basic <= mode_basic(4) ;
xhdl_69 <= (command(0) AND sample_point) OR reset_mode_xhdl3;
port_xhdl70 <= data_in(0);
command(0) <= port_xhdl71;
COMMAND_REG0 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl70,
data_out(0) => port_xhdl71,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_69);
xhdl_77 <= (sample_point AND (tx_request_xhdl10 OR (abort_tx_xhdl9 AND NOT transmitting))) OR reset_mode_xhdl3;
port_xhdl78 <= data_in(1);
command(1) <= port_xhdl79;
COMMAND_REG1 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl78,
data_out(0) => port_xhdl79,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_77);
xhdl_85 <= orv(command(3 DOWNTO 2)) OR reset_mode_xhdl3;
COMMAND_REG : can_register_asyn_syn
GENERIC MAP (2, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 2),
data_out => command(3 DOWNTO 2),
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_85);
xhdl_91 <= (command(4) AND sample_point) OR reset_mode_xhdl3;
port_xhdl92 <= data_in(4);
command(4) <= port_xhdl93;
COMMAND_REG4 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl92,
data_out(0) => port_xhdl93,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_91);
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
self_rx_request_xhdl11 <= '0';
ELSif clk'event and clk = '1' then
IF ((command(4) AND (NOT command(0))) = '1') THEN
self_rx_request_xhdl11 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
self_rx_request_xhdl11 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
clear_data_overrun_xhdl7 <= command(3) ;
release_buffer_xhdl8 <= command(2) ;
tx_request_xhdl10 <= command(0) OR command(4) ;
abort_tx_xhdl9 <= command(1) AND (NOT tx_request_xhdl10) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
single_shot_transmission_xhdl12 <= '0';
ELSif clk'event and clk = '1' then
IF (((tx_request_xhdl10 AND command(1)) AND sample_point) = '1') THEN
single_shot_transmission_xhdl12 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
single_shot_transmission_xhdl12 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
--
-- can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
-- ( .data_in(data_in[5]),
-- .data_out(overload_request),
-- .we(we_command),
-- .clk(clk),
-- .rst(rst),
-- .rst_sync(overload_frame & ~overload_frame_q)
-- );
-- reg overload_frame_q;
-- always @ (posedge clk or posedge rst)
-- begin
-- if (rst)
-- overload_frame_q <= 1'b0;
-- else
-- overload_frame_q <=#Tp overload_frame;
-- end
--
overload_request_xhdl13 <= '0' ;
status(7) <= node_bus_off ;
status(6) <= error_status ;
status(5) <= transmit_status ;
status(4) <= receive_status ;
status(3) <= transmission_complete ;
status(2) <= transmit_buffer_status ;
status(1) <= overrun_status ;
status(0) <= receive_buffer_status ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmission_complete <= '1';
ELSif clk'event and clk = '1' then
IF ((tx_successful AND ((NOT tx_successful_q) OR abort_tx_xhdl9)) = '1') THEN
-- transmission_complete was always set when abort_tx=1
-- Original code:
-- IF (((tx_successful AND (NOT tx_successful_q)) OR abort_tx_xhdl9) = '1') THEN
transmission_complete <= '1' ;
ELSE
IF (tx_request_xhdl10 = '1') THEN
transmission_complete <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_buffer_status <= '1';
ELSif clk'event and clk = '1' then
IF (tx_request_xhdl10 = '1') THEN
transmit_buffer_status <= '0' ;
ELSE
IF ((reset_mode_xhdl3 OR NOT need_to_tx) = '1') THEN
transmit_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overrun_status <= '0';
ELSif clk'event and clk = '1' then
IF ((overrun AND (NOT overrun_q)) = '1') THEN
overrun_status <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR clear_data_overrun_xhdl7) = '1') THEN
overrun_status <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_buffer_status <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_buffer_status <= '0' ;
ELSE
IF (NOT info_empty = '1') THEN
receive_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
IRQ_EN_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => irq_en_ext,
we => we_interrupt_enable,
clk => clk);
bus_error_irq_en <= irq_en_ext(7) ;
arbitration_lost_irq_en <= irq_en_ext(6) ;
error_passive_irq_en <= irq_en_ext(5) ;
data_overrun_irq_en_ext <= irq_en_ext(3) ;
error_warning_irq_en_ext <= irq_en_ext(2) ;
transmit_irq_en_ext <= irq_en_ext(1) ;
receive_irq_en_ext <= irq_en_ext(0) ;
BUS_TIMING_0_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_0,
we => we_bus_timing_0,
clk => clk);
baud_r_presc_xhdl16 <= bus_timing_0(5 DOWNTO 0) ;
sync_jump_width_xhdl17 <= bus_timing_0(7 DOWNTO 6) ;
BUS_TIMING_1_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_1,
we => we_bus_timing_1,
clk => clk);
time_segment1_xhdl18 <= bus_timing_1(3 DOWNTO 0) ;
time_segment2_xhdl19 <= bus_timing_1(6 DOWNTO 4) ;
triple_sampling_xhdl20 <= bus_timing_1(7) ;
-- End Bus Timing 1 register -- Error Warning Limit register
ERROR_WARNING_REG : can_register_asyn
GENERIC MAP (8, 96)
PORT MAP (
data_in => data_in,
data_out => error_warning_limit_xhdl21,
we => we_error_warning_limit,
clk => clk,
rst => rst);
port_xhdl116 <= data_in(7);
clock_divider(7) <= port_xhdl117;
CLOCK_DIVIDER_REG_7 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl116,
data_out(0) => port_xhdl117,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
clock_divider(6 DOWNTO 4) <= "000" ;
port_xhdl123 <= data_in(3);
clock_divider(3) <= port_xhdl124;
CLOCK_DIVIDER_REG_3 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl123,
data_out(0) => port_xhdl124,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
CLOCK_DIVIDER_REG_LOW : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(2 DOWNTO 0),
data_out => clock_divider(2 DOWNTO 0),
we => we_clock_divider_low,
clk => clk,
rst => rst);
extended_mode_xhdl24 <= clock_divider(7) ;
clock_off <= clock_divider(3) ;
cd(2 DOWNTO 0) <= clock_divider(2 DOWNTO 0) ;
PROCESS (cd)
VARIABLE clkout_div_xhdl130 : std_logic_vector(2 DOWNTO 0);
BEGIN
CASE cd IS
-- synthesis full_case parallel_case
WHEN "000" =>
clkout_div_xhdl130 := "000";
WHEN "001" =>
clkout_div_xhdl130 := "001";
WHEN "010" =>
clkout_div_xhdl130 := "010";
WHEN "011" =>
clkout_div_xhdl130 := "011";
WHEN "100" =>
clkout_div_xhdl130 := "100";
WHEN "101" =>
clkout_div_xhdl130 := "101";
WHEN "110" =>
clkout_div_xhdl130 := "110";
WHEN "111" =>
clkout_div_xhdl130 := "000";
WHEN OTHERS =>
NULL;
END CASE;
clkout_div <= clkout_div_xhdl130;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_cnt <= "000";
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_cnt <= "000" ;
ELSE
clkout_cnt <= clkout_cnt + "001";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_tmp <= '0';
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_tmp <= NOT clkout_tmp ;
END IF;
END IF;
END PROCESS;
temp_xhdl131 <= clk WHEN (andv(cd)) = '1' ELSE clkout_tmp;
temp_xhdl132 <= '1' WHEN clock_off = '1' ELSE (temp_xhdl131);
clkout_xhdl25 <= temp_xhdl132 ;
-- End Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register
ACCEPTANCE_CODE_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_0_xhdl26,
we => we_acceptance_code_0,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register
ACCEPTANCE_MASK_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_0_xhdl27,
we => we_acceptance_mask_0,
clk => clk);
-- End: Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- Tx data 0 register.
TX_DATA_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_0_xhdl34,
we => we_tx_data_0,
clk => clk);
-- End: Tx data 0 register. -- Tx data 1 register.
TX_DATA_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_1_xhdl35,
we => we_tx_data_1,
clk => clk);
-- End: Tx data 1 register. -- Tx data 2 register.
TX_DATA_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_2_xhdl36,
we => we_tx_data_2,
clk => clk);
-- End: Tx data 2 register. -- Tx data 3 register.
TX_DATA_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_3_xhdl37,
we => we_tx_data_3,
clk => clk);
-- End: Tx data 3 register. -- Tx data 4 register.
TX_DATA_REG4 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_4_xhdl38,
we => we_tx_data_4,
clk => clk);
-- End: Tx data 4 register. -- Tx data 5 register.
TX_DATA_REG5 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_5_xhdl39,
we => we_tx_data_5,
clk => clk);
-- End: Tx data 5 register. -- Tx data 6 register.
TX_DATA_REG6 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_6_xhdl40,
we => we_tx_data_6,
clk => clk);
-- End: Tx data 6 register. -- Tx data 7 register.
TX_DATA_REG7 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_7_xhdl41,
we => we_tx_data_7,
clk => clk);
-- End: Tx data 7 register. -- Tx data 8 register.
TX_DATA_REG8 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_8_xhdl42,
we => we_tx_data_8,
clk => clk);
-- End: Tx data 8 register. -- Tx data 9 register.
TX_DATA_REG9 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_9_xhdl43,
we => we_tx_data_9,
clk => clk);
-- End: Tx data 9 register. -- Tx data 10 register.
TX_DATA_REG10 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_10_xhdl44,
we => we_tx_data_10,
clk => clk);
-- End: Tx data 10 register. -- Tx data 11 register.
TX_DATA_REG11 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_11_xhdl45,
we => we_tx_data_11,
clk => clk);
-- End: Tx data 11 register. -- Tx data 12 register.
TX_DATA_REG12 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_12_xhdl46,
we => we_tx_data_12,
clk => clk);
-- End: Tx data 12 register. -- This section is for EXTENDED mode -- Acceptance code register 1
ACCEPTANCE_CODE_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_1_xhdl28,
we => we_acceptance_code_1,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 2
ACCEPTANCE_CODE_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_2_xhdl29,
we => we_acceptance_code_2,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 3
ACCEPTANCE_CODE_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_3_xhdl30,
we => we_acceptance_code_3,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 1
ACCEPTANCE_MASK_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_1_xhdl31,
we => we_acceptance_mask_1,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 2
ACCEPTANCE_MASK_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_2_xhdl32,
we => we_acceptance_mask_2,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 3
ACCEPTANCE_MASK_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_3_xhdl33,
we => we_acceptance_mask_3,
clk => clk);
temp_xhdl218 <= acceptance_code_0_xhdl26 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl219 <= acceptance_mask_0_xhdl27 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl220 <= bus_timing_0 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl221 <= bus_timing_1 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl222 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_0_xhdl34;
temp_xhdl223 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_1_xhdl35;
temp_xhdl224 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_2_xhdl36;
temp_xhdl225 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_3_xhdl37;
temp_xhdl226 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_4_xhdl38;
temp_xhdl227 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_5_xhdl39;
temp_xhdl228 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_6_xhdl40;
temp_xhdl229 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_7_xhdl41;
temp_xhdl230 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_8_xhdl42;
temp_xhdl231 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_9_xhdl43;
-- End: Acceptance code register -- End: This section is for EXTENDED mode -- Reading data from registers
PROCESS (addr, extended_mode_xhdl24, mode, bus_timing_0, bus_timing_1, clock_divider,
acceptance_code_0_xhdl26, acceptance_code_1_xhdl28, acceptance_code_2_xhdl29,
acceptance_code_3_xhdl30, acceptance_mask_0_xhdl27, acceptance_mask_1_xhdl31,
acceptance_mask_2_xhdl32, acceptance_mask_3_xhdl33, status,
error_warning_limit_xhdl21, rx_err_cnt, tx_err_cnt, irq_en_ext, irq_reg, mode_ext,
arbitration_lost_capture, rx_message_counter, mode_basic, error_capture_code,
temp_xhdl218, temp_xhdl219, temp_xhdl220, temp_xhdl221, temp_xhdl222, temp_xhdl223,
temp_xhdl224, temp_xhdl225, temp_xhdl226, temp_xhdl227, temp_xhdl228, temp_xhdl229,
temp_xhdl230, temp_xhdl231
)
VARIABLE data_out_xhdl1_xhdl217 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl232 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl232 := extended_mode_xhdl24 & addr(4 DOWNTO 0);
CASE temp_xhdl232 IS
WHEN "100000" =>
data_out_xhdl1_xhdl217 := "0000" & mode_ext(3 DOWNTO 1) & mode; -- extended mode
WHEN "100001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "100010" =>
data_out_xhdl1_xhdl217 := status; -- extended mode
WHEN "100011" =>
data_out_xhdl1_xhdl217 := irq_reg; -- extended mode
WHEN "100100" =>
data_out_xhdl1_xhdl217 := irq_en_ext; -- extended mode
WHEN "100110" =>
data_out_xhdl1_xhdl217 := bus_timing_0; -- extended mode
WHEN "100111" =>
data_out_xhdl1_xhdl217 := bus_timing_1; -- extended mode
WHEN "101011" =>
data_out_xhdl1_xhdl217 := "000" & arbitration_lost_capture(4 DOWNTO 0); -- extended mode
WHEN "101100" =>
data_out_xhdl1_xhdl217 := error_capture_code; -- extended mode
WHEN "101101" =>
data_out_xhdl1_xhdl217 := error_warning_limit_xhdl21; -- extended mode
WHEN "101110" =>
data_out_xhdl1_xhdl217 := rx_err_cnt; -- extended mode
WHEN "101111" =>
data_out_xhdl1_xhdl217 := tx_err_cnt; -- extended mode
WHEN "110000" =>
data_out_xhdl1_xhdl217 := acceptance_code_0_xhdl26; -- extended mode
WHEN "110001" =>
data_out_xhdl1_xhdl217 := acceptance_code_1_xhdl28; -- extended mode
WHEN "110010" =>
data_out_xhdl1_xhdl217 := acceptance_code_2_xhdl29; -- extended mode
WHEN "110011" =>
data_out_xhdl1_xhdl217 := acceptance_code_3_xhdl30; -- extended mode
WHEN "110100" =>
data_out_xhdl1_xhdl217 := acceptance_mask_0_xhdl27; -- extended mode
WHEN "110101" =>
data_out_xhdl1_xhdl217 := acceptance_mask_1_xhdl31; -- extended mode
WHEN "110110" =>
data_out_xhdl1_xhdl217 := acceptance_mask_2_xhdl32; -- extended mode
WHEN "110111" =>
data_out_xhdl1_xhdl217 := acceptance_mask_3_xhdl33; -- extended mode
WHEN "111000" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111010" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111011" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111100" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111101" =>
data_out_xhdl1_xhdl217 := '0' & rx_message_counter; -- extended mode
WHEN "111111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- extended mode
WHEN "000000" =>
data_out_xhdl1_xhdl217 := "001" & mode_basic(4 DOWNTO 1) & mode; -- basic mode
WHEN "000001" =>
data_out_xhdl1_xhdl217 := "11111111"; -- basic mode
WHEN "000010" =>
data_out_xhdl1_xhdl217 := status; -- basic mode
WHEN "000011" =>
data_out_xhdl1_xhdl217 := "1110" & irq_reg(3 DOWNTO 0); -- basic mode
WHEN "000100" =>
data_out_xhdl1_xhdl217 := temp_xhdl218;
WHEN "000101" =>
data_out_xhdl1_xhdl217 := temp_xhdl219;
WHEN "000110" =>
data_out_xhdl1_xhdl217 := temp_xhdl220;
WHEN "000111" =>
data_out_xhdl1_xhdl217 := temp_xhdl221;
WHEN "001010" =>
data_out_xhdl1_xhdl217 := temp_xhdl222;
WHEN "001011" =>
data_out_xhdl1_xhdl217 := temp_xhdl223;
WHEN "001100" =>
data_out_xhdl1_xhdl217 := temp_xhdl224;
WHEN "001101" =>
data_out_xhdl1_xhdl217 := temp_xhdl225;
WHEN "001110" =>
data_out_xhdl1_xhdl217 := temp_xhdl226;
WHEN "001111" =>
data_out_xhdl1_xhdl217 := temp_xhdl227;
WHEN "010000" =>
data_out_xhdl1_xhdl217 := temp_xhdl228;
WHEN "010001" =>
data_out_xhdl1_xhdl217 := temp_xhdl229;
WHEN "010010" =>
data_out_xhdl1_xhdl217 := temp_xhdl230;
WHEN "010011" =>
data_out_xhdl1_xhdl217 := temp_xhdl231;
WHEN "011111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- basic mode
WHEN OTHERS =>
data_out_xhdl1_xhdl217 := "00000000"; -- the rest is read as 0
END CASE;
data_out_xhdl1 <= data_out_xhdl1_xhdl217;
END PROCESS;
temp_xhdl233 <= data_overrun_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE overrun_irq_en_basic;
data_overrun_irq_en <= temp_xhdl233 ;
temp_xhdl234 <= error_warning_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE error_irq_en_basic;
error_warning_irq_en <= temp_xhdl234 ;
temp_xhdl235 <= transmit_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE transmit_irq_en_basic;
transmit_irq_en <= temp_xhdl235 ;
temp_xhdl236 <= receive_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE receive_irq_en_basic;
receive_irq_en <= temp_xhdl236 ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_overrun_irq <= '0';
ELSif clk'event and clk = '1' then
IF (((overrun AND (NOT overrun_q)) AND data_overrun_irq_en) = '1') THEN
data_overrun_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
data_overrun_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
transmit_irq <= '0' ;
ELSE
IF (((transmit_buffer_status AND (NOT transmit_buffer_status_q)) AND transmit_irq_en) = '1') THEN
transmit_irq <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((NOT info_empty) AND (NOT receive_irq)) AND receive_irq_en) = '1') THEN
receive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((error_status XOR error_status_q) OR (node_bus_off XOR node_bus_off_q)) AND error_warning_irq_en) = '1') THEN
error_irq <= '1' ;
ELSE
IF (reset_irq_reg = '1') THEN
error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_bus_error_irq AND bus_error_irq_en) = '1') THEN
bus_error_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
bus_error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_arbitration_lost_irq AND arbitration_lost_irq_en) = '1') THEN
arbitration_lost_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
arbitration_lost_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_passive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((node_error_passive AND (NOT node_error_passive_q)) OR (((NOT node_error_passive) AND node_error_passive_q) AND node_error_active)) AND error_passive_irq_en) = '1') THEN
error_passive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
error_passive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
irq_reg <= bus_error_irq & arbitration_lost_irq & error_passive_irq & '0' & data_overrun_irq & error_irq & transmit_irq & receive_irq ;
irq <= data_overrun_irq OR transmit_irq OR receive_irq OR error_irq OR bus_error_irq OR arbitration_lost_irq OR error_passive_irq ;
-- irq_o reset change /Kristoffer 2006-02-23 PROCESS (clk, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSif clk'event and clk = '1' then
-- IF (reset_irq_reg = '1' or release_buffer_xhdl8='1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSE
-- IF (irq = '1') THEN
-- irq_n_xhdl2 <= '0' ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1' or release_buffer_xhdl8 = '1') THEN
irq_n_xhdl2 <= '1';
ELSif clk'event and clk = '1' then
irq_n_xhdl2 <= not irq;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top IS
PORT (
-- wb_clk_i : IN std_logic;
-- wb_rst_i : IN std_logic;
-- wb_dat_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_dat_o : OUT std_logic_vector(7 DOWNTO 0);
-- wb_cyc_i : IN std_logic;
-- wb_stb_i : IN std_logic;
-- wb_we_i : IN std_logic;
-- wb_adr_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_ack_o : OUT std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
cs : IN std_logic;
we : IN std_logic;
clk_i : IN std_logic;
rx_i : IN std_logic;
tx_o : OUT std_logic;
bus_off_on : OUT std_logic;
irq_on : OUT std_logic;
clkout_o : OUT std_logic;
-- Bist
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_top;
ARCHITECTURE RTL OF can_top IS
COMPONENT can_bsp
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : IN std_logic;
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_btl
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
COMPONENT can_registers
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
read_arbitration_lost_capture_reg: OUT std_logic;
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : OUT std_logic;
we_tx_err_cnt : OUT std_logic;
extended_mode : OUT std_logic;
clkout : OUT std_logic;
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
-- SIGNAL cs_sync1 : std_logic;
-- SIGNAL cs_sync2 : std_logic;
-- SIGNAL cs_sync3 : std_logic;
-- SIGNAL cs_ack1 : std_logic;
-- SIGNAL cs_ack2 : std_logic;
-- SIGNAL cs_ack3 : std_logic;
-- SIGNAL cs_sync_rst1 : std_logic;
-- SIGNAL cs_sync_rst2 : std_logic;
-- SIGNAL cs_can_i : std_logic;
---------------------------------
SIGNAL data_out_fifo_selected : std_logic;
SIGNAL data_out_fifo : std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_regs : std_logic_vector(7 DOWNTO 0);
-- Mode register
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL acceptance_filter_mode : std_logic;
SIGNAL self_test_mode : std_logic;
-- Command register
SIGNAL release_buffer : std_logic;
SIGNAL tx_request : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
-- Arbitration Lost Capture Register
SIGNAL read_arbitration_lost_capture_reg: std_logic;
-- Error Code Capture Register
SIGNAL read_error_code_capture_reg : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
SIGNAL baud_r_presc : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width : std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
SIGNAL time_segment1 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling : std_logic;
-- Error Warning Limit register
SIGNAL error_warning_limit : std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
SIGNAL we_rx_err_cnt : std_logic;
-- Tx Error Counter register
SIGNAL we_tx_err_cnt : std_logic;
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_0 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_0 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
-- SIGNAL cs : std_logic;
-- Output signals from can_btl module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL set_reset_mode : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL error_status : std_logic;
SIGNAL rx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL tx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL info_empty : std_logic;
SIGNAL set_bus_error_irq : std_logic;
SIGNAL set_arbitration_lost_irq : std_logic;
SIGNAL arbitration_lost_capture : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL rx_message_counter : std_logic_vector(6 DOWNTO 0);
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
-- SIGNAL we : std_logic;
-- SIGNAL addr : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_in : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
-- From btl module
-- Mode register
-- Command register
-- Arbitration Lost Capture Register
-- Error Code Capture Register
-- Error Warning Limit register
-- Rx Error Counter register
-- Tx Error Counter register
-- Clock Divider register
-- output from can_bsp module
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
-- SIGNAL wb_dat_o_xhdl1 : std_logic_vector(7 DOWNTO 0);
-- SIGNAL wb_ack_o_xhdl2 : std_logic;
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL bus_off_on_xhdl4 : std_logic;
SIGNAL irq_on_xhdl5 : std_logic;
SIGNAL clkout_o_xhdl6 : std_logic;
SIGNAL data_64x8_xhdl7 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl8 : std_logic;
SIGNAL rden_64x8_xhdl9 : std_logic;
SIGNAL wraddress_64x8_xhdl10 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl11 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl12 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl13 : std_logic;
SIGNAL wraddress_64x4x1_xhdl14 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl15 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl16 : std_logic;
SIGNAL rx_inter : std_logic;
BEGIN
-- wb_dat_o <= wb_dat_o_xhdl1;
-- wb_ack_o <= wb_ack_o_xhdl2;
tx_o <= tx_o_xhdl3;
bus_off_on <= bus_off_on_xhdl4;
irq_on <= irq_on_xhdl5;
clkout_o <= clkout_o_xhdl6;
data_64x8 <= data_64x8_xhdl7;
wren_64x8 <= wren_64x8_xhdl8;
rden_64x8 <= rden_64x8_xhdl9;
wraddress_64x8 <= wraddress_64x8_xhdl10;
rdaddress_64x8 <= rdaddress_64x8_xhdl11;
data_64x4 <= data_64x4_xhdl12;
wren_64x4x1 <= wren_64x4x1_xhdl13;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl14;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl15;
data_64x1 <= data_64x1_xhdl16;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl7 <= w_data_64x8 ;
wren_64x8_xhdl8 <= w_wren_64x8 ;
rden_64x8_xhdl9 <= w_rden_64x8 ;
wraddress_64x8_xhdl10 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl11 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl12 <= w_data_64x4 ;
wren_64x4x1_xhdl13 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl14 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl15 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl16 <= w_data_64x1 ;
-- Connecting can_registers module -- Mode register -- Command register -- Arbitration Lost Capture Register -- Error Code Capture Register -- Bus Timing 0 register -- Bus Timing 1 register -- Error Warning Limit register -- Rx Error Counter register -- Tx Error Counter register -- Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers
i_can_registers : can_registers
PORT MAP (
clk => clk_i,
rst => rst,
cs => cs,
we => we,
addr => addr,
data_in => data_in,
data_out => data_out_regs,
irq_n => irq_on_xhdl5,
sample_point => sample_point,
transmitting => transmitting,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => rx_err_cnt,
tx_err_cnt => tx_err_cnt,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
clear_data_overrun => open,
release_buffer => release_buffer,
abort_tx => abort_tx,
tx_request => tx_request,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
clkout => clkout_o_xhdl6,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12);
-- Connecting can_btl module -- Bus Timing 0 register -- Bus Timing 1 register -- Output signals from this module -- output from can_bsp module
i_can_btl : can_btl
PORT MAP (
clk => clk_i,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- xhdl_148 <= rx_err_cnt_dummy & rx_err_cnt(7 DOWNTO 0);
rx_err_cnt_dummy <= xhdl_148(8);
rx_err_cnt(7 DOWNTO 0) <= xhdl_148(7 DOWNTO 0);
-- xhdl_150 <= tx_err_cnt_dummy & tx_err_cnt(7 DOWNTO 0);
tx_err_cnt_dummy <= xhdl_150(8);
tx_err_cnt(7 DOWNTO 0) <= xhdl_150(7 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
-- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers -- Tx signal -- port connections for Ram
--64x8
--64x4
--64x1
i_can_bsp : can_bsp
PORT MAP (
clk => clk_i,
rst => rst,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
addr => addr,
data_in => data_in,
data_out => data_out_fifo,
fifo_selected => data_out_fifo_selected,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
release_buffer => release_buffer,
tx_request => tx_request,
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
tx => tx_o_xhdl3,
tx_next => tx_next,
bus_off_on => bus_off_on_xhdl4,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Multiplexing wb_dat_o from registers and rx fifo
PROCESS (extended_mode, addr, reset_mode)
VARIABLE data_out_fifo_selected_xhdl203 : std_logic;
BEGIN
IF ((((extended_mode AND (NOT reset_mode)) AND CONV_STD_LOGIC((addr >= "00010000") AND (addr<="00011100"))) OR ((NOT extended_mode) AND CONV_STD_LOGIC((addr >= "00010100") AND (addr<="00011101")))) = '1') THEN
data_out_fifo_selected_xhdl203 := '1';
ELSE
data_out_fifo_selected_xhdl203 := '0';
END IF;
data_out_fifo_selected <= data_out_fifo_selected_xhdl203;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cs AND (NOT we)) = '1') THEN
IF (data_out_fifo_selected = '1') THEN
data_out <= data_out_fifo ;
ELSE
data_out <= data_out_regs ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i, rst)
BEGIN
IF (rst = '1') THEN
rx_sync_tmp <= '1';
rx_sync <= '1';
ELSIF (clk_i'EVENT AND clk_i = '1') THEN
rx_sync_tmp <= rx_i ;
rx_sync <= rx_sync_tmp ;
END IF;
END PROCESS;
-- cs_can_i <= '1' ;
-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
-- PROCESS (clk_i, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- cs_sync1 <= '0';
-- cs_sync2 <= '0';
-- cs_sync3 <= '0';
-- cs_sync_rst1 <= '0';
-- cs_sync_rst2 <= '0';
-- ELSIF (clk_i'EVENT AND clk_i = '1') THEN
-- cs_sync1 <= ((wb_cyc_i AND wb_stb_i) AND (NOT cs_sync_rst2)) AND cs_can_i ;
-- cs_sync2 <= cs_sync1 AND (NOT cs_sync_rst2) ;
-- cs_sync3 <= cs_sync2 AND (NOT cs_sync_rst2) ;
-- cs_sync_rst1 <= cs_ack3 ;
-- cs_sync_rst2 <= cs_sync_rst1 ;
-- END IF;
-- END PROCESS;
-- cs <= cs_sync2 AND (NOT cs_sync3) ;
--
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- cs_ack1 <= cs_sync3 ;
-- cs_ack2 <= cs_ack1 ;
-- cs_ack3 <= cs_ack2 ;
-- END IF;
-- END PROCESS;
-- Generating acknowledge signal
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- wb_ack_o_xhdl2 <= cs_ack2 AND (NOT cs_ack3) ;
-- END IF;
-- END PROCESS;
-- rst <= wb_rst_i ;
-- we <= wb_we_i ;
-- addr <= wb_adr_i ;
-- data_in <= wb_dat_i ;
-- wb_dat_o_xhdl1 <= data_out ;
END ARCHITECTURE RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
entity IP_complete_nomac is
generic (
use_arpv2 : boolean := true; -- use ARP with multipule entries. for signel entry, set
-- to false
no_default_gateway : boolean := false; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
architecture structural of IP_complete_nomac is
component IPv4
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
component arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
component tx_arbitrator
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end component;
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
-- for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
begin
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_layer : IPv4 port map
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
signle_entry_arp: if (not use_arpv2) generate
arp_layer : entity work.arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate signle_entry_arp;
multi_entry_arp: if (use_arpv2) generate
arp_layer : entity work.arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate multi_entry_arp;
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
end structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
entity IP_complete_nomac is
generic (
use_arpv2 : boolean := true; -- use ARP with multipule entries. for signel entry, set
-- to false
no_default_gateway : boolean := false; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
architecture structural of IP_complete_nomac is
component IPv4
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
component arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
component tx_arbitrator
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end component;
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
-- for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
begin
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_layer : IPv4 port map
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
signle_entry_arp: if (not use_arpv2) generate
arp_layer : entity work.arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate signle_entry_arp;
multi_entry_arp: if (use_arpv2) generate
arp_layer : entity work.arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate multi_entry_arp;
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
end structural;
|
---------------------------------------------------------------------------------
--RAM------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.all;
-----------------ENTITY FOR RAM------------------------------------------
ENTITY ram is
GENERIC ( bits : INTEGER := 8; -- # of bits per word
words : INTEGER := 32 ); -- # of words in the memory
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END ram;
-----------------BEHAVIOR OF RAM-----------------------------------------
ARCHITECTURE ram of ram IS
--TYPE row IS ARRAY (7 downto 0) OF STD_LOGIC; -- 1D array
--TYPE matrix IS ARRAY (0 to 3) of row; -- 1Dx1D array
--TYPE matrix IS ARRAY (0 to 4) of STD_LOGIC_VECTOR (7 DOWNTO 0)--1Dx1D
--Example: 2D array
--The array below is truly two-dimensional. Notice that its construction is not based on vectors, but rather entirely on scalars
--TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) of STD_LOGIC; --2D array
TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0);--32x8
signal memory : vector_array:=(others=> (others=>'0'));--matrix and set to 0 initially this is wrong but set for conceptual purposes
signal temp_addr: Integer;
-------------------PROCEDUREE------------------------------
BEGIN
--Design Question should it take 9 ram inputs before output begining output sequence
--Program works either way so it is up to the manufacturer
--temp_addr <= to_integer(unsigned(addr));--offset is 9 ctrl_out changes up here
PROCESS (clock, wr_ena)
BEGIN
IF(reset='0')THEN
memory <= (others=> (others=>'0'));
temp_addr <= 0; -- only enable if want offset of 1 instead of 9
ELSIF(rising_edge(clock)) THEN -- can also use clk'EVENT AND clk = '1'
temp_addr <= to_integer(unsigned(addr));--offset is 1 ctrl_out changes up here
IF (wr_ena = '1') THEN
memory(temp_addr) <= ram_in;
ELSE
ram_out <= memory(temp_addr);
END IF;
END IF;
END PROCESS;
--ram_out <= memory(temp_addr);--asynchronous
END ram;
|
---------------------------------------------------------------------------------
--RAM------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.all;
-----------------ENTITY FOR RAM------------------------------------------
ENTITY ram is
GENERIC ( bits : INTEGER := 8; -- # of bits per word
words : INTEGER := 32 ); -- # of words in the memory
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END ram;
-----------------BEHAVIOR OF RAM-----------------------------------------
ARCHITECTURE ram of ram IS
--TYPE row IS ARRAY (7 downto 0) OF STD_LOGIC; -- 1D array
--TYPE matrix IS ARRAY (0 to 3) of row; -- 1Dx1D array
--TYPE matrix IS ARRAY (0 to 4) of STD_LOGIC_VECTOR (7 DOWNTO 0)--1Dx1D
--Example: 2D array
--The array below is truly two-dimensional. Notice that its construction is not based on vectors, but rather entirely on scalars
--TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) of STD_LOGIC; --2D array
TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0);--32x8
signal memory : vector_array:=(others=> (others=>'0'));--matrix and set to 0 initially this is wrong but set for conceptual purposes
signal temp_addr: Integer;
-------------------PROCEDUREE------------------------------
BEGIN
--Design Question should it take 9 ram inputs before output begining output sequence
--Program works either way so it is up to the manufacturer
--temp_addr <= to_integer(unsigned(addr));--offset is 9 ctrl_out changes up here
PROCESS (clock, wr_ena)
BEGIN
IF(reset='0')THEN
memory <= (others=> (others=>'0'));
temp_addr <= 0; -- only enable if want offset of 1 instead of 9
ELSIF(rising_edge(clock)) THEN -- can also use clk'EVENT AND clk = '1'
temp_addr <= to_integer(unsigned(addr));--offset is 1 ctrl_out changes up here
IF (wr_ena = '1') THEN
memory(temp_addr) <= ram_in;
ELSE
ram_out <= memory(temp_addr);
END IF;
END IF;
END PROCESS;
--ram_out <= memory(temp_addr);--asynchronous
END ram;
|
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_master_pkg IS
COMPONENT spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_tx_start : IN STD_LOGIC;
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_done : OUT STD_LOGIC;
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT spi_master;
END PACKAGE spi_master_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); -- data to transmit, should not be changed after tx_start is asserted till rx_done is received
isl_tx_start : IN STD_LOGIC; --if this signal is set to one the transmission starts
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); --received data only valid if rx_done is high
osl_rx_done : OUT STD_LOGIC; --if this signal goes high the receiving of data is finished
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0); -- decides which ss line should be active always write a logic high to set the ss active. the block itselve handles the logic level of the ss depending on the sspol value
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY spi_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_master IS
CONSTANT NR_OF_TICKS_PER_SCLK_EDGE : INTEGER := BASE_CLK/SCLK_FREQUENCY/2;
CONSTANT CYCLE_COUNTHER_WIDTH : INTEGER := integer(ceil(log2(real(SCLK_FREQUENCY))))+1;
TYPE t_states IS (idle,wait_ss_enable_setup,process_data,wait_ss_disable_setup);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_miso_1 : STD_LOGIC;
sync_miso_2 : STD_LOGIC;
clk_count : UNSIGNED(CYCLE_COUNTHER_WIDTH-1 DOWNTO 0);
sclk : STD_LOGIC;
ss : STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
bit_count : INTEGER;
mosi : STD_LOGIC;
leading_edge : STD_LOGIC;
rx_data_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
rx_done : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_tx_start,islv_ss_activ,islv_tx_data,isl_miso)
VARIABLE vi: t_internal_register;
PROCEDURE change_bitcount IS
BEGIN
IF MSBFIRST = '0' THEN
IF vi.bit_count >= TRANSFER_WIDTH-1 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := 0;
ELSE
vi.bit_count := vi.bit_count + 1;
END IF;
ELSE
IF vi.bit_count <= 0 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := TRANSFER_WIDTH-1;
ELSE
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
END change_bitcount;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.rx_done := '0';
--synchronisation
vi.sync_miso_2 := vi.sync_miso_1;
vi.sync_miso_1 := isl_miso;
CASE vi.state IS
WHEN idle =>
vi.mosi := '0';
vi.ss := (OTHERS => NOT SSPOL);
vi.sclk := CPOL;
IF isl_tx_start = '1' THEN
vi.state := wait_ss_enable_setup;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
FOR i IN 0 TO NR_OF_SS-1 LOOP
IF islv_ss_activ(i) = '1' THEN
vi.ss(i) := SSPOL;
END IF;
END LOOP;
END IF;
WHEN wait_ss_enable_setup =>
vi.clk_count := vi.clk_count + 1;
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.leading_edge := '1';
vi.rx_data_buf := (OTHERS => '0');
vi.state := process_data;
END IF;
WHEN process_data =>
--toggle sclk
IF vi.clk_count = to_unsigned(0,CYCLE_COUNTHER_WIDTH) THEN
vi.sclk := NOT vi.sclk;
vi.clk_count := to_unsigned(NR_OF_TICKS_PER_SCLK_EDGE,CYCLE_COUNTHER_WIDTH);
IF CPHA = '0' THEN -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
IF vi.leading_edge = '1' THEN
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
ELSE --trailing edge
vi.mosi := islv_tx_data(vi.bit_count);
change_bitcount;
END IF;
ELSE -- clock phase 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
IF vi.leading_edge = '1' THEN
vi.mosi := islv_tx_data(vi.bit_count);
ELSE --trailing edge
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
change_bitcount;
END IF;
END IF;
vi.leading_edge := NOT vi.leading_edge;
ELSE
vi.clk_count := vi.clk_count - 1;
END IF;
WHEN wait_ss_disable_setup =>
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.ss := (OTHERS => NOT SSPOL);
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := idle;
vi.rx_done := '1';
ELSE
vi.clk_count := vi.clk_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.sclk := CPOL;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.ss := (OTHERS => NOT SSPOL);
IF MSBFIRST = '0' THEN
vi.bit_count := 0;
ELSE
vi.bit_count := TRANSFER_WIDTH-1;
END IF;
vi.mosi := '0';
vi.leading_edge := '0';
vi.rx_data_buf := (OTHERS => '0');
vi.rx_done := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--output assignement
osl_sclk <= ri.sclk;
oslv_ss <= ri.ss;
osl_mosi <= ri.mosi;
osl_rx_done <= ri.rx_done;
oslv_rx_data <= ri.rx_data_buf;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_master_pkg IS
COMPONENT spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_tx_start : IN STD_LOGIC;
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_done : OUT STD_LOGIC;
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT spi_master;
END PACKAGE spi_master_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); -- data to transmit, should not be changed after tx_start is asserted till rx_done is received
isl_tx_start : IN STD_LOGIC; --if this signal is set to one the transmission starts
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); --received data only valid if rx_done is high
osl_rx_done : OUT STD_LOGIC; --if this signal goes high the receiving of data is finished
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0); -- decides which ss line should be active always write a logic high to set the ss active. the block itselve handles the logic level of the ss depending on the sspol value
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY spi_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_master IS
CONSTANT NR_OF_TICKS_PER_SCLK_EDGE : INTEGER := BASE_CLK/SCLK_FREQUENCY/2;
CONSTANT CYCLE_COUNTHER_WIDTH : INTEGER := integer(ceil(log2(real(SCLK_FREQUENCY))))+1;
TYPE t_states IS (idle,wait_ss_enable_setup,process_data,wait_ss_disable_setup);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_miso_1 : STD_LOGIC;
sync_miso_2 : STD_LOGIC;
clk_count : UNSIGNED(CYCLE_COUNTHER_WIDTH-1 DOWNTO 0);
sclk : STD_LOGIC;
ss : STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
bit_count : INTEGER;
mosi : STD_LOGIC;
leading_edge : STD_LOGIC;
rx_data_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
rx_done : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_tx_start,islv_ss_activ,islv_tx_data,isl_miso)
VARIABLE vi: t_internal_register;
PROCEDURE change_bitcount IS
BEGIN
IF MSBFIRST = '0' THEN
IF vi.bit_count >= TRANSFER_WIDTH-1 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := 0;
ELSE
vi.bit_count := vi.bit_count + 1;
END IF;
ELSE
IF vi.bit_count <= 0 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := TRANSFER_WIDTH-1;
ELSE
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
END change_bitcount;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.rx_done := '0';
--synchronisation
vi.sync_miso_2 := vi.sync_miso_1;
vi.sync_miso_1 := isl_miso;
CASE vi.state IS
WHEN idle =>
vi.mosi := '0';
vi.ss := (OTHERS => NOT SSPOL);
vi.sclk := CPOL;
IF isl_tx_start = '1' THEN
vi.state := wait_ss_enable_setup;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
FOR i IN 0 TO NR_OF_SS-1 LOOP
IF islv_ss_activ(i) = '1' THEN
vi.ss(i) := SSPOL;
END IF;
END LOOP;
END IF;
WHEN wait_ss_enable_setup =>
vi.clk_count := vi.clk_count + 1;
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.leading_edge := '1';
vi.rx_data_buf := (OTHERS => '0');
vi.state := process_data;
END IF;
WHEN process_data =>
--toggle sclk
IF vi.clk_count = to_unsigned(0,CYCLE_COUNTHER_WIDTH) THEN
vi.sclk := NOT vi.sclk;
vi.clk_count := to_unsigned(NR_OF_TICKS_PER_SCLK_EDGE,CYCLE_COUNTHER_WIDTH);
IF CPHA = '0' THEN -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
IF vi.leading_edge = '1' THEN
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
ELSE --trailing edge
vi.mosi := islv_tx_data(vi.bit_count);
change_bitcount;
END IF;
ELSE -- clock phase 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
IF vi.leading_edge = '1' THEN
vi.mosi := islv_tx_data(vi.bit_count);
ELSE --trailing edge
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
change_bitcount;
END IF;
END IF;
vi.leading_edge := NOT vi.leading_edge;
ELSE
vi.clk_count := vi.clk_count - 1;
END IF;
WHEN wait_ss_disable_setup =>
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.ss := (OTHERS => NOT SSPOL);
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := idle;
vi.rx_done := '1';
ELSE
vi.clk_count := vi.clk_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.sclk := CPOL;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.ss := (OTHERS => NOT SSPOL);
IF MSBFIRST = '0' THEN
vi.bit_count := 0;
ELSE
vi.bit_count := TRANSFER_WIDTH-1;
END IF;
vi.mosi := '0';
vi.leading_edge := '0';
vi.rx_data_buf := (OTHERS => '0');
vi.rx_done := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--output assignement
osl_sclk <= ri.sclk;
oslv_ss <= ri.ss;
osl_mosi <= ri.mosi;
osl_rx_done <= ri.rx_done;
oslv_rx_data <= ri.rx_data_buf;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_master_pkg IS
COMPONENT spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_tx_start : IN STD_LOGIC;
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_done : OUT STD_LOGIC;
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT spi_master;
END PACKAGE spi_master_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); -- data to transmit, should not be changed after tx_start is asserted till rx_done is received
isl_tx_start : IN STD_LOGIC; --if this signal is set to one the transmission starts
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); --received data only valid if rx_done is high
osl_rx_done : OUT STD_LOGIC; --if this signal goes high the receiving of data is finished
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0); -- decides which ss line should be active always write a logic high to set the ss active. the block itselve handles the logic level of the ss depending on the sspol value
osl_sclk : OUT STD_LOGIC;
oslv_ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY spi_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_master IS
CONSTANT NR_OF_TICKS_PER_SCLK_EDGE : INTEGER := BASE_CLK/SCLK_FREQUENCY/2;
CONSTANT CYCLE_COUNTHER_WIDTH : INTEGER := integer(ceil(log2(real(SCLK_FREQUENCY))))+1;
TYPE t_states IS (idle,wait_ss_enable_setup,process_data,wait_ss_disable_setup);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_miso_1 : STD_LOGIC;
sync_miso_2 : STD_LOGIC;
clk_count : UNSIGNED(CYCLE_COUNTHER_WIDTH-1 DOWNTO 0);
sclk : STD_LOGIC;
ss : STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
bit_count : INTEGER;
mosi : STD_LOGIC;
leading_edge : STD_LOGIC;
rx_data_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
rx_done : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_tx_start,islv_ss_activ,islv_tx_data,isl_miso)
VARIABLE vi: t_internal_register;
PROCEDURE change_bitcount IS
BEGIN
IF MSBFIRST = '0' THEN
IF vi.bit_count >= TRANSFER_WIDTH-1 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := 0;
ELSE
vi.bit_count := vi.bit_count + 1;
END IF;
ELSE
IF vi.bit_count <= 0 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := TRANSFER_WIDTH-1;
ELSE
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
END change_bitcount;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.rx_done := '0';
--synchronisation
vi.sync_miso_2 := vi.sync_miso_1;
vi.sync_miso_1 := isl_miso;
CASE vi.state IS
WHEN idle =>
vi.mosi := '0';
vi.ss := (OTHERS => NOT SSPOL);
vi.sclk := CPOL;
IF isl_tx_start = '1' THEN
vi.state := wait_ss_enable_setup;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
FOR i IN 0 TO NR_OF_SS-1 LOOP
IF islv_ss_activ(i) = '1' THEN
vi.ss(i) := SSPOL;
END IF;
END LOOP;
END IF;
WHEN wait_ss_enable_setup =>
vi.clk_count := vi.clk_count + 1;
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.leading_edge := '1';
vi.rx_data_buf := (OTHERS => '0');
vi.state := process_data;
END IF;
WHEN process_data =>
--toggle sclk
IF vi.clk_count = to_unsigned(0,CYCLE_COUNTHER_WIDTH) THEN
vi.sclk := NOT vi.sclk;
vi.clk_count := to_unsigned(NR_OF_TICKS_PER_SCLK_EDGE,CYCLE_COUNTHER_WIDTH);
IF CPHA = '0' THEN -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
IF vi.leading_edge = '1' THEN
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
ELSE --trailing edge
vi.mosi := islv_tx_data(vi.bit_count);
change_bitcount;
END IF;
ELSE -- clock phase 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
IF vi.leading_edge = '1' THEN
vi.mosi := islv_tx_data(vi.bit_count);
ELSE --trailing edge
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
change_bitcount;
END IF;
END IF;
vi.leading_edge := NOT vi.leading_edge;
ELSE
vi.clk_count := vi.clk_count - 1;
END IF;
WHEN wait_ss_disable_setup =>
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.ss := (OTHERS => NOT SSPOL);
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := idle;
vi.rx_done := '1';
ELSE
vi.clk_count := vi.clk_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.sclk := CPOL;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.ss := (OTHERS => NOT SSPOL);
IF MSBFIRST = '0' THEN
vi.bit_count := 0;
ELSE
vi.bit_count := TRANSFER_WIDTH-1;
END IF;
vi.mosi := '0';
vi.leading_edge := '0';
vi.rx_data_buf := (OTHERS => '0');
vi.rx_done := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--output assignement
osl_sclk <= ri.sclk;
oslv_ss <= ri.ss;
osl_mosi <= ri.mosi;
osl_rx_done <= ri.rx_done;
oslv_rx_data <= ri.rx_data_buf;
END ARCHITECTURE rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:51 01/08/2014
-- Design Name:
-- Module Name: contador10bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity contador10bits is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
A_next : out STD_LOGIC_VECTOR (9 downto 0));
end contador10bits;
architecture Behavioral of contador10bits is
begin
process(A)
begin
A_next(0) <= not A(0);
if A(0) = '1' then
A_next(1) <= not A(1);
else
A_next(1) <= A(1);
end if;
if A(1 downto 0) = "11" then
A_next(2) <= not A(2);
else
A_next(2) <= A(2);
end if;
if A(2 downto 0) = "111" then
A_next(3) <= not A(3);
else
A_next(3) <= A(3);
end if;
if A(3 downto 0) = "1111" then
A_next(4) <= not A(4);
else
A_next(4) <= A(4);
end if;
if A(4 downto 0) = "11111" then
A_next(5) <= not A(5);
else
A_next(5) <= A(5);
end if;
if A(5 downto 0) = "111111" then
A_next(6) <= not A(6);
else
A_next(6) <= A(6);
end if;
if A(6 downto 0) = "1111111" then
A_next(7) <= not A(7);
else
A_next(7) <= A(7);
end if;
if A(7 downto 0) = "11111111" then
A_next(8) <= not A(8);
else
A_next(8) <= A(8);
end if;
if A(8 downto 0) = "111111111" then
A_next(9) <= not A(9);
else
A_next(9) <= A(9);
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_0;
ARCHITECTURE design_1_FIR_resized1_0_arch OF design_1_FIR_resized1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_0",
C_COEF_FILE => "design_1_FIR_resized1_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_0;
ARCHITECTURE design_1_FIR_resized1_0_arch OF design_1_FIR_resized1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_0",
C_COEF_FILE => "design_1_FIR_resized1_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_0;
ARCHITECTURE design_1_FIR_resized1_0_arch OF design_1_FIR_resized1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_0",
C_COEF_FILE => "design_1_FIR_resized1_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_0;
ARCHITECTURE design_1_FIR_resized1_0_arch OF design_1_FIR_resized1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_0",
C_COEF_FILE => "design_1_FIR_resized1_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_0_arch;
|
component ghrd_10as066n2_avlmm_pr_freeze_bridge_1 is
port (
clock : in std_logic := 'X'; -- clk
freeze_conduit_freeze : in std_logic := 'X'; -- freeze
freeze_conduit_illegal_request : out std_logic; -- illegal_request
mst_bridge_to_pr_read : in std_logic := 'X'; -- read
mst_bridge_to_pr_waitrequest : out std_logic; -- waitrequest
mst_bridge_to_pr_write : in std_logic := 'X'; -- write
mst_bridge_to_pr_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
mst_bridge_to_pr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
mst_bridge_to_pr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
mst_bridge_to_pr_readdata : out std_logic_vector(31 downto 0); -- readdata
mst_bridge_to_pr_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
mst_bridge_to_pr_readdatavalid : out std_logic; -- readdatavalid
mst_bridge_to_pr_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
mst_bridge_to_pr_debugaccess : in std_logic := 'X'; -- debugaccess
mst_bridge_to_pr_response : out std_logic_vector(1 downto 0); -- response
mst_bridge_to_pr_lock : in std_logic := 'X'; -- lock
mst_bridge_to_pr_writeresponsevalid : out std_logic; -- writeresponsevalid
mst_bridge_to_sr_read : out std_logic; -- read
mst_bridge_to_sr_waitrequest : in std_logic := 'X'; -- waitrequest
mst_bridge_to_sr_write : out std_logic; -- write
mst_bridge_to_sr_address : out std_logic_vector(31 downto 0); -- address
mst_bridge_to_sr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mst_bridge_to_sr_writedata : out std_logic_vector(31 downto 0); -- writedata
mst_bridge_to_sr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mst_bridge_to_sr_burstcount : out std_logic_vector(2 downto 0); -- burstcount
mst_bridge_to_sr_readdatavalid : in std_logic := 'X'; -- readdatavalid
mst_bridge_to_sr_beginbursttransfer : out std_logic; -- beginbursttransfer
mst_bridge_to_sr_debugaccess : out std_logic; -- debugaccess
mst_bridge_to_sr_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
mst_bridge_to_sr_lock : out std_logic; -- lock
mst_bridge_to_sr_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
reset_n : in std_logic := 'X' -- reset_n
);
end component ghrd_10as066n2_avlmm_pr_freeze_bridge_1;
u0 : component ghrd_10as066n2_avlmm_pr_freeze_bridge_1
port map (
clock => CONNECTED_TO_clock, -- clock.clk
freeze_conduit_freeze => CONNECTED_TO_freeze_conduit_freeze, -- freeze_conduit.freeze
freeze_conduit_illegal_request => CONNECTED_TO_freeze_conduit_illegal_request, -- .illegal_request
mst_bridge_to_pr_read => CONNECTED_TO_mst_bridge_to_pr_read, -- mst_bridge_to_pr.read
mst_bridge_to_pr_waitrequest => CONNECTED_TO_mst_bridge_to_pr_waitrequest, -- .waitrequest
mst_bridge_to_pr_write => CONNECTED_TO_mst_bridge_to_pr_write, -- .write
mst_bridge_to_pr_address => CONNECTED_TO_mst_bridge_to_pr_address, -- .address
mst_bridge_to_pr_byteenable => CONNECTED_TO_mst_bridge_to_pr_byteenable, -- .byteenable
mst_bridge_to_pr_writedata => CONNECTED_TO_mst_bridge_to_pr_writedata, -- .writedata
mst_bridge_to_pr_readdata => CONNECTED_TO_mst_bridge_to_pr_readdata, -- .readdata
mst_bridge_to_pr_burstcount => CONNECTED_TO_mst_bridge_to_pr_burstcount, -- .burstcount
mst_bridge_to_pr_readdatavalid => CONNECTED_TO_mst_bridge_to_pr_readdatavalid, -- .readdatavalid
mst_bridge_to_pr_beginbursttransfer => CONNECTED_TO_mst_bridge_to_pr_beginbursttransfer, -- .beginbursttransfer
mst_bridge_to_pr_debugaccess => CONNECTED_TO_mst_bridge_to_pr_debugaccess, -- .debugaccess
mst_bridge_to_pr_response => CONNECTED_TO_mst_bridge_to_pr_response, -- .response
mst_bridge_to_pr_lock => CONNECTED_TO_mst_bridge_to_pr_lock, -- .lock
mst_bridge_to_pr_writeresponsevalid => CONNECTED_TO_mst_bridge_to_pr_writeresponsevalid, -- .writeresponsevalid
mst_bridge_to_sr_read => CONNECTED_TO_mst_bridge_to_sr_read, -- mst_bridge_to_sr.read
mst_bridge_to_sr_waitrequest => CONNECTED_TO_mst_bridge_to_sr_waitrequest, -- .waitrequest
mst_bridge_to_sr_write => CONNECTED_TO_mst_bridge_to_sr_write, -- .write
mst_bridge_to_sr_address => CONNECTED_TO_mst_bridge_to_sr_address, -- .address
mst_bridge_to_sr_byteenable => CONNECTED_TO_mst_bridge_to_sr_byteenable, -- .byteenable
mst_bridge_to_sr_writedata => CONNECTED_TO_mst_bridge_to_sr_writedata, -- .writedata
mst_bridge_to_sr_readdata => CONNECTED_TO_mst_bridge_to_sr_readdata, -- .readdata
mst_bridge_to_sr_burstcount => CONNECTED_TO_mst_bridge_to_sr_burstcount, -- .burstcount
mst_bridge_to_sr_readdatavalid => CONNECTED_TO_mst_bridge_to_sr_readdatavalid, -- .readdatavalid
mst_bridge_to_sr_beginbursttransfer => CONNECTED_TO_mst_bridge_to_sr_beginbursttransfer, -- .beginbursttransfer
mst_bridge_to_sr_debugaccess => CONNECTED_TO_mst_bridge_to_sr_debugaccess, -- .debugaccess
mst_bridge_to_sr_response => CONNECTED_TO_mst_bridge_to_sr_response, -- .response
mst_bridge_to_sr_lock => CONNECTED_TO_mst_bridge_to_sr_lock, -- .lock
mst_bridge_to_sr_writeresponsevalid => CONNECTED_TO_mst_bridge_to_sr_writeresponsevalid, -- .writeresponsevalid
reset_n => CONNECTED_TO_reset_n -- reset_n.reset_n
);
|
architecture behav of tb is
begin
assert work.pkg2.get2 = 5;
end behav;
|
architecture behav of tb is
begin
assert work.pkg2.get2 = 5;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi_oc_tb is
end entity;
architecture behav of multi_oc_tb is
component multi_oc
port(
si : in std_logic_vector (3 downto 0);
se : in std_logic_vector (1 downto 0);
so : out std_logic
);
end component;
for multi_oc_0 : multi_oc use entity work.multi_oc;
signal si : std_logic_vector (3 downto 0);
signal se : std_logic_vector (1 downto 0);
signal so : std_logic;
begin
multi_oc_0 : multi_oc port map (si=>si, se=>se, so=>so);
process
begin
si<="1110";
se<="10";
wait for 5 ns;
si<="1110";
se<="00";
wait for 5 ns;
si<="1110";
se<="01";
wait for 5 ns;
si<="1110";
se<="11";
wait for 5 ns;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity NOC is
port(
clock : in regNrot;
reset : in std_logic;
clock_rxLocal : in regNrot;
rxLocal : in regNrot;
data_inLocal : in arrayNrot_regflit;
credit_oLocal : out regNrot;
clock_txLocal : out regNrot;
txLocal : out regNrot;
data_outLocal : out arrayNrot_regflit;
credit_iLocal : in regNrot);
end NOC;
architecture NOC of NOC is
signal rx, clock_rx, credit_i, tx, clock_tx, credit_o, testLink_i, testLink_o : arrayNrot_regNport;
signal data_in, data_out : matrixNrot_Nport_regflit;
begin
Router: FOR i IN 0 TO (NROT-1) GENERATE
n : Entity work.RouterCC
generic map
(
address => ADDRESS_FROM_INDEX(i),
ramInit => TAB(i)
)
port map
(
clock => clock(i),
reset => reset,
clock_rx => clock_rx(i),
rx => rx(i),
data_in => data_in(i),
credit_o => credit_o(i),
clock_tx => clock_tx(i),
tx => tx(i),
data_out => data_out(i),
credit_i => credit_i(i)
);
END GENERATE Router;
internal_ports: FOR i IN 0 TO (NROT-1) GENERATE
east: if i < NUM_Y*MAX_X GENERATE
clock_rx(i)(0) <= clock_tx(i+NUM_Y)(1);
rx(i)(0) <= tx(i+NUM_Y)(1);
data_in(i)(0) <= data_out(i+NUM_Y)(1);
credit_i(i)(0) <= credit_o(i+NUM_Y)(1);
end GENERATE;
west: if i >= NUM_Y GENERATE
clock_rx(i)(1) <= clock_tx(i-NUM_Y)(0);
rx(i)(1) <= tx(i-NUM_Y)(0);
data_in(i)(1) <= data_out(i-NUM_Y)(0);
credit_i(i)(1) <= credit_o(i-NUM_Y)(0);
end GENERATE;
north: if (i-(i/NUM_Y)*NUM_Y) < MAX_Y GENERATE
clock_rx(i)(2) <= clock_tx(i+1)(3);
rx(i)(2) <= tx(i+1)(3);
data_in(i)(2) <= data_out(i+1)(3);
credit_i(i)(2) <= credit_o(i+1)(3);
end GENERATE;
south: if (i-(i/NUM_Y)*NUM_Y) > MIN_Y GENERATE
clock_rx(i)(3) <= clock_tx(i-1)(2);
rx(i)(3)<=tx(i-1)(2);
data_in(i)(3)<=data_out(i-1)(2);
credit_i(i)(3)<=credit_o(i-1)(2);
end GENERATE;
END GENERATE;
local_port : FOR i IN 0 TO (NROT-1) GENERATE
clock_rx(i)(LOCAL)<= clock_rxLocal(i);
data_in(i)(LOCAL)<=data_inLocal(i);
credit_i(i)(LOCAL)<=credit_iLocal(i);
rx(i)(LOCAL)<=rxLocal(i);
clock_txLocal(i)<= clock_tx(i)(LOCAL);
data_outLocal(i)<=data_out(i)(LOCAL);
credit_oLocal(i)<=credit_o(i)(LOCAL);
txLocal(i)<=tx(i)(LOCAL);
END GENERATE;
end NOC;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity contact_discovery is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
contacts_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_in_V_TVALID : IN STD_LOGIC;
contacts_in_V_TREADY : OUT STD_LOGIC;
database_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
database_in_V_TVALID : IN STD_LOGIC;
database_in_V_TREADY : OUT STD_LOGIC;
matched_out_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
matched_out_V_TVALID : OUT STD_LOGIC;
matched_out_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of contact_discovery is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.932500,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=461,HLS_SYN_LUT=838}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal operation_ap_vld : STD_LOGIC;
signal operation_ap_vld_preg : STD_LOGIC := '0';
signal operation_ap_vld_in_sig : STD_LOGIC;
signal matched_out_V_1_data_out : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_vld_in : STD_LOGIC;
signal matched_out_V_1_vld_out : STD_LOGIC;
signal matched_out_V_1_ack_in : STD_LOGIC;
signal matched_out_V_1_ack_out : STD_LOGIC;
signal matched_out_V_1_payload_A : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_payload_B : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_sel_rd : STD_LOGIC := '0';
signal matched_out_V_1_sel_wr : STD_LOGIC := '0';
signal matched_out_V_1_sel : STD_LOGIC;
signal matched_out_V_1_load_A : STD_LOGIC;
signal matched_out_V_1_load_B : STD_LOGIC;
signal matched_out_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal matched_out_V_1_state_cmp_full : STD_LOGIC;
signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal matched_finished_1_vld_reg : STD_LOGIC := '0';
signal matched_finished_1_vld_in : STD_LOGIC;
signal matched_finished_1_ack_in : STD_LOGIC;
signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal error_out_1_vld_reg : STD_LOGIC := '0';
signal error_out_1_vld_in : STD_LOGIC;
signal error_out_1_ack_in : STD_LOGIC;
signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal contacts_size_out_1_vld_reg : STD_LOGIC := '0';
signal contacts_size_out_1_vld_in : STD_LOGIC;
signal contacts_size_out_1_ack_in : STD_LOGIC;
signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal contacts_ce0 : STD_LOGIC;
signal contacts_we0 : STD_LOGIC;
signal contacts_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal current_database_ite_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal current_database_ite_ce0 : STD_LOGIC;
signal current_database_ite_we0 : STD_LOGIC;
signal current_database_ite_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal operation_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal contacts_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal exitcond9_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal database_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal exitcond8_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal matched_out_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal exitcond7_fu_346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_read_fu_98_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_318_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_2_fu_335_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state6 : BOOLEAN;
signal i_5_fu_352_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_512 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state7_io : BOOLEAN;
signal tmp_i_fu_362_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_i_reg_517 : STD_LOGIC_VECTOR (12 downto 0);
signal cast_fu_370_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_fu_385_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_6_reg_530 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal exitcond_i_fu_379_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_1_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal icmp_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_nbreadreq_fu_151_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_450_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state13 : BOOLEAN;
signal tmp_9_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_reg_217 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal exitcond_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_reg_228 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_1_nbreadreq_fu_129_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_239 : STD_LOGIC_VECTOR (0 downto 0);
signal contact_index_assign_reg_251 : STD_LOGIC_VECTOR (7 downto 0);
signal i_i_reg_262 : STD_LOGIC_VECTOR (6 downto 0);
signal comp_reg_273 : STD_LOGIC_VECTOR (0 downto 0);
signal i1_reg_285 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_341_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_7_fu_391_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_i_fu_401_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_468_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_11_fu_358_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal i_i_cast7_fu_375_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_12_i_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_14_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_424_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_6_fu_456_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i1_cast_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_block_state11 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component contact_discoverybkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverycud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discovery_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0);
operation_ap_vld : OUT STD_LOGIC;
matched_finished : IN STD_LOGIC_VECTOR (31 downto 0);
error_out : IN STD_LOGIC_VECTOR (31 downto 0);
contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
contacts_U : component contact_discoverybkb
generic map (
DataWidth => 8,
AddressRange => 8192,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => contacts_address0,
ce0 => contacts_ce0,
we0 => contacts_we0,
d0 => contacts_d0,
q0 => contacts_q0);
current_database_ite_U : component contact_discoverycud
generic map (
DataWidth => 8,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => current_database_ite_address0,
ce0 => current_database_ite_ce0,
we0 => current_database_ite_we0,
d0 => database_in_V_TDATA,
q0 => current_database_ite_q0);
contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation,
operation_ap_vld => operation_ap_vld,
matched_finished => matched_finished_1_data_reg,
error_out => error_out_1_data_reg,
contacts_size_out => contacts_size_out_1_data_reg);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
matched_out_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_ack_out) and (ap_const_logic_1 = matched_out_V_1_vld_out))) then
matched_out_V_1_sel_rd <= not(matched_out_V_1_sel_rd);
end if;
end if;
end if;
end process;
matched_out_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_in))) then
matched_out_V_1_sel_wr <= not(matched_out_V_1_sel_wr);
end if;
end if;
end if;
end process;
matched_out_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)))) then
matched_out_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)))) then
matched_out_V_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)) or ((matched_out_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out))) and not(((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out)))))) then
matched_out_V_1_state <= ap_const_lv2_3;
else
matched_out_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
operation_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_ap_vld_preg <= operation_ap_vld;
elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
operation_ap_vld_preg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
operation_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_preg <= operation;
end if;
end if;
end if;
end process;
comp_reg_273_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
comp_reg_273 <= found_1_fu_418_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
comp_reg_273 <= ap_const_lv1_1;
end if;
end if;
end process;
contact_index_assign_reg_251_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
contact_index_assign_reg_251 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
contact_index_assign_reg_251 <= i_5_reg_512;
end if;
end if;
end process;
contacts_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size <= tmp_9_fu_473_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size <= ap_const_lv32_0;
end if;
end if;
end process;
contacts_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
error_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
i1_reg_285_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
i1_reg_285 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
i1_reg_285 <= i_4_fu_450_p2;
end if;
end if;
end process;
i_1_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
i_1_reg_228 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
i_1_reg_228 <= i_2_fu_335_p2;
end if;
end if;
end process;
i_3_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2))) then
i_3_reg_217 <= i_fu_318_p2;
elsif (((grp_read_fu_98_p2 = ap_const_lv32_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
i_3_reg_217 <= ap_const_lv8_0;
end if;
end if;
end process;
i_i_reg_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_i_reg_262 <= i_6_reg_530;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
i_i_reg_262 <= ap_const_lv7_0;
end if;
end if;
end process;
matched_finished_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
tmp_10_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
tmp_10_reg_239 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
tmp_10_reg_239 <= found_fu_406_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_data_reg <= contacts_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_data_reg <= error_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0))) then
i_5_reg_512 <= i_5_fu_352_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
i_6_reg_530 <= i_6_fu_385_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_data_reg <= matched_finished_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_A)) then
matched_out_V_1_payload_A <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_B)) then
matched_out_V_1_payload_B <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
tmp_i_reg_517(12 downto 6) <= tmp_i_fu_362_p3(12 downto 6);
end if;
end if;
end process;
tmp_i_reg_517(5 downto 0) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_in_V_TVALID, database_in_V_TVALID, matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state2, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10, grp_read_fu_98_p2, ap_CS_fsm_state4, ap_block_state7_io, ap_CS_fsm_state8, exitcond_i_fu_379_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3, ap_CS_fsm_state3, exitcond_fu_312_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3, ap_CS_fsm_state11)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
if ((not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_lv32_0 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state12;
elsif (((ap_const_lv32_1 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_312_p2))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
ap_NS_fsm <= ap_ST_fsm_state8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (matched_out_V_1_ack_in = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_0 = tmp_nbreadreq_fu_151_p3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state13;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state11_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in)
begin
ap_block_state11 <= ((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in));
end process;
ap_block_state13_assign_proc : process(contacts_in_V_TVALID, exitcond9_fu_444_p2)
begin
ap_block_state13 <= ((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID));
end process;
ap_block_state6_assign_proc : process(database_in_V_TVALID, exitcond8_fu_329_p2)
begin
ap_block_state6 <= ((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID));
end process;
ap_block_state7_io_assign_proc : process(matched_out_V_1_ack_in, exitcond7_fu_346_p2)
begin
ap_block_state7_io <= ((ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_const_logic_0 = matched_out_V_1_ack_in));
end process;
ap_done_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
cast_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_239),8));
contacts_address0_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state4, ap_CS_fsm_state8, tmp_3_fu_324_p1, tmp_13_i_fu_401_p1, tmp_s_fu_468_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address0 <= tmp_s_fu_468_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address0 <= tmp_13_i_fu_401_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= tmp_3_fu_324_p1(13 - 1 downto 0);
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_ce0 <= ap_const_logic_1;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_d0_assign_proc : process(contacts_in_V_TDATA, ap_CS_fsm_state13, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_d0 <= contacts_in_V_TDATA;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_d0 <= ap_const_lv8_0;
else
contacts_d0 <= "XXXXXXXX";
end if;
end process;
contacts_in_V_TDATA_blk_n_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2)))) then
contacts_in_V_TDATA_blk_n <= contacts_in_V_TVALID;
else
contacts_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
contacts_in_V_TREADY_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1)))) then
contacts_in_V_TREADY <= ap_const_logic_1;
else
contacts_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_ack_in <= ap_const_logic_1;
else
contacts_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, contacts_size, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, tmp_9_fu_473_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size_out_1_data_in <= tmp_9_fu_473_p2;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))))) then
contacts_size_out_1_data_in <= contacts_size;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size_out_1_data_in <= ap_const_lv32_0;
else
contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
contacts_size_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
contacts_size_out_1_vld_in <= ap_const_logic_1;
else
contacts_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
contacts_we0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, exitcond_fu_312_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_we0 <= ap_const_logic_1;
else
contacts_we0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state8, tmp_7_fu_341_p1, tmp_i_7_fu_391_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
current_database_ite_address0 <= tmp_i_7_fu_391_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
current_database_ite_address0 <= tmp_7_fu_341_p1(6 - 1 downto 0);
else
current_database_ite_address0 <= "XXXXXX";
end if;
end process;
current_database_ite_ce0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state8)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)))) or (ap_const_logic_1 = ap_CS_fsm_state8))) then
current_database_ite_ce0 <= ap_const_logic_1;
else
current_database_ite_ce0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_we0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
current_database_ite_we0 <= ap_const_logic_1;
else
current_database_ite_we0 <= ap_const_logic_0;
end if;
end process;
database_in_V_TDATA_blk_n_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2))) then
database_in_V_TDATA_blk_n <= database_in_V_TVALID;
else
database_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
database_in_V_TREADY_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
database_in_V_TREADY <= ap_const_logic_1;
else
database_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg)
begin
if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_ack_in <= ap_const_logic_1;
else
error_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
error_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2))) then
error_out_1_data_in <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_3;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_0;
else
error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
error_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2)))) then
error_out_1_vld_in <= ap_const_logic_1;
else
error_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
exitcond7_fu_346_p2 <= "1" when (contact_index_assign_reg_251 = ap_const_lv8_80) else "0";
exitcond8_fu_329_p2 <= "1" when (i_1_reg_228 = ap_const_lv7_40) else "0";
exitcond9_fu_444_p2 <= "1" when (i1_reg_285 = ap_const_lv7_40) else "0";
exitcond_fu_312_p2 <= "1" when (i_3_reg_217 = ap_const_lv8_80) else "0";
exitcond_i_fu_379_p2 <= "1" when (i_i_reg_262 = ap_const_lv7_40) else "0";
found_1_fu_418_p2 <= (tmp_14_i_fu_412_p2 and comp_reg_273);
found_fu_406_p2 <= (comp_reg_273 or tmp_10_reg_239);
grp_read_fu_98_p2 <= operation_preg;
i1_cast_fu_440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_reg_285),32));
i_2_fu_335_p2 <= std_logic_vector(unsigned(i_1_reg_228) + unsigned(ap_const_lv7_1));
i_4_fu_450_p2 <= std_logic_vector(unsigned(i1_reg_285) + unsigned(ap_const_lv7_1));
i_5_fu_352_p2 <= std_logic_vector(unsigned(contact_index_assign_reg_251) + unsigned(ap_const_lv8_1));
i_6_fu_385_p2 <= std_logic_vector(unsigned(i_i_reg_262) + unsigned(ap_const_lv7_1));
i_fu_318_p2 <= std_logic_vector(unsigned(i_3_reg_217) + unsigned(ap_const_lv8_1));
i_i_cast7_fu_375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),13));
icmp_fu_434_p2 <= "1" when (signed(tmp_2_fu_424_p4) > signed(ap_const_lv25_0)) else "0";
matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg)
begin
if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_ack_in <= ap_const_logic_1;
else
matched_finished_1_ack_in <= ap_const_logic_0;
end if;
end process;
matched_finished_1_data_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3))) then
matched_finished_1_data_in <= ap_const_lv32_1;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
matched_finished_1_data_in <= ap_const_lv32_0;
else
matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
matched_finished_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3)))) then
matched_finished_1_vld_in <= ap_const_logic_1;
else
matched_finished_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_ack_in <= matched_out_V_1_state(1);
matched_out_V_1_ack_out <= matched_out_V_TREADY;
matched_out_V_1_data_out_assign_proc : process(matched_out_V_1_payload_A, matched_out_V_1_payload_B, matched_out_V_1_sel)
begin
if ((ap_const_logic_1 = matched_out_V_1_sel)) then
matched_out_V_1_data_out <= matched_out_V_1_payload_B;
else
matched_out_V_1_data_out <= matched_out_V_1_payload_A;
end if;
end process;
matched_out_V_1_load_A <= (matched_out_V_1_state_cmp_full and not(matched_out_V_1_sel_wr));
matched_out_V_1_load_B <= (matched_out_V_1_sel_wr and matched_out_V_1_state_cmp_full);
matched_out_V_1_sel <= matched_out_V_1_sel_rd;
matched_out_V_1_state_cmp_full <= '0' when (matched_out_V_1_state = ap_const_lv2_1) else '1';
matched_out_V_1_vld_in_assign_proc : process(ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_block_state7_io)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
matched_out_V_1_vld_in <= ap_const_logic_1;
else
matched_out_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_vld_out <= matched_out_V_1_state(0);
matched_out_V_TDATA <= matched_out_V_1_data_out;
matched_out_V_TDATA_blk_n_assign_proc : process(matched_out_V_1_state, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2)) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
matched_out_V_TDATA_blk_n <= matched_out_V_1_state(1);
else
matched_out_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
matched_out_V_TVALID <= matched_out_V_1_state(0);
operation_ap_vld_in_sig <= operation_ap_vld_preg;
operation_blk_n_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
operation_blk_n <= ap_const_logic_0;
else
operation_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_11_fu_358_p1 <= contact_index_assign_reg_251(7 - 1 downto 0);
tmp_12_i_fu_396_p2 <= std_logic_vector(unsigned(i_i_cast7_fu_375_p1) + unsigned(tmp_i_reg_517));
tmp_13_i_fu_401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_i_fu_396_p2),64));
tmp_14_i_fu_412_p2 <= "1" when (current_database_ite_q0 = contacts_q0) else "0";
tmp_1_nbreadreq_fu_129_p3 <= (0=>database_in_V_TVALID, others=>'-');
tmp_2_fu_424_p4 <= contacts_size(31 downto 7);
tmp_3_fu_324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_3_reg_217),64));
tmp_6_fu_456_p2 <= std_logic_vector(shift_left(unsigned(contacts_size),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
tmp_7_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_228),64));
tmp_8_fu_462_p2 <= std_logic_vector(unsigned(tmp_6_fu_456_p2) + unsigned(i1_cast_fu_440_p1));
tmp_9_fu_473_p2 <= std_logic_vector(unsigned(contacts_size) + unsigned(ap_const_lv32_1));
tmp_i_7_fu_391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),64));
tmp_i_fu_362_p3 <= (tmp_11_fu_358_p1 & ap_const_lv6_0);
tmp_nbreadreq_fu_151_p3 <= (0=>contacts_in_V_TVALID, others=>'-');
tmp_s_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_fu_462_p2),64));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity contact_discovery is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
contacts_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_in_V_TVALID : IN STD_LOGIC;
contacts_in_V_TREADY : OUT STD_LOGIC;
database_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
database_in_V_TVALID : IN STD_LOGIC;
database_in_V_TREADY : OUT STD_LOGIC;
matched_out_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
matched_out_V_TVALID : OUT STD_LOGIC;
matched_out_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of contact_discovery is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.932500,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=461,HLS_SYN_LUT=838}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal operation_ap_vld : STD_LOGIC;
signal operation_ap_vld_preg : STD_LOGIC := '0';
signal operation_ap_vld_in_sig : STD_LOGIC;
signal matched_out_V_1_data_out : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_vld_in : STD_LOGIC;
signal matched_out_V_1_vld_out : STD_LOGIC;
signal matched_out_V_1_ack_in : STD_LOGIC;
signal matched_out_V_1_ack_out : STD_LOGIC;
signal matched_out_V_1_payload_A : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_payload_B : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_sel_rd : STD_LOGIC := '0';
signal matched_out_V_1_sel_wr : STD_LOGIC := '0';
signal matched_out_V_1_sel : STD_LOGIC;
signal matched_out_V_1_load_A : STD_LOGIC;
signal matched_out_V_1_load_B : STD_LOGIC;
signal matched_out_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal matched_out_V_1_state_cmp_full : STD_LOGIC;
signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal matched_finished_1_vld_reg : STD_LOGIC := '0';
signal matched_finished_1_vld_in : STD_LOGIC;
signal matched_finished_1_ack_in : STD_LOGIC;
signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal error_out_1_vld_reg : STD_LOGIC := '0';
signal error_out_1_vld_in : STD_LOGIC;
signal error_out_1_ack_in : STD_LOGIC;
signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal contacts_size_out_1_vld_reg : STD_LOGIC := '0';
signal contacts_size_out_1_vld_in : STD_LOGIC;
signal contacts_size_out_1_ack_in : STD_LOGIC;
signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal contacts_ce0 : STD_LOGIC;
signal contacts_we0 : STD_LOGIC;
signal contacts_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal current_database_ite_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal current_database_ite_ce0 : STD_LOGIC;
signal current_database_ite_we0 : STD_LOGIC;
signal current_database_ite_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal operation_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal contacts_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal exitcond9_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal database_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal exitcond8_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal matched_out_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal exitcond7_fu_346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_read_fu_98_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_318_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_2_fu_335_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state6 : BOOLEAN;
signal i_5_fu_352_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_512 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state7_io : BOOLEAN;
signal tmp_i_fu_362_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_i_reg_517 : STD_LOGIC_VECTOR (12 downto 0);
signal cast_fu_370_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_fu_385_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_6_reg_530 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal exitcond_i_fu_379_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_1_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal icmp_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_nbreadreq_fu_151_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_450_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state13 : BOOLEAN;
signal tmp_9_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_reg_217 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal exitcond_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_reg_228 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_1_nbreadreq_fu_129_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_239 : STD_LOGIC_VECTOR (0 downto 0);
signal contact_index_assign_reg_251 : STD_LOGIC_VECTOR (7 downto 0);
signal i_i_reg_262 : STD_LOGIC_VECTOR (6 downto 0);
signal comp_reg_273 : STD_LOGIC_VECTOR (0 downto 0);
signal i1_reg_285 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_341_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_7_fu_391_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_i_fu_401_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_468_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_11_fu_358_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal i_i_cast7_fu_375_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_12_i_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_14_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_424_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_6_fu_456_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i1_cast_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_block_state11 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component contact_discoverybkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverycud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discovery_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0);
operation_ap_vld : OUT STD_LOGIC;
matched_finished : IN STD_LOGIC_VECTOR (31 downto 0);
error_out : IN STD_LOGIC_VECTOR (31 downto 0);
contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
contacts_U : component contact_discoverybkb
generic map (
DataWidth => 8,
AddressRange => 8192,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => contacts_address0,
ce0 => contacts_ce0,
we0 => contacts_we0,
d0 => contacts_d0,
q0 => contacts_q0);
current_database_ite_U : component contact_discoverycud
generic map (
DataWidth => 8,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => current_database_ite_address0,
ce0 => current_database_ite_ce0,
we0 => current_database_ite_we0,
d0 => database_in_V_TDATA,
q0 => current_database_ite_q0);
contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation,
operation_ap_vld => operation_ap_vld,
matched_finished => matched_finished_1_data_reg,
error_out => error_out_1_data_reg,
contacts_size_out => contacts_size_out_1_data_reg);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
matched_out_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_ack_out) and (ap_const_logic_1 = matched_out_V_1_vld_out))) then
matched_out_V_1_sel_rd <= not(matched_out_V_1_sel_rd);
end if;
end if;
end if;
end process;
matched_out_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_in))) then
matched_out_V_1_sel_wr <= not(matched_out_V_1_sel_wr);
end if;
end if;
end if;
end process;
matched_out_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)))) then
matched_out_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)))) then
matched_out_V_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)) or ((matched_out_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out))) and not(((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out)))))) then
matched_out_V_1_state <= ap_const_lv2_3;
else
matched_out_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
operation_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_ap_vld_preg <= operation_ap_vld;
elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
operation_ap_vld_preg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
operation_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_preg <= operation;
end if;
end if;
end if;
end process;
comp_reg_273_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
comp_reg_273 <= found_1_fu_418_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
comp_reg_273 <= ap_const_lv1_1;
end if;
end if;
end process;
contact_index_assign_reg_251_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
contact_index_assign_reg_251 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
contact_index_assign_reg_251 <= i_5_reg_512;
end if;
end if;
end process;
contacts_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size <= tmp_9_fu_473_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size <= ap_const_lv32_0;
end if;
end if;
end process;
contacts_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
error_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
i1_reg_285_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
i1_reg_285 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
i1_reg_285 <= i_4_fu_450_p2;
end if;
end if;
end process;
i_1_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
i_1_reg_228 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
i_1_reg_228 <= i_2_fu_335_p2;
end if;
end if;
end process;
i_3_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2))) then
i_3_reg_217 <= i_fu_318_p2;
elsif (((grp_read_fu_98_p2 = ap_const_lv32_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
i_3_reg_217 <= ap_const_lv8_0;
end if;
end if;
end process;
i_i_reg_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_i_reg_262 <= i_6_reg_530;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
i_i_reg_262 <= ap_const_lv7_0;
end if;
end if;
end process;
matched_finished_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
tmp_10_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
tmp_10_reg_239 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
tmp_10_reg_239 <= found_fu_406_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_data_reg <= contacts_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_data_reg <= error_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0))) then
i_5_reg_512 <= i_5_fu_352_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
i_6_reg_530 <= i_6_fu_385_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_data_reg <= matched_finished_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_A)) then
matched_out_V_1_payload_A <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_B)) then
matched_out_V_1_payload_B <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
tmp_i_reg_517(12 downto 6) <= tmp_i_fu_362_p3(12 downto 6);
end if;
end if;
end process;
tmp_i_reg_517(5 downto 0) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_in_V_TVALID, database_in_V_TVALID, matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state2, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10, grp_read_fu_98_p2, ap_CS_fsm_state4, ap_block_state7_io, ap_CS_fsm_state8, exitcond_i_fu_379_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3, ap_CS_fsm_state3, exitcond_fu_312_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3, ap_CS_fsm_state11)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
if ((not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_lv32_0 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state12;
elsif (((ap_const_lv32_1 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_312_p2))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
ap_NS_fsm <= ap_ST_fsm_state8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (matched_out_V_1_ack_in = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_0 = tmp_nbreadreq_fu_151_p3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state13;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state11_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in)
begin
ap_block_state11 <= ((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in));
end process;
ap_block_state13_assign_proc : process(contacts_in_V_TVALID, exitcond9_fu_444_p2)
begin
ap_block_state13 <= ((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID));
end process;
ap_block_state6_assign_proc : process(database_in_V_TVALID, exitcond8_fu_329_p2)
begin
ap_block_state6 <= ((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID));
end process;
ap_block_state7_io_assign_proc : process(matched_out_V_1_ack_in, exitcond7_fu_346_p2)
begin
ap_block_state7_io <= ((ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_const_logic_0 = matched_out_V_1_ack_in));
end process;
ap_done_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
cast_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_239),8));
contacts_address0_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state4, ap_CS_fsm_state8, tmp_3_fu_324_p1, tmp_13_i_fu_401_p1, tmp_s_fu_468_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address0 <= tmp_s_fu_468_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address0 <= tmp_13_i_fu_401_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= tmp_3_fu_324_p1(13 - 1 downto 0);
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_ce0 <= ap_const_logic_1;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_d0_assign_proc : process(contacts_in_V_TDATA, ap_CS_fsm_state13, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_d0 <= contacts_in_V_TDATA;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_d0 <= ap_const_lv8_0;
else
contacts_d0 <= "XXXXXXXX";
end if;
end process;
contacts_in_V_TDATA_blk_n_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2)))) then
contacts_in_V_TDATA_blk_n <= contacts_in_V_TVALID;
else
contacts_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
contacts_in_V_TREADY_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1)))) then
contacts_in_V_TREADY <= ap_const_logic_1;
else
contacts_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_ack_in <= ap_const_logic_1;
else
contacts_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, contacts_size, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, tmp_9_fu_473_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size_out_1_data_in <= tmp_9_fu_473_p2;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))))) then
contacts_size_out_1_data_in <= contacts_size;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size_out_1_data_in <= ap_const_lv32_0;
else
contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
contacts_size_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
contacts_size_out_1_vld_in <= ap_const_logic_1;
else
contacts_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
contacts_we0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, exitcond_fu_312_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_we0 <= ap_const_logic_1;
else
contacts_we0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state8, tmp_7_fu_341_p1, tmp_i_7_fu_391_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
current_database_ite_address0 <= tmp_i_7_fu_391_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
current_database_ite_address0 <= tmp_7_fu_341_p1(6 - 1 downto 0);
else
current_database_ite_address0 <= "XXXXXX";
end if;
end process;
current_database_ite_ce0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state8)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)))) or (ap_const_logic_1 = ap_CS_fsm_state8))) then
current_database_ite_ce0 <= ap_const_logic_1;
else
current_database_ite_ce0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_we0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
current_database_ite_we0 <= ap_const_logic_1;
else
current_database_ite_we0 <= ap_const_logic_0;
end if;
end process;
database_in_V_TDATA_blk_n_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2))) then
database_in_V_TDATA_blk_n <= database_in_V_TVALID;
else
database_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
database_in_V_TREADY_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
database_in_V_TREADY <= ap_const_logic_1;
else
database_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg)
begin
if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_ack_in <= ap_const_logic_1;
else
error_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
error_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2))) then
error_out_1_data_in <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_3;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_0;
else
error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
error_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2)))) then
error_out_1_vld_in <= ap_const_logic_1;
else
error_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
exitcond7_fu_346_p2 <= "1" when (contact_index_assign_reg_251 = ap_const_lv8_80) else "0";
exitcond8_fu_329_p2 <= "1" when (i_1_reg_228 = ap_const_lv7_40) else "0";
exitcond9_fu_444_p2 <= "1" when (i1_reg_285 = ap_const_lv7_40) else "0";
exitcond_fu_312_p2 <= "1" when (i_3_reg_217 = ap_const_lv8_80) else "0";
exitcond_i_fu_379_p2 <= "1" when (i_i_reg_262 = ap_const_lv7_40) else "0";
found_1_fu_418_p2 <= (tmp_14_i_fu_412_p2 and comp_reg_273);
found_fu_406_p2 <= (comp_reg_273 or tmp_10_reg_239);
grp_read_fu_98_p2 <= operation_preg;
i1_cast_fu_440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_reg_285),32));
i_2_fu_335_p2 <= std_logic_vector(unsigned(i_1_reg_228) + unsigned(ap_const_lv7_1));
i_4_fu_450_p2 <= std_logic_vector(unsigned(i1_reg_285) + unsigned(ap_const_lv7_1));
i_5_fu_352_p2 <= std_logic_vector(unsigned(contact_index_assign_reg_251) + unsigned(ap_const_lv8_1));
i_6_fu_385_p2 <= std_logic_vector(unsigned(i_i_reg_262) + unsigned(ap_const_lv7_1));
i_fu_318_p2 <= std_logic_vector(unsigned(i_3_reg_217) + unsigned(ap_const_lv8_1));
i_i_cast7_fu_375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),13));
icmp_fu_434_p2 <= "1" when (signed(tmp_2_fu_424_p4) > signed(ap_const_lv25_0)) else "0";
matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg)
begin
if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_ack_in <= ap_const_logic_1;
else
matched_finished_1_ack_in <= ap_const_logic_0;
end if;
end process;
matched_finished_1_data_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3))) then
matched_finished_1_data_in <= ap_const_lv32_1;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
matched_finished_1_data_in <= ap_const_lv32_0;
else
matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
matched_finished_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3)))) then
matched_finished_1_vld_in <= ap_const_logic_1;
else
matched_finished_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_ack_in <= matched_out_V_1_state(1);
matched_out_V_1_ack_out <= matched_out_V_TREADY;
matched_out_V_1_data_out_assign_proc : process(matched_out_V_1_payload_A, matched_out_V_1_payload_B, matched_out_V_1_sel)
begin
if ((ap_const_logic_1 = matched_out_V_1_sel)) then
matched_out_V_1_data_out <= matched_out_V_1_payload_B;
else
matched_out_V_1_data_out <= matched_out_V_1_payload_A;
end if;
end process;
matched_out_V_1_load_A <= (matched_out_V_1_state_cmp_full and not(matched_out_V_1_sel_wr));
matched_out_V_1_load_B <= (matched_out_V_1_sel_wr and matched_out_V_1_state_cmp_full);
matched_out_V_1_sel <= matched_out_V_1_sel_rd;
matched_out_V_1_state_cmp_full <= '0' when (matched_out_V_1_state = ap_const_lv2_1) else '1';
matched_out_V_1_vld_in_assign_proc : process(ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_block_state7_io)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
matched_out_V_1_vld_in <= ap_const_logic_1;
else
matched_out_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_vld_out <= matched_out_V_1_state(0);
matched_out_V_TDATA <= matched_out_V_1_data_out;
matched_out_V_TDATA_blk_n_assign_proc : process(matched_out_V_1_state, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2)) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
matched_out_V_TDATA_blk_n <= matched_out_V_1_state(1);
else
matched_out_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
matched_out_V_TVALID <= matched_out_V_1_state(0);
operation_ap_vld_in_sig <= operation_ap_vld_preg;
operation_blk_n_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
operation_blk_n <= ap_const_logic_0;
else
operation_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_11_fu_358_p1 <= contact_index_assign_reg_251(7 - 1 downto 0);
tmp_12_i_fu_396_p2 <= std_logic_vector(unsigned(i_i_cast7_fu_375_p1) + unsigned(tmp_i_reg_517));
tmp_13_i_fu_401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_i_fu_396_p2),64));
tmp_14_i_fu_412_p2 <= "1" when (current_database_ite_q0 = contacts_q0) else "0";
tmp_1_nbreadreq_fu_129_p3 <= (0=>database_in_V_TVALID, others=>'-');
tmp_2_fu_424_p4 <= contacts_size(31 downto 7);
tmp_3_fu_324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_3_reg_217),64));
tmp_6_fu_456_p2 <= std_logic_vector(shift_left(unsigned(contacts_size),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
tmp_7_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_228),64));
tmp_8_fu_462_p2 <= std_logic_vector(unsigned(tmp_6_fu_456_p2) + unsigned(i1_cast_fu_440_p1));
tmp_9_fu_473_p2 <= std_logic_vector(unsigned(contacts_size) + unsigned(ap_const_lv32_1));
tmp_i_7_fu_391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),64));
tmp_i_fu_362_p3 <= (tmp_11_fu_358_p1 & ap_const_lv6_0);
tmp_nbreadreq_fu_151_p3 <= (0=>contacts_in_V_TVALID, others=>'-');
tmp_s_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_fu_462_p2),64));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity contact_discovery is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
contacts_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_in_V_TVALID : IN STD_LOGIC;
contacts_in_V_TREADY : OUT STD_LOGIC;
database_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
database_in_V_TVALID : IN STD_LOGIC;
database_in_V_TREADY : OUT STD_LOGIC;
matched_out_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
matched_out_V_TVALID : OUT STD_LOGIC;
matched_out_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of contact_discovery is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.932500,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=461,HLS_SYN_LUT=838}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal operation_ap_vld : STD_LOGIC;
signal operation_ap_vld_preg : STD_LOGIC := '0';
signal operation_ap_vld_in_sig : STD_LOGIC;
signal matched_out_V_1_data_out : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_vld_in : STD_LOGIC;
signal matched_out_V_1_vld_out : STD_LOGIC;
signal matched_out_V_1_ack_in : STD_LOGIC;
signal matched_out_V_1_ack_out : STD_LOGIC;
signal matched_out_V_1_payload_A : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_payload_B : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_sel_rd : STD_LOGIC := '0';
signal matched_out_V_1_sel_wr : STD_LOGIC := '0';
signal matched_out_V_1_sel : STD_LOGIC;
signal matched_out_V_1_load_A : STD_LOGIC;
signal matched_out_V_1_load_B : STD_LOGIC;
signal matched_out_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal matched_out_V_1_state_cmp_full : STD_LOGIC;
signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal matched_finished_1_vld_reg : STD_LOGIC := '0';
signal matched_finished_1_vld_in : STD_LOGIC;
signal matched_finished_1_ack_in : STD_LOGIC;
signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal error_out_1_vld_reg : STD_LOGIC := '0';
signal error_out_1_vld_in : STD_LOGIC;
signal error_out_1_ack_in : STD_LOGIC;
signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal contacts_size_out_1_vld_reg : STD_LOGIC := '0';
signal contacts_size_out_1_vld_in : STD_LOGIC;
signal contacts_size_out_1_ack_in : STD_LOGIC;
signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal contacts_ce0 : STD_LOGIC;
signal contacts_we0 : STD_LOGIC;
signal contacts_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal current_database_ite_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal current_database_ite_ce0 : STD_LOGIC;
signal current_database_ite_we0 : STD_LOGIC;
signal current_database_ite_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal operation_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal contacts_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal exitcond9_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal database_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal exitcond8_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal matched_out_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal exitcond7_fu_346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_read_fu_98_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_318_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_2_fu_335_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state6 : BOOLEAN;
signal i_5_fu_352_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_512 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state7_io : BOOLEAN;
signal tmp_i_fu_362_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_i_reg_517 : STD_LOGIC_VECTOR (12 downto 0);
signal cast_fu_370_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_fu_385_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_6_reg_530 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal exitcond_i_fu_379_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_1_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal icmp_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_nbreadreq_fu_151_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_450_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state13 : BOOLEAN;
signal tmp_9_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_reg_217 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal exitcond_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_reg_228 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_1_nbreadreq_fu_129_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_239 : STD_LOGIC_VECTOR (0 downto 0);
signal contact_index_assign_reg_251 : STD_LOGIC_VECTOR (7 downto 0);
signal i_i_reg_262 : STD_LOGIC_VECTOR (6 downto 0);
signal comp_reg_273 : STD_LOGIC_VECTOR (0 downto 0);
signal i1_reg_285 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_341_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_7_fu_391_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_i_fu_401_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_468_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_11_fu_358_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal i_i_cast7_fu_375_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_12_i_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_14_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_424_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_6_fu_456_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i1_cast_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_block_state11 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component contact_discoverybkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverycud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discovery_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0);
operation_ap_vld : OUT STD_LOGIC;
matched_finished : IN STD_LOGIC_VECTOR (31 downto 0);
error_out : IN STD_LOGIC_VECTOR (31 downto 0);
contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
contacts_U : component contact_discoverybkb
generic map (
DataWidth => 8,
AddressRange => 8192,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => contacts_address0,
ce0 => contacts_ce0,
we0 => contacts_we0,
d0 => contacts_d0,
q0 => contacts_q0);
current_database_ite_U : component contact_discoverycud
generic map (
DataWidth => 8,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => current_database_ite_address0,
ce0 => current_database_ite_ce0,
we0 => current_database_ite_we0,
d0 => database_in_V_TDATA,
q0 => current_database_ite_q0);
contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation,
operation_ap_vld => operation_ap_vld,
matched_finished => matched_finished_1_data_reg,
error_out => error_out_1_data_reg,
contacts_size_out => contacts_size_out_1_data_reg);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
matched_out_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_ack_out) and (ap_const_logic_1 = matched_out_V_1_vld_out))) then
matched_out_V_1_sel_rd <= not(matched_out_V_1_sel_rd);
end if;
end if;
end if;
end process;
matched_out_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_in))) then
matched_out_V_1_sel_wr <= not(matched_out_V_1_sel_wr);
end if;
end if;
end if;
end process;
matched_out_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)))) then
matched_out_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)))) then
matched_out_V_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)) or ((matched_out_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out))) and not(((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out)))))) then
matched_out_V_1_state <= ap_const_lv2_3;
else
matched_out_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
operation_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_ap_vld_preg <= operation_ap_vld;
elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
operation_ap_vld_preg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
operation_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_preg <= operation;
end if;
end if;
end if;
end process;
comp_reg_273_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
comp_reg_273 <= found_1_fu_418_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
comp_reg_273 <= ap_const_lv1_1;
end if;
end if;
end process;
contact_index_assign_reg_251_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
contact_index_assign_reg_251 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
contact_index_assign_reg_251 <= i_5_reg_512;
end if;
end if;
end process;
contacts_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size <= tmp_9_fu_473_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size <= ap_const_lv32_0;
end if;
end if;
end process;
contacts_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
error_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
i1_reg_285_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
i1_reg_285 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
i1_reg_285 <= i_4_fu_450_p2;
end if;
end if;
end process;
i_1_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
i_1_reg_228 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
i_1_reg_228 <= i_2_fu_335_p2;
end if;
end if;
end process;
i_3_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2))) then
i_3_reg_217 <= i_fu_318_p2;
elsif (((grp_read_fu_98_p2 = ap_const_lv32_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
i_3_reg_217 <= ap_const_lv8_0;
end if;
end if;
end process;
i_i_reg_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_i_reg_262 <= i_6_reg_530;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
i_i_reg_262 <= ap_const_lv7_0;
end if;
end if;
end process;
matched_finished_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
tmp_10_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
tmp_10_reg_239 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
tmp_10_reg_239 <= found_fu_406_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_data_reg <= contacts_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_data_reg <= error_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0))) then
i_5_reg_512 <= i_5_fu_352_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
i_6_reg_530 <= i_6_fu_385_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_data_reg <= matched_finished_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_A)) then
matched_out_V_1_payload_A <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_B)) then
matched_out_V_1_payload_B <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
tmp_i_reg_517(12 downto 6) <= tmp_i_fu_362_p3(12 downto 6);
end if;
end if;
end process;
tmp_i_reg_517(5 downto 0) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_in_V_TVALID, database_in_V_TVALID, matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state2, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10, grp_read_fu_98_p2, ap_CS_fsm_state4, ap_block_state7_io, ap_CS_fsm_state8, exitcond_i_fu_379_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3, ap_CS_fsm_state3, exitcond_fu_312_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3, ap_CS_fsm_state11)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
if ((not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_lv32_0 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state12;
elsif (((ap_const_lv32_1 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_312_p2))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
ap_NS_fsm <= ap_ST_fsm_state8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (matched_out_V_1_ack_in = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_0 = tmp_nbreadreq_fu_151_p3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state13;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state11_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in)
begin
ap_block_state11 <= ((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in));
end process;
ap_block_state13_assign_proc : process(contacts_in_V_TVALID, exitcond9_fu_444_p2)
begin
ap_block_state13 <= ((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID));
end process;
ap_block_state6_assign_proc : process(database_in_V_TVALID, exitcond8_fu_329_p2)
begin
ap_block_state6 <= ((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID));
end process;
ap_block_state7_io_assign_proc : process(matched_out_V_1_ack_in, exitcond7_fu_346_p2)
begin
ap_block_state7_io <= ((ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_const_logic_0 = matched_out_V_1_ack_in));
end process;
ap_done_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
cast_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_239),8));
contacts_address0_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state4, ap_CS_fsm_state8, tmp_3_fu_324_p1, tmp_13_i_fu_401_p1, tmp_s_fu_468_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address0 <= tmp_s_fu_468_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address0 <= tmp_13_i_fu_401_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= tmp_3_fu_324_p1(13 - 1 downto 0);
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_ce0 <= ap_const_logic_1;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_d0_assign_proc : process(contacts_in_V_TDATA, ap_CS_fsm_state13, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_d0 <= contacts_in_V_TDATA;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_d0 <= ap_const_lv8_0;
else
contacts_d0 <= "XXXXXXXX";
end if;
end process;
contacts_in_V_TDATA_blk_n_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2)))) then
contacts_in_V_TDATA_blk_n <= contacts_in_V_TVALID;
else
contacts_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
contacts_in_V_TREADY_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1)))) then
contacts_in_V_TREADY <= ap_const_logic_1;
else
contacts_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_ack_in <= ap_const_logic_1;
else
contacts_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, contacts_size, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, tmp_9_fu_473_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size_out_1_data_in <= tmp_9_fu_473_p2;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))))) then
contacts_size_out_1_data_in <= contacts_size;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size_out_1_data_in <= ap_const_lv32_0;
else
contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
contacts_size_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
contacts_size_out_1_vld_in <= ap_const_logic_1;
else
contacts_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
contacts_we0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, exitcond_fu_312_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_we0 <= ap_const_logic_1;
else
contacts_we0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state8, tmp_7_fu_341_p1, tmp_i_7_fu_391_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
current_database_ite_address0 <= tmp_i_7_fu_391_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
current_database_ite_address0 <= tmp_7_fu_341_p1(6 - 1 downto 0);
else
current_database_ite_address0 <= "XXXXXX";
end if;
end process;
current_database_ite_ce0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state8)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)))) or (ap_const_logic_1 = ap_CS_fsm_state8))) then
current_database_ite_ce0 <= ap_const_logic_1;
else
current_database_ite_ce0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_we0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
current_database_ite_we0 <= ap_const_logic_1;
else
current_database_ite_we0 <= ap_const_logic_0;
end if;
end process;
database_in_V_TDATA_blk_n_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2))) then
database_in_V_TDATA_blk_n <= database_in_V_TVALID;
else
database_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
database_in_V_TREADY_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
database_in_V_TREADY <= ap_const_logic_1;
else
database_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg)
begin
if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_ack_in <= ap_const_logic_1;
else
error_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
error_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2))) then
error_out_1_data_in <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_3;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_0;
else
error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
error_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2)))) then
error_out_1_vld_in <= ap_const_logic_1;
else
error_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
exitcond7_fu_346_p2 <= "1" when (contact_index_assign_reg_251 = ap_const_lv8_80) else "0";
exitcond8_fu_329_p2 <= "1" when (i_1_reg_228 = ap_const_lv7_40) else "0";
exitcond9_fu_444_p2 <= "1" when (i1_reg_285 = ap_const_lv7_40) else "0";
exitcond_fu_312_p2 <= "1" when (i_3_reg_217 = ap_const_lv8_80) else "0";
exitcond_i_fu_379_p2 <= "1" when (i_i_reg_262 = ap_const_lv7_40) else "0";
found_1_fu_418_p2 <= (tmp_14_i_fu_412_p2 and comp_reg_273);
found_fu_406_p2 <= (comp_reg_273 or tmp_10_reg_239);
grp_read_fu_98_p2 <= operation_preg;
i1_cast_fu_440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_reg_285),32));
i_2_fu_335_p2 <= std_logic_vector(unsigned(i_1_reg_228) + unsigned(ap_const_lv7_1));
i_4_fu_450_p2 <= std_logic_vector(unsigned(i1_reg_285) + unsigned(ap_const_lv7_1));
i_5_fu_352_p2 <= std_logic_vector(unsigned(contact_index_assign_reg_251) + unsigned(ap_const_lv8_1));
i_6_fu_385_p2 <= std_logic_vector(unsigned(i_i_reg_262) + unsigned(ap_const_lv7_1));
i_fu_318_p2 <= std_logic_vector(unsigned(i_3_reg_217) + unsigned(ap_const_lv8_1));
i_i_cast7_fu_375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),13));
icmp_fu_434_p2 <= "1" when (signed(tmp_2_fu_424_p4) > signed(ap_const_lv25_0)) else "0";
matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg)
begin
if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_ack_in <= ap_const_logic_1;
else
matched_finished_1_ack_in <= ap_const_logic_0;
end if;
end process;
matched_finished_1_data_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3))) then
matched_finished_1_data_in <= ap_const_lv32_1;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
matched_finished_1_data_in <= ap_const_lv32_0;
else
matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
matched_finished_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3)))) then
matched_finished_1_vld_in <= ap_const_logic_1;
else
matched_finished_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_ack_in <= matched_out_V_1_state(1);
matched_out_V_1_ack_out <= matched_out_V_TREADY;
matched_out_V_1_data_out_assign_proc : process(matched_out_V_1_payload_A, matched_out_V_1_payload_B, matched_out_V_1_sel)
begin
if ((ap_const_logic_1 = matched_out_V_1_sel)) then
matched_out_V_1_data_out <= matched_out_V_1_payload_B;
else
matched_out_V_1_data_out <= matched_out_V_1_payload_A;
end if;
end process;
matched_out_V_1_load_A <= (matched_out_V_1_state_cmp_full and not(matched_out_V_1_sel_wr));
matched_out_V_1_load_B <= (matched_out_V_1_sel_wr and matched_out_V_1_state_cmp_full);
matched_out_V_1_sel <= matched_out_V_1_sel_rd;
matched_out_V_1_state_cmp_full <= '0' when (matched_out_V_1_state = ap_const_lv2_1) else '1';
matched_out_V_1_vld_in_assign_proc : process(ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_block_state7_io)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
matched_out_V_1_vld_in <= ap_const_logic_1;
else
matched_out_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_vld_out <= matched_out_V_1_state(0);
matched_out_V_TDATA <= matched_out_V_1_data_out;
matched_out_V_TDATA_blk_n_assign_proc : process(matched_out_V_1_state, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2)) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
matched_out_V_TDATA_blk_n <= matched_out_V_1_state(1);
else
matched_out_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
matched_out_V_TVALID <= matched_out_V_1_state(0);
operation_ap_vld_in_sig <= operation_ap_vld_preg;
operation_blk_n_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
operation_blk_n <= ap_const_logic_0;
else
operation_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_11_fu_358_p1 <= contact_index_assign_reg_251(7 - 1 downto 0);
tmp_12_i_fu_396_p2 <= std_logic_vector(unsigned(i_i_cast7_fu_375_p1) + unsigned(tmp_i_reg_517));
tmp_13_i_fu_401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_i_fu_396_p2),64));
tmp_14_i_fu_412_p2 <= "1" when (current_database_ite_q0 = contacts_q0) else "0";
tmp_1_nbreadreq_fu_129_p3 <= (0=>database_in_V_TVALID, others=>'-');
tmp_2_fu_424_p4 <= contacts_size(31 downto 7);
tmp_3_fu_324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_3_reg_217),64));
tmp_6_fu_456_p2 <= std_logic_vector(shift_left(unsigned(contacts_size),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
tmp_7_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_228),64));
tmp_8_fu_462_p2 <= std_logic_vector(unsigned(tmp_6_fu_456_p2) + unsigned(i1_cast_fu_440_p1));
tmp_9_fu_473_p2 <= std_logic_vector(unsigned(contacts_size) + unsigned(ap_const_lv32_1));
tmp_i_7_fu_391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),64));
tmp_i_fu_362_p3 <= (tmp_11_fu_358_p1 & ap_const_lv6_0);
tmp_nbreadreq_fu_151_p3 <= (0=>contacts_in_V_TVALID, others=>'-');
tmp_s_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_fu_462_p2),64));
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
-- Entity Declaration
ENTITY pid_controller IS
PORT
(
CLK : IN STD_LOGIC;
en : IN STD_LOGIC;
init : IN STD_LOGIC;
error : IN STD_LOGIC_VECTOR(15 downto 0);
init_val : IN STD_LOGIC_VECTOR(15 downto 0);
kp : IN STD_LOGIC_VECTOR(15 downto 0);
ki : IN STD_LOGIC_VECTOR(15 downto 0);
output : OUT std_logic_vector(15 downto 0)
);
END pid_controller;
ARCHITECTURE arch OF pid_controller IS
signal integrall : std_logic_vector(15 downto 0);
BEGIN
process (clk, init, init_val)
variable kperror : integer range -2147483647 to 2147483647;
variable kierror : integer range -2147483647 to 2147483647;
begin
if (init = '1') then
integrall <= init_val;
output <= init_val;
else
if (clk'event and clk = '1') then
if (en = '1') then
kperror := conv_integer(kp) * conv_integer(error);
kierror := conv_integer(ki) * conv_integer(error);
if (conv_integer(integrall) < 65000) then -- 65000
integrall <= integrall + conv_std_logic_vector(kierror, 32)(31 downto 16);
end if;
output <= conv_std_logic_vector(kperror, 32)(31 downto 16) + integrall;
end if;
end if;
end if;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity test is
port(
clk : in vl_logic;
sda : in vl_logic;
\out\ : out vl_logic
);
end test;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_ADDR : in std_logic_vector(7 downto 0);
KEYB_DATA : out std_logic_vector(4 downto 0);
RESET_TICK : out std_logic;
NMI_TICK : out std_logic );
end keyboard;
architecture rtl of keyboard is
signal CODE : std_logic_vector(7 downto 0); -- Scancode recieved from keyboard
signal DONE : std_logic; -- Current scancode valid
signal ERROR : std_logic; -- Current scancode corrupted
signal LOOKUP : std_logic_vector(7 downto 0); -- bits 7-5 - A8..A15, bits 4-0 - D4..D0
signal RELEASED_KEY : std_logic;
signal EXTENDED_KEY : std_logic;
type MATRIX_IMAGE is array (natural range <>) of std_logic_vector(4 downto 0);
signal MATRIX : MATRIX_IMAGE(0 to 7); -- Speccy keyboard matrix
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
decoder : process (CODE)
begin
case CODE is
when X"12" => LOOKUP <= "00000001"; -- left/caps shift
when X"1a" => LOOKUP <= "00000010"; -- z
when X"22" => LOOKUP <= "00000100"; -- x
when X"21" => LOOKUP <= "00001000"; -- c
when X"2a" => LOOKUP <= "00010000"; -- v
when X"1c" => LOOKUP <= "00100001"; -- a
when X"1b" => LOOKUP <= "00100010"; -- s
when X"23" => LOOKUP <= "00100100"; -- d
when X"2b" => LOOKUP <= "00101000"; -- f
when X"34" => LOOKUP <= "00110000"; -- g
when X"15" => LOOKUP <= "01000001"; -- q
when X"1d" => LOOKUP <= "01000010"; -- w
when X"24" => LOOKUP <= "01000100"; -- e
when X"2d" => LOOKUP <= "01001000"; -- r
when X"2c" => LOOKUP <= "01010000"; -- t
when X"16" => LOOKUP <= "01100001"; -- 1
when X"69" => LOOKUP <= "01100001"; -- 1
when X"1e" => LOOKUP <= "01100010"; -- 2
when X"72" => LOOKUP <= "01100010"; -- 2
when X"26" => LOOKUP <= "01100100"; -- 3
when X"7a" => LOOKUP <= "01100100"; -- 3
when X"25" => LOOKUP <= "01101000"; -- 4
when X"6b" => LOOKUP <= "01101000"; -- 4
when X"2e" => LOOKUP <= "01110000"; -- 5
when X"73" => LOOKUP <= "01110000"; -- 5
when X"45" => LOOKUP <= "10000001"; -- 0
when X"70" => LOOKUP <= "10000001"; -- 0
when X"46" => LOOKUP <= "10000010"; -- 9
when X"7d" => LOOKUP <= "10000010"; -- 9
when X"3e" => LOOKUP <= "10000100"; -- 8
when X"75" => LOOKUP <= "10000100"; -- 8
when X"3d" => LOOKUP <= "10001000"; -- 7
when X"6c" => LOOKUP <= "10001000"; -- 7
when X"36" => LOOKUP <= "10010000"; -- 6
when X"74" => LOOKUP <= "10010000"; -- 6
when X"4d" => LOOKUP <= "10100001"; -- p
when X"44" => LOOKUP <= "10100010"; -- o
when X"43" => LOOKUP <= "10100100"; -- i
when X"3c" => LOOKUP <= "10101000"; -- u
when X"35" => LOOKUP <= "10110000"; -- y
when X"5a" => LOOKUP <= "11000001"; -- return
when X"4b" => LOOKUP <= "11000010"; -- l
when X"42" => LOOKUP <= "11000100"; -- k
when X"3b" => LOOKUP <= "11001000"; -- j
when X"33" => LOOKUP <= "11010000"; -- h
when X"29" => LOOKUP <= "11100001"; -- Space
when X"59" => LOOKUP <= "11100010"; -- right/symbol shift
when X"3a" => LOOKUP <= "11100100"; -- m
when X"31" => LOOKUP <= "11101000"; -- n
when X"32" => LOOKUP <= "11110000"; -- b
when others => LOOKUP <= "00000000";
end case;
end process;
main : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
MATRIX <= (others => (others => '0'));
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
RESET_TICK <= '0';
NMI_TICK <= '0';
else
RESET_TICK <= '0';
NMI_TICK <= '0';
if ERROR = '1' then
MATRIX <= (others => (others => '0'));
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
elsif DONE = '1' then
if CODE = X"F0" then
RELEASED_KEY <= '1';
elsif CODE = X"E0" then
EXTENDED_KEY <= '1';
elsif CODE = X"07" and RELEASED_KEY = '1' then
RESET_TICK <= '1';
elsif CODE = X"78" and RELEASED_KEY = '1' then
NMI_TICK <= '1';
else
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
-- if LOOKUP /= "00000000" then
if RELEASED_KEY = '0' then
MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) <= MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) or std_logic_vector(unsigned(LOOKUP(4 downto 0)));
else
MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) <= MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) and std_logic_vector(not unsigned(LOOKUP(4 downto 0)));
end if;
-- end if;
end if;
end if;
end if;
end if;
end process;
keyboard_output : for i in 0 to 4 generate
KEYB_DATA(i) <= not ((MATRIX(0)(i) and not KEYB_ADDR(0)) or
(MATRIX(1)(i) and not KEYB_ADDR(1)) or
(MATRIX(2)(i) and not KEYB_ADDR(2)) or
(MATRIX(3)(i) and not KEYB_ADDR(3)) or
(MATRIX(4)(i) and not KEYB_ADDR(4)) or
(MATRIX(5)(i) and not KEYB_ADDR(5)) or
(MATRIX(6)(i) and not KEYB_ADDR(6)) or
(MATRIX(7)(i) and not KEYB_ADDR(7)) );
end generate;
end; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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hHM4ejzywIKlt7A3nloNAcFwSbTQtzI0xJtNt1Kg3KvC32pz/BaTaEdiB8/GND8c+BQUudhXNEQB
rUrpeuYaKNWLcQMGEBs4CcmlznK+4hBrlcs55teAPpQGTlsIAgPgNGxD0K8WVN0W8a3JrH2L+kDJ
LOJ7VM9vw1b8NeIBlSWj43kk12ULezAba8s1L9vAOaYhOnn/jcKxOC3RCO/JDnwKoD7sdeeqYhj6
71pCtJQKEgYFVoy8vQ5akDj3KQdFblB3vQcE6msKu8+CE8KG9Y94nYfnrCv9kVDzubo+O84C8nAl
g6N0N11n/xORqQrW08rZ/GlQ9xddYhB64/LyZ4MOtFoW6myhLQ0R9Q2cl5SIsxKk9Qlz3yRTIvCG
3fY/sgx61COImxalq0mRz9pAUJABVHG1099eVsElGQ8AXh7EcuEd3g7rqdy70D/JlmEyxze5oAMH
+DznT16dxHdoXzynCj4F6KLVj8qipBD01O/tAPLeo27Bxci9IM5uSgzLqFDqGHudMcLh+Mx/ga2p
EAYrhOkMW8DYtByvnRY6w+3AJoXYSJetSx1TRYQk0iUtM6dXhtSJXZ2JhsgXh00Ek0eh6sIgOClH
fffub/UIrFs9rZMzFMgrSNn7qYAuR+4BoQvfwFAXChXG8BWxi0PL9Iq/DikA/mORfVq6w5yOkXQS
Pa2pE2ukLL06l/OQZ0OI/F9nQJcUFOzDDfhRHlieFASPI14WYUQ6x4jqt6hEkS8aZEjIcGH/ZVht
T1//KeeuKKBsYOa1pgpWxtx8ViiBDC6uboy5PaKgyuyrCeRG2hHN1zg60cchivZQ8IyqVDJazPad
891k/WJCQALUUE+yhWJzk8appdNjMAzgAa6PGz2WC354yUBLZuiYKPbt+nEZyt44SXK9e3Khy9zl
33v3JJB3l8TlbD5BTaS1PoO+kHUOStCHg7DE+M2/ffdNfm2ONuGMkM+Qe7N5cZn8jELlQpyjM2cY
ljalnhj+Y7M6l3uAqySFxvVX96we8GB9pf5Jm6xcFPQY8HGSOVuKPOplBR+p3fvhIqjV49fXgoin
MFg6g1EdDs79xVaJxZn8R7s6/Bq1pZozagxj2awIalXgKJwk/pHCIY20sRrJcod+/P4TKTkqMPAC
+CfHNgF1RnDJJqgUxJ07y8d8qqyPEeKUq2LIyxcrIEHTCq+n1CU90EGxFtPDbca8t+hc181emurV
/bJ07IFz/DcYD7lnpEBYsfZfqrNos71WVLg/cXNCv9tW3NcddsLCLNr8y32FsXvTx/WBGycYcRQO
R3K9LZJFjKYw2knLXzWwkydzxWBtSI1W0VySCRxPKY4WJ9eJO3QYUzyJHx0Nt8yVg6OJVvjutsh0
ks0dFREbMXgV1nY0VxzVdoLr7U5CanrJ0aEslQLfFzkzbe9brMXSpvj++qoTRDOyACLdEllVYR4d
RoauPbeq/Yc+nOtt8hHMAHV2pQHsKO9bVXQ=
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity state_machine is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
state_input : in STD_LOGIC;
tc : out STD_LOGIC);
end state_machine;
architecture architecture_state_machine of state_machine is
type T_etat is (idle,edge,one);
signal next_state, state_reg : T_etat;
begin
state_reg_process: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state_reg <= idle;
else
state_reg <= next_state;
end if;
end if;
end process state_reg_process;
tc <= '1' when state_reg = edge else '0';
next_state_process: process(state_reg, state_input)
begin
next_state <= state_reg;
case state_reg is
when idle =>
if state_input = '1' then
next_state <= edge;
end if;
when edge =>
next_state <= one;
when one =>
if state_input = '0' then
next_state <= idle;
end if;
end case;
end process next_state_process;
end architecture_state_machine;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementPartialOverrideNopVal IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
e : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementPartialOverrideNopVal IS
SIGNAL d : STD_LOGIC;
SIGNAL d_next : STD_LOGIC;
BEGIN
assig_process_d: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
d <= d_next;
END IF;
END PROCESS;
assig_process_d_next: PROCESS(a, b, c, d)
BEGIN
IF a = '1' THEN
IF b = '1' THEN
d_next <= '1';
ELSE
d_next <= d;
END IF;
IF c = '1' THEN
d_next <= '0';
END IF;
ELSE
d_next <= d;
END IF;
END PROCESS;
e <= d;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
generic (
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
);
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLK0 : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 15.855 =49.152 * 10 / 31
CLKFX_DIVIDE => ClkDiv,
CLKFX_MULTIPLY => ClkMult,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => ClkPer,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
generic (
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
);
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLK0 : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0, -- 15.855 =49.152 * 10 / 31
CLKFX_DIVIDE => ClkDiv,
CLKFX_MULTIPLY => ClkMult,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => ClkPer,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_memory_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END rom_memory_exdes;
ARCHITECTURE xilinx OF rom_memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT rom_memory IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : rom_memory
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc716.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p02n01i00716ent IS
END c01s01b00x00p02n01i00716ent;
ARCHITECTURE c01s01b00x00p02n01i00716arch OF c01s01b00x00p02n01i00716ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00716 - Missing is in entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00716arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc716.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p02n01i00716ent IS
END c01s01b00x00p02n01i00716ent;
ARCHITECTURE c01s01b00x00p02n01i00716arch OF c01s01b00x00p02n01i00716ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00716 - Missing is in entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00716arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc716.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p02n01i00716ent IS
END c01s01b00x00p02n01i00716ent;
ARCHITECTURE c01s01b00x00p02n01i00716arch OF c01s01b00x00p02n01i00716ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p02n01i00716 - Missing is in entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p02n01i00716arch;
|
-- author: Antonio Gutierrez
-- date: 03/10/13
-- description: shift register
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity shift_register is
generic (N: integer := 4;); ---- number of stages
port (
din, clk, rst: in std_logic;
dout: out std_logic);
end entity shift_register;
--------------------------------------
architecture shift_register of shift_register is
--signals and declarations
begin
main: process (clk, rst)
variable q: std_logic_vector(0 to N-1);
begin
if (rst = '1') then
q := (others => '0');
elsif (clk'event and clk = '1') then
q := din & q(0 to N-2); ---- concatenate din to three least significant bits of q
end if;
dout <= q(N-1); -- dout is the msb of q
end process main;
end architecture shift_register;
|
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