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module cmd_reader
(//System
input reset, input txclk, input [31:0] adc_time,
//FX2 Side
output reg skip, output reg rdreq,
input [31:0] fifodata, input pkt_waiting,
//Rx side
input rx_WR_enabled, output reg [15:0] rx_databus,
output reg rx_WR, output reg rx_WR_done,
//register io
input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
// States
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter TIMESTAMP = 4'd2;
parameter WAIT = 4'd3;
parameter TEST = 4'd4;
parameter SEND = 4'd5;
parameter PING = 4'd6;
parameter WRITE_REG = 4'd7;
parameter WRITE_REG_MASKED = 4'd8;
parameter READ_REG = 4'd9;
parameter DELAY = 4'd14;
`define OP_PING_FIXED 8'd0
`define OP_PING_FIXED_REPLY 8'd1
`define OP_WRITE_REG 8'd2
`define OP_WRITE_REG_MASKED 8'd3
`define OP_READ_REG 8'd4
`define OP_READ_REG_REPLY 8'd5
`define OP_DELAY 8'd12
reg [6:0] payload;
reg [6:0] payload_read;
reg [3:0] state;
reg [15:0] high;
reg [15:0] low;
reg pending;
reg [31:0] value0;
reg [31:0] value1;
reg [31:0] value2;
reg [1:0] lines_in;
reg [1:0] lines_out;
reg [1:0] lines_out_total;
`define JITTER 5
`define OP_CODE 31:24
`define PAYLOAD 8:2
wire [7:0] ops;
assign ops = value0[`OP_CODE];
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
always @(posedge txclk)
if (reset)
begin
pending <= 0;
state <= IDLE;
skip <= 0;
rdreq <= 0;
rx_WR <= 0;
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
stop <= 0;
end
else case (state)
IDLE :
begin
payload_read <= 0;
skip <= 0;
lines_in <= 0;
if(pkt_waiting)
begin
state <= HEADER;
rdreq <= 1;
end
end
HEADER :
begin
payload <= fifodata[`PAYLOAD];
state <= TIMESTAMP;
end
TIMESTAMP :
begin
value0 <= fifodata;
state <= WAIT;
rdreq <= 0;
end
WAIT :
begin
// Let's send it
if ((value0 <= adc_time + `JITTER
&& value0 > adc_time)
|| value0 == 32'hFFFFFFFF)
state <= TEST;
// Wait a little bit more
else if (value0 > adc_time + `JITTER)
state <= WAIT;
// Outdated
else if (value0 < adc_time)
begin
state <= IDLE;
skip <= 1;
end
end
TEST :
begin
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
state <= IDLE;
rdreq <= 0;
end
else
begin
value0 <= fifodata;
lines_in <= 2'd1;
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_out <= 0;
case (fifodata[`OP_CODE])
`OP_PING_FIXED:
begin
state <= PING;
end
`OP_WRITE_REG:
begin
state <= WRITE_REG;
pending <= 1;
end
`OP_WRITE_REG_MASKED:
begin
state <= WRITE_REG_MASKED;
pending <= 1;
end
`OP_READ_REG:
begin
state <= READ_REG;
end
`OP_DELAY:
begin
state <= DELAY;
end
default:
begin
//error, skip this packet
skip <= 1;
state <= IDLE;
end
endcase
end
end
SEND:
begin
rdreq <= 0;
rx_WR_done <= 0;
if (pending)
begin
rx_WR <= 1;
rx_databus <= high;
pending <= 0;
if (lines_out == lines_out_total)
state <= TEST;
else case (ops)
`OP_READ_REG:
begin
state <= READ_REG;
end
default:
begin
state <= TEST;
end
endcase
end
else
begin
if (rx_WR_enabled)
begin
rx_WR <= 1;
rx_databus <= low;
pending <= 1;
lines_out <= lines_out + 2'd1;
end
else
rx_WR <= 0;
end
end
PING:
begin
rx_WR <= 0;
rdreq <= 0;
rx_WR_done <= 0;
lines_out_total <= 2'd1;
pending <= 0;
state <= SEND;
high <= {`OP_PING_FIXED_REPLY, 8'd2};
low <= value0[15:0];
end
READ_REG:
begin
rx_WR <= 0;
rx_WR_done <= 0;
rdreq <= 0;
lines_out_total <= 2'd2;
pending <= 0;
state <= SEND;
if (lines_out == 0)
begin
high <= {`OP_READ_REG_REPLY, 8'd6};
low <= value0[15:0];
reg_io_enable <= 2'd3;
reg_addr <= value0[6:0];
end
else
begin
high <= reg_data_out[31:16];
low <= reg_data_out[15:0];
end
end
WRITE_REG:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
rdreq <= 0;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= value1;
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
WRITE_REG_MASKED:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
end
else if (lines_in == 2'd2)
begin
rdreq <= 0;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value2 <= fifodata;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= (value1 & value2);
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
DELAY :
begin
rdreq <= 0;
stop <= 1;
stop_time <= value0[15:0];
state <= TEST;
end
default :
begin
//error state handling
state <= IDLE;
end
endcase
endmodule
|
module cmd_reader
(//System
input reset, input txclk, input [31:0] adc_time,
//FX2 Side
output reg skip, output reg rdreq,
input [31:0] fifodata, input pkt_waiting,
//Rx side
input rx_WR_enabled, output reg [15:0] rx_databus,
output reg rx_WR, output reg rx_WR_done,
//register io
input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
// States
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter TIMESTAMP = 4'd2;
parameter WAIT = 4'd3;
parameter TEST = 4'd4;
parameter SEND = 4'd5;
parameter PING = 4'd6;
parameter WRITE_REG = 4'd7;
parameter WRITE_REG_MASKED = 4'd8;
parameter READ_REG = 4'd9;
parameter DELAY = 4'd14;
`define OP_PING_FIXED 8'd0
`define OP_PING_FIXED_REPLY 8'd1
`define OP_WRITE_REG 8'd2
`define OP_WRITE_REG_MASKED 8'd3
`define OP_READ_REG 8'd4
`define OP_READ_REG_REPLY 8'd5
`define OP_DELAY 8'd12
reg [6:0] payload;
reg [6:0] payload_read;
reg [3:0] state;
reg [15:0] high;
reg [15:0] low;
reg pending;
reg [31:0] value0;
reg [31:0] value1;
reg [31:0] value2;
reg [1:0] lines_in;
reg [1:0] lines_out;
reg [1:0] lines_out_total;
`define JITTER 5
`define OP_CODE 31:24
`define PAYLOAD 8:2
wire [7:0] ops;
assign ops = value0[`OP_CODE];
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
always @(posedge txclk)
if (reset)
begin
pending <= 0;
state <= IDLE;
skip <= 0;
rdreq <= 0;
rx_WR <= 0;
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
stop <= 0;
end
else case (state)
IDLE :
begin
payload_read <= 0;
skip <= 0;
lines_in <= 0;
if(pkt_waiting)
begin
state <= HEADER;
rdreq <= 1;
end
end
HEADER :
begin
payload <= fifodata[`PAYLOAD];
state <= TIMESTAMP;
end
TIMESTAMP :
begin
value0 <= fifodata;
state <= WAIT;
rdreq <= 0;
end
WAIT :
begin
// Let's send it
if ((value0 <= adc_time + `JITTER
&& value0 > adc_time)
|| value0 == 32'hFFFFFFFF)
state <= TEST;
// Wait a little bit more
else if (value0 > adc_time + `JITTER)
state <= WAIT;
// Outdated
else if (value0 < adc_time)
begin
state <= IDLE;
skip <= 1;
end
end
TEST :
begin
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
state <= IDLE;
rdreq <= 0;
end
else
begin
value0 <= fifodata;
lines_in <= 2'd1;
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_out <= 0;
case (fifodata[`OP_CODE])
`OP_PING_FIXED:
begin
state <= PING;
end
`OP_WRITE_REG:
begin
state <= WRITE_REG;
pending <= 1;
end
`OP_WRITE_REG_MASKED:
begin
state <= WRITE_REG_MASKED;
pending <= 1;
end
`OP_READ_REG:
begin
state <= READ_REG;
end
`OP_DELAY:
begin
state <= DELAY;
end
default:
begin
//error, skip this packet
skip <= 1;
state <= IDLE;
end
endcase
end
end
SEND:
begin
rdreq <= 0;
rx_WR_done <= 0;
if (pending)
begin
rx_WR <= 1;
rx_databus <= high;
pending <= 0;
if (lines_out == lines_out_total)
state <= TEST;
else case (ops)
`OP_READ_REG:
begin
state <= READ_REG;
end
default:
begin
state <= TEST;
end
endcase
end
else
begin
if (rx_WR_enabled)
begin
rx_WR <= 1;
rx_databus <= low;
pending <= 1;
lines_out <= lines_out + 2'd1;
end
else
rx_WR <= 0;
end
end
PING:
begin
rx_WR <= 0;
rdreq <= 0;
rx_WR_done <= 0;
lines_out_total <= 2'd1;
pending <= 0;
state <= SEND;
high <= {`OP_PING_FIXED_REPLY, 8'd2};
low <= value0[15:0];
end
READ_REG:
begin
rx_WR <= 0;
rx_WR_done <= 0;
rdreq <= 0;
lines_out_total <= 2'd2;
pending <= 0;
state <= SEND;
if (lines_out == 0)
begin
high <= {`OP_READ_REG_REPLY, 8'd6};
low <= value0[15:0];
reg_io_enable <= 2'd3;
reg_addr <= value0[6:0];
end
else
begin
high <= reg_data_out[31:16];
low <= reg_data_out[15:0];
end
end
WRITE_REG:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
rdreq <= 0;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= value1;
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
WRITE_REG_MASKED:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
end
else if (lines_in == 2'd2)
begin
rdreq <= 0;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value2 <= fifodata;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= (value1 & value2);
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
DELAY :
begin
rdreq <= 0;
stop <= 1;
stop_time <= value0[15:0];
state <= TEST;
end
default :
begin
//error state handling
state <= IDLE;
end
endcase
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output dma_done_rd_en,
input [20:0] dma_done_rd_data,
input dma_done_empty_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt
);
localparam LP_NLB_WR_DELAY = 1;
localparam S_IDLE = 11'b00000000001;
localparam S_DMA_INFO = 11'b00000000010;
localparam S_NLB_RD_WAIT = 11'b00000000100;
localparam S_NLB_INFO = 11'b00000001000;
localparam S_NLB_CALC = 11'b00000010000;
localparam S_NLB_WR_WAIT = 11'b00000100000;
localparam S_NLB_WR = 11'b00001000000;
localparam S_NLB_WR_DELAY = 11'b00010000000;
localparam S_CQ_WR_WAIT = 11'b00100000000;
localparam S_CQ_WR = 11'b01000000000;
localparam S_NLB_DONE = 11'b10000000000;
reg [10:0] cur_state;
reg [10:0] next_state;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg r_dma_dir;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_dma_len;
reg [20:2] r_hcmd_data_len;
reg r_dma_done_rd_en;
reg r_hcmd_nlb_wr1_en;
reg r_hcmd_cq_wr0_en;
reg r_dma_rx_direct_done_en;
reg r_dma_tx_direct_done_en;
reg r_dma_rx_done_en;
reg r_dma_tx_done_en;
reg r_dma_rx_direct_done_en_d1;
reg r_dma_tx_direct_done_en_d1;
reg r_dma_rx_done_en_d1;
reg r_dma_tx_done_en_d1;
reg r_dma_rx_direct_done_en_sync;
reg r_dma_tx_direct_done_en_sync;
reg r_dma_rx_done_en_sync;
reg r_dma_tx_done_en_sync;
reg [3:0] r_nlb_wr_delay;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d2;
reg [7:0] r_dma_rx_direct_done_cnt;
reg [7:0] r_dma_tx_direct_done_cnt;
reg [7:0] r_dma_rx_done_cnt;
reg [7:0] r_dma_tx_done_cnt;
assign dma_done_rd_en = r_dma_done_rd_en;
assign hcmd_nlb_rd_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_en = r_hcmd_nlb_wr1_en;
assign hcmd_nlb_wr1_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_data = r_hcmd_data_len;
assign hcmd_cq_wr0_en = r_hcmd_cq_wr0_en;
assign hcmd_cq_wr0_data0 = {26'b0, r_hcmd_slot_tag, 1'b0, 1'b1};
assign hcmd_cq_wr0_data1 = 35'b0;
assign dma_rx_direct_done_cnt = r_dma_rx_direct_done_cnt;
assign dma_tx_direct_done_cnt = r_dma_tx_direct_done_cnt;
assign dma_rx_done_cnt = r_dma_rx_done_cnt;
assign dma_tx_done_cnt = r_dma_tx_done_cnt;
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0) begin
r_dma_rx_direct_done_cnt <= 0;
r_dma_tx_direct_done_cnt <= 0;
r_dma_rx_done_cnt <= 0;
r_dma_tx_done_cnt <= 0;
end
else begin
if(r_dma_rx_direct_done_d1 == 1 && r_dma_rx_direct_done_d2 == 0)
r_dma_rx_direct_done_cnt <= r_dma_rx_direct_done_cnt + 1;
if(r_dma_tx_direct_done_d1 == 1 && r_dma_tx_direct_done_d2 == 0)
r_dma_tx_direct_done_cnt <= r_dma_tx_direct_done_cnt + 1;
if(r_dma_rx_done_d1 == 1 && r_dma_rx_done_d2 == 0)
r_dma_rx_done_cnt <= r_dma_rx_done_cnt + 1;
if(r_dma_tx_done_d1 == 1 && r_dma_tx_done_d2 == 0)
r_dma_tx_done_cnt <= r_dma_tx_done_cnt + 1;
end
end
always @ (posedge cpu_bus_clk)
begin
r_dma_rx_direct_done <= r_dma_rx_direct_done_en_sync;
r_dma_tx_direct_done <= r_dma_tx_direct_done_en_sync;
r_dma_rx_done <= r_dma_rx_done_en_sync;
r_dma_tx_done <= r_dma_tx_done_en_sync;
r_dma_rx_direct_done_d1 <= r_dma_rx_direct_done;
r_dma_tx_direct_done_d1 <= r_dma_tx_direct_done;
r_dma_rx_done_d1 <= r_dma_rx_done;
r_dma_tx_done_d1 <= r_dma_tx_done;
r_dma_rx_direct_done_d2 <= r_dma_rx_direct_done_d1;
r_dma_tx_direct_done_d2 <= r_dma_tx_direct_done_d1;
r_dma_rx_done_d2 <= r_dma_rx_done_d1;
r_dma_tx_done_d2 <= r_dma_tx_done_d1;
end
always @ (posedge pcie_user_clk)
begin
r_dma_rx_direct_done_en_d1 <= r_dma_rx_direct_done_en;
r_dma_tx_direct_done_en_d1 <= r_dma_tx_direct_done_en;
r_dma_rx_done_en_d1 <= r_dma_rx_done_en;
r_dma_tx_done_en_d1 <= r_dma_tx_done_en;
r_dma_rx_direct_done_en_sync <= r_dma_rx_direct_done_en | r_dma_rx_direct_done_en_d1;
r_dma_tx_direct_done_en_sync <= r_dma_tx_direct_done_en | r_dma_tx_direct_done_en_d1;
r_dma_rx_done_en_sync <= r_dma_rx_done_en | r_dma_rx_done_en_d1;
r_dma_tx_done_en_sync <= r_dma_tx_done_en | r_dma_tx_done_en_d1;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_done_empty_n == 1'b1)
next_state <= S_DMA_INFO;
else
next_state <= S_IDLE;
end
S_DMA_INFO: begin
next_state <= S_NLB_RD_WAIT;
end
S_NLB_RD_WAIT: begin
if(r_dma_cmd_type == 1)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_INFO;
end
S_NLB_INFO: begin
next_state <= S_NLB_CALC;
end
S_NLB_CALC: begin
if(r_hcmd_data_len == r_dma_len)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_NLB_WR_WAIT;
end
S_NLB_WR_WAIT: begin
if(hcmd_nlb_wr1_rdy_n == 1)
next_state <= S_NLB_WR_WAIT;
else
next_state <= S_NLB_WR;
end
S_NLB_WR: begin
next_state <= S_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
if(r_nlb_wr_delay == 0)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_WR_DELAY;
end
S_CQ_WR_WAIT: begin
if(hcmd_cq_wr0_rdy_n == 1)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_CQ_WR;
end
S_CQ_WR: begin
next_state <= S_NLB_DONE;
end
S_NLB_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_DMA_INFO: begin
r_dma_cmd_type <= dma_done_rd_data[20];
r_dma_done_check <= dma_done_rd_data[19];
r_dma_dir <= dma_done_rd_data[18];
r_hcmd_slot_tag <= dma_done_rd_data[17:11];
r_dma_len <= dma_done_rd_data[10:0];
end
S_NLB_RD_WAIT: begin
end
S_NLB_INFO: begin
r_hcmd_data_len <= hcmd_nlb_rd_data;
end
S_NLB_CALC: begin
r_hcmd_data_len <= r_hcmd_data_len - r_dma_len;
end
S_NLB_WR_WAIT: begin
end
S_NLB_WR: begin
r_nlb_wr_delay <= LP_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
r_nlb_wr_delay <= r_nlb_wr_delay - 1;
end
S_CQ_WR_WAIT: begin
end
S_CQ_WR: begin
end
S_NLB_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_DMA_INFO: begin
r_dma_done_rd_en <= 1;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_RD_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_INFO: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_CALC: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 1;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_DELAY: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 1;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_DONE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & r_dma_dir;
r_dma_rx_done_en <= ~r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_done_en <= ~r_dma_cmd_type & r_dma_done_check & r_dma_dir;
end
default: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output dma_done_rd_en,
input [20:0] dma_done_rd_data,
input dma_done_empty_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt
);
localparam LP_NLB_WR_DELAY = 1;
localparam S_IDLE = 11'b00000000001;
localparam S_DMA_INFO = 11'b00000000010;
localparam S_NLB_RD_WAIT = 11'b00000000100;
localparam S_NLB_INFO = 11'b00000001000;
localparam S_NLB_CALC = 11'b00000010000;
localparam S_NLB_WR_WAIT = 11'b00000100000;
localparam S_NLB_WR = 11'b00001000000;
localparam S_NLB_WR_DELAY = 11'b00010000000;
localparam S_CQ_WR_WAIT = 11'b00100000000;
localparam S_CQ_WR = 11'b01000000000;
localparam S_NLB_DONE = 11'b10000000000;
reg [10:0] cur_state;
reg [10:0] next_state;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg r_dma_dir;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_dma_len;
reg [20:2] r_hcmd_data_len;
reg r_dma_done_rd_en;
reg r_hcmd_nlb_wr1_en;
reg r_hcmd_cq_wr0_en;
reg r_dma_rx_direct_done_en;
reg r_dma_tx_direct_done_en;
reg r_dma_rx_done_en;
reg r_dma_tx_done_en;
reg r_dma_rx_direct_done_en_d1;
reg r_dma_tx_direct_done_en_d1;
reg r_dma_rx_done_en_d1;
reg r_dma_tx_done_en_d1;
reg r_dma_rx_direct_done_en_sync;
reg r_dma_tx_direct_done_en_sync;
reg r_dma_rx_done_en_sync;
reg r_dma_tx_done_en_sync;
reg [3:0] r_nlb_wr_delay;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d2;
reg [7:0] r_dma_rx_direct_done_cnt;
reg [7:0] r_dma_tx_direct_done_cnt;
reg [7:0] r_dma_rx_done_cnt;
reg [7:0] r_dma_tx_done_cnt;
assign dma_done_rd_en = r_dma_done_rd_en;
assign hcmd_nlb_rd_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_en = r_hcmd_nlb_wr1_en;
assign hcmd_nlb_wr1_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_data = r_hcmd_data_len;
assign hcmd_cq_wr0_en = r_hcmd_cq_wr0_en;
assign hcmd_cq_wr0_data0 = {26'b0, r_hcmd_slot_tag, 1'b0, 1'b1};
assign hcmd_cq_wr0_data1 = 35'b0;
assign dma_rx_direct_done_cnt = r_dma_rx_direct_done_cnt;
assign dma_tx_direct_done_cnt = r_dma_tx_direct_done_cnt;
assign dma_rx_done_cnt = r_dma_rx_done_cnt;
assign dma_tx_done_cnt = r_dma_tx_done_cnt;
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0) begin
r_dma_rx_direct_done_cnt <= 0;
r_dma_tx_direct_done_cnt <= 0;
r_dma_rx_done_cnt <= 0;
r_dma_tx_done_cnt <= 0;
end
else begin
if(r_dma_rx_direct_done_d1 == 1 && r_dma_rx_direct_done_d2 == 0)
r_dma_rx_direct_done_cnt <= r_dma_rx_direct_done_cnt + 1;
if(r_dma_tx_direct_done_d1 == 1 && r_dma_tx_direct_done_d2 == 0)
r_dma_tx_direct_done_cnt <= r_dma_tx_direct_done_cnt + 1;
if(r_dma_rx_done_d1 == 1 && r_dma_rx_done_d2 == 0)
r_dma_rx_done_cnt <= r_dma_rx_done_cnt + 1;
if(r_dma_tx_done_d1 == 1 && r_dma_tx_done_d2 == 0)
r_dma_tx_done_cnt <= r_dma_tx_done_cnt + 1;
end
end
always @ (posedge cpu_bus_clk)
begin
r_dma_rx_direct_done <= r_dma_rx_direct_done_en_sync;
r_dma_tx_direct_done <= r_dma_tx_direct_done_en_sync;
r_dma_rx_done <= r_dma_rx_done_en_sync;
r_dma_tx_done <= r_dma_tx_done_en_sync;
r_dma_rx_direct_done_d1 <= r_dma_rx_direct_done;
r_dma_tx_direct_done_d1 <= r_dma_tx_direct_done;
r_dma_rx_done_d1 <= r_dma_rx_done;
r_dma_tx_done_d1 <= r_dma_tx_done;
r_dma_rx_direct_done_d2 <= r_dma_rx_direct_done_d1;
r_dma_tx_direct_done_d2 <= r_dma_tx_direct_done_d1;
r_dma_rx_done_d2 <= r_dma_rx_done_d1;
r_dma_tx_done_d2 <= r_dma_tx_done_d1;
end
always @ (posedge pcie_user_clk)
begin
r_dma_rx_direct_done_en_d1 <= r_dma_rx_direct_done_en;
r_dma_tx_direct_done_en_d1 <= r_dma_tx_direct_done_en;
r_dma_rx_done_en_d1 <= r_dma_rx_done_en;
r_dma_tx_done_en_d1 <= r_dma_tx_done_en;
r_dma_rx_direct_done_en_sync <= r_dma_rx_direct_done_en | r_dma_rx_direct_done_en_d1;
r_dma_tx_direct_done_en_sync <= r_dma_tx_direct_done_en | r_dma_tx_direct_done_en_d1;
r_dma_rx_done_en_sync <= r_dma_rx_done_en | r_dma_rx_done_en_d1;
r_dma_tx_done_en_sync <= r_dma_tx_done_en | r_dma_tx_done_en_d1;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_done_empty_n == 1'b1)
next_state <= S_DMA_INFO;
else
next_state <= S_IDLE;
end
S_DMA_INFO: begin
next_state <= S_NLB_RD_WAIT;
end
S_NLB_RD_WAIT: begin
if(r_dma_cmd_type == 1)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_INFO;
end
S_NLB_INFO: begin
next_state <= S_NLB_CALC;
end
S_NLB_CALC: begin
if(r_hcmd_data_len == r_dma_len)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_NLB_WR_WAIT;
end
S_NLB_WR_WAIT: begin
if(hcmd_nlb_wr1_rdy_n == 1)
next_state <= S_NLB_WR_WAIT;
else
next_state <= S_NLB_WR;
end
S_NLB_WR: begin
next_state <= S_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
if(r_nlb_wr_delay == 0)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_WR_DELAY;
end
S_CQ_WR_WAIT: begin
if(hcmd_cq_wr0_rdy_n == 1)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_CQ_WR;
end
S_CQ_WR: begin
next_state <= S_NLB_DONE;
end
S_NLB_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_DMA_INFO: begin
r_dma_cmd_type <= dma_done_rd_data[20];
r_dma_done_check <= dma_done_rd_data[19];
r_dma_dir <= dma_done_rd_data[18];
r_hcmd_slot_tag <= dma_done_rd_data[17:11];
r_dma_len <= dma_done_rd_data[10:0];
end
S_NLB_RD_WAIT: begin
end
S_NLB_INFO: begin
r_hcmd_data_len <= hcmd_nlb_rd_data;
end
S_NLB_CALC: begin
r_hcmd_data_len <= r_hcmd_data_len - r_dma_len;
end
S_NLB_WR_WAIT: begin
end
S_NLB_WR: begin
r_nlb_wr_delay <= LP_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
r_nlb_wr_delay <= r_nlb_wr_delay - 1;
end
S_CQ_WR_WAIT: begin
end
S_CQ_WR: begin
end
S_NLB_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_DMA_INFO: begin
r_dma_done_rd_en <= 1;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_RD_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_INFO: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_CALC: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 1;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_DELAY: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 1;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_DONE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & r_dma_dir;
r_dma_rx_done_en <= ~r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_done_en <= ~r_dma_cmd_type & r_dma_done_check & r_dma_dir;
end
default: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
endcase
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg [2*32-1:0] w2; initial w2 = {2 {32'h12345678}};
reg [9*32-1:0] w9; initial w9 = {9 {32'h12345678}};
reg [10*32-1:0] w10; initial w10 = {10{32'h12345678}};
reg [11*32-1:0] w11; initial w11 = {11{32'h12345678}};
reg [15*32-1:0] w15; initial w15 = {15{32'h12345678}};
reg [31*32-1:0] w31; initial w31 = {31{32'h12345678}};
reg [47*32-1:0] w47; initial w47 = {47{32'h12345678}};
reg [63*32-1:0] w63; initial w63 = {63{32'h12345678}};
// Aggregate outputs into a single result vector
wire [63:0] result = (w2[63:0]
^ w9[64:1]
^ w10[65:2]
^ w11[66:3]
^ w15[67:4]
^ w31[68:5]
^ w47[69:6]
^ w63[70:7]);
// What checksum will we end up with
`define EXPECTED_SUM 64'h184cb39122d8c6e3
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w2 <= w2 >> 1;
w9 <= w9 >> 1;
w10 <= w10 >> 1;
w11 <= w11 >> 1;
w15 <= w15 >> 1;
w31 <= w31 >> 1;
w47 <= w47 >> 1;
w63 <= w63 >> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_nlb # (
parameter P_DATA_WIDTH = 19,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input rst_n,
input wr0_en,
input [P_ADDR_WIDTH-1:0] wr0_addr,
input [P_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
input wr1_en,
input [P_ADDR_WIDTH-1:0] wr1_addr,
input [P_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
reg r_wr_en;
reg [P_ADDR_WIDTH-1:0] r_wr_addr;
reg [P_DATA_WIDTH-1:0] r_wr_data;
reg [P_ADDR_WIDTH-1:0] r_wr0_addr;
reg [P_DATA_WIDTH-1:0] r_wr0_data;
reg [P_ADDR_WIDTH-1:0] r_wr1_addr;
reg [P_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_req | r_wr0_req;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_addr <= wr0_addr;
r_wr0_data <= wr0_data;
end
if(wr1_en == 1) begin
r_wr1_addr <= wr1_addr;
r_wr1_data <= wr1_data;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1 || r_wr1_req == 1)
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
else if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: begin
r_wr_addr <= r_wr0_addr;
r_wr_data <= r_wr0_data;
end
2'b10: begin
r_wr_addr <= r_wr1_addr;
r_wr_data <= r_wr1_data;
end
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = r_wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_nlb # (
parameter P_DATA_WIDTH = 19,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input rst_n,
input wr0_en,
input [P_ADDR_WIDTH-1:0] wr0_addr,
input [P_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
input wr1_en,
input [P_ADDR_WIDTH-1:0] wr1_addr,
input [P_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
reg r_wr_en;
reg [P_ADDR_WIDTH-1:0] r_wr_addr;
reg [P_DATA_WIDTH-1:0] r_wr_data;
reg [P_ADDR_WIDTH-1:0] r_wr0_addr;
reg [P_DATA_WIDTH-1:0] r_wr0_data;
reg [P_ADDR_WIDTH-1:0] r_wr1_addr;
reg [P_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_req | r_wr0_req;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_addr <= wr0_addr;
r_wr0_data <= wr0_data;
end
if(wr1_en == 1) begin
r_wr1_addr <= wr1_addr;
r_wr1_data <= wr1_data;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1 || r_wr1_req == 1)
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
else if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: begin
r_wr_addr <= r_wr0_addr;
r_wr_data <= r_wr0_data;
end
2'b10: begin
r_wr_addr <= r_wr1_addr;
r_wr_data <= r_wr1_data;
end
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = r_wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done_fifo # (
parameter P_FIFO_DATA_WIDTH = 21,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= r_wr1_en_sync_d1 | wr1_en;
if(wr1_en == 1) begin
r_wr1_data_sync <= wr1_data;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data <= wr0_data;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data <= r_wr1_data_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
else if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: r_wr_data <= r_wr0_data;
2'b10: r_wr_data <= r_wr1_data;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg negate;
reg enable;
wire [31:0] datA = crc[31:0];
wire [31:0] datB = crc[63:32];
// Predict result
wire [63:0] muled = (negate ? (- {32'h0,datA} * {32'h0,datB})
: ( {32'h0,datA} * {32'h0,datB}));
reg [63:0] muled_d1;
reg [63:0] muled_d2;
reg [63:0] muled_d3;
reg [63:0] muled_d4;
reg enable_d1;
reg enable_d2;
reg enable_d3;
always @ (posedge clk) enable_d1 <= enable;
always @ (posedge clk) enable_d2 <= enable_d1;
always @ (posedge clk) enable_d3 <= enable_d2;
always @ (posedge clk) if (enable) muled_d1 <= muled;
always @ (posedge clk) if (enable_d1) muled_d2 <= muled_d1;
always @ (posedge clk) if (enable_d2) muled_d3 <= muled_d2;
always @ (posedge clk) if (enable_d3) muled_d4 <= muled_d3;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [64:0] product_d4; // From test of t_math_synmul_mul.v
// End of automatics
t_math_synmul_mul test (/*AUTOINST*/
// Outputs
.product_d4 (product_d4[64:0]),
// Inputs
.clk (clk),
.enable (enable),
.negate (negate),
.datA (datA[31:0]),
.datB (datB[31:0]));
integer cycs_enabled; initial cycs_enabled = 0;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n",$time, cyc,
crc, enable, negate, muled_d4, product_d4[63:0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
negate <= 1'b0; // Negation not currently supported
// Always enable in low cycle counts to clear out the pipe
//enable <= 1'b1; // 100% activity factor
enable <= (cyc<10 || cyc[4]); // 50% activity factor
//enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor
if (enable) cycs_enabled=cycs_enabled+1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else begin
if (product_d4[63:0] !== muled_d4) begin
$write("[%0t] BAD product, got=%x exp=%x\n",$time, product_d4[63:0], muled_d4);
$stop;
end
if (cyc==99) begin
if (crc !== 64'hc77bb9b3784ea091) $stop;
end
`ifndef SIM_CYCLES
`define SIM_CYCLES 99
`endif
if (cyc==`SIM_CYCLES) begin
$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled*100)/cyc));
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg negate;
reg enable;
wire [31:0] datA = crc[31:0];
wire [31:0] datB = crc[63:32];
// Predict result
wire [63:0] muled = (negate ? (- {32'h0,datA} * {32'h0,datB})
: ( {32'h0,datA} * {32'h0,datB}));
reg [63:0] muled_d1;
reg [63:0] muled_d2;
reg [63:0] muled_d3;
reg [63:0] muled_d4;
reg enable_d1;
reg enable_d2;
reg enable_d3;
always @ (posedge clk) enable_d1 <= enable;
always @ (posedge clk) enable_d2 <= enable_d1;
always @ (posedge clk) enable_d3 <= enable_d2;
always @ (posedge clk) if (enable) muled_d1 <= muled;
always @ (posedge clk) if (enable_d1) muled_d2 <= muled_d1;
always @ (posedge clk) if (enable_d2) muled_d3 <= muled_d2;
always @ (posedge clk) if (enable_d3) muled_d4 <= muled_d3;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [64:0] product_d4; // From test of t_math_synmul_mul.v
// End of automatics
t_math_synmul_mul test (/*AUTOINST*/
// Outputs
.product_d4 (product_d4[64:0]),
// Inputs
.clk (clk),
.enable (enable),
.negate (negate),
.datA (datA[31:0]),
.datB (datB[31:0]));
integer cycs_enabled; initial cycs_enabled = 0;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n",$time, cyc,
crc, enable, negate, muled_d4, product_d4[63:0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
negate <= 1'b0; // Negation not currently supported
// Always enable in low cycle counts to clear out the pipe
//enable <= 1'b1; // 100% activity factor
enable <= (cyc<10 || cyc[4]); // 50% activity factor
//enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor
if (enable) cycs_enabled=cycs_enabled+1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else begin
if (product_d4[63:0] !== muled_d4) begin
$write("[%0t] BAD product, got=%x exp=%x\n",$time, product_d4[63:0], muled_d4);
$stop;
end
if (cyc==99) begin
if (crc !== 64'hc77bb9b3784ea091) $stop;
end
`ifndef SIM_CYCLES
`define SIM_CYCLES 99
`endif
if (cyc==`SIM_CYCLES) begin
$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled*100)/cyc));
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg negate;
reg enable;
wire [31:0] datA = crc[31:0];
wire [31:0] datB = crc[63:32];
// Predict result
wire [63:0] muled = (negate ? (- {32'h0,datA} * {32'h0,datB})
: ( {32'h0,datA} * {32'h0,datB}));
reg [63:0] muled_d1;
reg [63:0] muled_d2;
reg [63:0] muled_d3;
reg [63:0] muled_d4;
reg enable_d1;
reg enable_d2;
reg enable_d3;
always @ (posedge clk) enable_d1 <= enable;
always @ (posedge clk) enable_d2 <= enable_d1;
always @ (posedge clk) enable_d3 <= enable_d2;
always @ (posedge clk) if (enable) muled_d1 <= muled;
always @ (posedge clk) if (enable_d1) muled_d2 <= muled_d1;
always @ (posedge clk) if (enable_d2) muled_d3 <= muled_d2;
always @ (posedge clk) if (enable_d3) muled_d4 <= muled_d3;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [64:0] product_d4; // From test of t_math_synmul_mul.v
// End of automatics
t_math_synmul_mul test (/*AUTOINST*/
// Outputs
.product_d4 (product_d4[64:0]),
// Inputs
.clk (clk),
.enable (enable),
.negate (negate),
.datA (datA[31:0]),
.datB (datB[31:0]));
integer cycs_enabled; initial cycs_enabled = 0;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n",$time, cyc,
crc, enable, negate, muled_d4, product_d4[63:0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
negate <= 1'b0; // Negation not currently supported
// Always enable in low cycle counts to clear out the pipe
//enable <= 1'b1; // 100% activity factor
enable <= (cyc<10 || cyc[4]); // 50% activity factor
//enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor
if (enable) cycs_enabled=cycs_enabled+1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else begin
if (product_d4[63:0] !== muled_d4) begin
$write("[%0t] BAD product, got=%x exp=%x\n",$time, product_d4[63:0], muled_d4);
$stop;
end
if (cyc==99) begin
if (crc !== 64'hc77bb9b3784ea091) $stop;
end
`ifndef SIM_CYCLES
`define SIM_CYCLES 99
`endif
if (cyc==`SIM_CYCLES) begin
$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled*100)/cyc));
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t;
sub a (.inst(1));
sub b (.inst(2));
// Returns integer line number, or -1 for all ok
import "DPI-C" context function int dpix_run_tests();
export "DPI-C" task dpix_t_int;
task dpix_t_int(input int i, output int o); o = ~i; endtask
export "DPI-C" dpix_t_renamed = task dpix_t_ren;
task dpix_t_ren(input int i, output int o); o = i+2; endtask
export "DPI-C" function dpix_int123;
function int dpix_int123(); dpix_int123 = 32'h123; endfunction
export "DPI-C" function dpix_f_bit;
export "DPI-C" function dpix_f_bit15;
export "DPI-C" function dpix_f_int;
export "DPI-C" function dpix_f_byte;
export "DPI-C" function dpix_f_shortint;
export "DPI-C" function dpix_f_longint;
export "DPI-C" function dpix_f_chandle;
function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction
function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction
function int dpix_f_int (int i); dpix_f_int = ~i; endfunction
function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction
function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction
function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction
function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction
export "DPI-C" task dpix_t_bit95;
task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask
export "DPI-C" task dpix_t_bit96;
task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask
int lineno;
initial begin
lineno = dpix_run_tests();
if (lineno != -1) begin
$display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input int inst);
export "DPI-C" function dpix_sub_inst;
function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t;
sub a (.inst(1));
sub b (.inst(2));
// Returns integer line number, or -1 for all ok
import "DPI-C" context function int dpix_run_tests();
export "DPI-C" task dpix_t_int;
task dpix_t_int(input int i, output int o); o = ~i; endtask
export "DPI-C" dpix_t_renamed = task dpix_t_ren;
task dpix_t_ren(input int i, output int o); o = i+2; endtask
export "DPI-C" function dpix_int123;
function int dpix_int123(); dpix_int123 = 32'h123; endfunction
export "DPI-C" function dpix_f_bit;
export "DPI-C" function dpix_f_bit15;
export "DPI-C" function dpix_f_int;
export "DPI-C" function dpix_f_byte;
export "DPI-C" function dpix_f_shortint;
export "DPI-C" function dpix_f_longint;
export "DPI-C" function dpix_f_chandle;
function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction
function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction
function int dpix_f_int (int i); dpix_f_int = ~i; endfunction
function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction
function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction
function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction
function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction
export "DPI-C" task dpix_t_bit95;
task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask
export "DPI-C" task dpix_t_bit96;
task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask
int lineno;
initial begin
lineno = dpix_run_tests();
if (lineno != -1) begin
$display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input int inst);
export "DPI-C" function dpix_sub_inst;
function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire noswap = crc[32];
wire nibble = crc[33];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] swapped; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
.swapped (swapped[31:0]),
// Inputs
.clk (clk),
.noswap (noswap),
.nibble (nibble),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, swapped,
// Inputs
clk, noswap, nibble, in
);
input clk;
input noswap;
input nibble;
input [31:0] in;
output [31:0] out;
output [31:0] swapped;
function [7:0] EndianSwap;
input Nibble;
input [7:0] Data;
begin
EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
Data[4], Data[5], Data[6], Data[7] }
: { 4'h0, Data[0], Data[1], Data[2], Data[3] });
end
endfunction
assign out[31:24] = (noswap ? in[31:24]
: EndianSwap(nibble, in[31:24]));
assign out[23:16] = (noswap ? in[23:16]
: EndianSwap(nibble, in[23:16]));
assign out[15:8] = (noswap ? in[15:8]
: EndianSwap(nibble, in[15:8]));
assign out[7:0] = (noswap ? in[7:0]
: EndianSwap(nibble, in[7:0]));
reg [31:0] swapped;
always @(posedge clk) begin
swapped[31:24] <= EndianSwap(nibble, in[31:24]);
swapped[23:16] <= EndianSwap(nibble, in[23:16]);
swapped[15:8] <= EndianSwap(nibble, in[15:8] );
swapped[7:0] <= EndianSwap(nibble, in[7:0] );
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_fifo # (
parameter P_FIFO_DATA_WIDTH = 19,
parameter P_FIFO_DEPTH_WIDTH = 7
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_fifo # (
parameter P_FIFO_DATA_WIDTH = 19,
parameter P_FIFO_DEPTH_WIDTH = 7
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg okidoki;
always @* begin
rf[63:32] = biu[63:32] & {32{okidoki}};
rf[31:0] = {32{okidoki}};
rf2 = rf;
rf2[31:0] = ~{32{okidoki}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
okidoki <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
okidoki <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
okidoki <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg okidoki;
always @* begin
rf[63:32] = biu[63:32] & {32{okidoki}};
rf[31:0] = {32{okidoki}};
rf2 = rf;
rf2[31:0] = ~{32{okidoki}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
okidoki <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
okidoki <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
okidoki <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq_fifo # (
parameter P_FIFO_DATA_WIDTH = 35,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data1,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data1,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
localparam S_IDLE = 3'b001;
localparam S_WRITE0 = 3'b010;
localparam S_WRITE1 = 3'b100;
reg [2:0] cur_state;
reg [2:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [3:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0_sync;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data0;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= wr1_en | r_wr1_en_sync_d1;
if(wr1_en == 1) begin
r_wr1_data0_sync <= wr1_data0;
r_wr1_data1_sync <= wr1_data1;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data0 <= wr0_data0;
r_wr0_data1 <= wr0_data1;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data0 <= r_wr1_data0_sync;
r_wr1_data1 <= r_wr1_data1_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE0;
else
next_state <= S_IDLE;
end
S_WRITE0: begin
next_state <= S_WRITE1;
end
S_WRITE1: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 4'b0001;
else if(r_wr1_req == 1)
r_wr_gnt <= 4'b0100;
end
S_WRITE0: begin
r_wr_gnt <= {r_wr_gnt[2:0], 1'b0};
end
S_WRITE1: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE0: begin
r_wr_en <= 1;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE1: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[1];
r_wr1_req_ack <= r_wr_gnt[3];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
4'b0001: r_wr_data <= r_wr0_data0;
4'b0010: r_wr_data <= r_wr0_data1;
4'b0100: r_wr_data <= r_wr1_data0;
4'b1000: r_wr_data <= r_wr1_data1;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq_fifo # (
parameter P_FIFO_DATA_WIDTH = 35,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data1,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data1,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
localparam S_IDLE = 3'b001;
localparam S_WRITE0 = 3'b010;
localparam S_WRITE1 = 3'b100;
reg [2:0] cur_state;
reg [2:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [3:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0_sync;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data0;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= wr1_en | r_wr1_en_sync_d1;
if(wr1_en == 1) begin
r_wr1_data0_sync <= wr1_data0;
r_wr1_data1_sync <= wr1_data1;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data0 <= wr0_data0;
r_wr0_data1 <= wr0_data1;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data0 <= r_wr1_data0_sync;
r_wr1_data1 <= r_wr1_data1_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE0;
else
next_state <= S_IDLE;
end
S_WRITE0: begin
next_state <= S_WRITE1;
end
S_WRITE1: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 4'b0001;
else if(r_wr1_req == 1)
r_wr_gnt <= 4'b0100;
end
S_WRITE0: begin
r_wr_gnt <= {r_wr_gnt[2:0], 1'b0};
end
S_WRITE1: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE0: begin
r_wr_en <= 1;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE1: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[1];
r_wr1_req_ack <= r_wr_gnt[3];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
4'b0001: r_wr_data <= r_wr0_data0;
4'b0010: r_wr_data <= r_wr0_data1;
4'b0100: r_wr_data <= r_wr1_data0;
4'b1000: r_wr_data <= r_wr1_data1;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_tag # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_tag_alloc,
input [7:0] pcie_alloc_tag,
input [5:4] pcie_tag_alloc_len,
output pcie_tag_full_n,
input [7:0] cpld_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input cpld_fifo_wr_en,
input cpld_fifo_tag_last,
output fifo_wr_en,
output [P_FIFO_DEPTH_WIDTH-1:0] fifo_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] fifo_wr_data,
output [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
output [P_FIFO_DEPTH_WIDTH:0] rear_addr
);
localparam LP_PCIE_TAG_PREFIX = 5'b00001;
localparam LP_PCIE_TAG_WITDH = 3;
localparam LP_NUM_OF_PCIE_TAG = 6;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_rear;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_front;
reg [P_FIFO_DEPTH_WIDTH:0] r_alloc_base_addr;
reg [LP_PCIE_TAG_WITDH-1:0] r_pcie_tag [LP_NUM_OF_PCIE_TAG-1:0];
reg [P_FIFO_DEPTH_WIDTH:0] r_pcie_tag_addr [LP_NUM_OF_PCIE_TAG-1:0];
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_wr_en;
reg r_cpld_fifo_tag_last;
wire [LP_NUM_OF_PCIE_TAG-1:0] w_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_alloc_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_update_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_free_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_valid;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH-1:0] r_fifo_wr_addr;
assign pcie_tag_full_n = ~((r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] ^ r_pcie_tag_front[LP_NUM_OF_PCIE_TAG])
& (r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] == r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0]));
assign fifo_wr_en = r_cpld_fifo_wr_en;
assign fifo_wr_addr = r_fifo_wr_addr;
assign fifo_wr_data = r_cpld_fifo_wr_data;
assign rear_full_addr = r_alloc_base_addr;
assign rear_addr = r_rear_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_rear <= 1;
r_alloc_base_addr <= 0;
r_pcie_tag[0] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[1] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[2] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[3] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[4] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[5] <= {LP_PCIE_TAG_WITDH{1'b1}};
end
else begin
if(pcie_tag_alloc == 1) begin
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1]};
r_alloc_base_addr <= r_alloc_base_addr + pcie_tag_alloc_len;
if(r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG];
end
if(r_pcie_tag_alloc_mask[0])
r_pcie_tag[0] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[1])
r_pcie_tag[1] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[2])
r_pcie_tag[2] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[3])
r_pcie_tag[3] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[4])
r_pcie_tag[4] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[5])
r_pcie_tag[5] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
end
end
always @ (*)
begin
if(pcie_tag_alloc == 1)
r_pcie_tag_alloc_mask <= r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0];
else
r_pcie_tag_alloc_mask <= 0;
if(cpld_fifo_wr_en == 1)
r_pcie_tag_update_mask <= w_pcie_tag_hit;
else
r_pcie_tag_update_mask <= 0;
if(r_cpld_fifo_tag_last == 1)
r_pcie_tag_invalid_mask <= r_pcie_tag_hit;
else
r_pcie_tag_invalid_mask <= 0;
r_pcie_tag_free_mask <= r_pcie_tag_valid & r_pcie_tag_invalid & r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0];
end
always @ (posedge pcie_user_clk)
begin
case({r_pcie_tag_update_mask[0], r_pcie_tag_alloc_mask[0]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[0] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[0] <= r_pcie_tag_addr[0] + 1;
endcase
case({r_pcie_tag_update_mask[1], r_pcie_tag_alloc_mask[1]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[1] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[1] <= r_pcie_tag_addr[1] + 1;
endcase
case({r_pcie_tag_update_mask[2], r_pcie_tag_alloc_mask[2]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[2] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[2] <= r_pcie_tag_addr[2] + 1;
endcase
case({r_pcie_tag_update_mask[3], r_pcie_tag_alloc_mask[3]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[3] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[3] <= r_pcie_tag_addr[3] + 1;
endcase
case({r_pcie_tag_update_mask[4], r_pcie_tag_alloc_mask[4]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[4] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[4] <= r_pcie_tag_addr[4] + 1;
endcase
case({r_pcie_tag_update_mask[5], r_pcie_tag_alloc_mask[5]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[5] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[5] <= r_pcie_tag_addr[5] + 1;
endcase
end
assign w_pcie_tag_hit[0] = (r_pcie_tag[0] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[0];
assign w_pcie_tag_hit[1] = (r_pcie_tag[1] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[1];
assign w_pcie_tag_hit[2] = (r_pcie_tag[2] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[2];
assign w_pcie_tag_hit[3] = (r_pcie_tag[3] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[3];
assign w_pcie_tag_hit[4] = (r_pcie_tag[4] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[4];
assign w_pcie_tag_hit[5] = (r_pcie_tag[5] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[5];
always @ (posedge pcie_user_clk)
begin
r_cpld_fifo_tag_last <= cpld_fifo_tag_last;
r_cpld_fifo_wr_en <= cpld_fifo_wr_en;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
end
always @ (posedge pcie_user_clk)
begin
r_pcie_tag_hit <= w_pcie_tag_hit;
case(w_pcie_tag_hit) // synthesis parallel_case
6'b000001: r_fifo_wr_addr <= r_pcie_tag_addr[0][P_FIFO_DEPTH_WIDTH-1:0];
6'b000010: r_fifo_wr_addr <= r_pcie_tag_addr[1][P_FIFO_DEPTH_WIDTH-1:0];
6'b000100: r_fifo_wr_addr <= r_pcie_tag_addr[2][P_FIFO_DEPTH_WIDTH-1:0];
6'b001000: r_fifo_wr_addr <= r_pcie_tag_addr[3][P_FIFO_DEPTH_WIDTH-1:0];
6'b010000: r_fifo_wr_addr <= r_pcie_tag_addr[4][P_FIFO_DEPTH_WIDTH-1:0];
6'b100000: r_fifo_wr_addr <= r_pcie_tag_addr[5][P_FIFO_DEPTH_WIDTH-1:0];
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_front <= 1;
r_rear_addr <= 0;
r_pcie_tag_valid <= 0;
r_pcie_tag_invalid <= 0;
end
else begin
r_pcie_tag_valid <= (r_pcie_tag_valid | r_pcie_tag_alloc_mask) & ~r_pcie_tag_free_mask;
r_pcie_tag_invalid <= (r_pcie_tag_invalid | r_pcie_tag_invalid_mask) & ~r_pcie_tag_free_mask;
if(r_pcie_tag_free_mask != 0) begin
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1]};
if(r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_front[LP_NUM_OF_PCIE_TAG];
end
case(r_pcie_tag_free_mask) // synthesis parallel_case
6'b000001: r_rear_addr <= r_pcie_tag_addr[0];
6'b000010: r_rear_addr <= r_pcie_tag_addr[1];
6'b000100: r_rear_addr <= r_pcie_tag_addr[2];
6'b001000: r_rear_addr <= r_pcie_tag_addr[3];
6'b010000: r_rear_addr <= r_pcie_tag_addr[4];
6'b100000: r_rear_addr <= r_pcie_tag_addr[5];
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input arb_sq_rdy,
input [3:0] sq_qid,
input [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
output sq_hcmd_ack,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
output pcie_sq_cmd_fifo_wr_en,
output [10:0] pcie_sq_cmd_fifo_wr_data,
input pcie_sq_cmd_fifo_full_n,
output pcie_sq_rx_tag_alloc,
output [7:0] pcie_sq_rx_alloc_tag,
output [6:4] pcie_sq_rx_tag_alloc_len,
input pcie_sq_rx_tag_full_n,
input pcie_sq_rx_fifo_full_n,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack
);
localparam LP_HCMD_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_HCMD_PCIE_SIZE = 10'h10;
localparam S_IDLE = 6'b000001;
localparam S_CMD_INFO = 6'b000010;
localparam S_CHECK_FIFO = 6'b000100;
localparam S_PCIE_MRD_REQ = 6'b001000;
localparam S_PCIE_MRD_ACK = 6'b010000;
localparam S_PCIE_MRD_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_sq_hcmd_ack;
reg r_hcmd_slot_alloc_en;
reg r_tx_mrd_req;
reg [2:0] r_hcmd_pcie_tag;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
reg r_hcmd_pcie_tag_update;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_sq_cmd_fifo_wr_en;
reg r_pcie_sq_rx_tag_alloc;
assign sq_hcmd_ack = r_sq_hcmd_ack;
assign hcmd_slot_alloc_en = r_hcmd_slot_alloc_en;
assign pcie_sq_cmd_fifo_wr_en = r_pcie_sq_cmd_fifo_wr_en;
assign pcie_sq_cmd_fifo_wr_data = {r_sq_qid, r_hcmd_slot_tag};
assign pcie_sq_rx_tag_alloc = r_pcie_sq_rx_tag_alloc;
assign pcie_sq_rx_alloc_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign pcie_sq_rx_tag_alloc_len = 3'b100;
assign tx_mrd_req = r_tx_mrd_req;
assign tx_mrd_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign tx_mrd_len = LP_HCMD_PCIE_SIZE;
assign tx_mrd_addr = r_hcmd_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(arb_sq_rdy == 1 && hcmd_slot_rdy == 1)
next_state <= S_CMD_INFO;
else
next_state <= S_IDLE;
end
S_CMD_INFO: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_cmd_fifo_full_n == 1 && pcie_sq_rx_tag_full_n == 1 && pcie_sq_rx_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_pcie_tag <= 0;
end
else begin
if(r_hcmd_pcie_tag_update == 1)
r_hcmd_pcie_tag <= r_hcmd_pcie_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_INFO: begin
r_sq_qid <= sq_qid;
r_hcmd_pcie_addr <= hcmd_pcie_addr;
r_hcmd_slot_tag <= hcmd_slot_tag;
end
S_CHECK_FIFO: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CMD_INFO: begin
r_sq_hcmd_ack <= 1;
r_hcmd_slot_alloc_en <= 1;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 1;
r_pcie_sq_rx_tag_alloc <= 1;
r_tx_mrd_req <= 1;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 1;
end
default: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input arb_sq_rdy,
input [3:0] sq_qid,
input [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
output sq_hcmd_ack,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
output pcie_sq_cmd_fifo_wr_en,
output [10:0] pcie_sq_cmd_fifo_wr_data,
input pcie_sq_cmd_fifo_full_n,
output pcie_sq_rx_tag_alloc,
output [7:0] pcie_sq_rx_alloc_tag,
output [6:4] pcie_sq_rx_tag_alloc_len,
input pcie_sq_rx_tag_full_n,
input pcie_sq_rx_fifo_full_n,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack
);
localparam LP_HCMD_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_HCMD_PCIE_SIZE = 10'h10;
localparam S_IDLE = 6'b000001;
localparam S_CMD_INFO = 6'b000010;
localparam S_CHECK_FIFO = 6'b000100;
localparam S_PCIE_MRD_REQ = 6'b001000;
localparam S_PCIE_MRD_ACK = 6'b010000;
localparam S_PCIE_MRD_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_sq_hcmd_ack;
reg r_hcmd_slot_alloc_en;
reg r_tx_mrd_req;
reg [2:0] r_hcmd_pcie_tag;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
reg r_hcmd_pcie_tag_update;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_sq_cmd_fifo_wr_en;
reg r_pcie_sq_rx_tag_alloc;
assign sq_hcmd_ack = r_sq_hcmd_ack;
assign hcmd_slot_alloc_en = r_hcmd_slot_alloc_en;
assign pcie_sq_cmd_fifo_wr_en = r_pcie_sq_cmd_fifo_wr_en;
assign pcie_sq_cmd_fifo_wr_data = {r_sq_qid, r_hcmd_slot_tag};
assign pcie_sq_rx_tag_alloc = r_pcie_sq_rx_tag_alloc;
assign pcie_sq_rx_alloc_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign pcie_sq_rx_tag_alloc_len = 3'b100;
assign tx_mrd_req = r_tx_mrd_req;
assign tx_mrd_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign tx_mrd_len = LP_HCMD_PCIE_SIZE;
assign tx_mrd_addr = r_hcmd_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(arb_sq_rdy == 1 && hcmd_slot_rdy == 1)
next_state <= S_CMD_INFO;
else
next_state <= S_IDLE;
end
S_CMD_INFO: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_cmd_fifo_full_n == 1 && pcie_sq_rx_tag_full_n == 1 && pcie_sq_rx_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_pcie_tag <= 0;
end
else begin
if(r_hcmd_pcie_tag_update == 1)
r_hcmd_pcie_tag <= r_hcmd_pcie_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_INFO: begin
r_sq_qid <= sq_qid;
r_hcmd_pcie_addr <= hcmd_pcie_addr;
r_hcmd_slot_tag <= hcmd_slot_tag;
end
S_CHECK_FIFO: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CMD_INFO: begin
r_sq_hcmd_ack <= 1;
r_hcmd_slot_alloc_en <= 1;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 1;
r_pcie_sq_rx_tag_alloc <= 1;
r_tx_mrd_req <= 1;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 1;
end
default: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd_gen # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output dma_cmd_rd_en,
input [49:0] dma_cmd_rd_data,
input dma_cmd_empty_n,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output pcie_cmd_wr_en,
output [33:0] pcie_cmd_wr_data,
input pcie_cmd_full_n,
output prp_pcie_alloc,
output [7:0] prp_pcie_alloc_tag,
output [5:4] prp_pcie_tag_alloc_len,
input pcie_tag_full_n,
input prp_fifo_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack
);
localparam LP_PRP_PCIE_TAG_PREFIX = 5'b00001;
localparam S_IDLE = 17'b00000000000000001;
localparam S_DMA_CMD0 = 17'b00000000000000010;
localparam S_DMA_CMD1 = 17'b00000000000000100;
localparam S_PRP_INFO0 = 17'b00000000000001000;
localparam S_PRP_INFO1 = 17'b00000000000010000;
localparam S_CALC_LEN0 = 17'b00000000000100000;
localparam S_CALC_LEN1 = 17'b00000000001000000;
localparam S_CALC_LEN2 = 17'b00000000010000000;
localparam S_CHECK_FIFO = 17'b00000000100000000;
localparam S_CMD0 = 17'b00000001000000000;
localparam S_CMD1 = 17'b00000010000000000;
localparam S_CMD2 = 17'b00000100000000000;
localparam S_CMD3 = 17'b00001000000000000;
localparam S_PCIE_MRD_CHECK = 17'b00010000000000000;
localparam S_PCIE_MRD_REQ = 17'b00100000000000000;
localparam S_PCIE_MRD_ACK = 17'b01000000000000000;
localparam S_PCIE_MRD_REQ_DONE = 17'b10000000000000000;
reg [16:0] cur_state;
reg [16:0] next_state;
reg r_pcie_rcb;
reg r_pcie_rcb_cross;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [8:0] r_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [8:0] r_hcmd_nlb;
reg r_prp2_type;
reg [8:0] r_prp_offset;
reg r_prp_offset_is_0;
reg [11:2] r_prp_4b_offset;
reg [12:2] r_1st_prp_4b_len;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
wire w_2st_mrd_need;
reg [2:0] r_tx_prp_mrd_tag;
reg [4:3] r_pcie_mrd_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_prp_mrd_addr;
wire [20:2] w_4b_offset;
wire w_dev_cmd_full_n;
reg r_dma_cmd_rd_en;
reg r_hcmd_prp_rd_sel;
reg r_dev_rx_cmd_wr_en;
reg r_dev_tx_cmd_wr_en;
reg r_dev_cmd_wr_data_sel;
reg r_pcie_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg r_prp_pcie_alloc;
reg r_tx_prp_mrd_req;
reg r_mrd_tag_update;
reg [29:0] r_dev_cmd_wr_data;
reg [33:0] r_pcie_cmd_wr_data;
assign dma_cmd_rd_en = r_dma_cmd_rd_en;
assign hcmd_prp_rd_addr = {r_hcmd_slot_tag, r_hcmd_prp_rd_sel};
assign dev_rx_cmd_wr_en = r_dev_rx_cmd_wr_en;
assign dev_rx_cmd_wr_data = r_dev_cmd_wr_data;
assign dev_tx_cmd_wr_en = r_dev_tx_cmd_wr_en;
assign dev_tx_cmd_wr_data = r_dev_cmd_wr_data;
assign pcie_cmd_wr_en = r_pcie_cmd_wr_en;
assign pcie_cmd_wr_data = r_pcie_cmd_wr_data;
assign prp_pcie_alloc = r_prp_pcie_alloc;
assign prp_pcie_alloc_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign prp_pcie_tag_alloc_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign tx_prp_mrd_req = r_tx_prp_mrd_req;
assign tx_prp_mrd_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign tx_prp_mrd_len = {7'b0, r_pcie_mrd_len, 1'b0};
assign tx_prp_mrd_addr = r_tx_prp_mrd_addr;
always @ (posedge pcie_user_clk)
begin
r_pcie_rcb <= pcie_rcb;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_dev_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? dev_tx_cmd_full_n : dev_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_cmd_empty_n == 1'b1)
next_state <= S_DMA_CMD0;
else
next_state <= S_IDLE;
end
S_DMA_CMD0: begin
next_state <= S_DMA_CMD1;
end
S_DMA_CMD1: begin
if(r_dma_cmd_type == 1'b1)
next_state <= S_CHECK_FIFO;
else
next_state <= S_PRP_INFO0;
end
S_PRP_INFO0: begin
next_state <= S_PRP_INFO1;
end
S_PRP_INFO1: begin
next_state <= S_CALC_LEN0;
end
S_CALC_LEN0: begin
next_state <= S_CALC_LEN1;
end
S_CALC_LEN1: begin
next_state <= S_CALC_LEN2;
end
S_CALC_LEN2: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(w_dev_cmd_full_n == 1'b1 && pcie_cmd_full_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_CHECK_FIFO;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_PCIE_MRD_CHECK;
else
next_state <= S_IDLE;
end
S_PCIE_MRD_CHECK: begin
if(pcie_tag_full_n == 1 && prp_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_MRD_CHECK;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_prp_mrd_req_ack == 1'b1)
next_state <= S_PCIE_MRD_REQ_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_REQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_prp_mrd_tag <= 0;
end
else begin
if(r_mrd_tag_update == 1)
r_tx_prp_mrd_tag <= r_tx_prp_mrd_tag + 1;
end
end
assign w_4b_offset[20:2] = {r_4k_offset, 10'b0} + r_hcmd_prp_1[11:2];
assign w_2st_mrd_need = r_2st_valid & r_2st_mrd_need;
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_2st_valid <= 0;
r_1st_mrd_need <= 0;
r_2st_mrd_need <= 0;
r_pcie_rcb_cross <= 0;
end
S_DMA_CMD0: begin
r_dev_addr <= dma_cmd_rd_data[29:0];
r_dev_dma_len <= dma_cmd_rd_data[40:30];
r_hcmd_slot_tag <= dma_cmd_rd_data[47:41];
r_dma_cmd_dir <= dma_cmd_rd_data[48];
r_dma_cmd_type <= dma_cmd_rd_data[49];
end
S_DMA_CMD1: begin
r_hcmd_prp_1 <= dma_cmd_rd_data[33:0];
r_4k_offset <= dma_cmd_rd_data[42:34];
r_1st_4b_len <= r_dev_dma_len;
end
S_PRP_INFO0: begin
r_hcmd_prp_1 <= hcmd_prp_rd_data[33:0];
end
S_PRP_INFO1: begin
r_hcmd_nlb <= {1'b0, hcmd_prp_rd_data[41:34]};
r_hcmd_prp_2 <= hcmd_prp_rd_data[33:0];
end
S_CALC_LEN0: begin
r_prp_offset <= w_4b_offset[20:12];
r_prp_4b_offset <= w_4b_offset[11:2];
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_CALC_LEN1: begin
r_dev_addr[11:2] <= 0;
r_dev_dma_len <= 11'h400;
r_prp_offset_is_0 <= (r_prp_offset == 0);
r_1st_prp_4b_len <= 11'h400 - r_prp_4b_offset;
if((12'h800 - r_hcmd_prp_1[11:2]) >= {r_hcmd_nlb, 10'b0})
r_prp2_type <= 0;
else
r_prp2_type <= 1;
end
S_CALC_LEN2: begin
if(r_dev_dma_len > r_1st_prp_4b_len) begin
r_1st_4b_len <= r_1st_prp_4b_len;
r_2st_4b_len <= r_dev_dma_len - r_1st_prp_4b_len;
r_2st_valid <= 1;
end
else begin
r_1st_4b_len <= r_dev_dma_len;
r_2st_valid <= 0;
end
if(r_prp_offset_is_0 == 1) begin
r_1st_mrd_need <= 0;
r_2st_mrd_need <= r_prp2_type;
end
else begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12];
r_1st_mrd_need <= r_prp2_type;
r_2st_mrd_need <= r_prp2_type;
r_prp_offset <= r_prp_offset - 1'b1;
end
r_hcmd_prp_1[11:2] <= r_prp_4b_offset;
end
S_CHECK_FIFO: begin
r_tx_prp_mrd_addr <= r_hcmd_prp_2 + {r_prp_offset, 1'b0};
r_pcie_mrd_len <= r_1st_mrd_need + w_2st_mrd_need;
end
S_CMD0: begin
if(r_pcie_mrd_len == 2 && r_tx_prp_mrd_addr[5:2] == 4'b1110) begin
if(r_pcie_rcb == 1)
r_pcie_rcb_cross <= r_tx_prp_mrd_addr[6];
else
r_pcie_rcb_cross <= 1;
end
else
r_pcie_rcb_cross <= 0;
end
S_CMD1: begin
end
S_CMD2: begin
end
S_CMD3: begin
end
S_PCIE_MRD_CHECK: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_REQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_dev_cmd_wr_data_sel == 0)
r_dev_cmd_wr_data <= {10'b0, r_dma_cmd_type, 1'b0, r_hcmd_slot_tag, r_dev_dma_len};
else
r_dev_cmd_wr_data <= r_dev_addr;
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {22'b0, r_dma_cmd_type, r_dma_cmd_dir, r_2st_valid, r_1st_mrd_need, r_2st_mrd_need, r_hcmd_slot_tag};
4'b0010: r_pcie_cmd_wr_data <= {11'b0, r_pcie_rcb_cross, r_1st_4b_len, r_2st_4b_len};
4'b0100: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD0: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD1: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 1;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0001;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 1;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0010;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0100;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD3: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b1000;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_CHECK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 1;
r_tx_prp_mrd_req <= 1;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ_DONE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 1;
end
default: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd_gen # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output dma_cmd_rd_en,
input [49:0] dma_cmd_rd_data,
input dma_cmd_empty_n,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output pcie_cmd_wr_en,
output [33:0] pcie_cmd_wr_data,
input pcie_cmd_full_n,
output prp_pcie_alloc,
output [7:0] prp_pcie_alloc_tag,
output [5:4] prp_pcie_tag_alloc_len,
input pcie_tag_full_n,
input prp_fifo_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack
);
localparam LP_PRP_PCIE_TAG_PREFIX = 5'b00001;
localparam S_IDLE = 17'b00000000000000001;
localparam S_DMA_CMD0 = 17'b00000000000000010;
localparam S_DMA_CMD1 = 17'b00000000000000100;
localparam S_PRP_INFO0 = 17'b00000000000001000;
localparam S_PRP_INFO1 = 17'b00000000000010000;
localparam S_CALC_LEN0 = 17'b00000000000100000;
localparam S_CALC_LEN1 = 17'b00000000001000000;
localparam S_CALC_LEN2 = 17'b00000000010000000;
localparam S_CHECK_FIFO = 17'b00000000100000000;
localparam S_CMD0 = 17'b00000001000000000;
localparam S_CMD1 = 17'b00000010000000000;
localparam S_CMD2 = 17'b00000100000000000;
localparam S_CMD3 = 17'b00001000000000000;
localparam S_PCIE_MRD_CHECK = 17'b00010000000000000;
localparam S_PCIE_MRD_REQ = 17'b00100000000000000;
localparam S_PCIE_MRD_ACK = 17'b01000000000000000;
localparam S_PCIE_MRD_REQ_DONE = 17'b10000000000000000;
reg [16:0] cur_state;
reg [16:0] next_state;
reg r_pcie_rcb;
reg r_pcie_rcb_cross;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [8:0] r_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [8:0] r_hcmd_nlb;
reg r_prp2_type;
reg [8:0] r_prp_offset;
reg r_prp_offset_is_0;
reg [11:2] r_prp_4b_offset;
reg [12:2] r_1st_prp_4b_len;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
wire w_2st_mrd_need;
reg [2:0] r_tx_prp_mrd_tag;
reg [4:3] r_pcie_mrd_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_prp_mrd_addr;
wire [20:2] w_4b_offset;
wire w_dev_cmd_full_n;
reg r_dma_cmd_rd_en;
reg r_hcmd_prp_rd_sel;
reg r_dev_rx_cmd_wr_en;
reg r_dev_tx_cmd_wr_en;
reg r_dev_cmd_wr_data_sel;
reg r_pcie_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg r_prp_pcie_alloc;
reg r_tx_prp_mrd_req;
reg r_mrd_tag_update;
reg [29:0] r_dev_cmd_wr_data;
reg [33:0] r_pcie_cmd_wr_data;
assign dma_cmd_rd_en = r_dma_cmd_rd_en;
assign hcmd_prp_rd_addr = {r_hcmd_slot_tag, r_hcmd_prp_rd_sel};
assign dev_rx_cmd_wr_en = r_dev_rx_cmd_wr_en;
assign dev_rx_cmd_wr_data = r_dev_cmd_wr_data;
assign dev_tx_cmd_wr_en = r_dev_tx_cmd_wr_en;
assign dev_tx_cmd_wr_data = r_dev_cmd_wr_data;
assign pcie_cmd_wr_en = r_pcie_cmd_wr_en;
assign pcie_cmd_wr_data = r_pcie_cmd_wr_data;
assign prp_pcie_alloc = r_prp_pcie_alloc;
assign prp_pcie_alloc_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign prp_pcie_tag_alloc_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign tx_prp_mrd_req = r_tx_prp_mrd_req;
assign tx_prp_mrd_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign tx_prp_mrd_len = {7'b0, r_pcie_mrd_len, 1'b0};
assign tx_prp_mrd_addr = r_tx_prp_mrd_addr;
always @ (posedge pcie_user_clk)
begin
r_pcie_rcb <= pcie_rcb;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_dev_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? dev_tx_cmd_full_n : dev_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_cmd_empty_n == 1'b1)
next_state <= S_DMA_CMD0;
else
next_state <= S_IDLE;
end
S_DMA_CMD0: begin
next_state <= S_DMA_CMD1;
end
S_DMA_CMD1: begin
if(r_dma_cmd_type == 1'b1)
next_state <= S_CHECK_FIFO;
else
next_state <= S_PRP_INFO0;
end
S_PRP_INFO0: begin
next_state <= S_PRP_INFO1;
end
S_PRP_INFO1: begin
next_state <= S_CALC_LEN0;
end
S_CALC_LEN0: begin
next_state <= S_CALC_LEN1;
end
S_CALC_LEN1: begin
next_state <= S_CALC_LEN2;
end
S_CALC_LEN2: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(w_dev_cmd_full_n == 1'b1 && pcie_cmd_full_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_CHECK_FIFO;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_PCIE_MRD_CHECK;
else
next_state <= S_IDLE;
end
S_PCIE_MRD_CHECK: begin
if(pcie_tag_full_n == 1 && prp_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_MRD_CHECK;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_prp_mrd_req_ack == 1'b1)
next_state <= S_PCIE_MRD_REQ_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_REQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_prp_mrd_tag <= 0;
end
else begin
if(r_mrd_tag_update == 1)
r_tx_prp_mrd_tag <= r_tx_prp_mrd_tag + 1;
end
end
assign w_4b_offset[20:2] = {r_4k_offset, 10'b0} + r_hcmd_prp_1[11:2];
assign w_2st_mrd_need = r_2st_valid & r_2st_mrd_need;
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_2st_valid <= 0;
r_1st_mrd_need <= 0;
r_2st_mrd_need <= 0;
r_pcie_rcb_cross <= 0;
end
S_DMA_CMD0: begin
r_dev_addr <= dma_cmd_rd_data[29:0];
r_dev_dma_len <= dma_cmd_rd_data[40:30];
r_hcmd_slot_tag <= dma_cmd_rd_data[47:41];
r_dma_cmd_dir <= dma_cmd_rd_data[48];
r_dma_cmd_type <= dma_cmd_rd_data[49];
end
S_DMA_CMD1: begin
r_hcmd_prp_1 <= dma_cmd_rd_data[33:0];
r_4k_offset <= dma_cmd_rd_data[42:34];
r_1st_4b_len <= r_dev_dma_len;
end
S_PRP_INFO0: begin
r_hcmd_prp_1 <= hcmd_prp_rd_data[33:0];
end
S_PRP_INFO1: begin
r_hcmd_nlb <= {1'b0, hcmd_prp_rd_data[41:34]};
r_hcmd_prp_2 <= hcmd_prp_rd_data[33:0];
end
S_CALC_LEN0: begin
r_prp_offset <= w_4b_offset[20:12];
r_prp_4b_offset <= w_4b_offset[11:2];
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_CALC_LEN1: begin
r_dev_addr[11:2] <= 0;
r_dev_dma_len <= 11'h400;
r_prp_offset_is_0 <= (r_prp_offset == 0);
r_1st_prp_4b_len <= 11'h400 - r_prp_4b_offset;
if((12'h800 - r_hcmd_prp_1[11:2]) >= {r_hcmd_nlb, 10'b0})
r_prp2_type <= 0;
else
r_prp2_type <= 1;
end
S_CALC_LEN2: begin
if(r_dev_dma_len > r_1st_prp_4b_len) begin
r_1st_4b_len <= r_1st_prp_4b_len;
r_2st_4b_len <= r_dev_dma_len - r_1st_prp_4b_len;
r_2st_valid <= 1;
end
else begin
r_1st_4b_len <= r_dev_dma_len;
r_2st_valid <= 0;
end
if(r_prp_offset_is_0 == 1) begin
r_1st_mrd_need <= 0;
r_2st_mrd_need <= r_prp2_type;
end
else begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12];
r_1st_mrd_need <= r_prp2_type;
r_2st_mrd_need <= r_prp2_type;
r_prp_offset <= r_prp_offset - 1'b1;
end
r_hcmd_prp_1[11:2] <= r_prp_4b_offset;
end
S_CHECK_FIFO: begin
r_tx_prp_mrd_addr <= r_hcmd_prp_2 + {r_prp_offset, 1'b0};
r_pcie_mrd_len <= r_1st_mrd_need + w_2st_mrd_need;
end
S_CMD0: begin
if(r_pcie_mrd_len == 2 && r_tx_prp_mrd_addr[5:2] == 4'b1110) begin
if(r_pcie_rcb == 1)
r_pcie_rcb_cross <= r_tx_prp_mrd_addr[6];
else
r_pcie_rcb_cross <= 1;
end
else
r_pcie_rcb_cross <= 0;
end
S_CMD1: begin
end
S_CMD2: begin
end
S_CMD3: begin
end
S_PCIE_MRD_CHECK: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_REQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_dev_cmd_wr_data_sel == 0)
r_dev_cmd_wr_data <= {10'b0, r_dma_cmd_type, 1'b0, r_hcmd_slot_tag, r_dev_dma_len};
else
r_dev_cmd_wr_data <= r_dev_addr;
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {22'b0, r_dma_cmd_type, r_dma_cmd_dir, r_2st_valid, r_1st_mrd_need, r_2st_mrd_need, r_hcmd_slot_tag};
4'b0010: r_pcie_cmd_wr_data <= {11'b0, r_pcie_rcb_cross, r_1st_4b_len, r_2st_4b_len};
4'b0100: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD0: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD1: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 1;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0001;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 1;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0010;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0100;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD3: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b1000;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_CHECK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 1;
r_tx_prp_mrd_req <= 1;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ_DONE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 1;
end
default: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
endcase
end
endmodule |
module packet_builder #(parameter NUM_CHAN = 1)(
// System
input rxclk,
input reset,
input [31:0] adctime,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
//assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end //end of `IDLE
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
chan_rdreq <= #1 1;
state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
module packet_builder #(parameter NUM_CHAN = 1)(
// System
input rxclk,
input reset,
input [31:0] adctime,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
//assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end //end of `IDLE
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
chan_rdreq <= #1 1;
state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
reg inmod;
generate
if (1) begin
// Traces as genblk1.ingen
integer ingen;
initial $display("ingen: {mod}.genblk1 %m");
end
endgenerate
integer rawmod;
initial begin
begin
integer upa;
begin : d3nameda
// %m='.d3nameda' var=_unnamed#.d3nameda.b1
integer d3a;
$display("d3a: {mod}.d3nameda %m");
end
end
end
initial begin
integer b2;
$display("b2: {mod} %m");
begin : b3named
integer b3n;
$display("b3n: {mod}.b3named: %m");
end
if (1) begin
integer b3;
$display("b3: {mod} %m");
if (1) begin
begin
begin
begin
integer b4;
$display("b4: {mod} %m");
end
end
end
end
else begin
integer b4;
$display("bb %m");
end
end
else begin
integer b4;
$display("b4 %m");
end
tsk;
$write("*-* All Finished *-*\n");
$finish;
end
task tsk;
integer t1;
$display("t1 {mod}.tsk %m");
begin
integer t2;
$display("t2 {mod}.tsk %m");
end
endtask
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
reg inmod;
generate
if (1) begin
// Traces as genblk1.ingen
integer ingen;
initial $display("ingen: {mod}.genblk1 %m");
end
endgenerate
integer rawmod;
initial begin
begin
integer upa;
begin : d3nameda
// %m='.d3nameda' var=_unnamed#.d3nameda.b1
integer d3a;
$display("d3a: {mod}.d3nameda %m");
end
end
end
initial begin
integer b2;
$display("b2: {mod} %m");
begin : b3named
integer b3n;
$display("b3n: {mod}.b3named: %m");
end
if (1) begin
integer b3;
$display("b3: {mod} %m");
if (1) begin
begin
begin
begin
integer b4;
$display("b4: {mod} %m");
end
end
end
end
else begin
integer b4;
$display("bb %m");
end
end
else begin
integer b4;
$display("b4 %m");
end
tsk;
$write("*-* All Finished *-*\n");
$finish;
end
task tsk;
integer t1;
$display("t1 {mod}.tsk %m");
begin
integer t2;
$display("t2 {mod}.tsk %m");
end
endtask
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_cid # (
parameter P_DATA_WIDTH = 20,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_cid # (
parameter P_DATA_WIDTH = 20,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_cid # (
parameter P_DATA_WIDTH = 20,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_tran # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output tx_err_drop,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_arb_valid,
input [5:0] tx_arb_gnt,
input [2:0] tx_arb_type,
input [11:2] tx_pcie_len,
input [127:0] tx_pcie_head,
input [31:0] tx_cpld_udata,
output tx_arb_rdy,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
localparam S_TX_IDLE = 9'b000000001;
localparam S_TX_CPLD_HEAD = 9'b000000010;
localparam S_TX_CPLD_DATA = 9'b000000100;
localparam S_TX_MRD_HEAD = 9'b000001000;
localparam S_TX_MWR_HEAD = 9'b000010000;
localparam S_TX_MWR_HEAD_WAIT = 9'b000100000;
localparam S_TX_MWR_DATA = 9'b001000000;
localparam S_TX_MWR_WAIT = 9'b010000000;
localparam S_TX_MWR_DATA_LAST = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg [C_PCIE_DATA_WIDTH-1:0] r_m_axis_tx_tdata;
reg [(C_PCIE_DATA_WIDTH/8)-1:0] r_m_axis_tx_tkeep;
reg [3:0] r_m_axis_tx_tuser;
reg r_m_axis_tx_tlast;
reg r_m_axis_tx_tvalid;
reg [5:0] r_tx_arb_gnt;
reg [11:2] r_tx_pcie_len;
reg [11:2] r_tx_pcie_data_cnt;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_pcie_head;
reg [31:0] r_tx_cpld_udata;
reg r_tx_arb_rdy;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_rd_data;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_data;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_data_d1;
reg r_tx_mwr0_rd_en;
reg r_tx_mwr0_data_last;
reg r_tx_mwr1_rd_en;
reg r_tx_mwr1_data_last;
assign m_axis_tx_tdata = r_m_axis_tx_tdata;
assign m_axis_tx_tkeep = r_m_axis_tx_tkeep;
assign m_axis_tx_tuser = r_m_axis_tx_tuser;
assign m_axis_tx_tlast = r_m_axis_tx_tlast;
assign m_axis_tx_tvalid = r_m_axis_tx_tvalid;
assign tx_err_drop = 1'b0;
assign tx_arb_rdy = r_tx_arb_rdy;
assign tx_mwr0_rd_en = r_tx_mwr0_rd_en;
assign tx_mwr0_data_last = r_tx_mwr0_data_last;
assign tx_mwr1_rd_en = r_tx_mwr1_rd_en;
assign tx_mwr1_data_last = r_tx_mwr1_data_last;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_TX_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_TX_IDLE: begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
S_TX_CPLD_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_len[3] == 1)
next_state <= S_TX_CPLD_DATA;
else if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_CPLD_HEAD;
end
S_TX_CPLD_DATA: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_CPLD_DATA;
end
S_TX_MRD_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_MRD_HEAD;
end
S_TX_MWR_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_len == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_HEAD_WAIT;
end
S_TX_MWR_HEAD_WAIT: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_HEAD_WAIT;
end
S_TX_MWR_DATA: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 8)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_WAIT;
end
S_TX_MWR_WAIT: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_WAIT;
end
S_TX_MWR_DATA_LAST: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_MWR_DATA_LAST;
end
default: begin
next_state <= S_TX_IDLE;
end
endcase
end
always @ (*)
begin
case(r_tx_arb_gnt[5:4]) // synthesis parallel_case full_case
2'b01: begin
r_tx_mwr_rd_data[31:0] <= {tx_mwr0_rd_data[7:0], tx_mwr0_rd_data[15:8], tx_mwr0_rd_data[23:16], tx_mwr0_rd_data[31:24]};
r_tx_mwr_rd_data[63:32] <= {tx_mwr0_rd_data[39:32], tx_mwr0_rd_data[47:40], tx_mwr0_rd_data[55:48], tx_mwr0_rd_data[63:56]};
r_tx_mwr_rd_data[95:64] <= {tx_mwr0_rd_data[71:64], tx_mwr0_rd_data[79:72], tx_mwr0_rd_data[87:80], tx_mwr0_rd_data[95:88]};
r_tx_mwr_rd_data[127:96] <= {tx_mwr0_rd_data[103:96], tx_mwr0_rd_data[111:104], tx_mwr0_rd_data[119:112], tx_mwr0_rd_data[127:120]};
end
2'b10: begin
r_tx_mwr_rd_data[31:0] <= {tx_mwr1_rd_data[7:0], tx_mwr1_rd_data[15:8], tx_mwr1_rd_data[23:16], tx_mwr1_rd_data[31:24]};
r_tx_mwr_rd_data[63:32] <= {tx_mwr1_rd_data[39:32], tx_mwr1_rd_data[47:40], tx_mwr1_rd_data[55:48], tx_mwr1_rd_data[63:56]};
r_tx_mwr_rd_data[95:64] <= {tx_mwr1_rd_data[71:64], tx_mwr1_rd_data[79:72], tx_mwr1_rd_data[87:80], tx_mwr1_rd_data[95:88]};
r_tx_mwr_rd_data[127:96] <= {tx_mwr1_rd_data[103:96], tx_mwr1_rd_data[111:104], tx_mwr1_rd_data[119:112], tx_mwr1_rd_data[127:120]};
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(r_tx_arb_rdy == 1) begin
r_tx_arb_gnt <= tx_arb_gnt;
r_tx_pcie_len <= tx_pcie_len;
r_tx_pcie_head <= tx_pcie_head;
r_tx_cpld_udata <= tx_cpld_udata;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_TX_IDLE: begin
end
S_TX_CPLD_HEAD: begin
end
S_TX_CPLD_DATA: begin
end
S_TX_MRD_HEAD: begin
end
S_TX_MWR_HEAD: begin
r_tx_pcie_data_cnt <= r_tx_pcie_len;
r_tx_mwr_data <= r_tx_mwr_rd_data;
end
S_TX_MWR_HEAD_WAIT: begin
end
S_TX_MWR_DATA: begin
r_tx_pcie_data_cnt <= r_tx_pcie_data_cnt - 4;
r_tx_mwr_data <= r_tx_mwr_rd_data;
r_tx_mwr_data_d1 <= r_tx_mwr_data;
end
S_TX_MWR_WAIT: begin
end
S_TX_MWR_DATA_LAST: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_TX_IDLE: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'h0000;
r_m_axis_tx_tuser <= 4'b0000;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 0;
r_tx_arb_rdy <= 1;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_CPLD_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= r_tx_pcie_len[2];
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= r_tx_pcie_len[2] & m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_CPLD_DATA: begin
r_m_axis_tx_tdata <= {96'h0, r_tx_cpld_udata};
r_m_axis_tx_tkeep <= 16'h000F;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MRD_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= r_tx_arb_gnt[4];
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= r_tx_arb_gnt[5];
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_HEAD_WAIT: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_DATA: begin
r_m_axis_tx_tdata <= r_tx_mwr_data;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= r_tx_arb_gnt[4];
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= r_tx_arb_gnt[5];
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_WAIT: begin
r_m_axis_tx_tdata <= r_tx_mwr_data_d1;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_DATA_LAST: begin
r_m_axis_tx_tdata <= r_tx_mwr_data;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= r_tx_arb_gnt[4] & m_axis_tx_tready;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= r_tx_arb_gnt[5] & m_axis_tx_tready;
end
default: begin
r_m_axis_tx_tdata <= 128'b0;
r_m_axis_tx_tkeep <= 16'h0000;
r_m_axis_tx_tuser <= 4'b0000;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 0;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_tran # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output tx_err_drop,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_arb_valid,
input [5:0] tx_arb_gnt,
input [2:0] tx_arb_type,
input [11:2] tx_pcie_len,
input [127:0] tx_pcie_head,
input [31:0] tx_cpld_udata,
output tx_arb_rdy,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
localparam S_TX_IDLE = 9'b000000001;
localparam S_TX_CPLD_HEAD = 9'b000000010;
localparam S_TX_CPLD_DATA = 9'b000000100;
localparam S_TX_MRD_HEAD = 9'b000001000;
localparam S_TX_MWR_HEAD = 9'b000010000;
localparam S_TX_MWR_HEAD_WAIT = 9'b000100000;
localparam S_TX_MWR_DATA = 9'b001000000;
localparam S_TX_MWR_WAIT = 9'b010000000;
localparam S_TX_MWR_DATA_LAST = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg [C_PCIE_DATA_WIDTH-1:0] r_m_axis_tx_tdata;
reg [(C_PCIE_DATA_WIDTH/8)-1:0] r_m_axis_tx_tkeep;
reg [3:0] r_m_axis_tx_tuser;
reg r_m_axis_tx_tlast;
reg r_m_axis_tx_tvalid;
reg [5:0] r_tx_arb_gnt;
reg [11:2] r_tx_pcie_len;
reg [11:2] r_tx_pcie_data_cnt;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_pcie_head;
reg [31:0] r_tx_cpld_udata;
reg r_tx_arb_rdy;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_rd_data;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_data;
reg [C_PCIE_DATA_WIDTH-1:0] r_tx_mwr_data_d1;
reg r_tx_mwr0_rd_en;
reg r_tx_mwr0_data_last;
reg r_tx_mwr1_rd_en;
reg r_tx_mwr1_data_last;
assign m_axis_tx_tdata = r_m_axis_tx_tdata;
assign m_axis_tx_tkeep = r_m_axis_tx_tkeep;
assign m_axis_tx_tuser = r_m_axis_tx_tuser;
assign m_axis_tx_tlast = r_m_axis_tx_tlast;
assign m_axis_tx_tvalid = r_m_axis_tx_tvalid;
assign tx_err_drop = 1'b0;
assign tx_arb_rdy = r_tx_arb_rdy;
assign tx_mwr0_rd_en = r_tx_mwr0_rd_en;
assign tx_mwr0_data_last = r_tx_mwr0_data_last;
assign tx_mwr1_rd_en = r_tx_mwr1_rd_en;
assign tx_mwr1_data_last = r_tx_mwr1_data_last;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_TX_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_TX_IDLE: begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
S_TX_CPLD_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_len[3] == 1)
next_state <= S_TX_CPLD_DATA;
else if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_CPLD_HEAD;
end
S_TX_CPLD_DATA: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_CPLD_DATA;
end
S_TX_MRD_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_MRD_HEAD;
end
S_TX_MWR_HEAD: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_len == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_HEAD_WAIT;
end
S_TX_MWR_HEAD_WAIT: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_HEAD_WAIT;
end
S_TX_MWR_DATA: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 8)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_WAIT;
end
S_TX_MWR_WAIT: begin
if(m_axis_tx_tready == 1) begin
if(r_tx_pcie_data_cnt == 4)
next_state <= S_TX_MWR_DATA_LAST;
else
next_state <= S_TX_MWR_DATA;
end
else
next_state <= S_TX_MWR_WAIT;
end
S_TX_MWR_DATA_LAST: begin
if(m_axis_tx_tready == 1) begin
if(tx_arb_valid == 1) begin
case(tx_arb_type) // synthesis parallel_case full_case
3'b001: next_state <= S_TX_CPLD_HEAD;
3'b010: next_state <= S_TX_MRD_HEAD;
3'b100: next_state <= S_TX_MWR_HEAD;
endcase
end
else
next_state <= S_TX_IDLE;
end
else
next_state <= S_TX_MWR_DATA_LAST;
end
default: begin
next_state <= S_TX_IDLE;
end
endcase
end
always @ (*)
begin
case(r_tx_arb_gnt[5:4]) // synthesis parallel_case full_case
2'b01: begin
r_tx_mwr_rd_data[31:0] <= {tx_mwr0_rd_data[7:0], tx_mwr0_rd_data[15:8], tx_mwr0_rd_data[23:16], tx_mwr0_rd_data[31:24]};
r_tx_mwr_rd_data[63:32] <= {tx_mwr0_rd_data[39:32], tx_mwr0_rd_data[47:40], tx_mwr0_rd_data[55:48], tx_mwr0_rd_data[63:56]};
r_tx_mwr_rd_data[95:64] <= {tx_mwr0_rd_data[71:64], tx_mwr0_rd_data[79:72], tx_mwr0_rd_data[87:80], tx_mwr0_rd_data[95:88]};
r_tx_mwr_rd_data[127:96] <= {tx_mwr0_rd_data[103:96], tx_mwr0_rd_data[111:104], tx_mwr0_rd_data[119:112], tx_mwr0_rd_data[127:120]};
end
2'b10: begin
r_tx_mwr_rd_data[31:0] <= {tx_mwr1_rd_data[7:0], tx_mwr1_rd_data[15:8], tx_mwr1_rd_data[23:16], tx_mwr1_rd_data[31:24]};
r_tx_mwr_rd_data[63:32] <= {tx_mwr1_rd_data[39:32], tx_mwr1_rd_data[47:40], tx_mwr1_rd_data[55:48], tx_mwr1_rd_data[63:56]};
r_tx_mwr_rd_data[95:64] <= {tx_mwr1_rd_data[71:64], tx_mwr1_rd_data[79:72], tx_mwr1_rd_data[87:80], tx_mwr1_rd_data[95:88]};
r_tx_mwr_rd_data[127:96] <= {tx_mwr1_rd_data[103:96], tx_mwr1_rd_data[111:104], tx_mwr1_rd_data[119:112], tx_mwr1_rd_data[127:120]};
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(r_tx_arb_rdy == 1) begin
r_tx_arb_gnt <= tx_arb_gnt;
r_tx_pcie_len <= tx_pcie_len;
r_tx_pcie_head <= tx_pcie_head;
r_tx_cpld_udata <= tx_cpld_udata;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_TX_IDLE: begin
end
S_TX_CPLD_HEAD: begin
end
S_TX_CPLD_DATA: begin
end
S_TX_MRD_HEAD: begin
end
S_TX_MWR_HEAD: begin
r_tx_pcie_data_cnt <= r_tx_pcie_len;
r_tx_mwr_data <= r_tx_mwr_rd_data;
end
S_TX_MWR_HEAD_WAIT: begin
end
S_TX_MWR_DATA: begin
r_tx_pcie_data_cnt <= r_tx_pcie_data_cnt - 4;
r_tx_mwr_data <= r_tx_mwr_rd_data;
r_tx_mwr_data_d1 <= r_tx_mwr_data;
end
S_TX_MWR_WAIT: begin
end
S_TX_MWR_DATA_LAST: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_TX_IDLE: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'h0000;
r_m_axis_tx_tuser <= 4'b0000;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 0;
r_tx_arb_rdy <= 1;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_CPLD_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= r_tx_pcie_len[2];
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= r_tx_pcie_len[2] & m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_CPLD_DATA: begin
r_m_axis_tx_tdata <= {96'h0, r_tx_cpld_udata};
r_m_axis_tx_tkeep <= 16'h000F;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MRD_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_HEAD: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= r_tx_arb_gnt[4];
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= r_tx_arb_gnt[5];
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_HEAD_WAIT: begin
r_m_axis_tx_tdata <= r_tx_pcie_head;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_DATA: begin
r_m_axis_tx_tdata <= r_tx_mwr_data;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= r_tx_arb_gnt[4];
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= r_tx_arb_gnt[5];
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_WAIT: begin
r_m_axis_tx_tdata <= r_tx_mwr_data_d1;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
S_TX_MWR_DATA_LAST: begin
r_m_axis_tx_tdata <= r_tx_mwr_data;
r_m_axis_tx_tkeep <= 16'hFFFF;
r_m_axis_tx_tuser <= 4'b0100;
r_m_axis_tx_tlast <= 1;
r_m_axis_tx_tvalid <= 1;
r_tx_arb_rdy <= m_axis_tx_tready;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= r_tx_arb_gnt[4] & m_axis_tx_tready;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= r_tx_arb_gnt[5] & m_axis_tx_tready;
end
default: begin
r_m_axis_tx_tdata <= 128'b0;
r_m_axis_tx_tkeep <= 16'h0000;
r_m_axis_tx_tuser <= 4'b0000;
r_m_axis_tx_tlast <= 0;
r_m_axis_tx_tvalid <= 0;
r_tx_arb_rdy <= 0;
r_tx_mwr0_rd_en <= 0;
r_tx_mwr0_data_last <= 0;
r_tx_mwr1_rd_en <= 0;
r_tx_mwr1_data_last <= 0;
end
endcase
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_on GENCLK
reg [31:0] long;
reg [63:0] quad;
wire [31:0] longout;
wire [63:0] quadout;
wire [7:0] narrow = long[7:0];
sub sub (/*AUTOINST*/
// Outputs
.longout (longout[31:0]),
.quadout (quadout[63:0]),
// Inputs
.narrow (narrow[7:0]),
.quad (quad[63:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
long <= 32'h12345678;
quad <= 64'h12345678_abcdef12;
end
if (cyc==2) begin
if (longout !== 32'h79) $stop;
if (quadout !== 64'h12345678_abcdef13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
wire [31:0] longout = $c32("(",narrow,"+1)");
wire [63:0] quadout = $c64("(",quad,"+1)");
`else
wire [31:0] longout = narrow + 8'd1;
wire [63:0] quadout = quad + 64'd1;
`endif
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 11,
parameter P_FIFO_DEPTH_WIDTH = 2
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 2;
localparam LP_ADDR_TOTAL_WITDH = 10;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_shift.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_shift (clk, rst, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [4:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input /*31*/ [17:0] p_in; // parallel in
output [17:0] p_out; // parallel out
input s_clk; // serial clock
output s_out; // serial out
reg s_out;
reg tip;
reg [5:0] cnt; // data bit count
wire [17:0] data; // shift register
wire [5:0] tx_bit_pos; // next bit position
wire [5:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//assign p_out = data;
assign data = p_in;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{5{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{5{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{5{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {6{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{5{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {5{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[4:0]] : s_out;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_shift.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_shift (clk, rst, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [4:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input /*31*/ [17:0] p_in; // parallel in
output [17:0] p_out; // parallel out
input s_clk; // serial clock
output s_out; // serial out
reg s_out;
reg tip;
reg [5:0] cnt; // data bit count
wire [17:0] data; // shift register
wire [5:0] tx_bit_pos; // next bit position
wire [5:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//assign p_out = data;
assign data = p_in;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{5{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{5{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{5{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {6{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{5{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {5{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[4:0]] : s_out;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_shift.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_shift (clk, rst, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [4:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input /*31*/ [17:0] p_in; // parallel in
output [17:0] p_out; // parallel out
input s_clk; // serial clock
output s_out; // serial out
reg s_out;
reg tip;
reg [5:0] cnt; // data bit count
wire [17:0] data; // shift register
wire [5:0] tx_bit_pos; // next bit position
wire [5:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//assign p_out = data;
assign data = p_in;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{5{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{5{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{5{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {6{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{5{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {5{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[4:0]] : s_out;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output [6:0] hcmd_cid_rd_addr,
input [19:0] hcmd_cid_rd_data,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_cq_size,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
input [7:0] admin_sq_head_ptr,
input [7:0] io_sq1_head_ptr,
input [7:0] io_sq2_head_ptr,
input [7:0] io_sq3_head_ptr,
input [7:0] io_sq4_head_ptr,
input [7:0] io_sq5_head_ptr,
input [7:0] io_sq6_head_ptr,
input [7:0] io_sq7_head_ptr,
input [7:0] io_sq8_head_ptr,
output hcmd_slot_free_en,
output [6:0] hcmd_slot_invalid_tag,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] sq_valid,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_cq_rd_en;
wire [34:0] w_hcmd_cq_rd_data;
wire w_hcmd_cq_empty_n;
pcie_hcmd_cq_fifo
pcie_hcmd_cq_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (hcmd_cq_wr0_en),
.wr0_data0 (hcmd_cq_wr0_data0),
.wr0_data1 (hcmd_cq_wr0_data1),
.wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.full_n (),
.rd_en (w_hcmd_cq_rd_en),
.rd_data (w_hcmd_cq_rd_data),
.empty_n (w_hcmd_cq_empty_n),
.wr1_clk (cpu_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (hcmd_cq_wr1_en),
.wr1_data0 (hcmd_cq_wr1_data0),
.wr1_data1 (hcmd_cq_wr1_data1),
.wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
pcie_hcmd_cq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cq_rd_en (w_hcmd_cq_rd_en),
.hcmd_cq_rd_data (w_hcmd_cq_rd_data),
.hcmd_cq_empty_n (w_hcmd_cq_empty_n),
.hcmd_cid_rd_addr (hcmd_cid_rd_addr),
.hcmd_cid_rd_data (hcmd_cid_rd_data),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.admin_cq_size (admin_cq_size),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.admin_cq_bs_addr (admin_cq_bs_addr),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr),
.hcmd_slot_free_en (hcmd_slot_free_en),
.hcmd_slot_invalid_tag (hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_recv # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld_fifo_tag,
output [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
output cpld_fifo_wr_en,
output cpld_fifo_tag_last
);
localparam S_RX_IDLE_SOF = 4'b0001;
localparam S_RX_DATA = 4'b0010;
localparam S_RX_STRADDLED = 4'b0100;
localparam S_RX_STRADDLED_HOLD = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
wire [4:0] w_rx_is_sof;
wire [4:0] w_rx_is_eof;
reg [31:0] r_pcie_head0;
reg [31:0] r_pcie_head1;
reg [31:0] r_pcie_head2;
wire [2:0] w_mreq_head_fmt;
wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_atqtr0;
//wire [1:0] w_mreq_head_at;
//wire [9:0] w_mreq_head_len;
//wire [7:0] w_mreq_head_re_bus_num;
//wire [4:0] w_mreq_head_req_dev_num;
//wire [2:0] w_mreq_head_req_func_num;
//wire [15:0] w_mreq_head_req_id;
//wire [7:0] w_mreq_head_tag;
wire [2:0] w_cpld_head_fmt;
wire [4:0] w_cpld_head_type;
//wire [2:0] w_cpld_head_tc;
//wire w_cpld_head_attr1;
//wire w_cpld_head_th;
//wire w_cpld_head_td;
wire w_cpld_head_ep;
//wire [1:0] w_cpld_head_attr0;
//wire [1:0] w_cpld_head_at;
wire [9:0] w_cpld_head_len;
//wire [7:0] w_cpld_head_cpl_bus_num;
//wire [4:0] w_cpld_head_cpl_dev_num;
//wire [2:0] w_cpld_head_cpl_func_num;
//wire [15:0] w_cpld_head_cpl_id;
wire [2:0] w_cpld_head_cs;
//wire w_cpld_head_bcm;
wire [11:0] w_cpld_head_bc;
//wire [7:0] w_cpld_head_req_bus_num;
//wire [4:0] w_cpld_head_req_dev_num;
//wire [2:0] w_cpld_head_req_func_num;
//wire [15:0] w_cpld_head_req_id;
wire [7:0] w_cpld_head_tag;
//wire [6:0] w_cpld_head_la;
wire w_pcie_mreq_type;
wire w_pcie_cpld_type;
reg r_pcie_mreq_type;
reg r_pcie_cpld_type;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
reg [7:0] r_cpld_tag;
reg [11:2] r_cpld_len;
reg [11:2] r_cpld_bc;
reg r_cpld_lhead;
reg r_mem_req_en;
reg r_cpld_data_en;
reg r_cpld_tag_last;
reg r_rx_straddled;
reg r_rx_straddled_hold;
reg r_rx_data_straddled;
reg [127:0] r_s_axis_rx_tdata;
reg [127:0] r_s_axis_rx_tdata_d1;
reg r_mreq_fifo_wr_en;
reg [127:0] r_mreq_fifo_wr_data;
reg r_cpld_fifo_tag_en;
reg r_cpld_fifo_wr_en;
reg [127:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_tag_last;
assign s_axis_rx_tready = ~r_rx_straddled_hold;
assign pcie_mreq_err = r_pcie_mreq_err;
assign pcie_cpld_err = r_pcie_cpld_err;
assign pcie_cpld_len_err = r_pcie_cpld_len_err;
assign mreq_fifo_wr_en = r_mreq_fifo_wr_en;
assign mreq_fifo_wr_data = r_mreq_fifo_wr_data;
assign cpld_fifo_tag = r_cpld_tag;
assign cpld_fifo_wr_en = r_cpld_fifo_wr_en;
assign cpld_fifo_wr_data[31:0] = {r_cpld_fifo_wr_data[7:0], r_cpld_fifo_wr_data[15:8], r_cpld_fifo_wr_data[23:16], r_cpld_fifo_wr_data[31:24]};
assign cpld_fifo_wr_data[63:32] = {r_cpld_fifo_wr_data[39:32], r_cpld_fifo_wr_data[47:40], r_cpld_fifo_wr_data[55:48], r_cpld_fifo_wr_data[63:56]};
assign cpld_fifo_wr_data[95:64] = {r_cpld_fifo_wr_data[71:64], r_cpld_fifo_wr_data[79:72], r_cpld_fifo_wr_data[87:80], r_cpld_fifo_wr_data[95:88]};
assign cpld_fifo_wr_data[127:96] = {r_cpld_fifo_wr_data[103:96], r_cpld_fifo_wr_data[111:104], r_cpld_fifo_wr_data[119:112], r_cpld_fifo_wr_data[127:120]};
assign cpld_fifo_tag_last = r_cpld_fifo_tag_last;
assign w_rx_is_sof = s_axis_rx_tuser[14:10];
assign w_rx_is_eof = s_axis_rx_tuser[21:17];
always @ (*)
begin
if(w_rx_is_sof[3] == 1) begin
r_pcie_head0 <= s_axis_rx_tdata[95:64];
r_pcie_head1 <= s_axis_rx_tdata[127:96];
end
else begin
r_pcie_head0 <= s_axis_rx_tdata[31:0];
r_pcie_head1 <= s_axis_rx_tdata[63:32];
end
if(r_rx_straddled == 1)
r_pcie_head2 <= s_axis_rx_tdata[31:0];
else
r_pcie_head2 <= s_axis_rx_tdata[95:64];
end
//pcie mrd or mwr, memory rd/wr request
assign w_mreq_head_fmt = r_pcie_head0[31:29];
assign w_mreq_head_type = r_pcie_head0[28:24];
//assign w_mreq_head_tc = r_pcie_head0[22:20];
//assign w_mreq_head_attr1 = r_pcie_head0[18];
//assign w_mreq_head_th = r_pcie_head0[16];
//assign w_mreq_head_td = r_pcie_head0[15];
assign w_mreq_head_ep = r_pcie_head0[14];
//assign w_mreq_head_attr0 = r_pcie_head0[13:12];
//assign w_mreq_head_at = r_pcie_head0[11:10];
//assign w_mreq_head_len = r_pcie_head0[9:0];
//assign w_mreq_head_req_bus_num = r_pcie_head1[31:24];
//assign w_mreq_head_req_dev_num = r_pcie_head1[23:19];
//assign w_mreq_head_req_func_num = r_pcie_head1[18:16];
//assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
//assign w_mreq_head_tag = r_pcie_head1[15:8];
//pcie cpl or cpld
assign w_cpld_head_fmt = r_pcie_head0[31:29];
assign w_cpld_head_type = r_pcie_head0[28:24];
//assign w_cpld_head_tc = r_pcie_head0[22:20];
//assign w_cpld_head_attr1 = r_pcie_head0[18];
//assign w_cpld_head_th = r_pcie_head0[16];
//assign w_cpld_head_td = r_pcie_head0[15];
assign w_cpld_head_ep = r_pcie_head0[14];
//assign w_cpld_head_attr0 = r_pcie_head0[13:12];
//assign w_cpld_head_at = r_pcie_head0[11:10];
assign w_cpld_head_len = r_pcie_head0[9:0];
//assign w_cpld_head_cpl_bus_num = r_pcie_head1[31:24];
//assign w_cpld_head_cpl_dev_num = r_pcie_head1[23:19];
//assign w_cpld_head_cpl_func_num = r_pcie_head1[18:16];
//assign w_cpld_head_cpl_id = {w_cpld_head_cpl_bus_num, w_cpld_head_cpl_dev_num, w_cpld_head_cpl_func_num};
assign w_cpld_head_cs = r_pcie_head1[15:13];
//assign w_cpld_head_bcm = r_pcie_head1[12];
assign w_cpld_head_bc = r_pcie_head1[11:0];
//assign w_cpld_head_req_bus_num = r_pcie_head2[31:24];
//assign w_cpld_head_req_dev_num = r_pcie_head2[23:19];
//assign w_cpld_head_req_func_num = r_pcie_head2[18:16];
//assign w_cpld_head_req_id = {w_cpld_head_req_bus_num, w_cpld_head_req_dev_num, w_cpld_head_req_func_num};
assign w_cpld_head_tag = r_pcie_head2[15:8];
//assign w_cpld_head_la = r_pcie_head2[6:0];
assign w_pcie_mreq_type = ({w_mreq_head_fmt[2], w_mreq_head_type} == {1'b0, 5'b00000});
assign w_pcie_cpld_type = ({w_cpld_head_fmt, w_cpld_head_type} == {3'b010, 5'b01010});
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_IDLE_SOF;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1 && w_rx_is_eof[4] == 0 ) begin
if(w_rx_is_sof[3] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_DATA;
end
else
next_state <= S_RX_IDLE_SOF;
end
S_RX_DATA: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_DATA;
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else if(w_rx_is_eof[3] == 1)
next_state <= S_RX_STRADDLED_HOLD;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_STRADDLED;
end
S_RX_STRADDLED_HOLD: begin
next_state <= S_RX_IDLE_SOF;
end
default: begin
next_state <= S_RX_IDLE_SOF;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_type <= w_pcie_mreq_type & ~w_mreq_head_ep;
r_pcie_cpld_type <= w_pcie_cpld_type & ~w_cpld_head_ep & (w_cpld_head_cs == 0);
r_cpld_len <= w_cpld_head_len;
r_cpld_bc[11:2] <= w_cpld_head_bc[11:2];
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_mreq_err <= 0;
r_pcie_cpld_err <= 0;
r_pcie_cpld_len_err <= 0;
end
else begin
if(r_pcie_cpld_type == 1 && r_cpld_len < 2) begin
r_pcie_cpld_len_err <= 1;
end
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_err <= w_pcie_mreq_type & w_mreq_head_ep;
r_pcie_cpld_err <= w_pcie_cpld_type & (w_cpld_head_ep | (w_cpld_head_cs != 0));
end
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_cpld_tag <= w_cpld_head_tag;
r_cpld_lhead <= 0;
end
S_RX_DATA: begin
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1)
r_cpld_lhead <= ~w_rx_is_sof[4];
if(r_cpld_lhead == 0)
r_cpld_tag <= w_cpld_head_tag;
end
S_RX_STRADDLED_HOLD: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_mem_req_en <= (s_axis_rx_tvalid & w_rx_is_sof[4] & ~w_rx_is_sof[3]) & w_pcie_mreq_type;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_DATA: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4]);
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type & r_cpld_lhead;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4] & ~w_rx_is_eof[3]);
r_rx_straddled <= 1;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED_HOLD: begin
r_mem_req_en <= r_pcie_mreq_type;
r_cpld_data_en <= r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & r_pcie_cpld_type;
r_rx_straddled <= 1;
r_rx_straddled_hold <= 1;
end
default: begin
r_mem_req_en <= 0;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_mreq_fifo_wr_en <= r_mem_req_en;
r_cpld_fifo_wr_en <= r_cpld_data_en;
r_cpld_fifo_tag_last <= r_cpld_tag_last;
r_rx_data_straddled <= r_rx_straddled;
if(s_axis_rx_tvalid == 1 || r_rx_straddled_hold == 1) begin
r_s_axis_rx_tdata <= s_axis_rx_tdata;
r_s_axis_rx_tdata_d1 <= r_s_axis_rx_tdata;
end
end
always @ (*)
begin
if(r_rx_data_straddled == 1)
r_mreq_fifo_wr_data <= {r_s_axis_rx_tdata[63:0], r_s_axis_rx_tdata_d1[127:64]};
else
r_mreq_fifo_wr_data <= r_s_axis_rx_tdata;
if(r_rx_data_straddled == 1)
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[31:0], r_s_axis_rx_tdata_d1[127:32]};
else
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[95:0], r_s_axis_rx_tdata_d1[127:96]};
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module reg_cpu_pcie_sync # (
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input cpu_bus_clk,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
output pcie_link_up_sync,
output [5:0] pl_ltssm_state_sync,
output [15:0] cfg_command_sync,
output [2:0] cfg_interrupt_mmenable_sync,
output cfg_interrupt_msienable_sync,
output cfg_interrupt_msixenable_sync,
output pcie_mreq_err_sync,
output pcie_cpld_err_sync,
output pcie_cpld_len_err_sync,
output nvme_cc_en_sync,
output [1:0] nvme_cc_shn_sync,
input pcie_user_clk,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst_sync,
output nvme_csts_rdy_sync,
output [8:0] sq_rst_n_sync,
output [8:0] sq_valid_sync,
output [7:0] io_sq1_size_sync,
output [7:0] io_sq2_size_sync,
output [7:0] io_sq3_size_sync,
output [7:0] io_sq4_size_sync,
output [7:0] io_sq5_size_sync,
output [7:0] io_sq6_size_sync,
output [7:0] io_sq7_size_sync,
output [7:0] io_sq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr_sync,
output [3:0] io_sq1_cq_vec_sync,
output [3:0] io_sq2_cq_vec_sync,
output [3:0] io_sq3_cq_vec_sync,
output [3:0] io_sq4_cq_vec_sync,
output [3:0] io_sq5_cq_vec_sync,
output [3:0] io_sq6_cq_vec_sync,
output [3:0] io_sq7_cq_vec_sync,
output [3:0] io_sq8_cq_vec_sync,
output [8:0] cq_rst_n_sync,
output [8:0] cq_valid_sync,
output [7:0] io_cq1_size_sync,
output [7:0] io_cq2_size_sync,
output [7:0] io_cq3_size_sync,
output [7:0] io_cq4_size_sync,
output [7:0] io_cq5_size_sync,
output [7:0] io_cq6_size_sync,
output [7:0] io_cq7_size_sync,
output [7:0] io_cq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr_sync,
output [8:0] io_cq_irq_en_sync,
output [2:0] io_cq1_iv_sync,
output [2:0] io_cq2_iv_sync,
output [2:0] io_cq3_iv_sync,
output [2:0] io_cq4_iv_sync,
output [2:0] io_cq5_iv_sync,
output [2:0] io_cq6_iv_sync,
output [2:0] io_cq7_iv_sync,
output [2:0] io_cq8_iv_sync
);
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq1_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq2_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq3_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq4_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq5_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq6_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq7_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq8_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq1_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq2_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq3_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq4_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq5_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq6_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq7_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq8_iv;
assign pcie_link_up_sync = r_pcie_link_up_d1;
assign pl_ltssm_state_sync = r_pl_ltssm_state_d1;
assign cfg_command_sync = r_cfg_command_d1;
assign cfg_interrupt_mmenable_sync = r_cfg_interrupt_mmenable_d1;
assign cfg_interrupt_msienable_sync = r_cfg_interrupt_msienable_d1;
assign cfg_interrupt_msixenable_sync = r_cfg_interrupt_msixenable_d1;
assign pcie_mreq_err_sync = r_pcie_mreq_err_d1;
assign pcie_cpld_err_sync = r_pcie_cpld_err_d1;
assign pcie_cpld_len_err_sync = r_pcie_cpld_len_err_d1;
assign nvme_cc_en_sync = r_nvme_cc_en_d1;
assign nvme_cc_shn_sync = r_nvme_cc_shn_d1;
assign nvme_csts_shst_sync = r_nvme_csts_shst_d1;
assign nvme_csts_rdy_sync = r_nvme_csts_rdy_d1;
assign sq_rst_n_sync = r_sq_valid_d3;
assign sq_valid_sync = r_sq_valid_d1;
assign io_sq1_size_sync = r_io_sq1_size;
assign io_sq2_size_sync = r_io_sq2_size;
assign io_sq3_size_sync = r_io_sq3_size;
assign io_sq4_size_sync = r_io_sq4_size;
assign io_sq5_size_sync = r_io_sq5_size;
assign io_sq6_size_sync = r_io_sq6_size;
assign io_sq7_size_sync = r_io_sq7_size;
assign io_sq8_size_sync = r_io_sq8_size;
assign io_sq1_bs_addr_sync = r_io_sq1_bs_addr;
assign io_sq2_bs_addr_sync = r_io_sq2_bs_addr;
assign io_sq3_bs_addr_sync = r_io_sq3_bs_addr;
assign io_sq4_bs_addr_sync = r_io_sq4_bs_addr;
assign io_sq5_bs_addr_sync = r_io_sq5_bs_addr;
assign io_sq6_bs_addr_sync = r_io_sq6_bs_addr;
assign io_sq7_bs_addr_sync = r_io_sq7_bs_addr;
assign io_sq8_bs_addr_sync = r_io_sq8_bs_addr;
assign io_sq1_cq_vec_sync = r_io_sq1_cq_vec;
assign io_sq2_cq_vec_sync = r_io_sq2_cq_vec;
assign io_sq3_cq_vec_sync = r_io_sq3_cq_vec;
assign io_sq4_cq_vec_sync = r_io_sq4_cq_vec;
assign io_sq5_cq_vec_sync = r_io_sq5_cq_vec;
assign io_sq6_cq_vec_sync = r_io_sq6_cq_vec;
assign io_sq7_cq_vec_sync = r_io_sq7_cq_vec;
assign io_sq8_cq_vec_sync = r_io_sq8_cq_vec;
assign cq_rst_n_sync = r_cq_valid_d3;
assign cq_valid_sync = r_cq_valid_d1;
assign io_cq1_size_sync = r_io_cq1_size;
assign io_cq2_size_sync = r_io_cq2_size;
assign io_cq3_size_sync = r_io_cq3_size;
assign io_cq4_size_sync = r_io_cq4_size;
assign io_cq5_size_sync = r_io_cq5_size;
assign io_cq6_size_sync = r_io_cq6_size;
assign io_cq7_size_sync = r_io_cq7_size;
assign io_cq8_size_sync = r_io_cq8_size;
assign io_cq1_bs_addr_sync = r_io_cq1_bs_addr;
assign io_cq2_bs_addr_sync = r_io_cq2_bs_addr;
assign io_cq3_bs_addr_sync = r_io_cq3_bs_addr;
assign io_cq4_bs_addr_sync = r_io_cq4_bs_addr;
assign io_cq5_bs_addr_sync = r_io_cq5_bs_addr;
assign io_cq6_bs_addr_sync = r_io_cq6_bs_addr;
assign io_cq7_bs_addr_sync = r_io_cq7_bs_addr;
assign io_cq8_bs_addr_sync = r_io_cq8_bs_addr;
assign io_cq_irq_en_sync = r_io_cq_irq_en_d1;
assign io_cq1_iv_sync = r_io_cq1_iv;
assign io_cq2_iv_sync = r_io_cq2_iv;
assign io_cq3_iv_sync = r_io_cq3_iv;
assign io_cq4_iv_sync = r_io_cq4_iv;
assign io_cq5_iv_sync = r_io_cq5_iv;
assign io_cq6_iv_sync = r_io_cq6_iv;
assign io_cq7_iv_sync = r_io_cq7_iv;
assign io_cq8_iv_sync = r_io_cq8_iv;
always @ (posedge cpu_bus_clk)
begin
r_pcie_link_up <= pcie_link_up;
r_pcie_link_up_d1 <= r_pcie_link_up;
r_pl_ltssm_state <= pl_ltssm_state;
r_pl_ltssm_state_d1 <= r_pl_ltssm_state;
r_cfg_command <= cfg_command;
r_cfg_command_d1 <= r_cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_mmenable_d1 <= r_cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msienable_d1 <= r_cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_cfg_interrupt_msixenable_d1 <= r_cfg_interrupt_msixenable;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_mreq_err_d1 <= r_pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_err_d1 <= r_pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
r_pcie_cpld_len_err_d1 <= r_pcie_cpld_len_err;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_en_d1 <= r_nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_nvme_cc_shn_d1 <= r_nvme_cc_shn;
end
always @ (posedge pcie_user_clk)
begin
r_nvme_csts_shst <= nvme_csts_shst;
r_nvme_csts_shst_d1 <= r_nvme_csts_shst;
r_nvme_csts_rdy <= nvme_csts_rdy;
r_nvme_csts_rdy_d1 <= r_nvme_csts_rdy;
r_sq_valid <= sq_valid;
r_sq_valid_d1 <= r_sq_valid;
r_sq_valid_d2 <= r_sq_valid_d1;
r_sq_valid_d3 <= r_sq_valid_d2;
r_io_sq1_size <= io_sq1_size;
r_io_sq2_size <= io_sq2_size;
r_io_sq3_size <= io_sq3_size;
r_io_sq4_size <= io_sq4_size;
r_io_sq5_size <= io_sq5_size;
r_io_sq6_size <= io_sq6_size;
r_io_sq7_size <= io_sq7_size;
r_io_sq8_size <= io_sq8_size;
r_io_sq1_bs_addr <= io_sq1_bs_addr;
r_io_sq2_bs_addr <= io_sq2_bs_addr;
r_io_sq3_bs_addr <= io_sq3_bs_addr;
r_io_sq4_bs_addr <= io_sq4_bs_addr;
r_io_sq5_bs_addr <= io_sq5_bs_addr;
r_io_sq6_bs_addr <= io_sq6_bs_addr;
r_io_sq7_bs_addr <= io_sq7_bs_addr;
r_io_sq8_bs_addr <= io_sq8_bs_addr;
r_io_sq1_cq_vec <= io_sq1_cq_vec;
r_io_sq2_cq_vec <= io_sq2_cq_vec;
r_io_sq3_cq_vec <= io_sq3_cq_vec;
r_io_sq4_cq_vec <= io_sq4_cq_vec;
r_io_sq5_cq_vec <= io_sq5_cq_vec;
r_io_sq6_cq_vec <= io_sq6_cq_vec;
r_io_sq7_cq_vec <= io_sq7_cq_vec;
r_io_sq8_cq_vec <= io_sq8_cq_vec;
r_cq_valid <= cq_valid;
r_cq_valid_d1 <= r_cq_valid;
r_cq_valid_d2 <= r_cq_valid_d1;
r_cq_valid_d3 <= r_cq_valid_d2;
r_io_cq1_size <= io_cq1_size;
r_io_cq2_size <= io_cq2_size;
r_io_cq3_size <= io_cq3_size;
r_io_cq4_size <= io_cq4_size;
r_io_cq5_size <= io_cq5_size;
r_io_cq6_size <= io_cq6_size;
r_io_cq7_size <= io_cq7_size;
r_io_cq8_size <= io_cq8_size;
r_io_cq1_bs_addr <= io_cq1_bs_addr;
r_io_cq2_bs_addr <= io_cq2_bs_addr;
r_io_cq3_bs_addr <= io_cq3_bs_addr;
r_io_cq4_bs_addr <= io_cq4_bs_addr;
r_io_cq5_bs_addr <= io_cq5_bs_addr;
r_io_cq6_bs_addr <= io_cq6_bs_addr;
r_io_cq7_bs_addr <= io_cq7_bs_addr;
r_io_cq8_bs_addr <= io_cq8_bs_addr;
r_io_cq_irq_en <= io_cq_irq_en;
r_io_cq_irq_en_d1 <= r_io_cq_irq_en;
r_io_cq1_iv <= io_cq1_iv;
r_io_cq2_iv <= io_cq2_iv;
r_io_cq3_iv <= io_cq3_iv;
r_io_cq4_iv <= io_cq4_iv;
r_io_cq5_iv <= io_cq5_iv;
r_io_cq6_iv <= io_cq6_iv;
r_io_cq7_iv <= io_cq7_iv;
r_io_cq8_iv <= io_cq8_iv;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file golden_nonce_fifo.v when simulating
// the core, golden_nonce_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module golden_nonce_fifo(
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_2 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(7),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(125),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(124),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(7),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(7),
.C_WR_DEPTH(128),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Async clears must not race with clocks if we want repeatable results
reg set_l = in[20];
reg clr_l = in[21];
always @ (negedge clk) begin
set_l <= in[20];
clr_l <= in[21];
end
//====== Mux
wire [1:0] qm;
// delay z a b sel
udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]);
`define verilatorxx
`ifdef verilatorxx
reg [1:0] ql;
reg [1:0] qd;
// No sequential tables, yet
// always @* begin
// if (!clk) ql = in[13:12];
// end
always @(posedge clk or negedge set_l or negedge clr_l) begin
if (!set_l) qd <= ~2'b0;
else if (!clr_l) qd <= 2'b0;
else qd <= in[17:16];
end
`else
//====== Latch
// wire [1:0] ql;
// // q clk d
// udp_latch l0 (ql[0], !in[8], in[12]);
// udp_latch l1 (ql[1], !in[8], in[13]);
//====== DFF
wire [1:0] qd;
//always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
// q clk d set_l clr_l
udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l);
udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l);
`endif
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm};
// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
// Note not all simulators agree about the latch result. Maybe have a race?
`define EXPECTED_SUM 64'hb73acf228acaeaa3
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
primitive udp_mux2 (z, a, b, sel);
output z;
input a, b, sel;
table
//a b s o
? 1 1 : 1 ;
? 0 1 : 0 ;
1 ? 0 : 1 ;
0 ? 0 : 0 ;
1 1 x : 1 ;
0 0 x : 0 ;
endtable
endprimitive
primitive udp_latch (q, clk, d);
output q; reg q;
input clk, d;
table
//clk d q q'
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
primitive udp_dff (q, clk, d, set_l, clr_l);
output q;
input clk, d, set_l, clr_l;
reg q;
table
//ck d s c : q : q'
r 0 1 ? : ? : 0 ;
r 1 ? 1 : ? : 1 ;
* 1 ? 1 : 1 : 1 ;
* 0 1 ? : 0 : 0 ;
f ? ? ? : ? : - ;
b * ? ? : ? : - ;
? ? 0 ? : ? : 1 ;
b ? * 1 : 1 : 1 ;
x 1 * 1 : 1 : 1 ;
? ? 1 0 : ? : 0 ;
b ? 1 * : 0 : 0 ;
x 0 1 * : 0 : 0 ;
endtable
endprimitive
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_tag # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_tag_alloc,
input [7:0] pcie_alloc_tag,
input [6:4] pcie_tag_alloc_len,
output pcie_tag_full_n,
input [7:0] cpld_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input cpld_fifo_wr_en,
input cpld_fifo_tag_last,
output fifo_wr_en,
output [P_FIFO_DEPTH_WIDTH-1:0] fifo_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] fifo_wr_data,
output [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
output [P_FIFO_DEPTH_WIDTH:0] rear_addr
);
localparam LP_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_PCIE_TAG_WITDH = 3;
localparam LP_NUM_OF_PCIE_TAG = 2;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_rear;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_front;
reg [P_FIFO_DEPTH_WIDTH:0] r_alloc_base_addr;
reg [LP_PCIE_TAG_WITDH-1:0] r_pcie_tag [LP_NUM_OF_PCIE_TAG-1:0];
reg [P_FIFO_DEPTH_WIDTH:0] r_pcie_tag_addr [LP_NUM_OF_PCIE_TAG-1:0];
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_wr_en;
reg r_cpld_fifo_tag_last;
wire [LP_NUM_OF_PCIE_TAG-1:0] w_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_alloc_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_update_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_free_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_valid;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH-1:0] r_fifo_wr_addr;
assign pcie_tag_full_n = ~((r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] ^ r_pcie_tag_front[LP_NUM_OF_PCIE_TAG])
& (r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] == r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0]));
assign fifo_wr_en = r_cpld_fifo_wr_en;
assign fifo_wr_addr = r_fifo_wr_addr;
assign fifo_wr_data = r_cpld_fifo_wr_data;
assign rear_full_addr = r_alloc_base_addr;
assign rear_addr = r_rear_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_rear <= 1;
r_alloc_base_addr <= 0;
r_pcie_tag[0] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[1] <= {LP_PCIE_TAG_WITDH{1'b1}};
end
else begin
if(pcie_tag_alloc == 1) begin
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1]};
r_alloc_base_addr <= r_alloc_base_addr + pcie_tag_alloc_len;
if(r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG];
end
if(r_pcie_tag_alloc_mask[0])
r_pcie_tag[0] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[1])
r_pcie_tag[1] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
end
end
always @ (*)
begin
if(pcie_tag_alloc == 1)
r_pcie_tag_alloc_mask <= r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0];
else
r_pcie_tag_alloc_mask <= 0;
if(cpld_fifo_wr_en == 1)
r_pcie_tag_update_mask <= w_pcie_tag_hit;
else
r_pcie_tag_update_mask <= 0;
if(r_cpld_fifo_tag_last == 1)
r_pcie_tag_invalid_mask <= r_pcie_tag_hit;
else
r_pcie_tag_invalid_mask <= 0;
r_pcie_tag_free_mask <= r_pcie_tag_valid & r_pcie_tag_invalid & r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0];
end
always @ (posedge pcie_user_clk)
begin
case({r_pcie_tag_update_mask[0], r_pcie_tag_alloc_mask[0]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[0] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[0] <= r_pcie_tag_addr[0] + 1;
endcase
case({r_pcie_tag_update_mask[1], r_pcie_tag_alloc_mask[1]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[1] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[1] <= r_pcie_tag_addr[1] + 1;
endcase
end
assign w_pcie_tag_hit[0] = (r_pcie_tag[0] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[0];
assign w_pcie_tag_hit[1] = (r_pcie_tag[1] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[1];
always @ (posedge pcie_user_clk)
begin
r_cpld_fifo_tag_last <= cpld_fifo_tag_last;
r_cpld_fifo_wr_en <= cpld_fifo_wr_en;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
end
always @ (posedge pcie_user_clk)
begin
r_pcie_tag_hit <= w_pcie_tag_hit;
case(w_pcie_tag_hit) // synthesis parallel_case
2'b01: r_fifo_wr_addr <= r_pcie_tag_addr[0][P_FIFO_DEPTH_WIDTH-1:0];
2'b10: r_fifo_wr_addr <= r_pcie_tag_addr[1][P_FIFO_DEPTH_WIDTH-1:0];
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_front <= 1;
r_rear_addr <= 0;
r_pcie_tag_valid <= 0;
r_pcie_tag_invalid <= 0;
end
else begin
r_pcie_tag_valid <= (r_pcie_tag_valid | r_pcie_tag_alloc_mask) & ~r_pcie_tag_free_mask;
r_pcie_tag_invalid <= (r_pcie_tag_invalid | r_pcie_tag_invalid_mask) & ~r_pcie_tag_free_mask;
if(r_pcie_tag_free_mask != 0) begin
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1]};
if(r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_front[LP_NUM_OF_PCIE_TAG];
end
case(r_pcie_tag_free_mask) // synthesis parallel_case
2'b01: r_rear_addr <= r_pcie_tag_addr[0];
2'b10: r_rear_addr <= r_pcie_tag_addr[1];
endcase
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_tag # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_tag_alloc,
input [7:0] pcie_alloc_tag,
input [6:4] pcie_tag_alloc_len,
output pcie_tag_full_n,
input [7:0] cpld_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input cpld_fifo_wr_en,
input cpld_fifo_tag_last,
output fifo_wr_en,
output [P_FIFO_DEPTH_WIDTH-1:0] fifo_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] fifo_wr_data,
output [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
output [P_FIFO_DEPTH_WIDTH:0] rear_addr
);
localparam LP_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_PCIE_TAG_WITDH = 3;
localparam LP_NUM_OF_PCIE_TAG = 2;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_rear;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_front;
reg [P_FIFO_DEPTH_WIDTH:0] r_alloc_base_addr;
reg [LP_PCIE_TAG_WITDH-1:0] r_pcie_tag [LP_NUM_OF_PCIE_TAG-1:0];
reg [P_FIFO_DEPTH_WIDTH:0] r_pcie_tag_addr [LP_NUM_OF_PCIE_TAG-1:0];
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_wr_en;
reg r_cpld_fifo_tag_last;
wire [LP_NUM_OF_PCIE_TAG-1:0] w_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_alloc_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_update_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_free_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_valid;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH-1:0] r_fifo_wr_addr;
assign pcie_tag_full_n = ~((r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] ^ r_pcie_tag_front[LP_NUM_OF_PCIE_TAG])
& (r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] == r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0]));
assign fifo_wr_en = r_cpld_fifo_wr_en;
assign fifo_wr_addr = r_fifo_wr_addr;
assign fifo_wr_data = r_cpld_fifo_wr_data;
assign rear_full_addr = r_alloc_base_addr;
assign rear_addr = r_rear_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_rear <= 1;
r_alloc_base_addr <= 0;
r_pcie_tag[0] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[1] <= {LP_PCIE_TAG_WITDH{1'b1}};
end
else begin
if(pcie_tag_alloc == 1) begin
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1]};
r_alloc_base_addr <= r_alloc_base_addr + pcie_tag_alloc_len;
if(r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG];
end
if(r_pcie_tag_alloc_mask[0])
r_pcie_tag[0] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[1])
r_pcie_tag[1] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
end
end
always @ (*)
begin
if(pcie_tag_alloc == 1)
r_pcie_tag_alloc_mask <= r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0];
else
r_pcie_tag_alloc_mask <= 0;
if(cpld_fifo_wr_en == 1)
r_pcie_tag_update_mask <= w_pcie_tag_hit;
else
r_pcie_tag_update_mask <= 0;
if(r_cpld_fifo_tag_last == 1)
r_pcie_tag_invalid_mask <= r_pcie_tag_hit;
else
r_pcie_tag_invalid_mask <= 0;
r_pcie_tag_free_mask <= r_pcie_tag_valid & r_pcie_tag_invalid & r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0];
end
always @ (posedge pcie_user_clk)
begin
case({r_pcie_tag_update_mask[0], r_pcie_tag_alloc_mask[0]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[0] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[0] <= r_pcie_tag_addr[0] + 1;
endcase
case({r_pcie_tag_update_mask[1], r_pcie_tag_alloc_mask[1]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[1] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[1] <= r_pcie_tag_addr[1] + 1;
endcase
end
assign w_pcie_tag_hit[0] = (r_pcie_tag[0] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[0];
assign w_pcie_tag_hit[1] = (r_pcie_tag[1] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[1];
always @ (posedge pcie_user_clk)
begin
r_cpld_fifo_tag_last <= cpld_fifo_tag_last;
r_cpld_fifo_wr_en <= cpld_fifo_wr_en;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
end
always @ (posedge pcie_user_clk)
begin
r_pcie_tag_hit <= w_pcie_tag_hit;
case(w_pcie_tag_hit) // synthesis parallel_case
2'b01: r_fifo_wr_addr <= r_pcie_tag_addr[0][P_FIFO_DEPTH_WIDTH-1:0];
2'b10: r_fifo_wr_addr <= r_pcie_tag_addr[1][P_FIFO_DEPTH_WIDTH-1:0];
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_front <= 1;
r_rear_addr <= 0;
r_pcie_tag_valid <= 0;
r_pcie_tag_invalid <= 0;
end
else begin
r_pcie_tag_valid <= (r_pcie_tag_valid | r_pcie_tag_alloc_mask) & ~r_pcie_tag_free_mask;
r_pcie_tag_invalid <= (r_pcie_tag_invalid | r_pcie_tag_invalid_mask) & ~r_pcie_tag_free_mask;
if(r_pcie_tag_free_mask != 0) begin
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1]};
if(r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_front[LP_NUM_OF_PCIE_TAG];
end
case(r_pcie_tag_free_mask) // synthesis parallel_case
2'b01: r_rear_addr <= r_pcie_tag_addr[0];
2'b10: r_rear_addr <= r_pcie_tag_addr[1];
endcase
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_write # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_AWUSER_WIDTH = 1,
parameter C_M_AXI_WUSER_WIDTH = 1,
parameter C_M_AXI_BUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master write channel signal
input m_axi_aclk,
input m_axi_aresetn,
// Write address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [7:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [1:0] m_axi_awlock,
output [3:0] m_axi_awcache,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awregion,
output [3:0] m_axi_awqos,
output [C_M_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
// Write data channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_M_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
// Write response channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_bid,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [C_M_AXI_BUSER_WIDTH-1:0] m_axi_buser,
output m_axi_bready,
output m_axi_bresp_err,
output dev_rx_cmd_rd_en,
input [29:0] dev_rx_cmd_rd_data,
input dev_rx_cmd_empty_n,
output pcie_rx_fifo_rd_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n
);
localparam LP_AW_DELAY = 7;
localparam S_AW_IDLE = 11'b00000000001;
localparam S_AW_CMD_0 = 11'b00000000010;
localparam S_AW_CMD_1 = 11'b00000000100;
localparam S_AW_WAIT_EMPTY_N = 11'b00000001000;
localparam S_AW_REQ = 11'b00000010000;
localparam S_AW_WAIT = 11'b00000100000;
localparam S_AW_W_REQ = 11'b00001000000;
localparam S_AW_DONE = 11'b00010000000;
localparam S_AW_DELAY = 11'b00100000000;
localparam S_AW_DMA_DONE_WR_WAIT = 11'b01000000000;
localparam S_AW_DMA_DONE_WR = 11'b10000000000;
reg [10:0] cur_aw_state;
reg [10:0] next_aw_state;
localparam S_W_IDLE = 4'b0001;
localparam S_W_DATA = 4'b0010;
localparam S_W_READY_WAIT = 4'b0100;
localparam S_W_DATA_LAST = 4'b1000;
reg [4:0] cur_w_state;
reg [4:0] next_w_state;
reg r_dma_cmd_type;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [12:2] r_dev_dma_orig_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_wr_data_cnt;
reg [4:0] r_aw_delay;
reg [9:2] r_m_axi_awlen;
reg r_m_axi_awvalid;
reg [C_M_AXI_DATA_WIDTH-1:0] r_m_axi_wdata;
reg r_m_axi_wlast;
reg r_m_axi_wvalid;
reg r_m_axi_wdata_sel;
reg r_m_axi_bvalid;
//reg r_m_axi_bvalid_d1;
//wire w_m_axi_bvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_bid;
reg [1:0] r_m_axi_bresp;
reg r_m_axi_bresp_err;
reg r_m_axi_bresp_err_d1;
reg r_m_axi_bresp_err_d2;
reg [2:0] r_axi_aw_req_gnt;
reg r_axi_aw_req;
wire w_axi_aw_req_gnt;
reg r_axi_wr_req;
reg r_axi_wr_rdy;
reg r_dev_rx_cmd_rd_en;
reg r_pcie_rx_fifo_rd_en;
reg [C_M_AXI_DATA_WIDTH-1:0] r_pcie_rx_fifo_rd_data;
reg [C_M_AXI_DATA_WIDTH-1:0] r_pcie_rx_fifo_rd_data_d1;
reg r_pcie_rx_fifo_free_en;
reg r_dma_rx_done_wr_en;
wire [63:0] w_one_padding;
assign w_one_padding = 64'hFFFF_FFFF_FFFF_FFFF;
assign m_axi_awid = 0;
assign m_axi_awaddr = {r_dev_addr, 2'b0};
assign m_axi_awlen = {1'b0, r_m_axi_awlen[9:3]};
assign m_axi_awsize = `D_AXSIZE_008_BYTES;
assign m_axi_awburst = `D_AXBURST_INCR;
assign m_axi_awlock = `D_AXLOCK_NORMAL;
assign m_axi_awcache = `D_AXCACHE_NON_CACHE;
assign m_axi_awprot = `D_AXPROT_SECURE;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_awvalid = r_m_axi_awvalid;
assign m_axi_wid = 0;
assign m_axi_wdata = r_m_axi_wdata;
assign m_axi_wstrb = w_one_padding[(C_M_AXI_DATA_WIDTH/8)-1:0];
assign m_axi_wlast = r_m_axi_wlast;
assign m_axi_wuser = 0;
assign m_axi_wvalid = r_m_axi_wvalid;
assign m_axi_bready = 1;
assign m_axi_bresp_err = r_m_axi_bresp_err_d2;
assign dev_rx_cmd_rd_en = r_dev_rx_cmd_rd_en;
assign pcie_rx_fifo_rd_en = r_pcie_rx_fifo_rd_en;
assign pcie_rx_fifo_free_en = r_pcie_rx_fifo_free_en;
assign pcie_rx_fifo_free_len = r_dev_cur_len[9:4];
assign dma_rx_done_wr_en = r_dma_rx_done_wr_en;
assign dma_rx_done_wr_data = {r_dma_cmd_type, 1'b1, 1'b0, r_hcmd_slot_tag, r_dev_dma_orig_len};
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_aw_state <= S_AW_IDLE;
else
cur_aw_state <= next_aw_state;
end
always @ (*)
begin
case(cur_aw_state)
S_AW_IDLE: begin
if(dev_rx_cmd_empty_n == 1)
next_aw_state <= S_AW_CMD_0;
else
next_aw_state <= S_AW_IDLE;
end
S_AW_CMD_0: begin
next_aw_state <= S_AW_CMD_1;
end
S_AW_CMD_1: begin
next_aw_state <= S_AW_WAIT_EMPTY_N;
end
S_AW_WAIT_EMPTY_N: begin
if(pcie_rx_fifo_empty_n == 1 && w_axi_aw_req_gnt == 1)
next_aw_state <= S_AW_REQ;
else
next_aw_state <= S_AW_WAIT_EMPTY_N;
end
S_AW_REQ: begin
if(m_axi_awready == 1)
next_aw_state <= S_AW_W_REQ;
else
next_aw_state <= S_AW_WAIT;
end
S_AW_WAIT: begin
if(m_axi_awready == 1)
next_aw_state <= S_AW_W_REQ;
else
next_aw_state <= S_AW_WAIT;
end
S_AW_W_REQ: begin
if(r_axi_wr_rdy == 1)
next_aw_state <= S_AW_DONE;
else
next_aw_state <= S_AW_W_REQ;
end
S_AW_DONE: begin
if(r_dev_dma_len == 0)
next_aw_state <= S_AW_DMA_DONE_WR_WAIT;
else
next_aw_state <= S_AW_DELAY;
end
S_AW_DELAY: begin
if(r_aw_delay == 0)
next_aw_state <= S_AW_WAIT_EMPTY_N;
else
next_aw_state <= S_AW_DELAY;
end
S_AW_DMA_DONE_WR_WAIT: begin
if(dma_rx_done_wr_rdy_n == 1)
next_aw_state <= S_AW_DMA_DONE_WR_WAIT;
else
next_aw_state <= S_AW_DMA_DONE_WR;
end
S_AW_DMA_DONE_WR: begin
next_aw_state <= S_AW_IDLE;
end
default: begin
next_aw_state <= S_AW_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_aw_state)
S_AW_IDLE: begin
end
S_AW_CMD_0: begin
r_dma_cmd_type <= dev_rx_cmd_rd_data[19];
r_hcmd_slot_tag <= dev_rx_cmd_rd_data[17:11];
r_dev_dma_len <= {dev_rx_cmd_rd_data[10:2], 2'b0};
end
S_AW_CMD_1: begin
r_dev_dma_orig_len <= r_dev_dma_len;
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_rx_cmd_rd_data[29:2], 2'b0};
end
S_AW_WAIT_EMPTY_N: begin
r_m_axi_awlen <= r_dev_cur_len - 2;
end
S_AW_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AW_WAIT: begin
end
S_AW_W_REQ: begin
end
S_AW_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_aw_delay <= LP_AW_DELAY;
end
S_AW_DELAY: begin
r_aw_delay <= r_aw_delay - 1;
end
S_AW_DMA_DONE_WR_WAIT: begin
end
S_AW_DMA_DONE_WR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_aw_state)
S_AW_IDLE: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_CMD_0: begin
r_dev_rx_cmd_rd_en <= 1;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_CMD_1: begin
r_dev_rx_cmd_rd_en <= 1;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_WAIT_EMPTY_N: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_REQ: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 1;
r_axi_aw_req <= 1;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 1;
r_dma_rx_done_wr_en <= 0;
end
S_AW_WAIT: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 1;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_W_REQ: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 1;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DONE: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DELAY: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DMA_DONE_WR_WAIT: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DMA_DONE_WR: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 1;
end
default: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
endcase
end
assign w_axi_aw_req_gnt = r_axi_aw_req_gnt[2];
//assign w_m_axi_bvalid = r_m_axi_bvalid & ~r_m_axi_bvalid_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_bvalid <= m_axi_bvalid;
// r_m_axi_bvalid_d1 <= r_m_axi_bvalid;
r_m_axi_bid <= m_axi_bid;
r_m_axi_bresp <= m_axi_bresp;
r_m_axi_bresp_err_d1 <= r_m_axi_bresp_err;
r_m_axi_bresp_err_d2 <= r_m_axi_bresp_err | r_m_axi_bresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_bvalid == 1 && (r_m_axi_bresp != `D_AXI_RESP_OKAY || r_m_axi_bid != 0))
r_m_axi_bresp_err <= 1;
else
r_m_axi_bresp_err <= 0;
end
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_aw_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_bvalid, r_axi_aw_req})
2'b01: begin
r_axi_aw_req_gnt <= {r_axi_aw_req_gnt[1:0], r_axi_aw_req_gnt[2]};
end
2'b10: begin
r_axi_aw_req_gnt <= {r_axi_aw_req_gnt[0], r_axi_aw_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_w_state <= S_W_IDLE;
else
cur_w_state <= next_w_state;
end
always @ (*)
begin
case(cur_w_state)
S_W_IDLE: begin
if(r_axi_wr_req == 1) begin
if(r_m_axi_awlen == 0)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_IDLE;
end
S_W_DATA: begin
if(m_axi_wready == 1) begin
if(r_wr_data_cnt == 2)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_READY_WAIT;
end
S_W_READY_WAIT: begin
if(m_axi_wready == 1) begin
if(r_wr_data_cnt == 0)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_READY_WAIT;
end
S_W_DATA_LAST: begin
if(m_axi_wready == 1)
next_w_state <= S_W_IDLE;
else
next_w_state <= S_W_DATA_LAST;
end
default: begin
next_w_state <= S_W_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_w_state)
S_W_IDLE: begin
r_wr_data_cnt <= r_m_axi_awlen;
r_pcie_rx_fifo_rd_data <= pcie_rx_fifo_rd_data;
end
S_W_DATA: begin
r_wr_data_cnt <= r_wr_data_cnt - 2;
r_pcie_rx_fifo_rd_data <= pcie_rx_fifo_rd_data;
r_pcie_rx_fifo_rd_data_d1 <= r_pcie_rx_fifo_rd_data;
end
S_W_READY_WAIT: begin
end
S_W_DATA_LAST: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_m_axi_wdata_sel == 1)
r_m_axi_wdata <= r_pcie_rx_fifo_rd_data_d1;
else
r_m_axi_wdata <= r_pcie_rx_fifo_rd_data;
end
always @ (*)
begin
case(cur_w_state)
S_W_IDLE: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 0;
r_axi_wr_rdy <= 1;
r_pcie_rx_fifo_rd_en <= r_axi_wr_req;
end
S_W_DATA: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 1;
end
S_W_READY_WAIT: begin
r_m_axi_wdata_sel <= 1;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
S_W_DATA_LAST: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 1;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
default: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 0;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_write # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_AWUSER_WIDTH = 1,
parameter C_M_AXI_WUSER_WIDTH = 1,
parameter C_M_AXI_BUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master write channel signal
input m_axi_aclk,
input m_axi_aresetn,
// Write address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [7:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [1:0] m_axi_awlock,
output [3:0] m_axi_awcache,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awregion,
output [3:0] m_axi_awqos,
output [C_M_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
// Write data channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_M_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
// Write response channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_bid,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [C_M_AXI_BUSER_WIDTH-1:0] m_axi_buser,
output m_axi_bready,
output m_axi_bresp_err,
output dev_rx_cmd_rd_en,
input [29:0] dev_rx_cmd_rd_data,
input dev_rx_cmd_empty_n,
output pcie_rx_fifo_rd_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n
);
localparam LP_AW_DELAY = 7;
localparam S_AW_IDLE = 11'b00000000001;
localparam S_AW_CMD_0 = 11'b00000000010;
localparam S_AW_CMD_1 = 11'b00000000100;
localparam S_AW_WAIT_EMPTY_N = 11'b00000001000;
localparam S_AW_REQ = 11'b00000010000;
localparam S_AW_WAIT = 11'b00000100000;
localparam S_AW_W_REQ = 11'b00001000000;
localparam S_AW_DONE = 11'b00010000000;
localparam S_AW_DELAY = 11'b00100000000;
localparam S_AW_DMA_DONE_WR_WAIT = 11'b01000000000;
localparam S_AW_DMA_DONE_WR = 11'b10000000000;
reg [10:0] cur_aw_state;
reg [10:0] next_aw_state;
localparam S_W_IDLE = 4'b0001;
localparam S_W_DATA = 4'b0010;
localparam S_W_READY_WAIT = 4'b0100;
localparam S_W_DATA_LAST = 4'b1000;
reg [4:0] cur_w_state;
reg [4:0] next_w_state;
reg r_dma_cmd_type;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [12:2] r_dev_dma_orig_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_wr_data_cnt;
reg [4:0] r_aw_delay;
reg [9:2] r_m_axi_awlen;
reg r_m_axi_awvalid;
reg [C_M_AXI_DATA_WIDTH-1:0] r_m_axi_wdata;
reg r_m_axi_wlast;
reg r_m_axi_wvalid;
reg r_m_axi_wdata_sel;
reg r_m_axi_bvalid;
//reg r_m_axi_bvalid_d1;
//wire w_m_axi_bvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_bid;
reg [1:0] r_m_axi_bresp;
reg r_m_axi_bresp_err;
reg r_m_axi_bresp_err_d1;
reg r_m_axi_bresp_err_d2;
reg [2:0] r_axi_aw_req_gnt;
reg r_axi_aw_req;
wire w_axi_aw_req_gnt;
reg r_axi_wr_req;
reg r_axi_wr_rdy;
reg r_dev_rx_cmd_rd_en;
reg r_pcie_rx_fifo_rd_en;
reg [C_M_AXI_DATA_WIDTH-1:0] r_pcie_rx_fifo_rd_data;
reg [C_M_AXI_DATA_WIDTH-1:0] r_pcie_rx_fifo_rd_data_d1;
reg r_pcie_rx_fifo_free_en;
reg r_dma_rx_done_wr_en;
wire [63:0] w_one_padding;
assign w_one_padding = 64'hFFFF_FFFF_FFFF_FFFF;
assign m_axi_awid = 0;
assign m_axi_awaddr = {r_dev_addr, 2'b0};
assign m_axi_awlen = {1'b0, r_m_axi_awlen[9:3]};
assign m_axi_awsize = `D_AXSIZE_008_BYTES;
assign m_axi_awburst = `D_AXBURST_INCR;
assign m_axi_awlock = `D_AXLOCK_NORMAL;
assign m_axi_awcache = `D_AXCACHE_NON_CACHE;
assign m_axi_awprot = `D_AXPROT_SECURE;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_awvalid = r_m_axi_awvalid;
assign m_axi_wid = 0;
assign m_axi_wdata = r_m_axi_wdata;
assign m_axi_wstrb = w_one_padding[(C_M_AXI_DATA_WIDTH/8)-1:0];
assign m_axi_wlast = r_m_axi_wlast;
assign m_axi_wuser = 0;
assign m_axi_wvalid = r_m_axi_wvalid;
assign m_axi_bready = 1;
assign m_axi_bresp_err = r_m_axi_bresp_err_d2;
assign dev_rx_cmd_rd_en = r_dev_rx_cmd_rd_en;
assign pcie_rx_fifo_rd_en = r_pcie_rx_fifo_rd_en;
assign pcie_rx_fifo_free_en = r_pcie_rx_fifo_free_en;
assign pcie_rx_fifo_free_len = r_dev_cur_len[9:4];
assign dma_rx_done_wr_en = r_dma_rx_done_wr_en;
assign dma_rx_done_wr_data = {r_dma_cmd_type, 1'b1, 1'b0, r_hcmd_slot_tag, r_dev_dma_orig_len};
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_aw_state <= S_AW_IDLE;
else
cur_aw_state <= next_aw_state;
end
always @ (*)
begin
case(cur_aw_state)
S_AW_IDLE: begin
if(dev_rx_cmd_empty_n == 1)
next_aw_state <= S_AW_CMD_0;
else
next_aw_state <= S_AW_IDLE;
end
S_AW_CMD_0: begin
next_aw_state <= S_AW_CMD_1;
end
S_AW_CMD_1: begin
next_aw_state <= S_AW_WAIT_EMPTY_N;
end
S_AW_WAIT_EMPTY_N: begin
if(pcie_rx_fifo_empty_n == 1 && w_axi_aw_req_gnt == 1)
next_aw_state <= S_AW_REQ;
else
next_aw_state <= S_AW_WAIT_EMPTY_N;
end
S_AW_REQ: begin
if(m_axi_awready == 1)
next_aw_state <= S_AW_W_REQ;
else
next_aw_state <= S_AW_WAIT;
end
S_AW_WAIT: begin
if(m_axi_awready == 1)
next_aw_state <= S_AW_W_REQ;
else
next_aw_state <= S_AW_WAIT;
end
S_AW_W_REQ: begin
if(r_axi_wr_rdy == 1)
next_aw_state <= S_AW_DONE;
else
next_aw_state <= S_AW_W_REQ;
end
S_AW_DONE: begin
if(r_dev_dma_len == 0)
next_aw_state <= S_AW_DMA_DONE_WR_WAIT;
else
next_aw_state <= S_AW_DELAY;
end
S_AW_DELAY: begin
if(r_aw_delay == 0)
next_aw_state <= S_AW_WAIT_EMPTY_N;
else
next_aw_state <= S_AW_DELAY;
end
S_AW_DMA_DONE_WR_WAIT: begin
if(dma_rx_done_wr_rdy_n == 1)
next_aw_state <= S_AW_DMA_DONE_WR_WAIT;
else
next_aw_state <= S_AW_DMA_DONE_WR;
end
S_AW_DMA_DONE_WR: begin
next_aw_state <= S_AW_IDLE;
end
default: begin
next_aw_state <= S_AW_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_aw_state)
S_AW_IDLE: begin
end
S_AW_CMD_0: begin
r_dma_cmd_type <= dev_rx_cmd_rd_data[19];
r_hcmd_slot_tag <= dev_rx_cmd_rd_data[17:11];
r_dev_dma_len <= {dev_rx_cmd_rd_data[10:2], 2'b0};
end
S_AW_CMD_1: begin
r_dev_dma_orig_len <= r_dev_dma_len;
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_rx_cmd_rd_data[29:2], 2'b0};
end
S_AW_WAIT_EMPTY_N: begin
r_m_axi_awlen <= r_dev_cur_len - 2;
end
S_AW_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AW_WAIT: begin
end
S_AW_W_REQ: begin
end
S_AW_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_aw_delay <= LP_AW_DELAY;
end
S_AW_DELAY: begin
r_aw_delay <= r_aw_delay - 1;
end
S_AW_DMA_DONE_WR_WAIT: begin
end
S_AW_DMA_DONE_WR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_aw_state)
S_AW_IDLE: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_CMD_0: begin
r_dev_rx_cmd_rd_en <= 1;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_CMD_1: begin
r_dev_rx_cmd_rd_en <= 1;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_WAIT_EMPTY_N: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_REQ: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 1;
r_axi_aw_req <= 1;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 1;
r_dma_rx_done_wr_en <= 0;
end
S_AW_WAIT: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 1;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_W_REQ: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 1;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DONE: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DELAY: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DMA_DONE_WR_WAIT: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
S_AW_DMA_DONE_WR: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 1;
end
default: begin
r_dev_rx_cmd_rd_en <= 0;
r_m_axi_awvalid <= 0;
r_axi_aw_req <= 0;
r_axi_wr_req <= 0;
r_pcie_rx_fifo_free_en <= 0;
r_dma_rx_done_wr_en <= 0;
end
endcase
end
assign w_axi_aw_req_gnt = r_axi_aw_req_gnt[2];
//assign w_m_axi_bvalid = r_m_axi_bvalid & ~r_m_axi_bvalid_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_bvalid <= m_axi_bvalid;
// r_m_axi_bvalid_d1 <= r_m_axi_bvalid;
r_m_axi_bid <= m_axi_bid;
r_m_axi_bresp <= m_axi_bresp;
r_m_axi_bresp_err_d1 <= r_m_axi_bresp_err;
r_m_axi_bresp_err_d2 <= r_m_axi_bresp_err | r_m_axi_bresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_bvalid == 1 && (r_m_axi_bresp != `D_AXI_RESP_OKAY || r_m_axi_bid != 0))
r_m_axi_bresp_err <= 1;
else
r_m_axi_bresp_err <= 0;
end
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_aw_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_bvalid, r_axi_aw_req})
2'b01: begin
r_axi_aw_req_gnt <= {r_axi_aw_req_gnt[1:0], r_axi_aw_req_gnt[2]};
end
2'b10: begin
r_axi_aw_req_gnt <= {r_axi_aw_req_gnt[0], r_axi_aw_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_w_state <= S_W_IDLE;
else
cur_w_state <= next_w_state;
end
always @ (*)
begin
case(cur_w_state)
S_W_IDLE: begin
if(r_axi_wr_req == 1) begin
if(r_m_axi_awlen == 0)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_IDLE;
end
S_W_DATA: begin
if(m_axi_wready == 1) begin
if(r_wr_data_cnt == 2)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_READY_WAIT;
end
S_W_READY_WAIT: begin
if(m_axi_wready == 1) begin
if(r_wr_data_cnt == 0)
next_w_state <= S_W_DATA_LAST;
else
next_w_state <= S_W_DATA;
end
else
next_w_state <= S_W_READY_WAIT;
end
S_W_DATA_LAST: begin
if(m_axi_wready == 1)
next_w_state <= S_W_IDLE;
else
next_w_state <= S_W_DATA_LAST;
end
default: begin
next_w_state <= S_W_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_w_state)
S_W_IDLE: begin
r_wr_data_cnt <= r_m_axi_awlen;
r_pcie_rx_fifo_rd_data <= pcie_rx_fifo_rd_data;
end
S_W_DATA: begin
r_wr_data_cnt <= r_wr_data_cnt - 2;
r_pcie_rx_fifo_rd_data <= pcie_rx_fifo_rd_data;
r_pcie_rx_fifo_rd_data_d1 <= r_pcie_rx_fifo_rd_data;
end
S_W_READY_WAIT: begin
end
S_W_DATA_LAST: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_m_axi_wdata_sel == 1)
r_m_axi_wdata <= r_pcie_rx_fifo_rd_data_d1;
else
r_m_axi_wdata <= r_pcie_rx_fifo_rd_data;
end
always @ (*)
begin
case(cur_w_state)
S_W_IDLE: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 0;
r_axi_wr_rdy <= 1;
r_pcie_rx_fifo_rd_en <= r_axi_wr_req;
end
S_W_DATA: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 1;
end
S_W_READY_WAIT: begin
r_m_axi_wdata_sel <= 1;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
S_W_DATA_LAST: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 1;
r_m_axi_wvalid <= 1;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
default: begin
r_m_axi_wdata_sel <= 0;
r_m_axi_wlast <= 0;
r_m_axi_wvalid <= 0;
r_axi_wr_rdy <= 0;
r_pcie_rx_fifo_rd_en <= 0;
end
endcase
end
endmodule
|
module register_io
(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, decim_rate,
atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3,
txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
input clk;
input reset;
input wire [1:0] enable;
input wire [6:0] addr;
input wire [31:0] datain;
output reg [31:0] dataout;
output wire [15:0] debugbus;
output reg [6:0] addr_wr;
output reg [31:0] data_wr;
output wire strobe_wr;
input wire [31:0] rssi_0;
input wire [31:0] rssi_1;
input wire [31:0] rssi_2;
input wire [31:0] rssi_3;
output wire [31:0] threshhold;
output wire [31:0] rssi_wait;
input wire [15:0] reg_0;
input wire [15:0] reg_1;
input wire [15:0] reg_2;
input wire [15:0] reg_3;
input wire [11:0] atr_tx_delay;
input wire [11:0] atr_rx_delay;
input wire [7:0] master_controls;
input wire [3:0] debug_en;
input wire [15:0] atr_mask_0;
input wire [15:0] atr_txval_0;
input wire [15:0] atr_rxval_0;
input wire [15:0] atr_mask_1;
input wire [15:0] atr_txval_1;
input wire [15:0] atr_rxval_1;
input wire [15:0] atr_mask_2;
input wire [15:0] atr_txval_2;
input wire [15:0] atr_rxval_2;
input wire [15:0] atr_mask_3;
input wire [15:0] atr_txval_3;
input wire [15:0] atr_rxval_3;
input wire [7:0] txa_refclk;
input wire [7:0] txb_refclk;
input wire [7:0] rxa_refclk;
input wire [7:0] rxb_refclk;
input wire [7:0] interp_rate;
input wire [7:0] decim_rate;
input wire [7:0] misc;
input wire [31:0] txmux;
wire [31:0] bundle[43:0];
assign bundle[0] = 32'hFFFFFFFF;
assign bundle[1] = 32'hFFFFFFFF;
assign bundle[2] = {20'd0, atr_tx_delay};
assign bundle[3] = {20'd0, atr_rx_delay};
assign bundle[4] = {24'sd0, master_controls};
assign bundle[5] = 32'hFFFFFFFF;
assign bundle[6] = 32'hFFFFFFFF;
assign bundle[7] = 32'hFFFFFFFF;
assign bundle[8] = 32'hFFFFFFFF;
assign bundle[9] = {15'd0, reg_0};
assign bundle[10] = {15'd0, reg_1};
assign bundle[11] = {15'd0, reg_2};
assign bundle[12] = {15'd0, reg_3};
assign bundle[13] = {15'd0, misc};
assign bundle[14] = {28'd0, debug_en};
assign bundle[15] = 32'hFFFFFFFF;
assign bundle[16] = 32'hFFFFFFFF;
assign bundle[17] = 32'hFFFFFFFF;
assign bundle[18] = 32'hFFFFFFFF;
assign bundle[19] = 32'hFFFFFFFF;
assign bundle[20] = {16'd0, atr_mask_0};
assign bundle[21] = {16'd0, atr_txval_0};
assign bundle[22] = {16'd0, atr_rxval_0};
assign bundle[23] = {16'd0, atr_mask_1};
assign bundle[24] = {16'd0, atr_txval_1};
assign bundle[25] = {16'd0, atr_rxval_1};
assign bundle[26] = {16'd0, atr_mask_2};
assign bundle[27] = {16'd0, atr_txval_2};
assign bundle[28] = {16'd0, atr_rxval_2};
assign bundle[29] = {16'd0, atr_mask_3};
assign bundle[30] = {16'd0, atr_txval_3};
assign bundle[31] = {16'd0, atr_rxval_3};
assign bundle[32] = {24'd0, interp_rate};
assign bundle[33] = {24'd0, decim_rate};
assign bundle[34] = 32'hFFFFFFFF;
assign bundle[35] = 32'hFFFFFFFF;
assign bundle[36] = 32'hFFFFFFFF;
assign bundle[37] = 32'hFFFFFFFF;
assign bundle[38] = 32'hFFFFFFFF;
assign bundle[39] = txmux;
assign bundle[40] = {24'd0, txa_refclk};
assign bundle[41] = {24'd0, rxa_refclk};
assign bundle[42] = {24'd0, txb_refclk};
assign bundle[43] = {24'd0, rxb_refclk};
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
assign rssi_wait = out[2];
assign strobe_wr = strobe;
always @(*)
if (reset | ~enable[1])
begin
strobe <= 0;
dataout <= 0;
end
else
begin
if (enable[0])
begin
//read
if (addr <= 7'd43)
dataout <= bundle[addr];
else if (addr <= 7'd57 && addr >= 7'd50)
dataout <= out[addr-7'd50];
else
dataout <= 32'hFFFFFFFF;
strobe <= 0;
end
else
begin
//write
dataout <= dataout;
strobe <= 1;
data_wr <= datain;
addr_wr <= addr;
end
end
//register declarations
setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_recv # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output pcie_sq_cmd_fifo_rd_en,
input [10:0] pcie_sq_cmd_fifo_rd_data,
input pcie_sq_cmd_fifo_empty_n,
output pcie_sq_rx_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] pcie_sq_rx_fifo_rd_data,
output pcie_sq_rx_fifo_free_en,
output [6:4] pcie_sq_rx_fifo_free_len,
input pcie_sq_rx_fifo_empty_n,
output hcmd_table_wr_en,
output [8:0] hcmd_table_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] hcmd_table_wr_data,
output hcmd_cid_wr_en,
output [6:0] hcmd_cid_wr_addr,
output [19:0] hcmd_cid_wr_data,
output hcmd_prp_wr_en,
output [7:0] hcmd_prp_wr_addr,
output [44:0] hcmd_prp_wr_data,
output hcmd_nlb_wr0_en,
output [6:0] hcmd_nlb_wr0_addr,
output [18:0] hcmd_nlb_wr0_data,
input hcmd_nlb_wr0_rdy_n,
output hcmd_sq_wr_en,
output [18:0] hcmd_sq_wr_data,
input hcmd_sq_full_n,
input [8:0] sq_rst_n,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
output [7:0] admin_sq_head_ptr,
output [7:0] io_sq1_head_ptr,
output [7:0] io_sq2_head_ptr,
output [7:0] io_sq3_head_ptr,
output [7:0] io_sq4_head_ptr,
output [7:0] io_sq5_head_ptr,
output [7:0] io_sq6_head_ptr,
output [7:0] io_sq7_head_ptr,
output [7:0] io_sq8_head_ptr
);
localparam S_IDLE = 10'b0000000001;
localparam S_SQ_CMD = 10'b0000000010;
localparam S_CHECK_FIFO = 10'b0000000100;
localparam S_PCIE_HCMD_0 = 10'b0000001000;
localparam S_PCIE_HCMD_1 = 10'b0000010000;
localparam S_PCIE_HCMD_2 = 10'b0000100000;
localparam S_PCIE_HCMD_3 = 10'b0001000000;
localparam S_PCIE_NLB = 10'b0010000000;
localparam S_PCIE_NLB_WAIT = 10'b0100000000;
localparam S_PCIE_HCMD_DONE = 10'b1000000000;
reg [9:0] cur_state;
reg [9:0] next_state;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg [7:0] r_hcmd_num;
reg r_pcie_sq_cmd_fifo_rd_en;
reg r_pcie_sq_rx_fifo_rd_en;
reg [C_PCIE_DATA_WIDTH-1:0] r_pcie_sq_rx_fifo_rd_data;
reg r_pcie_sq_rx_fifo_free_en;
reg [63:2] r_hcmd_prp1;
reg [63:2] r_hcmd_prp2;
reg [8:0] r_hcmd_nlb;
reg [2:0] r_hcmd_slba;
reg r_hcmd_table_wr_en;
reg [1:0] r_hcmd_table_addr;
reg r_hcmd_cid_wr_en;
reg r_hcmd_prp_wr_en;
reg r_hcmd_prp_sel;
reg r_hcmd_sq_wr_en;
reg r_hcmd_nlb_wr0_en;
reg [8:0] r_sq_valid_entry;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
assign pcie_sq_cmd_fifo_rd_en = r_pcie_sq_cmd_fifo_rd_en;
assign pcie_sq_rx_fifo_rd_en = r_pcie_sq_rx_fifo_rd_en;
assign pcie_sq_rx_fifo_free_en = r_pcie_sq_rx_fifo_free_en;
assign pcie_sq_rx_fifo_free_len = 3'b100;
//assign hcmd_table_wr_en = cpld_fifo_wr_en;
assign hcmd_table_wr_en = r_hcmd_table_wr_en;
assign hcmd_table_wr_addr = {r_hcmd_slot_tag, r_hcmd_table_addr};
assign hcmd_table_wr_data = r_pcie_sq_rx_fifo_rd_data;
assign hcmd_sq_wr_en = r_hcmd_sq_wr_en;
assign hcmd_sq_wr_data = {r_hcmd_num, r_hcmd_slot_tag, r_sq_qid};
assign hcmd_cid_wr_en = r_hcmd_cid_wr_en;
assign hcmd_cid_wr_addr = r_hcmd_slot_tag;
assign hcmd_cid_wr_data = {r_sq_qid, r_pcie_sq_rx_fifo_rd_data[31:16]};
assign hcmd_nlb_wr0_en = r_hcmd_nlb_wr0_en;
assign hcmd_nlb_wr0_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr0_data = {r_hcmd_nlb, 10'b0};
assign hcmd_prp_wr_en = r_hcmd_prp_wr_en;
assign hcmd_prp_wr_addr = {r_hcmd_slot_tag, r_hcmd_prp_sel};
assign hcmd_prp_wr_data = (r_hcmd_prp_sel == 0) ? {8'b0, r_hcmd_slba, r_hcmd_prp1[C_PCIE_ADDR_WIDTH-1:2]}
: {3'b0, r_hcmd_nlb[7:0], r_hcmd_prp2[C_PCIE_ADDR_WIDTH-1:2]};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_sq_cmd_fifo_empty_n == 1)
next_state <= S_SQ_CMD;
else
next_state <= S_IDLE;
end
S_SQ_CMD: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_rx_fifo_empty_n == 1)
next_state <= S_PCIE_HCMD_0;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_HCMD_0: begin
next_state <= S_PCIE_HCMD_1;
end
S_PCIE_HCMD_1: begin
next_state <= S_PCIE_HCMD_2;
end
S_PCIE_HCMD_2: begin
next_state <= S_PCIE_HCMD_3;
end
S_PCIE_HCMD_3: begin
next_state <= S_PCIE_NLB;
end
S_PCIE_NLB: begin
next_state <= S_PCIE_NLB_WAIT;
end
S_PCIE_NLB_WAIT: begin
if(hcmd_nlb_wr0_rdy_n == 1 || hcmd_sq_full_n == 0)
next_state <= S_PCIE_NLB_WAIT;
else
next_state <= S_PCIE_HCMD_DONE;
end
S_PCIE_HCMD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_num <= 0;
end
else begin
case(cur_state)
S_IDLE: begin
end
S_SQ_CMD: begin
end
S_CHECK_FIFO: begin
end
S_PCIE_HCMD_0: begin
end
S_PCIE_HCMD_1: begin
end
S_PCIE_HCMD_2: begin
end
S_PCIE_HCMD_3: begin
end
S_PCIE_NLB: begin
end
S_PCIE_NLB_WAIT: begin
end
S_PCIE_HCMD_DONE: begin
r_hcmd_num <= r_hcmd_num + 1;
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_SQ_CMD: begin
r_sq_qid <= pcie_sq_cmd_fifo_rd_data[10:7];
r_hcmd_slot_tag <= pcie_sq_cmd_fifo_rd_data[6:0];
end
S_CHECK_FIFO: begin
end
S_PCIE_HCMD_0: begin
end
S_PCIE_HCMD_1: begin
r_hcmd_prp1[63:2] <= pcie_sq_rx_fifo_rd_data[127:66];
end
S_PCIE_HCMD_2: begin
r_hcmd_prp2[63:2] <= pcie_sq_rx_fifo_rd_data[63:2];
r_hcmd_slba <= pcie_sq_rx_fifo_rd_data[66:64];
end
S_PCIE_HCMD_3: begin
r_hcmd_nlb <= {1'b0, pcie_sq_rx_fifo_rd_data[7:0]};
end
S_PCIE_NLB: begin
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_PCIE_NLB_WAIT: begin
case(r_sq_qid) // synthesis parallel_case full_case
4'h0: r_sq_valid_entry <= 9'b000000001;
4'h1: r_sq_valid_entry <= 9'b000000010;
4'h2: r_sq_valid_entry <= 9'b000000100;
4'h3: r_sq_valid_entry <= 9'b000001000;
4'h4: r_sq_valid_entry <= 9'b000010000;
4'h5: r_sq_valid_entry <= 9'b000100000;
4'h6: r_sq_valid_entry <= 9'b001000000;
4'h7: r_sq_valid_entry <= 9'b010000000;
4'h8: r_sq_valid_entry <= 9'b100000000;
endcase
end
S_PCIE_HCMD_DONE: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_pcie_sq_rx_fifo_rd_data <= pcie_sq_rx_fifo_rd_data;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_SQ_CMD: begin
r_pcie_sq_cmd_fifo_rd_en <= 1;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_CHECK_FIFO: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_HCMD_0: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 1;
r_pcie_sq_rx_fifo_free_en <= 1;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_HCMD_1: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 1;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 1;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 1;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_HCMD_2: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 1;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 1;
r_hcmd_table_addr <= 2'b01;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_HCMD_3: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 1;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 1;
r_hcmd_table_addr <= 2'b10;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 1;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_NLB: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 1;
r_hcmd_table_addr <= 2'b11;
r_hcmd_cid_wr_en <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_prp_wr_en <= 1;
r_hcmd_prp_sel <= 1;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_NLB_WAIT: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
S_PCIE_HCMD_DONE: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 1;
r_hcmd_sq_wr_en <= 1;
r_sq_update_entry <= r_sq_valid_entry;
end
default: begin
r_pcie_sq_cmd_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_rd_en <= 0;
r_pcie_sq_rx_fifo_free_en <= 0;
r_hcmd_table_wr_en <= 0;
r_hcmd_table_addr <= 2'b00;
r_hcmd_cid_wr_en <= 0;
r_hcmd_prp_wr_en <= 0;
r_hcmd_prp_sel <= 0;
r_hcmd_nlb_wr0_en <= 0;
r_hcmd_sq_wr_en <= 0;
r_sq_update_entry <= 0;
end
endcase
end
assign admin_sq_head_ptr = r_admin_sq_head_ptr;
assign io_sq1_head_ptr = r_io_sq1_head_ptr;
assign io_sq2_head_ptr = r_io_sq2_head_ptr;
assign io_sq3_head_ptr = r_io_sq3_head_ptr;
assign io_sq4_head_ptr = r_io_sq4_head_ptr;
assign io_sq5_head_ptr = r_io_sq5_head_ptr;
assign io_sq6_head_ptr = r_io_sq6_head_ptr;
assign io_sq7_head_ptr = r_io_sq7_head_ptr;
assign io_sq8_head_ptr = r_io_sq8_head_ptr;
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_admin_sq_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_io_sq1_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_io_sq2_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_io_sq3_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_io_sq4_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_io_sq5_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_io_sq6_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_io_sq7_head_ptr + 1;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_io_sq8_head_ptr + 1;
end
end
end
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outc_w30, outd_w73,
// Inputs
clk, ina_w1, inb_w61
);
input clk;
input ina_w1;
input [60:0] inb_w61;
output [29:0] outc_w30;
output [72:0] outd_w73;
sub sub (
// Outputs
.outy_w92 (outc_w30), // .large => (small)
.outz_w22 (outd_w73), // .small => (large)
// Inputs
.clk (clk),
.inw_w31 (ina_w1), // .large <= (small)
.inx_w11 (inb_w61) // .small <= (large)
);
endmodule
module sub (/*AUTOARG*/
// Outputs
outy_w92, outz_w22,
// Inputs
clk, inw_w31, inx_w11
);
input clk;
input [30:0] inw_w31;
input [10:0] inx_w11;
output reg [91:0] outy_w92 /*verilator public*/;
output reg [21:0] outz_w22 /*verilator public*/;
always @(posedge clk) begin
outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
end
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outc_w30, outd_w73,
// Inputs
clk, ina_w1, inb_w61
);
input clk;
input ina_w1;
input [60:0] inb_w61;
output [29:0] outc_w30;
output [72:0] outd_w73;
sub sub (
// Outputs
.outy_w92 (outc_w30), // .large => (small)
.outz_w22 (outd_w73), // .small => (large)
// Inputs
.clk (clk),
.inw_w31 (ina_w1), // .large <= (small)
.inx_w11 (inb_w61) // .small <= (large)
);
endmodule
module sub (/*AUTOARG*/
// Outputs
outy_w92, outz_w22,
// Inputs
clk, inw_w31, inx_w11
);
input clk;
input [30:0] inw_w31;
input [10:0] inx_w11;
output reg [91:0] outy_w92 /*verilator public*/;
output reg [21:0] outz_w22 /*verilator public*/;
always @(posedge clk) begin
outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
end
endmodule // regfile
|
(** * Auto: More Automation *)
Require Export Imp.
(** Up to now, we've continued to use a quite restricted set of
Coq's tactic facilities. In this chapter, we'll learn more about
two very powerful features of Coq's tactic language:
proof search via the [auto] and [eauto] tactics, and
automated forward reasoning via the [Ltac] hypothesis matching
machinery. Using these features together with Ltac's scripting facilities
will enable us to make our proofs startlingly short! Used properly,
they can also make proofs more maintainable and robust in the face
of incremental changes to underlying definitions.
There's a third major source of automation we haven't
fully studied yet, namely built-in decision procedures for specific
kinds of problems: [omega] is one example, but there are others.
This topic will be defered for a while longer.
*)
(** Our motivating example will be this proof, repeated with
just a few small changes from [Imp]. We will try to simplify
this proof in several stages. *)
Ltac inv H := inversion H; subst; clear H.
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b evaluates to true".
apply IHE1. assumption.
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b evaluates to false".
reflexivity.
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(** * The [auto] and [eauto] tactics *)
(** Thus far, we have (nearly) always written proof scripts that
apply relevant hypothoses or lemmas by name. In particular, when
a chain of hypothesis applications is needed, we have specified
them explicitly. (The only exceptions introduced so far are using
[assumption] to find a matching unqualified hypothesis
or [(e)constructor] to find a matching constructor.) *)
Example auto_example_1 : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
apply H2. apply H1. assumption.
Qed.
(** The [auto] tactic frees us from this drudgery by _searching_
for a sequence of applications that will prove the goal *)
Example auto_example_1' : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
auto.
Qed.
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros],
- [apply] (with a local hypothesis, by default).
The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply]. *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing.
*)
(** A more complicated example: *)
Example auto_example_2 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** Search can take an arbitrarily long time, so there are limits to
how far [auto] will search by default *)
Example auto_example_3 : forall (P Q R S T U: Prop),
(P -> Q) -> (Q -> R) -> (R -> S) ->
(S -> T) -> (T -> U) -> P -> U.
Proof.
auto. (* When it cannot solve the goal, does nothing! *)
auto 6. (* Optional argument says how deep to search (default depth is 5) *)
Qed.
(** When searching for potential proofs of the current goal, [auto]
and [eauto] consider the hypotheses in the current context
together with a _hint database_ of other lemmas and constructors.
Some of the lemmas and constructors we've already seen -- e.g.,
[eq_refl], [conj], [or_introl], and [or_intror] -- are installed in this hint
database by default. *)
Example auto_example_4 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof.
auto. Qed.
(** If we want to see which facts [auto] is using, we can use [info_auto] instead. *)
Example auto_example_5: 2 = 2.
Proof.
info_auto. (* subsumes reflexivity because eq_refl is in hint database *)
Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] or [eauto] by writing [auto using ...]. *)
Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m.
Proof. intros. omega. Qed.
Example auto_example_6 : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* does nothing: auto doesn't destruct hypotheses! *)
auto using le_antisym.
Qed.
(** Of course, in any given development there will also be some of our
own specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand
uses of [d] and enable further possibilities for applying
lemmas that it knows about. *)
Hint Resolve le_antisym.
Example auto_example_6' : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* picks up hint from database *)
Qed.
Definition is_fortytwo x := x = 42.
Example auto_example_7: forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
auto. (* does nothing *)
Abort.
Hint Unfold is_fortytwo.
Example auto_example_7' : forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
info_auto.
Qed.
Hint Constructors ceval.
Definition st12 := update (update empty_state X 1) Y 2.
Definition st21 := update (update empty_state X 2) Y 1.
Example auto_example_8 : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st21 || s'.
Proof.
eexists. info_auto.
Qed.
Example auto_example_8' : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st12 || s'.
Proof.
eexists. info_auto.
Qed.
(** Now let's take a pass over [ceval_deterministic] using [auto]
to simplify the proof script. We see that all simple sequences of hypothesis
applications and all uses of [reflexivity] can be replaced by [auto],
which we add to the default tactic to be applied to each case.
*)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto.
Qed.
(** When we are using a particular tactic many times in a proof,
we can use a variant of the [Proof] command to make that tactic
into a default within the proof.
Saying [Proof with t] (where [t] is an arbitrary tactic)
allows us to use [t1...] as a shorthand for [t1;t] within the proof.
As an illustration, here is an alternate version of the previous proof,
using [Proof with auto].
*)
Theorem ceval_deterministic'_alt: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof with auto.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2...
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion"...
subst st'0...
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion"...
subst st'0...
Qed.
(** * Searching Hypotheses *)
(** The proof has become simpler, but there is still an annoying amount
of repetition. Let's start by tackling the contradiction cases. Each
of them occurs in a situation where we have both
[H1: beval st b = false]
and
[H2: beval st b = true]
as hypotheses. The contradiction is evident, but demonstrating it
is a little complicated: we have to locate the two hypotheses [H1] and [H2]
and do a [rewrite] following by an [inversion]. We'd like to automate
this process.
Note: In fact, Coq has a built-in tactic [congruence] that will do the
job. But we'll ignore the existence of this tactic for now, in order
to demonstrate how to build forward search tactics by hand.
*)
(** As a first step, we can abstract out the piece of script in question by
writing a small amount of paramerized Ltac. *)
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rwinv H H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rwinv H H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rwinv H H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rwinv H H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** But this is not much better. We really want Coq to discover
the relevant hypotheses for us. We can do this by using the
[match goal with ... end] facility of Ltac. *)
Ltac find_rwinv :=
match goal with
H1: ?E = true, H2: ?E = false |- _ => rwinv H1 H2
end.
(** In words, this [match goal] looks for two (distinct) hypotheses that have
the form of equalities with the same arbitrary expression [E] on the
left and conflicting boolean values on the right; if such hypotheses are
found, it binds [H1] and [H2] to their names, and applies the tactic
after the [=>].
Adding this tactic to our default string handles all the contradiction cases. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** Finally, let's see about the remaining cases. Each of them involves
applying a conditional hypothesis to extract an equality. Currently
we have phrased these as assertions, so that we have to predict what
the resulting equality will be (although we can then use [auto]
to prove it.) An alternative is to pick the relevant
hypotheses to use, and then rewrite with them, as follows:
*)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
rewrite (IHE1_1 st'0 H1) in *. auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
rewrite (IHE1_1 st'0 H3) in *. auto. Qed.
(** Now we can automate the task of finding the relevant hypotheses to
rewrite with. *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R, H2: ?P ?X |- _ =>
rewrite (H1 X H2) in *
end.
(** But there are several pairs of hypotheses that have the right
general form, and it seems tricky to pick out the ones we actually need.
A key trick is to realize that we can _try them all_!
Here's how this works:
- [rewrite] will fail given a trivial equation of the form [X = X].
- each execution of [match goal] will keep trying to find a valid pair of
hypotheses until the tactic on the RHS of the match succeeds;
if there are no such pairs, it fails.
- we can wrap the whole thing in a [repeat] which will keep
doing useful rewrites until only trivial ones are left.
*)
Theorem ceval_deterministic''''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Qed.
(** The big pay-off in this approach is that our proof script
should be robust in the face of modest changes to our language.
For example, we can add a [REPEAT] command to the language.
(This was an exercise in [Hoare.v].) *)
Module Repeat.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (CRepeat c1 b1) st'
| E_RepeatLoop : forall st st' st'' b1 c1,
ceval st c1 st' ->
beval st' b1 = false ->
ceval st' (CRepeat c1 b1) st'' ->
ceval st (CRepeat c1 b1) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Case "E_RepeatEnd".
SCase "b evaluates to false (contradiction)".
find_rwinv.
(* oops: why didn't [find_rwinv] solve this for us already?
answer: we did things in the wrong order. *)
case "E_RepeatLoop".
SCase "b evaluates to true (contradiction)".
find_rwinv.
Qed.
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto.
Qed.
End Repeat.
(** These examples just give a flavor of what "hyper-automation" can do...
The details of using [match goal] are tricky, and debugging is
not pleasant at all. But it is well worth adding at least simple
uses to your proofs to avoid tedium and "future proof" your scripts.
*)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off MULTIDRIVEN
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [15:0] out2; // From test of Test.v
// End of automatics
// verilator lint_on MULTIDRIVEN
Test test (
.en (crc[21:20]),
.a1 (crc[19:18]),
.a0 (crc[17:16]),
.d1 (crc[15:8]),
.d0 (crc[7:0]),
/*AUTOINST*/
// Outputs
.out (out[31:0]),
.out2 (out2[15:0]),
// Inputs
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {out2, 16'h0, out};
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
test.clear();
end
else if (cyc<10) begin
sum <= 64'h0;
test.clear();
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, en, a0, a1, d0, d1
);
input clk;
input [1:0] en;
input [1:0] a0;
input [1:0] a1;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN
task clear();
for (int i=0; i<4; ++i) mem[i] = 0;
endtask
always @(posedge clk) begin
if (en[0]) begin
mem[a0] <= d0;
out2[7:0] <= d0;
end
end
always @(negedge clk) begin
if (en[1]) begin
mem[a1] <= d1;
out2[15:8] <= d0;
end
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off MULTIDRIVEN
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [15:0] out2; // From test of Test.v
// End of automatics
// verilator lint_on MULTIDRIVEN
Test test (
.en (crc[21:20]),
.a1 (crc[19:18]),
.a0 (crc[17:16]),
.d1 (crc[15:8]),
.d0 (crc[7:0]),
/*AUTOINST*/
// Outputs
.out (out[31:0]),
.out2 (out2[15:0]),
// Inputs
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {out2, 16'h0, out};
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
test.clear();
end
else if (cyc<10) begin
sum <= 64'h0;
test.clear();
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, en, a0, a1, d0, d1
);
input clk;
input [1:0] en;
input [1:0] a0;
input [1:0] a1;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN
task clear();
for (int i=0; i<4; ++i) mem[i] = 0;
endtask
always @(posedge clk) begin
if (en[0]) begin
mem[a0] <= d0;
out2[7:0] <= d0;
end
end
always @(negedge clk) begin
if (en[1]) begin
mem[a1] <= d1;
out2[15:8] <= d0;
end
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max interp rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_int_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases
8'd4 : bitgain = 6;
8'd8 : bitgain = 9;
8'd16 : bitgain = 12;
8'd32 : bitgain = 15;
8'd64 : bitgain = 18;
8'd128 : bitgain = 21;
// Nearest without overflow
8'd5 : bitgain = 7;
8'd6 : bitgain = 8;
8'd7 : bitgain = 9;
8'd9,8'd10 : bitgain = 10;
8'd11,8'd12 : bitgain = 11;
8'd13,8'd14,8'd15 : bitgain = 12;
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
default : bitgain = 19;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd6 : signal_out = signal_in[6+bw-1:6];
5'd9 : signal_out = signal_in[9+bw-1:9];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
default : signal_out = signal_in[21+bw-1:21];
endcase // case(shift)
endmodule // cic_int_shifter
|
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN =1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] adctime;
always @(posedge rxclk)
if (reset)
adctime <= 0;
else if (rxstrobe)
adctime <= adctime + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il;
reg [15:0] fifodata_16;
wire WR;
wire have_space;
assign fifodata_il = fifodata_16;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
wire [7:0] debug;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.adctime ( adctime ),
.channels ( 4'd1 ), //need to be tested and changed to channels
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// TODO write this genericly
//wire [15:0]ch[NUM_CHAN:0];
//assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Switching of channels
reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
else if(rxstrobe & (store_next == 0))
store_next <= #1 4'd1;
else if(~rx_full & (store_next == 4'd2))
store_next <= #1 4'd0;
else if(~rx_full & (store_next != 0))
store_next <= #1 store_next + 4'd1;
always @*
case(store_next)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
default: fifodata_16 = 16'hFFFF;
endcase
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & (store_next != 0)),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]};
endmodule
|
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN =1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] adctime;
always @(posedge rxclk)
if (reset)
adctime <= 0;
else if (rxstrobe)
adctime <= adctime + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il;
reg [15:0] fifodata_16;
wire WR;
wire have_space;
assign fifodata_il = fifodata_16;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
wire [7:0] debug;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.adctime ( adctime ),
.channels ( 4'd1 ), //need to be tested and changed to channels
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// TODO write this genericly
//wire [15:0]ch[NUM_CHAN:0];
//assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Switching of channels
reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
else if(rxstrobe & (store_next == 0))
store_next <= #1 4'd1;
else if(~rx_full & (store_next == 4'd2))
store_next <= #1 4'd0;
else if(~rx_full & (store_next != 0))
store_next <= #1 store_next + 4'd1;
always @*
case(store_next)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
default: fifodata_16 = 16'hFFFF;
endcase
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & (store_next != 0)),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]};
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
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