text
stringlengths 938
1.05M
|
|---|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_read # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
input m_axi_aclk,
input m_axi_aresetn,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_rresp_err,
output dev_tx_cmd_rd_en,
input [29:0] dev_tx_cmd_rd_data,
input dev_tx_cmd_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n
);
localparam LP_AR_DELAY = 7;
localparam S_IDLE = 8'b00000001;
localparam S_CMD_0 = 8'b00000010;
localparam S_CMD_1 = 8'b00000100;
localparam S_WAIT_FULL_N = 8'b00001000;
localparam S_AR_REQ = 8'b00010000;
localparam S_AR_WAIT = 8'b00100000;
localparam S_AR_DONE = 8'b01000000;
localparam S_AR_DELAY = 8'b10000000;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_m_axi_arlen;
reg [4:0] r_ar_delay;
reg r_dev_tx_cmd_rd_en;
reg r_pcie_tx_fifo_alloc_en;
wire w_axi_ar_req_gnt;
reg [2:0] r_axi_ar_req_gnt;
reg r_axi_ar_req;
reg r_m_axi_arvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] r_m_axi_rdata;
reg r_m_axi_rlast;
//reg r_m_axi_rlast_d1;
//wire w_m_axi_rlast;
reg r_m_axi_rvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_rid;
reg [1:0] r_m_axi_rresp;
reg r_m_axi_rresp_err;
reg r_m_axi_rresp_err_d1;
reg r_m_axi_rresp_err_d2;
assign m_axi_arid = 0;
assign m_axi_araddr = {r_dev_addr, 2'b0};
assign m_axi_arlen = {1'b0, r_m_axi_arlen[9:3]};
assign m_axi_arsize = `D_AXSIZE_008_BYTES;
assign m_axi_arburst = `D_AXBURST_INCR;
assign m_axi_arlock = `D_AXLOCK_NORMAL;
assign m_axi_arcache = `D_AXCACHE_NON_CACHE;
assign m_axi_arprot = `D_AXPROT_SECURE;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
assign m_axi_arvalid = r_m_axi_arvalid;
assign m_axi_rready = 1;
assign m_axi_rresp_err = r_m_axi_rresp_err_d2;
assign dev_tx_cmd_rd_en = r_dev_tx_cmd_rd_en;
assign pcie_tx_fifo_alloc_en = r_pcie_tx_fifo_alloc_en;
assign pcie_tx_fifo_alloc_len = r_dev_cur_len[9:4];
assign pcie_tx_fifo_wr_en = r_m_axi_rvalid;
assign pcie_tx_fifo_wr_data = r_m_axi_rdata;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dev_tx_cmd_empty_n == 1)
next_state <= S_CMD_0;
else
next_state <= S_IDLE;
end
S_CMD_0: begin
next_state <= S_CMD_1;
end
S_CMD_1: begin
next_state <= S_WAIT_FULL_N;
end
S_WAIT_FULL_N: begin
if(pcie_tx_fifo_full_n == 1 && w_axi_ar_req_gnt == 1)
next_state <= S_AR_REQ;
else
next_state <= S_WAIT_FULL_N;
end
S_AR_REQ: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_WAIT: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_DONE: begin
if(r_dev_dma_len == 0)
next_state <= S_IDLE;
else
next_state <= S_AR_DELAY;
end
S_AR_DELAY: begin
if(r_ar_delay == 0)
next_state <= S_WAIT_FULL_N;
else
next_state <= S_AR_DELAY;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_0: begin
r_dev_dma_len <= {dev_tx_cmd_rd_data[10:2], 2'b0};
end
S_CMD_1: begin
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_tx_cmd_rd_data[29:2], 2'b0};
end
S_WAIT_FULL_N: begin
r_m_axi_arlen <= r_dev_cur_len - 2;
end
S_AR_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AR_WAIT: begin
end
S_AR_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_ar_delay <= LP_AR_DELAY;
end
S_AR_DELAY: begin
r_ar_delay <= r_ar_delay - 1;
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_0: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_1: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_WAIT_FULL_N: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_REQ: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 1;
r_axi_ar_req <= 1;
end
S_AR_WAIT: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DONE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DELAY: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
default: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
endcase
end
//assign w_m_axi_rlast = r_m_axi_rlast & ~r_m_axi_rlast_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_rid <= m_axi_rid;
r_m_axi_rdata <= m_axi_rdata;
r_m_axi_rlast <= m_axi_rlast & m_axi_rvalid;
//r_m_axi_rlast_d1 <= r_m_axi_rlast;
r_m_axi_rvalid <= m_axi_rvalid;
r_m_axi_rresp <= m_axi_rresp;
r_m_axi_rresp_err_d1 <= r_m_axi_rresp_err;
r_m_axi_rresp_err_d2 <= r_m_axi_rresp_err | r_m_axi_rresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_rvalid == 1 && (r_m_axi_rresp != `D_AXI_RESP_OKAY || r_m_axi_rid != 0))
r_m_axi_rresp_err <= 1;
else
r_m_axi_rresp_err <= 0;
end
assign w_axi_ar_req_gnt = r_axi_ar_req_gnt[2];
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_ar_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_rlast, r_axi_ar_req})
2'b01: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[1:0], r_axi_ar_req_gnt[2]};
end
2'b10: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[0], r_axi_ar_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq_handler # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
input cfg_interrupt_msienable,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update,
output pcie_legacy_irq_set,
output pcie_msi_irq_set,
output [2:0] pcie_irq_vector,
output pcie_legacy_irq_clear,
input pcie_irq_done
);
localparam LP_LEGACY_IRQ_DELAY_TIME = 8'h10;
localparam S_IDLE = 6'b000001;
localparam S_PCIE_MSI_IRQ_SET = 6'b000010;
localparam S_LEGACY_IRQ_SET = 6'b000100;
localparam S_LEGACY_IRQ_TIMER = 6'b001000;
localparam S_CQ_MSI_IRQ_MASK = 6'b010000;
localparam S_CQ_IRQ_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_pcie_irq_en;
reg r_pcie_msi_en;
wire [8:0] w_cq_legacy_irq_status;
reg r_cq_legacy_irq_req;
wire [8:0] w_cq_msi_irq_status;
wire [8:0] w_cq_msi_irq_mask;
reg [8:0] r_cq_msi_irq_sel;
wire w_cq_msi_irq_req;
reg [8:0] r_cq_msi_irq_ack;
reg r_pcie_msi_irq_set;
reg [2:0] r_pcie_irq_vector;
reg r_pcie_legacy_irq_set;
reg [7:0] r_legacy_irq_timer;
assign w_cq_msi_irq_mask = {r_cq_msi_irq_sel[7:0], r_cq_msi_irq_sel[8]};
assign w_cq_msi_irq_req = ((w_cq_msi_irq_status & w_cq_msi_irq_mask) != 0);
assign pcie_legacy_irq_set = r_pcie_legacy_irq_set;
assign pcie_msi_irq_set = r_pcie_msi_irq_set;
assign pcie_irq_vector = r_pcie_irq_vector;
assign pcie_legacy_irq_clear = ((nvme_intms_ivms | nvme_intmc_ivmc) | (~r_cq_legacy_irq_req | ~r_pcie_irq_en) | r_pcie_msi_en);
assign cq_irq_status = r_pcie_legacy_irq_set;
always @ (posedge pcie_user_clk)
begin
r_pcie_irq_en <= ~cfg_command[10];
r_pcie_msi_en <= cfg_interrupt_msienable;
r_cq_legacy_irq_req <= (w_cq_legacy_irq_status != 0);
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_pcie_msi_en == 1) begin
if((w_cq_msi_irq_req | w_cq_msi_irq_status[0]) == 1)
next_state <= S_PCIE_MSI_IRQ_SET;
else
next_state <= S_IDLE;
end
else if(r_pcie_irq_en == 1)begin
if(r_cq_legacy_irq_req == 1)
next_state <= S_LEGACY_IRQ_SET;
else
next_state <= S_IDLE;
end
else
next_state <= S_IDLE;
end
S_PCIE_MSI_IRQ_SET: begin
if(pcie_irq_done == 1)
next_state <= S_CQ_MSI_IRQ_MASK;
else
next_state <= S_PCIE_MSI_IRQ_SET;
end
S_LEGACY_IRQ_SET: begin
if(pcie_irq_done == 1)
next_state <= S_LEGACY_IRQ_TIMER;
else
next_state <= S_LEGACY_IRQ_SET;
end
S_LEGACY_IRQ_TIMER: begin
if(r_legacy_irq_timer == 0)
next_state <= S_CQ_IRQ_DONE;
else
next_state <= S_LEGACY_IRQ_TIMER;
end
S_CQ_MSI_IRQ_MASK: begin
next_state <= S_CQ_IRQ_DONE;
end
S_CQ_IRQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_MSI_IRQ_SET: begin
end
S_LEGACY_IRQ_SET: begin
r_legacy_irq_timer <= LP_LEGACY_IRQ_DELAY_TIME;
end
S_LEGACY_IRQ_TIMER: begin
r_legacy_irq_timer <= r_legacy_irq_timer - 1;
end
S_CQ_MSI_IRQ_MASK: begin
end
S_CQ_IRQ_DONE: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_cq_msi_irq_sel <= 1;
end
else begin
case(cur_state)
S_IDLE: begin
if(w_cq_msi_irq_status[0] == 1)
r_cq_msi_irq_sel <= 1;
else
r_cq_msi_irq_sel <= w_cq_msi_irq_mask;
end
S_PCIE_MSI_IRQ_SET: begin
end
S_LEGACY_IRQ_SET: begin
end
S_LEGACY_IRQ_TIMER: begin
end
S_CQ_MSI_IRQ_MASK: begin
end
S_CQ_IRQ_DONE: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(r_cq_msi_irq_sel) // synthesis parallel_case full_case
9'b000000001: r_pcie_irq_vector <= 0;
9'b000000010: r_pcie_irq_vector <= io_cq1_iv;
9'b000000100: r_pcie_irq_vector <= io_cq2_iv;
9'b000001000: r_pcie_irq_vector <= io_cq3_iv;
9'b000010000: r_pcie_irq_vector <= io_cq4_iv;
9'b000100000: r_pcie_irq_vector <= io_cq5_iv;
9'b001000000: r_pcie_irq_vector <= io_cq6_iv;
9'b010000000: r_pcie_irq_vector <= io_cq7_iv;
9'b100000000: r_pcie_irq_vector <= io_cq8_iv;
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_PCIE_MSI_IRQ_SET: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 1;
r_cq_msi_irq_ack <= 0;
end
S_LEGACY_IRQ_SET: begin
r_pcie_legacy_irq_set <= 1;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_LEGACY_IRQ_TIMER: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_CQ_MSI_IRQ_MASK: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= r_cq_msi_irq_sel;
end
S_CQ_IRQ_DONE: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
default: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
endcase
end
nvme_cq_check
nvme_cq_check_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[0]),
.cq_valid (cq_valid[0]),
.io_cq_irq_en (io_cq_irq_en[0]),
.cq_tail_ptr (admin_cq_tail_ptr),
.cq_head_ptr (admin_cq_head_ptr),
.cq_head_update (cq_head_update[0]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[0]),
.cq_msi_irq_req (w_cq_msi_irq_status[0]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[0])
);
nvme_cq_check
nvme_cq_check_inst1
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[1]),
.cq_valid (cq_valid[1]),
.io_cq_irq_en (io_cq_irq_en[1]),
.cq_tail_ptr (io_cq1_tail_ptr),
.cq_head_ptr (io_cq1_head_ptr),
.cq_head_update (cq_head_update[1]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[1]),
.cq_msi_irq_req (w_cq_msi_irq_status[1]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[1])
);
nvme_cq_check
nvme_cq_check_inst2
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[2]),
.cq_valid (cq_valid[2]),
.io_cq_irq_en (io_cq_irq_en[2]),
.cq_tail_ptr (io_cq2_tail_ptr),
.cq_head_ptr (io_cq2_head_ptr),
.cq_head_update (cq_head_update[2]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[2]),
.cq_msi_irq_req (w_cq_msi_irq_status[2]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[2])
);
nvme_cq_check
nvme_cq_check_inst3
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[3]),
.cq_valid (cq_valid[3]),
.io_cq_irq_en (io_cq_irq_en[3]),
.cq_tail_ptr (io_cq3_tail_ptr),
.cq_head_ptr (io_cq3_head_ptr),
.cq_head_update (cq_head_update[3]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[3]),
.cq_msi_irq_req (w_cq_msi_irq_status[3]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[3])
);
nvme_cq_check
nvme_cq_check_inst4
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[4]),
.cq_valid (cq_valid[4]),
.io_cq_irq_en (io_cq_irq_en[4]),
.cq_tail_ptr (io_cq4_tail_ptr),
.cq_head_ptr (io_cq4_head_ptr),
.cq_head_update (cq_head_update[4]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[4]),
.cq_msi_irq_req (w_cq_msi_irq_status[4]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[4])
);
nvme_cq_check
nvme_cq_check_inst5
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[5]),
.cq_valid (cq_valid[5]),
.io_cq_irq_en (io_cq_irq_en[5]),
.cq_tail_ptr (io_cq5_tail_ptr),
.cq_head_ptr (io_cq5_head_ptr),
.cq_head_update (cq_head_update[5]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[5]),
.cq_msi_irq_req (w_cq_msi_irq_status[5]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[5])
);
nvme_cq_check
nvme_cq_check_inst6
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[6]),
.cq_valid (cq_valid[6]),
.io_cq_irq_en (io_cq_irq_en[6]),
.cq_tail_ptr (io_cq6_tail_ptr),
.cq_head_ptr (io_cq6_head_ptr),
.cq_head_update (cq_head_update[6]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[6]),
.cq_msi_irq_req (w_cq_msi_irq_status[6]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[6])
);
nvme_cq_check
nvme_cq_check_inst7
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[7]),
.cq_valid (cq_valid[7]),
.io_cq_irq_en (io_cq_irq_en[7]),
.cq_tail_ptr (io_cq7_tail_ptr),
.cq_head_ptr (io_cq7_head_ptr),
.cq_head_update (cq_head_update[7]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[7]),
.cq_msi_irq_req (w_cq_msi_irq_status[7]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[7])
);
nvme_cq_check
nvme_cq_check_inst8
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[8]),
.cq_valid (cq_valid[8]),
.io_cq_irq_en (io_cq_irq_en[8]),
.cq_tail_ptr (io_cq8_tail_ptr),
.cq_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update[8]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[8]),
.cq_msi_irq_req (w_cq_msi_irq_status[8]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[8])
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module s_axi_reg # (
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_BASEADDR = 32'h80000000,
parameter C_S_AXI_HIGHADDR = 32'h80010000,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s_axi_aclk,
input s_axi_aresetn,
//Write address channel
input s_axi_awvalid,
output s_axi_awready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
//Write data channel
input s_axi_wvalid,
output s_axi_wready,
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
//Write response channel
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
//Read address channel
input s_axi_arvalid,
output s_axi_arready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [2:0] s_axi_arprot,
//Read data channel
output s_axi_rvalid,
input s_axi_rready,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input m0_axi_bresp_err,
input m0_axi_rresp_err,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
localparam S_WR_IDLE = 8'b00000001;
localparam S_AW_VAILD = 8'b00000010;
localparam S_W_READY = 8'b00000100;
localparam S_B_VALID = 8'b00001000;
localparam S_WAIT_CQ_RDY = 8'b00010000;
localparam S_WR_CQ = 8'b00100000;
localparam S_WAIT_DMA_RDY = 8'b01000000;
localparam S_WR_DMA = 8'b10000000;
reg [7:0] cur_wr_state;
reg [7:0] next_wr_state;
localparam S_RD_IDLE = 5'b00001;
localparam S_AR_VAILD = 5'b00010;
localparam S_AR_REG = 5'b00100;
localparam S_BRAM_READ = 5'b01000;
localparam S_R_READY = 5'b10000;
reg [4:0] cur_rd_state;
reg [4:0] next_rd_state;
reg r_s_axi_awready;
reg [15:2] r_s_axi_awaddr;
reg r_s_axi_wready;
reg r_s_axi_bvalid;
reg [1:0] r_s_axi_bresp;
reg r_s_axi_arready;
reg [15:2] r_s_axi_araddr;
reg r_s_axi_rvalid;
reg [C_S_AXI_DATA_WIDTH-1:0] r_s_axi_rdata;
reg [1:0] r_s_axi_rresp;
reg r_irq_assert;
reg [11:0] r_irq_req;
reg [11:0] r_irq_mask;
reg [11:0] r_irq_clear;
reg [11:0] r_irq_set;
reg r_pcie_user_logic_rst;
reg [1:0] r_nvme_csts_shst;
reg r_nvme_csts_rdy;
reg [8:0] r_sq_valid;
reg [7:0] r_io_sq1_size;
reg [7:0] r_io_sq2_size;
reg [7:0] r_io_sq3_size;
reg [7:0] r_io_sq4_size;
reg [7:0] r_io_sq5_size;
reg [7:0] r_io_sq6_size;
reg [7:0] r_io_sq7_size;
reg [7:0] r_io_sq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
reg [3:0] r_io_sq1_cq_vec;
reg [3:0] r_io_sq2_cq_vec;
reg [3:0] r_io_sq3_cq_vec;
reg [3:0] r_io_sq4_cq_vec;
reg [3:0] r_io_sq5_cq_vec;
reg [3:0] r_io_sq6_cq_vec;
reg [3:0] r_io_sq7_cq_vec;
reg [3:0] r_io_sq8_cq_vec;
reg [8:0] r_cq_valid;
reg [7:0] r_io_cq1_size;
reg [7:0] r_io_cq2_size;
reg [7:0] r_io_cq3_size;
reg [7:0] r_io_cq4_size;
reg [7:0] r_io_cq5_size;
reg [7:0] r_io_cq6_size;
reg [7:0] r_io_cq7_size;
reg [7:0] r_io_cq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
reg [8:0] r_io_cq_irq_en;
reg [2:0] r_io_cq1_iv;
reg [2:0] r_io_cq2_iv;
reg [2:0] r_io_cq3_iv;
reg [2:0] r_io_cq4_iv;
reg [2:0] r_io_cq5_iv;
reg [2:0] r_io_cq6_iv;
reg [2:0] r_io_cq7_iv;
reg [2:0] r_io_cq8_iv;
reg [1:0] r_cql_type;
reg [3:0] r_cpl_sq_qid;
reg [15:0] r_cpl_cid;
reg [6:0] r_hcmd_slot_tag;
reg [14:0] r_cpl_status;
reg [31:0] r_cpl_specific;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_dma_cmd_hcmd_slot_tag;
reg [31:2] r_dma_cmd_dev_addr;
reg [12:2] r_dma_cmd_dev_len;
reg [8:0] r_dma_cmd_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_dma_cmd_pcie_addr;
reg r_hcmd_cq_wr1_en;
reg r_dma_cmd_wr_en;
reg r_hcmd_sq_rd_en;
reg [31:0] r_wdata;
reg r_awaddr_cntl_reg_en;
//reg r_awaddr_pcie_reg_en;
reg r_awaddr_nvme_reg_en;
reg r_awaddr_nvme_fifo_en;
reg r_awaddr_hcmd_cq_wr1_en;
reg r_awaddr_dma_cmd_wr_en;
reg r_cntl_reg_en;
//reg r_pcie_reg_en;
reg r_nvme_reg_en;
reg r_nvme_fifo_en;
reg [31:0] r_rdata;
reg r_araddr_cntl_reg_en;
reg r_araddr_pcie_reg_en;
reg r_araddr_nvme_reg_en;
reg r_araddr_nvme_fifo_en;
reg r_araddr_hcmd_table_rd_en;
reg r_araddr_hcmd_sq_rd_en;
reg [31:0] r_cntl_reg_rdata;
reg [31:0] r_pcie_reg_rdata;
reg [31:0] r_nvme_reg_rdata;
reg [31:0] r_nvme_fifo_rdata;
reg r_pcie_link_up;
reg [15:0] r_cfg_command;
reg [2:0] r_cfg_interrupt_mmenable;
reg r_cfg_interrupt_msienable;
reg r_cfg_interrupt_msixenable;
reg r_nvme_cc_en;
reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d2;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
assign s_axi_awready = r_s_axi_awready;
assign s_axi_wready = r_s_axi_wready;
assign s_axi_bvalid = r_s_axi_bvalid;
assign s_axi_bresp = r_s_axi_bresp;
assign s_axi_arready = r_s_axi_arready;
assign s_axi_rvalid = r_s_axi_rvalid;
assign s_axi_rdata = r_s_axi_rdata;
assign s_axi_rresp = r_s_axi_rresp;
assign dev_irq_assert = r_irq_assert;
assign sq_valid = r_sq_valid;
assign io_sq1_size = r_io_sq1_size;
assign io_sq2_size = r_io_sq2_size;
assign io_sq3_size = r_io_sq3_size;
assign io_sq4_size = r_io_sq4_size;
assign io_sq5_size = r_io_sq5_size;
assign io_sq6_size = r_io_sq6_size;
assign io_sq7_size = r_io_sq7_size;
assign io_sq8_size = r_io_sq8_size;
assign io_sq1_bs_addr = r_io_sq1_bs_addr;
assign io_sq2_bs_addr = r_io_sq2_bs_addr;
assign io_sq3_bs_addr = r_io_sq3_bs_addr;
assign io_sq4_bs_addr = r_io_sq4_bs_addr;
assign io_sq5_bs_addr = r_io_sq5_bs_addr;
assign io_sq6_bs_addr = r_io_sq6_bs_addr;
assign io_sq7_bs_addr = r_io_sq7_bs_addr;
assign io_sq8_bs_addr = r_io_sq8_bs_addr;
assign io_sq1_cq_vec = r_io_sq1_cq_vec;
assign io_sq2_cq_vec = r_io_sq2_cq_vec;
assign io_sq3_cq_vec = r_io_sq3_cq_vec;
assign io_sq4_cq_vec = r_io_sq4_cq_vec;
assign io_sq5_cq_vec = r_io_sq5_cq_vec;
assign io_sq6_cq_vec = r_io_sq6_cq_vec;
assign io_sq7_cq_vec = r_io_sq7_cq_vec;
assign io_sq8_cq_vec = r_io_sq8_cq_vec;
assign cq_valid = r_cq_valid;
assign io_cq1_size = r_io_cq1_size;
assign io_cq2_size = r_io_cq2_size;
assign io_cq3_size = r_io_cq3_size;
assign io_cq4_size = r_io_cq4_size;
assign io_cq5_size = r_io_cq5_size;
assign io_cq6_size = r_io_cq6_size;
assign io_cq7_size = r_io_cq7_size;
assign io_cq8_size = r_io_cq8_size;
assign io_cq1_bs_addr = r_io_cq1_bs_addr;
assign io_cq2_bs_addr = r_io_cq2_bs_addr;
assign io_cq3_bs_addr = r_io_cq3_bs_addr;
assign io_cq4_bs_addr = r_io_cq4_bs_addr;
assign io_cq5_bs_addr = r_io_cq5_bs_addr;
assign io_cq6_bs_addr = r_io_cq6_bs_addr;
assign io_cq7_bs_addr = r_io_cq7_bs_addr;
assign io_cq8_bs_addr = r_io_cq8_bs_addr;
assign io_cq_irq_en = r_io_cq_irq_en;
assign io_cq1_iv = r_io_cq1_iv;
assign io_cq2_iv = r_io_cq2_iv;
assign io_cq3_iv = r_io_cq3_iv;
assign io_cq4_iv = r_io_cq4_iv;
assign io_cq5_iv = r_io_cq5_iv;
assign io_cq6_iv = r_io_cq6_iv;
assign io_cq7_iv = r_io_cq7_iv;
assign io_cq8_iv = r_io_cq8_iv;
assign pcie_user_logic_rst = r_pcie_user_logic_rst;
assign nvme_csts_shst = r_nvme_csts_shst;
assign nvme_csts_rdy = r_nvme_csts_rdy;
assign hcmd_table_rd_addr = r_s_axi_araddr[12:2];
assign hcmd_sq_rd_en = r_hcmd_sq_rd_en;
assign hcmd_cq_wr1_en = r_hcmd_cq_wr1_en;
assign hcmd_cq_wr1_data0 = ((r_cql_type[1] | r_cql_type[0]) == 1) ? {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid[15:7], r_hcmd_slot_tag, r_cql_type}
: {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid, r_cql_type};
assign hcmd_cq_wr1_data1 = {1'b0, r_cpl_specific[31:0], r_cpl_status[14:13]};
assign dma_cmd_wr_en = r_dma_cmd_wr_en;
assign dma_cmd_wr_data0 = {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_dev_len, r_dma_cmd_dev_addr};
assign dma_cmd_wr_data1 = {7'b0, r_dma_cmd_4k_offset, r_dma_cmd_pcie_addr};
always @ (posedge s_axi_aclk)
begin
r_pcie_link_up <= pcie_link_up;
r_cfg_command <= cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_m0_axi_bresp_err <= m0_axi_bresp_err;
r_m0_axi_bresp_err_d1 <= r_m0_axi_bresp_err;
r_m0_axi_bresp_err_d2 <= r_m0_axi_bresp_err_d1;
r_m0_axi_rresp_err <= m0_axi_rresp_err;
r_m0_axi_rresp_err_d1 <= r_m0_axi_rresp_err;
r_m0_axi_rresp_err_d2 <= r_m0_axi_rresp_err_d1;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
end
always @ (posedge s_axi_aclk)
begin
r_irq_req[0] <= (pcie_link_up ^ r_pcie_link_up);
r_irq_req[1] <= (cfg_command[2] ^ r_cfg_command[2]);
r_irq_req[2] <= (cfg_command[10] ^ r_cfg_command[10]);
r_irq_req[3] <= (cfg_interrupt_msienable ^ r_cfg_interrupt_msienable);
r_irq_req[4] <= (cfg_interrupt_msixenable ^ r_cfg_interrupt_msixenable);
r_irq_req[5] <= (nvme_cc_en ^ r_nvme_cc_en);
r_irq_req[6] <= (nvme_cc_shn != r_nvme_cc_shn);
r_irq_req[7] <= (r_m0_axi_bresp_err_d1 ^ r_m0_axi_bresp_err_d2);
r_irq_req[8] <= (r_m0_axi_rresp_err_d1 ^ r_m0_axi_rresp_err_d2);
r_irq_req[9] <= (pcie_mreq_err ^ r_pcie_mreq_err);
r_irq_req[10] <= (pcie_cpld_err ^ r_pcie_cpld_err);
r_irq_req[11] <= (pcie_cpld_len_err ^ r_pcie_cpld_len_err);
r_irq_assert <= (r_irq_set != 0);
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_wr_state <= S_WR_IDLE;
else
cur_wr_state <= next_wr_state;
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
if(s_axi_awvalid == 1)
next_wr_state <= S_AW_VAILD;
else
next_wr_state <= S_WR_IDLE;
end
S_AW_VAILD: begin
next_wr_state <= S_W_READY;
end
S_W_READY: begin
if(s_axi_wvalid == 1)
next_wr_state <= S_B_VALID;
else
next_wr_state <= S_W_READY;
end
S_B_VALID: begin
if(s_axi_bready == 1) begin
if(r_awaddr_hcmd_cq_wr1_en == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else if(r_awaddr_dma_cmd_wr_en == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_IDLE;
end
else
next_wr_state <= S_B_VALID;
end
S_WAIT_CQ_RDY: begin
if(hcmd_cq_wr1_rdy_n == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else
next_wr_state <= S_WR_CQ;
end
S_WR_CQ: begin
next_wr_state <= S_WR_IDLE;
end
S_WAIT_DMA_RDY: begin
if(dma_cmd_wr_rdy_n == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_DMA;
end
S_WR_DMA: begin
next_wr_state <= S_WR_IDLE;
end
default: begin
next_wr_state <= S_WR_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awaddr[15:2] <= s_axi_awaddr[15:2];
end
S_AW_VAILD: begin
r_awaddr_cntl_reg_en <= (r_s_axi_awaddr[15:8] == 8'h0);
// r_awaddr_pcie_reg_en <= (r_s_axi_awaddr[15:8] == 8'h1);
r_awaddr_nvme_reg_en <= (r_s_axi_awaddr[15:8] == 8'h2);
r_awaddr_nvme_fifo_en <= (r_s_axi_awaddr[15:8] == 8'h3);
r_awaddr_hcmd_cq_wr1_en <= (r_s_axi_awaddr[15:2] == 14'hC3);
r_awaddr_dma_cmd_wr_en <= (r_s_axi_awaddr[15:2] == 14'hC7);
end
S_W_READY: begin
r_wdata <= s_axi_wdata;
end
S_B_VALID: begin
end
S_WAIT_CQ_RDY: begin
end
S_WR_CQ: begin
end
S_WAIT_DMA_RDY: begin
end
S_WR_DMA: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_AW_VAILD: begin
r_s_axi_awready <= 1;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_W_READY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 1;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_B_VALID: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 1;
r_s_axi_bresp <= `D_AXI_RESP_OKAY;
r_cntl_reg_en <= r_awaddr_cntl_reg_en;
// r_pcie_reg_en <= r_awaddr_pcie_reg_en;
r_nvme_reg_en <= r_awaddr_nvme_reg_en;
r_nvme_fifo_en <= r_awaddr_nvme_fifo_en;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_CQ_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_CQ: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 1;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_DMA_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_DMA: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 1;
end
default: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
endcase
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_mask <= 0;
end
else begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: r_irq_mask <= r_wdata[11:0];
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_pcie_user_logic_rst <= r_wdata[0];
r_irq_clear <= 0;
end
6'h02: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= r_wdata[11:0];
end
default: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
endcase
end
else begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_set <= 0;
end
else begin
r_irq_set <= (r_irq_set | r_irq_req) & (~r_irq_clear & r_irq_mask);
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_sq_valid <= 0;
r_cq_valid <= 0;
r_io_cq_irq_en <= 0;
r_nvme_csts_shst <= 0;
r_nvme_csts_rdy <= 0;
end
else begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_nvme_csts_shst <= r_wdata[6:5];
r_nvme_csts_rdy <= r_wdata[4];
end
6'h07: begin
r_io_cq_irq_en[0] <= r_wdata[2];
r_sq_valid[0] <= r_wdata[1];
r_cq_valid[0] <= r_wdata[0];
end
6'h09: begin
r_sq_valid[1] <= r_wdata[15];
end
6'h0B: begin
r_sq_valid[2] <= r_wdata[15];
end
6'h0D: begin
r_sq_valid[3] <= r_wdata[15];
end
6'h0F: begin
r_sq_valid[4] <= r_wdata[15];
end
6'h11: begin
r_sq_valid[5] <= r_wdata[15];
end
6'h13: begin
r_sq_valid[6] <= r_wdata[15];
end
6'h15: begin
r_sq_valid[7] <= r_wdata[15];
end
6'h17: begin
r_sq_valid[8] <= r_wdata[15];
end
6'h19: begin
r_io_cq_irq_en[1] <= r_wdata[19];
r_cq_valid[1] <= r_wdata[15];
end
6'h1B: begin
r_io_cq_irq_en[2] <= r_wdata[19];
r_cq_valid[2] <= r_wdata[15];
end
6'h1D: begin
r_io_cq_irq_en[3] <= r_wdata[19];
r_cq_valid[3] <= r_wdata[15];
end
6'h1F: begin
r_io_cq_irq_en[4] <= r_wdata[19];
r_cq_valid[4] <= r_wdata[15];
end
6'h21: begin
r_io_cq_irq_en[5] <= r_wdata[19];
r_cq_valid[5] <= r_wdata[15];
end
6'h23: begin
r_io_cq_irq_en[6] <= r_wdata[19];
r_cq_valid[6] <= r_wdata[15];
end
6'h25: begin
r_io_cq_irq_en[7] <= r_wdata[19];
r_cq_valid[7] <= r_wdata[15];
end
6'h27: begin
r_io_cq_irq_en[8] <= r_wdata[19];
r_cq_valid[8] <= r_wdata[15];
end
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h08: begin
r_io_sq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h09: begin
r_io_sq1_size <= r_wdata[31:24];
r_io_sq1_cq_vec <= r_wdata[19:16];
r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0A: begin
r_io_sq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0B: begin
r_io_sq2_size <= r_wdata[31:24];
r_io_sq2_cq_vec <= r_wdata[19:16];
r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0C: begin
r_io_sq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0D: begin
r_io_sq3_size <= r_wdata[31:24];
r_io_sq3_cq_vec <= r_wdata[19:16];
r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0E: begin
r_io_sq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0F: begin
r_io_sq4_size <= r_wdata[31:24];
r_io_sq4_cq_vec <= r_wdata[19:16];
r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h10: begin
r_io_sq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h11: begin
r_io_sq5_size <= r_wdata[31:24];
r_io_sq5_cq_vec <= r_wdata[19:16];
r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h12: begin
r_io_sq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h13: begin
r_io_sq6_size <= r_wdata[31:24];
r_io_sq6_cq_vec <= r_wdata[19:16];
r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h14: begin
r_io_sq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h15: begin
r_io_sq7_size <= r_wdata[31:24];
r_io_sq7_cq_vec <= r_wdata[19:16];
r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h16: begin
r_io_sq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h17: begin
r_io_sq8_size <= r_wdata[31:24];
r_io_sq8_cq_vec <= r_wdata[19:16];
r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h18: begin
r_io_cq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h19: begin
r_io_cq1_size <= r_wdata[31:24];
r_io_cq1_iv <= r_wdata[18:16];
r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1A: begin
r_io_cq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1B: begin
r_io_cq2_size <= r_wdata[31:24];
r_io_cq2_iv <= r_wdata[18:16];
r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1C: begin
r_io_cq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1D: begin
r_io_cq3_size <= r_wdata[31:24];
r_io_cq3_iv <= r_wdata[18:16];
r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1E: begin
r_io_cq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1F: begin
r_io_cq4_size <= r_wdata[31:24];
r_io_cq4_iv <= r_wdata[18:16];
r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h20: begin
r_io_cq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h21: begin
r_io_cq5_size <= r_wdata[31:24];
r_io_cq5_iv <= r_wdata[18:16];
r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h22: begin
r_io_cq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h23: begin
r_io_cq6_size <= r_wdata[31:24];
r_io_cq6_iv <= r_wdata[18:16];
r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h24: begin
r_io_cq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h25: begin
r_io_cq7_size <= r_wdata[31:24];
r_io_cq7_iv <= r_wdata[18:16];
r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h26: begin
r_io_cq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h27: begin
r_io_cq8_size <= r_wdata[31:24];
r_io_cq8_iv <= r_wdata[18:16];
r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
endcase
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_fifo_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: {r_cpl_sq_qid, r_cpl_cid} <= r_wdata[19:0];
6'h02: r_cpl_specific <= r_wdata;
6'h03: {r_cpl_status, r_cql_type, r_hcmd_slot_tag} <= {r_wdata[31:17], r_wdata[15:14], r_wdata[6:0]};
6'h04: r_dma_cmd_dev_addr <= r_wdata[31:2];
6'h05: r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[C_PCIE_ADDR_WIDTH-1-32:0];
6'h06: r_dma_cmd_pcie_addr[31:2] <= r_wdata[31:2];
6'h07: begin
r_dma_cmd_type <= r_wdata[31];
r_dma_cmd_dir <= r_wdata[30];
r_dma_cmd_hcmd_slot_tag <= r_wdata[29:23];
r_dma_cmd_4k_offset <= r_wdata[22:14];
r_dma_cmd_dev_len <= r_wdata[12:2];
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_rd_state <= S_RD_IDLE;
else
cur_rd_state <= next_rd_state;
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
if(s_axi_arvalid == 1)
next_rd_state <= S_AR_VAILD;
else
next_rd_state <= S_RD_IDLE;
end
S_AR_VAILD: begin
next_rd_state <= S_AR_REG;
end
S_AR_REG: begin
if(r_araddr_hcmd_sq_rd_en == 1 || r_araddr_hcmd_table_rd_en == 1)
next_rd_state <= S_BRAM_READ;
else
next_rd_state <= S_R_READY;
end
S_BRAM_READ: begin
next_rd_state <= S_R_READY;
end
S_R_READY: begin
if(s_axi_rready == 1)
next_rd_state <= S_RD_IDLE;
else
next_rd_state <= S_R_READY;
end
default: begin
next_rd_state <= S_RD_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_araddr <= s_axi_araddr[15:2];
end
S_AR_VAILD: begin
r_araddr_cntl_reg_en <= (r_s_axi_araddr[15:8] == 8'h0);
r_araddr_pcie_reg_en <= (r_s_axi_araddr[15:8] == 8'h1);
r_araddr_nvme_reg_en <= (r_s_axi_araddr[15:8] == 8'h2);
r_araddr_nvme_fifo_en <= (r_s_axi_araddr[15:8] == 8'h3);
r_araddr_hcmd_table_rd_en <= (r_s_axi_araddr[15:13] == 3'h1);
r_araddr_hcmd_sq_rd_en <= (r_s_axi_araddr[15:2] == 14'hC0) & hcmd_sq_empty_n;
end
S_AR_REG: begin
case({r_araddr_nvme_fifo_en, r_araddr_nvme_reg_en, r_araddr_pcie_reg_en, r_araddr_cntl_reg_en}) // synthesis parallel_case full_case
4'b0001: r_rdata <= r_cntl_reg_rdata;
4'b0010: r_rdata <= r_pcie_reg_rdata;
4'b0100: r_rdata <= r_nvme_reg_rdata;
4'b1000: r_rdata <= r_nvme_fifo_rdata;
endcase
end
S_BRAM_READ: begin
case({r_araddr_hcmd_table_rd_en, r_araddr_hcmd_sq_rd_en}) // synthesis parallel_case full_case
2'b01: r_rdata <= {1'b1, 7'b0, hcmd_sq_rd_data[18:11], 1'b0, hcmd_sq_rd_data[10:4], 4'b0, hcmd_sq_rd_data[3:0]};
2'b10: r_rdata <= hcmd_table_rd_data;
endcase
end
S_R_READY: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_VAILD: begin
r_s_axi_arready <= 1;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_REG: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_BRAM_READ: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= r_araddr_hcmd_sq_rd_en;
end
S_R_READY: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 1;
r_s_axi_rdata <= r_rdata;
r_s_axi_rresp <= `D_AXI_RESP_OKAY;
r_hcmd_sq_rd_en <= 0;
end
default: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h01: r_cntl_reg_rdata <= {20'b0, r_irq_mask};
6'h03: r_cntl_reg_rdata <= {20'b0, r_irq_set};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_pcie_reg_rdata <= {23'b0, r_pcie_link_up, 2'b0, pl_ltssm_state};
6'h01: r_pcie_reg_rdata <= {25'b0, r_cfg_interrupt_mmenable, ~r_cfg_command[10], r_cfg_interrupt_msixenable, r_cfg_interrupt_msienable, r_cfg_command[2]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_reg_rdata <= {25'b0, r_nvme_csts_shst, r_nvme_csts_rdy, 1'b0, r_nvme_cc_shn, r_nvme_cc_en};
6'h01: r_nvme_reg_rdata <= {dma_tx_done_cnt, dma_rx_done_cnt, dma_tx_direct_done_cnt, dma_rx_direct_done_cnt};
6'h07: r_nvme_reg_rdata <= {19'b0, r_io_cq_irq_en[0], r_sq_valid[0], r_cq_valid[0]};
6'h08: r_nvme_reg_rdata <= {r_io_sq1_bs_addr[31:2], 2'b0};
6'h09: r_nvme_reg_rdata <= {r_io_sq1_size, 4'b0, r_io_sq1_cq_vec, r_sq_valid[1], 11'b0, r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0A: r_nvme_reg_rdata <= {r_io_sq2_bs_addr[31:2], 2'b0};
6'h0B: r_nvme_reg_rdata <= {r_io_sq2_size, 4'b0, r_io_sq2_cq_vec, r_sq_valid[2], 11'b0, r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0C: r_nvme_reg_rdata <= {r_io_sq3_bs_addr[31:2], 2'b0};
6'h0D: r_nvme_reg_rdata <= {r_io_sq3_size, 4'b0, r_io_sq3_cq_vec, r_sq_valid[3], 11'b0, r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0E: r_nvme_reg_rdata <= {r_io_sq4_bs_addr[31:2], 2'b0};
6'h0F: r_nvme_reg_rdata <= {r_io_sq4_size, 4'b0, r_io_sq4_cq_vec, r_sq_valid[4], 11'b0, r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h10: r_nvme_reg_rdata <= {r_io_sq5_bs_addr[31:2], 2'b0};
6'h11: r_nvme_reg_rdata <= {r_io_sq5_size, 4'b0, r_io_sq5_cq_vec, r_sq_valid[5], 11'b0, r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h12: r_nvme_reg_rdata <= {r_io_sq6_bs_addr[31:2], 2'b0};
6'h13: r_nvme_reg_rdata <= {r_io_sq6_size, 4'b0, r_io_sq6_cq_vec, r_sq_valid[6], 11'b0, r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h14: r_nvme_reg_rdata <= {r_io_sq7_bs_addr[31:2], 2'b0};
6'h15: r_nvme_reg_rdata <= {r_io_sq7_size, 4'b0, r_io_sq7_cq_vec, r_sq_valid[7], 11'b0, r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h16: r_nvme_reg_rdata <= {r_io_sq8_bs_addr[31:2], 2'b0};
6'h17: r_nvme_reg_rdata <= {r_io_sq8_size, 4'b0, r_io_sq8_cq_vec, r_sq_valid[8], 11'b0, r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h18: r_nvme_reg_rdata <= {r_io_cq1_bs_addr[31:2], 2'b0};
6'h19: r_nvme_reg_rdata <= {r_io_cq1_size, 4'b0, r_io_cq_irq_en[1], r_io_cq1_iv, r_cq_valid[1], 11'b0, r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1A: r_nvme_reg_rdata <= {r_io_cq2_bs_addr[31:2], 2'b0};
6'h1B: r_nvme_reg_rdata <= {r_io_cq2_size, 4'b0, r_io_cq_irq_en[2], r_io_cq2_iv, r_cq_valid[2], 11'b0, r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1C: r_nvme_reg_rdata <= {r_io_cq3_bs_addr[31:2], 2'b0};
6'h1D: r_nvme_reg_rdata <= {r_io_cq3_size, 4'b0, r_io_cq_irq_en[3], r_io_cq3_iv, r_cq_valid[3], 11'b0, r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1E: r_nvme_reg_rdata <= {r_io_cq4_bs_addr[31:2], 2'b0};
6'h1F: r_nvme_reg_rdata <= {r_io_cq4_size, 4'b0, r_io_cq_irq_en[4], r_io_cq4_iv, r_cq_valid[4], 11'b0, r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h20: r_nvme_reg_rdata <= {r_io_cq5_bs_addr[31:2], 2'b0};
6'h21: r_nvme_reg_rdata <= {r_io_cq5_size, 4'b0, r_io_cq_irq_en[5], r_io_cq5_iv, r_cq_valid[5], 11'b0, r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h22: r_nvme_reg_rdata <= {r_io_cq6_bs_addr[31:2], 2'b0};
6'h23: r_nvme_reg_rdata <= {r_io_cq6_size, 4'b0, r_io_cq_irq_en[6], r_io_cq6_iv, r_cq_valid[6], 11'b0, r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h24: r_nvme_reg_rdata <= {r_io_cq7_bs_addr[31:2], 2'b0};
6'h25: r_nvme_reg_rdata <= {r_io_cq7_size, 4'b0, r_io_cq_irq_en[7], r_io_cq7_iv, r_cq_valid[7], 11'b0, r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h26: r_nvme_reg_rdata <= {r_io_cq8_bs_addr[31:2], 2'b0};
6'h27: r_nvme_reg_rdata <= {r_io_cq8_size, 4'b0, r_io_cq_irq_en[8], r_io_cq8_iv, r_cq_valid[8], 11'b0, r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_fifo_rdata <= 0;
6'h01: r_nvme_fifo_rdata <= {12'b0, r_cpl_sq_qid, r_cpl_cid};
6'h02: r_nvme_fifo_rdata <= r_cpl_specific;
6'h03: r_nvme_fifo_rdata <= {r_cpl_status, 1'b0, r_cql_type, 7'b0, r_hcmd_slot_tag};
6'h04: r_nvme_fifo_rdata <= {r_dma_cmd_dev_addr, 2'b0};
6'h05: r_nvme_fifo_rdata <= {28'b0, r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h06: r_nvme_fifo_rdata <= {r_dma_cmd_pcie_addr[31:2], 2'b0};
6'h07: r_nvme_fifo_rdata <= {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_4k_offset, 1'b0, r_dma_cmd_dev_len, 2'b0};
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_slave # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
input mreq_fifo_wr_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
wire w_mreq_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_rd_data;
wire w_mreq_fifo_empty_n;
pcie_cntl_reg # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_reg_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (),
.rx_np_req (rx_np_req),
.mreq_fifo_rd_en (w_mreq_fifo_rd_en),
.mreq_fifo_rd_data (w_mreq_fifo_rd_data),
.mreq_fifo_empty_n (w_mreq_fifo_empty_n),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_cq_size (admin_cq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update)
);
pcie_cntl_rx_fifo
pcie_cntl_rx_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
////////////////////////////////////////////////////////////////
//bram fifo write signals
.wr_en (mreq_fifo_wr_en),
.wr_data (mreq_fifo_wr_data),
.full_n (),
.almost_full_n (rx_np_ok),
////////////////////////////////////////////////////////////////
//bram fifo read signals
.rd_en (w_mreq_fifo_rd_en),
.rd_data (w_mreq_fifo_rd_data),
.empty_n (w_mreq_fifo_empty_n)
);
endmodule |
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output [7:0] admin_sq_head_ptr,
output [7:0] io_sq1_head_ptr,
output [7:0] io_sq2_head_ptr,
output [7:0] io_sq3_head_ptr,
output [7:0] io_sq4_head_ptr,
output [7:0] io_sq5_head_ptr,
output [7:0] io_sq6_head_ptr,
output [7:0] io_sq7_head_ptr,
output [7:0] io_sq8_head_ptr,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output hcmd_table_wr_en,
output [8:0] hcmd_table_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] hcmd_table_wr_data,
output hcmd_cid_wr_en,
output [6:0] hcmd_cid_wr_addr,
output [19:0] hcmd_cid_wr_data,
output hcmd_prp_wr_en,
output [7:0] hcmd_prp_wr_addr,
output [44:0] hcmd_prp_wr_data,
output hcmd_nlb_wr0_en,
output [6:0] hcmd_nlb_wr0_addr,
output [18:0] hcmd_nlb_wr0_data,
input hcmd_nlb_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n
);
wire w_arb_sq_rdy;
wire [3:0] w_sq_qid;
wire [C_PCIE_ADDR_WIDTH-1:2] w_hcmd_pcie_addr;
wire w_sq_hcmd_ack;
wire w_hcmd_sq_wr_en;
wire [18:0] w_hcmd_sq_wr_data;
wire w_hcmd_sq_full_n;
wire w_pcie_sq_cmd_fifo_wr_en;
wire [10:0] w_pcie_sq_cmd_fifo_wr_data;
wire w_pcie_sq_cmd_fifo_full_n;
wire w_pcie_sq_cmd_fifo_rd_en;
wire [10:0] w_pcie_sq_cmd_fifo_rd_data;
wire w_pcie_sq_cmd_fifo_empty_n;
wire w_pcie_sq_rx_tag_alloc;
wire [7:0] w_pcie_sq_rx_alloc_tag;
wire [6:4] w_pcie_sq_rx_tag_alloc_len;
wire w_pcie_sq_rx_tag_full_n;
wire w_pcie_sq_rx_fifo_wr_en;
wire [3:0] w_pcie_sq_rx_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_wr_data;
wire [4:0] w_pcie_sq_rx_fifo_rear_full_addr;
wire [4:0] w_pcie_sq_rx_fifo_rear_addr;
wire w_pcie_sq_rx_fifo_full_n;
wire w_pcie_sq_rx_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_rd_data;
wire w_pcie_sq_rx_fifo_free_en;
wire [6:4] w_pcie_sq_rx_fifo_free_len;
wire w_pcie_sq_rx_fifo_empty_n;
pcie_hcmd_sq_fifo
pcie_hcmd_sq_fifo_inst0(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_hcmd_sq_wr_en),
.wr_data (w_hcmd_sq_wr_data),
.full_n (w_hcmd_sq_full_n),
.rd_clk (cpu_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (hcmd_sq_rd_en),
.rd_data (hcmd_sq_rd_data),
.empty_n (hcmd_sq_empty_n)
);
pcie_sq_cmd_fifo
pcie_sq_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_cmd_fifo_wr_en),
.wr_data (w_pcie_sq_cmd_fifo_wr_data),
.full_n (w_pcie_sq_cmd_fifo_full_n),
.rd_en (w_pcie_sq_cmd_fifo_rd_en),
.rd_data (w_pcie_sq_cmd_fifo_rd_data),
.empty_n (w_pcie_sq_cmd_fifo_empty_n)
);
pcie_sq_rx_fifo
pcie_sq_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_rx_fifo_wr_en),
.wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr),
.alloc_len (w_pcie_sq_rx_tag_alloc_len),
.full_n (w_pcie_sq_rx_fifo_full_n),
.rd_en (w_pcie_sq_rx_fifo_rd_en),
.rd_data (w_pcie_sq_rx_fifo_rd_data),
.free_en (w_pcie_sq_rx_fifo_free_en),
.free_len (w_pcie_sq_rx_fifo_free_len),
.empty_n (w_pcie_sq_rx_fifo_empty_n)
);
pcie_sq_rx_tag
pcie_sq_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_tag_full_n (w_pcie_sq_rx_tag_full_n),
.cpld_fifo_tag (cpld_sq_fifo_tag),
.cpld_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_fifo_tag_last (cpld_sq_fifo_tag_last),
.fifo_wr_en (w_pcie_sq_rx_fifo_wr_en),
.fifo_wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.fifo_wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr)
);
pcie_hcmd_sq_arb
pcie_hcmd_sq_arb_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_bs_addr (admin_sq_bs_addr),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack)
);
pcie_hcmd_sq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack),
.hcmd_slot_rdy (hcmd_slot_rdy),
.hcmd_slot_tag (hcmd_slot_tag),
.hcmd_slot_alloc_en (hcmd_slot_alloc_en),
.pcie_sq_cmd_fifo_wr_en (w_pcie_sq_cmd_fifo_wr_en),
.pcie_sq_cmd_fifo_wr_data (w_pcie_sq_cmd_fifo_wr_data),
.pcie_sq_cmd_fifo_full_n (w_pcie_sq_cmd_fifo_full_n),
.pcie_sq_rx_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_sq_rx_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_sq_rx_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_sq_rx_tag_full_n (w_pcie_sq_rx_tag_full_n),
.pcie_sq_rx_fifo_full_n (w_pcie_sq_rx_fifo_full_n),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack)
);
pcie_hcmd_sq_recv
pcie_hcmd_sq_recv_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_sq_cmd_fifo_rd_en (w_pcie_sq_cmd_fifo_rd_en),
.pcie_sq_cmd_fifo_rd_data (w_pcie_sq_cmd_fifo_rd_data),
.pcie_sq_cmd_fifo_empty_n (w_pcie_sq_cmd_fifo_empty_n),
.pcie_sq_rx_fifo_rd_en (w_pcie_sq_rx_fifo_rd_en),
.pcie_sq_rx_fifo_rd_data (w_pcie_sq_rx_fifo_rd_data),
.pcie_sq_rx_fifo_free_en (w_pcie_sq_rx_fifo_free_en),
.pcie_sq_rx_fifo_free_len (w_pcie_sq_rx_fifo_free_len),
.pcie_sq_rx_fifo_empty_n (w_pcie_sq_rx_fifo_empty_n),
.hcmd_table_wr_en (hcmd_table_wr_en),
.hcmd_table_wr_addr (hcmd_table_wr_addr),
.hcmd_table_wr_data (hcmd_table_wr_data),
.hcmd_cid_wr_en (hcmd_cid_wr_en),
.hcmd_cid_wr_addr (hcmd_cid_wr_addr),
.hcmd_cid_wr_data (hcmd_cid_wr_data),
.hcmd_prp_wr_en (hcmd_prp_wr_en),
.hcmd_prp_wr_addr (hcmd_prp_wr_addr),
.hcmd_prp_wr_data (hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (hcmd_nlb_wr0_rdy_n),
.hcmd_sq_wr_en (w_hcmd_sq_wr_en),
.hcmd_sq_wr_data (w_hcmd_sq_wr_data),
.hcmd_sq_full_n (w_hcmd_sq_full_n),
.sq_rst_n (sq_rst_n),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output [7:0] admin_sq_head_ptr,
output [7:0] io_sq1_head_ptr,
output [7:0] io_sq2_head_ptr,
output [7:0] io_sq3_head_ptr,
output [7:0] io_sq4_head_ptr,
output [7:0] io_sq5_head_ptr,
output [7:0] io_sq6_head_ptr,
output [7:0] io_sq7_head_ptr,
output [7:0] io_sq8_head_ptr,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output hcmd_table_wr_en,
output [8:0] hcmd_table_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] hcmd_table_wr_data,
output hcmd_cid_wr_en,
output [6:0] hcmd_cid_wr_addr,
output [19:0] hcmd_cid_wr_data,
output hcmd_prp_wr_en,
output [7:0] hcmd_prp_wr_addr,
output [44:0] hcmd_prp_wr_data,
output hcmd_nlb_wr0_en,
output [6:0] hcmd_nlb_wr0_addr,
output [18:0] hcmd_nlb_wr0_data,
input hcmd_nlb_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n
);
wire w_arb_sq_rdy;
wire [3:0] w_sq_qid;
wire [C_PCIE_ADDR_WIDTH-1:2] w_hcmd_pcie_addr;
wire w_sq_hcmd_ack;
wire w_hcmd_sq_wr_en;
wire [18:0] w_hcmd_sq_wr_data;
wire w_hcmd_sq_full_n;
wire w_pcie_sq_cmd_fifo_wr_en;
wire [10:0] w_pcie_sq_cmd_fifo_wr_data;
wire w_pcie_sq_cmd_fifo_full_n;
wire w_pcie_sq_cmd_fifo_rd_en;
wire [10:0] w_pcie_sq_cmd_fifo_rd_data;
wire w_pcie_sq_cmd_fifo_empty_n;
wire w_pcie_sq_rx_tag_alloc;
wire [7:0] w_pcie_sq_rx_alloc_tag;
wire [6:4] w_pcie_sq_rx_tag_alloc_len;
wire w_pcie_sq_rx_tag_full_n;
wire w_pcie_sq_rx_fifo_wr_en;
wire [3:0] w_pcie_sq_rx_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_wr_data;
wire [4:0] w_pcie_sq_rx_fifo_rear_full_addr;
wire [4:0] w_pcie_sq_rx_fifo_rear_addr;
wire w_pcie_sq_rx_fifo_full_n;
wire w_pcie_sq_rx_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_rd_data;
wire w_pcie_sq_rx_fifo_free_en;
wire [6:4] w_pcie_sq_rx_fifo_free_len;
wire w_pcie_sq_rx_fifo_empty_n;
pcie_hcmd_sq_fifo
pcie_hcmd_sq_fifo_inst0(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_hcmd_sq_wr_en),
.wr_data (w_hcmd_sq_wr_data),
.full_n (w_hcmd_sq_full_n),
.rd_clk (cpu_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (hcmd_sq_rd_en),
.rd_data (hcmd_sq_rd_data),
.empty_n (hcmd_sq_empty_n)
);
pcie_sq_cmd_fifo
pcie_sq_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_cmd_fifo_wr_en),
.wr_data (w_pcie_sq_cmd_fifo_wr_data),
.full_n (w_pcie_sq_cmd_fifo_full_n),
.rd_en (w_pcie_sq_cmd_fifo_rd_en),
.rd_data (w_pcie_sq_cmd_fifo_rd_data),
.empty_n (w_pcie_sq_cmd_fifo_empty_n)
);
pcie_sq_rx_fifo
pcie_sq_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_rx_fifo_wr_en),
.wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr),
.alloc_len (w_pcie_sq_rx_tag_alloc_len),
.full_n (w_pcie_sq_rx_fifo_full_n),
.rd_en (w_pcie_sq_rx_fifo_rd_en),
.rd_data (w_pcie_sq_rx_fifo_rd_data),
.free_en (w_pcie_sq_rx_fifo_free_en),
.free_len (w_pcie_sq_rx_fifo_free_len),
.empty_n (w_pcie_sq_rx_fifo_empty_n)
);
pcie_sq_rx_tag
pcie_sq_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_tag_full_n (w_pcie_sq_rx_tag_full_n),
.cpld_fifo_tag (cpld_sq_fifo_tag),
.cpld_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_fifo_tag_last (cpld_sq_fifo_tag_last),
.fifo_wr_en (w_pcie_sq_rx_fifo_wr_en),
.fifo_wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.fifo_wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr)
);
pcie_hcmd_sq_arb
pcie_hcmd_sq_arb_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_bs_addr (admin_sq_bs_addr),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack)
);
pcie_hcmd_sq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack),
.hcmd_slot_rdy (hcmd_slot_rdy),
.hcmd_slot_tag (hcmd_slot_tag),
.hcmd_slot_alloc_en (hcmd_slot_alloc_en),
.pcie_sq_cmd_fifo_wr_en (w_pcie_sq_cmd_fifo_wr_en),
.pcie_sq_cmd_fifo_wr_data (w_pcie_sq_cmd_fifo_wr_data),
.pcie_sq_cmd_fifo_full_n (w_pcie_sq_cmd_fifo_full_n),
.pcie_sq_rx_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_sq_rx_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_sq_rx_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_sq_rx_tag_full_n (w_pcie_sq_rx_tag_full_n),
.pcie_sq_rx_fifo_full_n (w_pcie_sq_rx_fifo_full_n),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack)
);
pcie_hcmd_sq_recv
pcie_hcmd_sq_recv_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_sq_cmd_fifo_rd_en (w_pcie_sq_cmd_fifo_rd_en),
.pcie_sq_cmd_fifo_rd_data (w_pcie_sq_cmd_fifo_rd_data),
.pcie_sq_cmd_fifo_empty_n (w_pcie_sq_cmd_fifo_empty_n),
.pcie_sq_rx_fifo_rd_en (w_pcie_sq_rx_fifo_rd_en),
.pcie_sq_rx_fifo_rd_data (w_pcie_sq_rx_fifo_rd_data),
.pcie_sq_rx_fifo_free_en (w_pcie_sq_rx_fifo_free_en),
.pcie_sq_rx_fifo_free_len (w_pcie_sq_rx_fifo_free_len),
.pcie_sq_rx_fifo_empty_n (w_pcie_sq_rx_fifo_empty_n),
.hcmd_table_wr_en (hcmd_table_wr_en),
.hcmd_table_wr_addr (hcmd_table_wr_addr),
.hcmd_table_wr_data (hcmd_table_wr_data),
.hcmd_cid_wr_en (hcmd_cid_wr_en),
.hcmd_cid_wr_addr (hcmd_cid_wr_addr),
.hcmd_cid_wr_data (hcmd_cid_wr_data),
.hcmd_prp_wr_en (hcmd_prp_wr_en),
.hcmd_prp_wr_addr (hcmd_prp_wr_addr),
.hcmd_prp_wr_data (hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (hcmd_nlb_wr0_rdy_n),
.hcmd_sq_wr_en (w_hcmd_sq_wr_en),
.hcmd_sq_wr_data (w_hcmd_sq_wr_data),
.hcmd_sq_full_n (w_hcmd_sq_full_n),
.sq_rst_n (sq_rst_n),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output [7:0] admin_sq_head_ptr,
output [7:0] io_sq1_head_ptr,
output [7:0] io_sq2_head_ptr,
output [7:0] io_sq3_head_ptr,
output [7:0] io_sq4_head_ptr,
output [7:0] io_sq5_head_ptr,
output [7:0] io_sq6_head_ptr,
output [7:0] io_sq7_head_ptr,
output [7:0] io_sq8_head_ptr,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output hcmd_table_wr_en,
output [8:0] hcmd_table_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] hcmd_table_wr_data,
output hcmd_cid_wr_en,
output [6:0] hcmd_cid_wr_addr,
output [19:0] hcmd_cid_wr_data,
output hcmd_prp_wr_en,
output [7:0] hcmd_prp_wr_addr,
output [44:0] hcmd_prp_wr_data,
output hcmd_nlb_wr0_en,
output [6:0] hcmd_nlb_wr0_addr,
output [18:0] hcmd_nlb_wr0_data,
input hcmd_nlb_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n
);
wire w_arb_sq_rdy;
wire [3:0] w_sq_qid;
wire [C_PCIE_ADDR_WIDTH-1:2] w_hcmd_pcie_addr;
wire w_sq_hcmd_ack;
wire w_hcmd_sq_wr_en;
wire [18:0] w_hcmd_sq_wr_data;
wire w_hcmd_sq_full_n;
wire w_pcie_sq_cmd_fifo_wr_en;
wire [10:0] w_pcie_sq_cmd_fifo_wr_data;
wire w_pcie_sq_cmd_fifo_full_n;
wire w_pcie_sq_cmd_fifo_rd_en;
wire [10:0] w_pcie_sq_cmd_fifo_rd_data;
wire w_pcie_sq_cmd_fifo_empty_n;
wire w_pcie_sq_rx_tag_alloc;
wire [7:0] w_pcie_sq_rx_alloc_tag;
wire [6:4] w_pcie_sq_rx_tag_alloc_len;
wire w_pcie_sq_rx_tag_full_n;
wire w_pcie_sq_rx_fifo_wr_en;
wire [3:0] w_pcie_sq_rx_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_wr_data;
wire [4:0] w_pcie_sq_rx_fifo_rear_full_addr;
wire [4:0] w_pcie_sq_rx_fifo_rear_addr;
wire w_pcie_sq_rx_fifo_full_n;
wire w_pcie_sq_rx_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_rd_data;
wire w_pcie_sq_rx_fifo_free_en;
wire [6:4] w_pcie_sq_rx_fifo_free_len;
wire w_pcie_sq_rx_fifo_empty_n;
pcie_hcmd_sq_fifo
pcie_hcmd_sq_fifo_inst0(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_hcmd_sq_wr_en),
.wr_data (w_hcmd_sq_wr_data),
.full_n (w_hcmd_sq_full_n),
.rd_clk (cpu_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (hcmd_sq_rd_en),
.rd_data (hcmd_sq_rd_data),
.empty_n (hcmd_sq_empty_n)
);
pcie_sq_cmd_fifo
pcie_sq_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_cmd_fifo_wr_en),
.wr_data (w_pcie_sq_cmd_fifo_wr_data),
.full_n (w_pcie_sq_cmd_fifo_full_n),
.rd_en (w_pcie_sq_cmd_fifo_rd_en),
.rd_data (w_pcie_sq_cmd_fifo_rd_data),
.empty_n (w_pcie_sq_cmd_fifo_empty_n)
);
pcie_sq_rx_fifo
pcie_sq_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_rx_fifo_wr_en),
.wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr),
.alloc_len (w_pcie_sq_rx_tag_alloc_len),
.full_n (w_pcie_sq_rx_fifo_full_n),
.rd_en (w_pcie_sq_rx_fifo_rd_en),
.rd_data (w_pcie_sq_rx_fifo_rd_data),
.free_en (w_pcie_sq_rx_fifo_free_en),
.free_len (w_pcie_sq_rx_fifo_free_len),
.empty_n (w_pcie_sq_rx_fifo_empty_n)
);
pcie_sq_rx_tag
pcie_sq_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_tag_full_n (w_pcie_sq_rx_tag_full_n),
.cpld_fifo_tag (cpld_sq_fifo_tag),
.cpld_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_fifo_tag_last (cpld_sq_fifo_tag_last),
.fifo_wr_en (w_pcie_sq_rx_fifo_wr_en),
.fifo_wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.fifo_wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr)
);
pcie_hcmd_sq_arb
pcie_hcmd_sq_arb_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_bs_addr (admin_sq_bs_addr),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack)
);
pcie_hcmd_sq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack),
.hcmd_slot_rdy (hcmd_slot_rdy),
.hcmd_slot_tag (hcmd_slot_tag),
.hcmd_slot_alloc_en (hcmd_slot_alloc_en),
.pcie_sq_cmd_fifo_wr_en (w_pcie_sq_cmd_fifo_wr_en),
.pcie_sq_cmd_fifo_wr_data (w_pcie_sq_cmd_fifo_wr_data),
.pcie_sq_cmd_fifo_full_n (w_pcie_sq_cmd_fifo_full_n),
.pcie_sq_rx_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_sq_rx_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_sq_rx_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_sq_rx_tag_full_n (w_pcie_sq_rx_tag_full_n),
.pcie_sq_rx_fifo_full_n (w_pcie_sq_rx_fifo_full_n),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack)
);
pcie_hcmd_sq_recv
pcie_hcmd_sq_recv_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_sq_cmd_fifo_rd_en (w_pcie_sq_cmd_fifo_rd_en),
.pcie_sq_cmd_fifo_rd_data (w_pcie_sq_cmd_fifo_rd_data),
.pcie_sq_cmd_fifo_empty_n (w_pcie_sq_cmd_fifo_empty_n),
.pcie_sq_rx_fifo_rd_en (w_pcie_sq_rx_fifo_rd_en),
.pcie_sq_rx_fifo_rd_data (w_pcie_sq_rx_fifo_rd_data),
.pcie_sq_rx_fifo_free_en (w_pcie_sq_rx_fifo_free_en),
.pcie_sq_rx_fifo_free_len (w_pcie_sq_rx_fifo_free_len),
.pcie_sq_rx_fifo_empty_n (w_pcie_sq_rx_fifo_empty_n),
.hcmd_table_wr_en (hcmd_table_wr_en),
.hcmd_table_wr_addr (hcmd_table_wr_addr),
.hcmd_table_wr_data (hcmd_table_wr_data),
.hcmd_cid_wr_en (hcmd_cid_wr_en),
.hcmd_cid_wr_addr (hcmd_cid_wr_addr),
.hcmd_cid_wr_data (hcmd_cid_wr_data),
.hcmd_prp_wr_en (hcmd_prp_wr_en),
.hcmd_prp_wr_addr (hcmd_prp_wr_addr),
.hcmd_prp_wr_data (hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (hcmd_nlb_wr0_rdy_n),
.hcmd_sq_wr_en (w_hcmd_sq_wr_en),
.hcmd_sq_wr_data (w_hcmd_sq_wr_data),
.hcmd_sq_full_n (w_hcmd_sq_full_n),
.sq_rst_n (sq_rst_n),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output [ 7:0 ] z
);
wire [7:0] z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
wire [7:0] zi;
reg [7:0] z;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench UART Decoder ////
//// ////
//// Description ////
//// ORPSoC Testbench UART output decoder ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - jb, [email protected] ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
`timescale 1ns/1ns
module uart_decoder(clk, uart_tx);
input clk;
input uart_tx;
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
// Something to trigger the task
always @(posedge clk)
uart_decoder;
task uart_decoder;
reg [7:0] tx_byte;
begin
while (uart_tx !== 1'b1)
@(uart_tx);
// Wait for start bit
while (uart_tx !== 1'b0)
@(uart_tx);
#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
tx_byte[0] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[1] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[2] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[3] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[4] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[5] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[6] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[7] = uart_tx;
#uart_baudrate_period_ns;
//Check for stop bit
if (uart_tx !== 1'b1)
begin
// Wait for return to idle
while (uart_tx !== 1'b1)
@(uart_tx);
end
// display the char
$write("%c", tx_byte);
end
endtask // user_uart_read_byte
endmodule // uart_decoder
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
initial begin
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longp, longp, longp, longp, longp, longp);
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longn, longn, longn, longn, longn, longn);
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widep, widep, widep, widep);
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
initial begin
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longp, longp, longp, longp, longp, longp);
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longn, longn, longn, longn, longn, longn);
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widep, widep, widep, widep);
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_slot_mgt
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_slot_rdy,
output [6:0] hcmd_slot_tag,
input hcmd_slot_alloc_en,
input hcmd_slot_free_en,
input [6:0] hcmd_slot_invalid_tag
);
localparam S_RESET_SEARCH_SLOT = 5'b00001;
localparam S_SEARCH_L1_SLOT = 5'b00010;
localparam S_SEARCH_L2_SLOT = 5'b00100;
localparam S_GNT_VAILD_SLOT = 5'b01000;
localparam S_VAILD_SLOT = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [127:0] r_slot_valid;
reg [127:0] r_slot_search_mask;
reg [127:0] r_slot_valid_mask;
reg [6:0] r_slot_tag;
reg r_slot_rdy;
reg [15:0] r_slot_l1_valid;
wire [7:0] w_slot_l1_mask;
wire r_slot_l1_ok;
//wire [7:0] w_slot_l2_valid;
wire [127:0] w_slot_l2_mask;
wire w_slot_l2_ok;
reg r_slot_free_en;
reg [6:0] r_slot_invalid_tag;
reg [127:0] r_slot_invalid_mask;
wire [127:0] w_slot_invalid_mask;
assign hcmd_slot_rdy = r_slot_rdy;
assign hcmd_slot_tag = r_slot_tag;
assign w_slot_l1_mask = { r_slot_search_mask[95],
r_slot_search_mask[79],
r_slot_search_mask[63],
r_slot_search_mask[47],
r_slot_search_mask[31],
r_slot_search_mask[15],
r_slot_search_mask[127],
r_slot_search_mask[111]};
always @ (*)
begin
case(w_slot_l1_mask) // synthesis parallel_case full_case
8'b00000001: r_slot_l1_valid <= r_slot_valid[15:0];
8'b00000010: r_slot_l1_valid <= r_slot_valid[31:16];
8'b00000100: r_slot_l1_valid <= r_slot_valid[47:32];
8'b00001000: r_slot_l1_valid <= r_slot_valid[63:48];
8'b00010000: r_slot_l1_valid <= r_slot_valid[79:64];
8'b00100000: r_slot_l1_valid <= r_slot_valid[95:80];
8'b01000000: r_slot_l1_valid <= r_slot_valid[111:96];
8'b10000000: r_slot_l1_valid <= r_slot_valid[127:112];
endcase
end
assign r_slot_l1_ok = (r_slot_l1_valid != 16'hFFFF);
assign w_slot_l2_mask = {r_slot_search_mask[126:0], r_slot_search_mask[127]};
assign w_slot_l2_ok = ((r_slot_valid & w_slot_l2_mask) == 0);
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RESET_SEARCH_SLOT;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L1_SLOT: begin
if(r_slot_l1_ok == 1)
next_state <= S_SEARCH_L2_SLOT;
else
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L2_SLOT: begin
if(w_slot_l2_ok == 1)
next_state <= S_GNT_VAILD_SLOT;
else
next_state <= S_SEARCH_L2_SLOT;
end
S_GNT_VAILD_SLOT: begin
if(hcmd_slot_alloc_en == 1)
next_state <= S_VAILD_SLOT;
else
next_state <= S_GNT_VAILD_SLOT;
end
S_VAILD_SLOT: begin
next_state <= S_RESET_SEARCH_SLOT;
end
default: begin
next_state <= S_RESET_SEARCH_SLOT;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_search_mask[127:112] <= 0;
r_slot_search_mask[111] <= 1'b1;
r_slot_search_mask[110:0] <= 0;
r_slot_tag <= 7'h6F;
end
S_SEARCH_L1_SLOT: begin
r_slot_search_mask[111] <= w_slot_l1_mask[7];
r_slot_search_mask[95] <= w_slot_l1_mask[6];
r_slot_search_mask[79] <= w_slot_l1_mask[5];
r_slot_search_mask[63] <= w_slot_l1_mask[4];
r_slot_search_mask[47] <= w_slot_l1_mask[3];
r_slot_search_mask[31] <= w_slot_l1_mask[2];
r_slot_search_mask[15] <= w_slot_l1_mask[1];
r_slot_search_mask[127] <= w_slot_l1_mask[0];
r_slot_tag <= r_slot_tag + 16;
end
S_SEARCH_L2_SLOT: begin
r_slot_search_mask <= w_slot_l2_mask;
r_slot_tag <= r_slot_tag + 1;
end
S_GNT_VAILD_SLOT: begin
end
S_VAILD_SLOT: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_slot_valid <= 0;
end
else begin
r_slot_valid <= (r_slot_valid | r_slot_valid_mask) & r_slot_invalid_mask;
//r_slot_valid <= (r_slot_valid | r_slot_valid_mask);
end
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L1_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L2_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_GNT_VAILD_SLOT: begin
r_slot_rdy <= 1;
r_slot_valid_mask <= 0;
end
S_VAILD_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= r_slot_search_mask;
end
default: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_slot_free_en <= hcmd_slot_free_en;
r_slot_invalid_tag <= hcmd_slot_invalid_tag;
if(r_slot_free_en == 1)
r_slot_invalid_mask <= w_slot_invalid_mask;
else
r_slot_invalid_mask <= {128{1'b1}};
end
genvar i;
generate
for(i = 0; i < 128; i = i + 1)
begin : INVALID_TAG
assign w_slot_invalid_mask[i] = (r_slot_invalid_tag != i);
end
endgenerate
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_fc_cntl
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input tx_cfg_req,
output tx_cfg_gnt,
input [5:0] tx_buf_av,
output tx_cpld_gnt,
output tx_mrd_gnt,
output tx_mwr_gnt
);
parameter P_RX_CONSTRAINT_FC_CPLD = 32;
parameter P_RX_CONSTRAINT_FC_CPLH = 8;
parameter P_TX_CONSTRAINT_FC_CPLD = 1;
parameter P_TX_CONSTRAINT_FC_CPLH = 1;
parameter P_TX_CONSTRAINT_FC_NPD = 1;
parameter P_TX_CONSTRAINT_FC_NPH = 1;
parameter P_TX_CONSTRAINT_FC_PD = 32;
parameter P_TX_CONSTRAINT_FC_PH = 1;
localparam S_RX_AVAILABLE_FC_SEL = 2'b01;
localparam S_TX_AVAILABLE_FC_SEL = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
wire w_rx_available_fc_cpld;
wire w_rx_available_fc_cplh;
wire w_tx_available_fc_cpld;
wire w_tx_available_fc_cplh;
wire w_tx_available_fc_npd;
wire w_tx_available_fc_nph;
wire w_tx_available_fc_pd;
wire w_tx_available_fc_ph;
reg [2:0] r_fc_sel;
reg [1:0] r_rd_fc_sel;
reg [1:0] r_rd_fc_sel_d1;
reg [1:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign fc_sel = r_fc_sel;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b01;
end
S_TX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 2'b10;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b00;
end
endcase
end
assign w_rx_available_fc_cpld = (r_rx_available_fc_cpld > P_RX_CONSTRAINT_FC_CPLD);
assign w_rx_available_fc_cplh = (r_rx_available_fc_cplh > P_RX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_cpld = (r_tx_available_fc_cpld > P_TX_CONSTRAINT_FC_CPLD);
assign w_tx_available_fc_cplh = (r_tx_available_fc_cplh > P_TX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_npd = (r_tx_available_fc_npd > P_TX_CONSTRAINT_FC_NPD);
assign w_tx_available_fc_nph = (r_tx_available_fc_nph > P_TX_CONSTRAINT_FC_NPH);
assign w_tx_available_fc_pd = (r_tx_available_fc_pd > P_TX_CONSTRAINT_FC_PD);
assign w_tx_available_fc_ph = (r_tx_available_fc_ph > P_TX_CONSTRAINT_FC_PH);
always @ (posedge pcie_user_clk)
begin
r_tx_cpld_gnt <= w_tx_available_fc_cpld & w_tx_available_fc_cplh;
r_tx_mrd_gnt <= (w_tx_available_fc_npd & w_tx_available_fc_nph) & (w_rx_available_fc_cpld & w_rx_available_fc_cplh);
r_tx_mwr_gnt <= w_tx_available_fc_pd & w_tx_available_fc_ph;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
end
end
/*
parameter P_RX_AVAILABLE_FC_CPLD = 36;
parameter P_RX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_CPLD = 36;
parameter P_TX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_NPD = 36;
parameter P_TX_AVAILABLE_FC_NPH = 36;
parameter P_TX_AVAILABLE_FC_PD = 36;
parameter P_TX_AVAILABLE_FC_PH = 36;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_rx_limit_fc_cpld;
reg [7:0] r_rx_limit_fc_cplh;
reg [11:0] r_rx_limit_fc_npd;
reg [7:0] r_rx_limit_fc_nph;
reg [11:0] r_rx_limit_fc_pd;
reg [7:0] r_rx_limit_fc_ph;
reg [11:0] r_rx_consumed_fc_cpld;
reg [7:0] r_rx_consumed_fc_cplh;
reg [11:0] r_rx_consumed_fc_npd;
reg [7:0] r_rx_consumed_fc_nph;
reg [11:0] r_rx_consumed_fc_pd;
reg [7:0] r_rx_consumed_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
reg [11:0] r_tx_limit_fc_cpld;
reg [7:0] r_tx_limit_fc_cplh;
reg [11:0] r_tx_limit_fc_npd;
reg [7:0] r_tx_limit_fc_nph;
reg [11:0] r_tx_limit_fc_pd;
reg [7:0] r_tx_limit_fc_ph;
reg [11:0] r_tx_consumed_fc_cpld;
reg [7:0] r_tx_consumed_fc_cplh;
reg [11:0] r_tx_consumed_fc_npd;
reg [7:0] r_tx_consumed_fc_nph;
reg [11:0] r_tx_consumed_fc_pd;
reg [7:0] r_tx_consumed_fc_ph;
reg [2:0] r_fc_sel;
reg [5:0] r_rd_fc_sel;
reg [5:0] r_rd_fc_sel_d1;
reg [5:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_LITMIT_FC_SEL;
end
S_RX_LITMIT_FC_SEL: begin
next_state <= S_RX_CONSUMED_FC_SEL;
end
S_RX_CONSUMED_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_LITMIT_FC_SEL;
end
S_TX_LITMIT_FC_SEL: begin
next_state <= S_TX_CONSUMED_FC_SEL;
end
S_TX_CONSUMED_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000001;
end
S_RX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b001;
r_rd_fc_sel <= 6'b000010;
end
S_RX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b010;
r_rd_fc_sel <= 6'b000100;
end
S_TX_AVAILABLE_FC_SEL: begi
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 6'b001000;
end
S_TX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b101;
r_rd_fc_sel <= 6'b010000;
end
S_TX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b110;
r_rd_fc_sel <= 6'b100000;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000000;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
r_tx_cpld_gnt;
r_tx_mrd_gnt;
r_tx_mwr_gnt;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_rx_limit_fc_cpld <= 0;
r_rx_limit_fc_cplh <= 0;
r_rx_limit_fc_npd <= 0;
r_rx_limit_fc_nph <= 0;
r_rx_limit_fc_pd <= 0;
r_rx_limit_fc_ph <= 0;
r_rx_consumed_fc_cpld <= 0;
r_rx_consumed_fc_cplh <= 0;
r_rx_consumed_fc_npd <= 0;
r_rx_consumed_fc_nph <= 0;
r_rx_consumed_fc_pd <= 0;
r_rx_consumed_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
r_tx_limit_fc_cpld <= 0;
r_tx_limit_fc_cplh <= 0;
r_tx_limit_fc_npd <= 0;
r_tx_limit_fc_nph <= 0;
r_tx_limit_fc_pd <= 0;
r_tx_limit_fc_ph <= 0;
r_tx_consumed_fc_cpld <= 0;
r_tx_consumed_fc_cplh <= 0;
r_tx_consumed_fc_npd <= 0;
r_tx_consumed_fc_nph <= 0;
r_tx_consumed_fc_pd <= 0;
r_tx_consumed_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_rx_limit_fc_cpld <= fc_cpld;
r_rx_limit_fc_cplh <= fc_cplh;
r_rx_limit_fc_npd <= fc_npd;
r_rx_limit_fc_nph <= fc_nph;
r_rx_limit_fc_pd <= fc_pd;
r_rx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[2] == 1) begin
r_rx_consumed_fc_cpld <= fc_cpld;
r_rx_consumed_fc_cplh <= fc_cplh;
r_rx_consumed_fc_npd <= fc_npd;
r_rx_consumed_fc_nph <= fc_nph;
r_rx_consumed_fc_pd <= fc_pd;
r_rx_consumed_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[3] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[4] == 1) begin
r_tx_limit_fc_cpld <= fc_cpld;
r_tx_limit_fc_cplh <= fc_cplh;
r_tx_limit_fc_npd <= fc_npd;
r_tx_limit_fc_nph <= fc_nph;
r_tx_limit_fc_pd <= fc_pd;
r_tx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[5] == 1) begin
r_tx_consumed_fc_cpld <= fc_cpld;
r_tx_consumed_fc_cplh <= fc_cplh;
r_tx_consumed_fc_npd <= fc_npd;
r_tx_consumed_fc_nph <= fc_nph;
r_tx_consumed_fc_pd <= fc_pd;
r_tx_consumed_fc_ph <= fc_ph;
end
end
end
*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
q0, q1, q2, q3, q4, q5, q6a, q6b,
// Inputs
clk, d, rst0_n
);
input clk;
input d;
// OK -- from primary
input rst0_n;
output wire q0;
Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
// OK -- from flop
reg rst1_n;
always @ (posedge clk) rst1_n <= rst0_n;
output wire q1;
Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
// Bad - logic
wire rst2_bad_n = rst0_n | rst1_n;
output wire q2;
Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
// Bad - logic in submodule
wire rst3_bad_n;
Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
output wire q3;
Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
// OK - bit selection
reg [3:0] rst4_n;
always @ (posedge clk) rst4_n <= {4{rst0_n}};
output wire q4;
Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
// Bad - logic, but waived
// verilator lint_off CDCRSTLOGIC
wire rst5_waive_n = rst0_n & rst1_n;
// verilator lint_on CDCRSTLOGIC
output wire q5;
Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
// Bad - for graph test - logic feeds two signals, three destinations
wire rst6_bad_n = rst0_n ^ rst1_n;
wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization
wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
output wire q6a;
output wire q6b;
Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d));
Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d));
initial begin
$display("%%Error: Not a runnable test");
$stop;
end
endmodule
module Flop (
input clk,
input d,
input rst_n,
output q);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) q <= 1'b0;
else q <= d;
end
endmodule
module Sub (input a, b,
output z);
wire z = a|b;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
|
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 2;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
module usb_fifo_writer
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [FIFO_WIDTH-1:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [BUS_WIDTH-1:0] usbdata_delayed ;
reg writing ;
wire [FIFO_WIDTH-1:0] usbdata_packed ;
wire WR_packed ;
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [FIFO_WIDTH-1:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
reg [31:0] usbdata_final;
reg WR_final;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter WAIT = 4'd2;
parameter FORWARD = 4'd3;
`define CHANNEL 20:16
`define PKT_SIZE 512
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= 0;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ;
WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1;
//channel <= usbdata_final[`CHANNEL] ;
//WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 10'd4;
reader_state <= WAIT;
end
endcase
end
endmodule |
module usb_fifo_writer
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [FIFO_WIDTH-1:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [BUS_WIDTH-1:0] usbdata_delayed ;
reg writing ;
wire [FIFO_WIDTH-1:0] usbdata_packed ;
wire WR_packed ;
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [FIFO_WIDTH-1:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
reg [31:0] usbdata_final;
reg WR_final;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter WAIT = 4'd2;
parameter FORWARD = 4'd3;
`define CHANNEL 20:16
`define PKT_SIZE 512
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= 0;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ;
WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1;
//channel <= usbdata_final[`CHANNEL] ;
//WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 10'd4;
reader_state <= WAIT;
end
endcase
end
endmodule |
module usb_fifo_writer
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [FIFO_WIDTH-1:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [BUS_WIDTH-1:0] usbdata_delayed ;
reg writing ;
wire [FIFO_WIDTH-1:0] usbdata_packed ;
wire WR_packed ;
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [FIFO_WIDTH-1:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
reg [31:0] usbdata_final;
reg WR_final;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter WAIT = 4'd2;
parameter FORWARD = 4'd3;
`define CHANNEL 20:16
`define PKT_SIZE 512
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= 0;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ;
WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1;
//channel <= usbdata_final[`CHANNEL] ;
//WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 10'd4;
reader_state <= WAIT;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_cq_check # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_msi_en,
input cq_rst_n,
input cq_valid,
input io_cq_irq_en,
input [7:0] cq_tail_ptr,
input [7:0] cq_head_ptr,
input cq_head_update,
output cq_legacy_irq_req,
output cq_msi_irq_req,
input cq_msi_irq_ack
);
localparam LP_CQ_IRQ_DELAY_TIME = 8'h01;
localparam S_IDLE = 4'b0001;
localparam S_CQ_MSI_IRQ_REQ = 4'b0010;
localparam S_CQ_MSI_HEAD_SET = 4'b0100;
localparam S_CQ_MSI_IRQ_TIMER = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_cq_msi_irq_head_ptr;
reg [7:0] r_irq_timer;
reg r_cq_legacy_irq_req;
reg r_cq_msi_irq_req;
wire w_cq_rst_n;
assign cq_legacy_irq_req = r_cq_legacy_irq_req;
assign cq_msi_irq_req = r_cq_msi_irq_req;
assign w_cq_rst_n = pcie_user_rst_n & cq_rst_n;
always @ (posedge pcie_user_clk)
begin
r_cq_tail_ptr <= cq_tail_ptr;
r_cq_legacy_irq_req <= ((cq_head_ptr != r_cq_tail_ptr) && ((cq_valid & io_cq_irq_en) == 1));
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(((r_cq_msi_irq_head_ptr != r_cq_tail_ptr) & (pcie_msi_en & cq_valid & io_cq_irq_en)) == 1)
next_state <= S_CQ_MSI_IRQ_REQ;
else
next_state <= S_IDLE;
end
S_CQ_MSI_IRQ_REQ: begin
if(cq_msi_irq_ack == 1)
next_state <= S_CQ_MSI_HEAD_SET;
else
next_state <= S_CQ_MSI_IRQ_REQ;
end
S_CQ_MSI_HEAD_SET: begin
/*
if(cq_head_update == 1 || (cq_head_ptr == r_cq_tail_ptr))
next_state <= S_CQ_MSI_IRQ_TIMER;
else
next_state <= S_CQ_MSI_HEAD_SET;
*/
next_state <= S_CQ_MSI_IRQ_TIMER;
end
S_CQ_MSI_IRQ_TIMER: begin
if(r_irq_timer == 0)
next_state <= S_IDLE;
else
next_state <= S_CQ_MSI_IRQ_TIMER;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_irq_timer <= LP_CQ_IRQ_DELAY_TIME;
end
S_CQ_MSI_IRQ_TIMER: begin
r_irq_timer <= r_irq_timer - 1;
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0) begin
r_cq_msi_irq_head_ptr <= 0;
end
else begin
case(cur_state)
S_IDLE: begin
if((pcie_msi_en & cq_valid & io_cq_irq_en) == 0)
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_TIMER: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_REQ: begin
r_cq_msi_irq_req <= 1;
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_TIMER: begin
r_cq_msi_irq_req <= 0;
end
default: begin
r_cq_msi_irq_req <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_cq_check # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_msi_en,
input cq_rst_n,
input cq_valid,
input io_cq_irq_en,
input [7:0] cq_tail_ptr,
input [7:0] cq_head_ptr,
input cq_head_update,
output cq_legacy_irq_req,
output cq_msi_irq_req,
input cq_msi_irq_ack
);
localparam LP_CQ_IRQ_DELAY_TIME = 8'h01;
localparam S_IDLE = 4'b0001;
localparam S_CQ_MSI_IRQ_REQ = 4'b0010;
localparam S_CQ_MSI_HEAD_SET = 4'b0100;
localparam S_CQ_MSI_IRQ_TIMER = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_cq_msi_irq_head_ptr;
reg [7:0] r_irq_timer;
reg r_cq_legacy_irq_req;
reg r_cq_msi_irq_req;
wire w_cq_rst_n;
assign cq_legacy_irq_req = r_cq_legacy_irq_req;
assign cq_msi_irq_req = r_cq_msi_irq_req;
assign w_cq_rst_n = pcie_user_rst_n & cq_rst_n;
always @ (posedge pcie_user_clk)
begin
r_cq_tail_ptr <= cq_tail_ptr;
r_cq_legacy_irq_req <= ((cq_head_ptr != r_cq_tail_ptr) && ((cq_valid & io_cq_irq_en) == 1));
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(((r_cq_msi_irq_head_ptr != r_cq_tail_ptr) & (pcie_msi_en & cq_valid & io_cq_irq_en)) == 1)
next_state <= S_CQ_MSI_IRQ_REQ;
else
next_state <= S_IDLE;
end
S_CQ_MSI_IRQ_REQ: begin
if(cq_msi_irq_ack == 1)
next_state <= S_CQ_MSI_HEAD_SET;
else
next_state <= S_CQ_MSI_IRQ_REQ;
end
S_CQ_MSI_HEAD_SET: begin
/*
if(cq_head_update == 1 || (cq_head_ptr == r_cq_tail_ptr))
next_state <= S_CQ_MSI_IRQ_TIMER;
else
next_state <= S_CQ_MSI_HEAD_SET;
*/
next_state <= S_CQ_MSI_IRQ_TIMER;
end
S_CQ_MSI_IRQ_TIMER: begin
if(r_irq_timer == 0)
next_state <= S_IDLE;
else
next_state <= S_CQ_MSI_IRQ_TIMER;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_irq_timer <= LP_CQ_IRQ_DELAY_TIME;
end
S_CQ_MSI_IRQ_TIMER: begin
r_irq_timer <= r_irq_timer - 1;
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0) begin
r_cq_msi_irq_head_ptr <= 0;
end
else begin
case(cur_state)
S_IDLE: begin
if((pcie_msi_en & cq_valid & io_cq_irq_en) == 0)
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_TIMER: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_REQ: begin
r_cq_msi_irq_req <= 1;
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_TIMER: begin
r_cq_msi_irq_req <= 0;
end
default: begin
r_cq_msi_irq_req <= 0;
end
endcase
end
endmodule |
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_cq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input [7:0] hcmd_prp_rd_addr,
output [44:0] hcmd_prp_rd_data,
input hcmd_nlb_wr1_en,
input [6:0] hcmd_nlb_wr1_addr,
input [18:0] hcmd_nlb_wr1_data,
output hcmd_nlb_wr1_rdy_n,
input [6:0] hcmd_nlb_rd_addr,
output [18:0] hcmd_nlb_rd_data,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_table_wr_en;
wire [8:0] w_hcmd_table_wr_addr;
wire [127:0] w_hcmd_table_wr_data;
wire w_hcmd_cid_wr_en;
wire [6:0] w_hcmd_cid_wr_addr;
wire [19:0] w_hcmd_cid_wr_data;
wire [6:0] w_hcmd_cid_rd_addr;
wire [19:0] w_hcmd_cid_rd_data;
wire w_hcmd_prp_wr_en;
wire [7:0] w_hcmd_prp_wr_addr;
wire [44:0] w_hcmd_prp_wr_data;
wire w_hcmd_nlb_wr0_en;
wire [6:0] w_hcmd_nlb_wr0_addr;
wire [18:0] w_hcmd_nlb_wr0_data;
wire w_hcmd_nlb_wr0_rdy_n;
wire w_hcmd_slot_rdy;
wire [6:0] w_hcmd_slot_tag;
wire w_hcmd_slot_alloc_en;
wire w_hcmd_slot_free_en;
wire [6:0] w_hcmd_slot_invalid_tag;
wire [7:0] w_admin_sq_head_ptr;
wire [7:0] w_io_sq1_head_ptr;
wire [7:0] w_io_sq2_head_ptr;
wire [7:0] w_io_sq3_head_ptr;
wire [7:0] w_io_sq4_head_ptr;
wire [7:0] w_io_sq5_head_ptr;
wire [7:0] w_io_sq6_head_ptr;
wire [7:0] w_io_sq7_head_ptr;
wire [7:0] w_io_sq8_head_ptr;
pcie_hcmd_table
pcie_hcmd_table_inst0(
.wr_clk (pcie_user_clk),
.wr_en (w_hcmd_table_wr_en),
.wr_addr (w_hcmd_table_wr_addr),
.wr_data (w_hcmd_table_wr_data),
.rd_clk (cpu_bus_clk),
.rd_addr (hcmd_table_rd_addr),
.rd_data (hcmd_table_rd_data)
);
pcie_hcmd_table_cid
pcie_hcmd_table_cid_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_cid_wr_en),
.wr_addr (w_hcmd_cid_wr_addr),
.wr_data (w_hcmd_cid_wr_data),
.rd_addr (w_hcmd_cid_rd_addr),
.rd_data (w_hcmd_cid_rd_data)
);
pcie_hcmd_table_prp
pcie_hcmd_table_prp_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_prp_wr_en),
.wr_addr (w_hcmd_prp_wr_addr),
.wr_data (w_hcmd_prp_wr_data),
.rd_addr (hcmd_prp_rd_addr),
.rd_data (hcmd_prp_rd_data)
);
pcie_hcmd_nlb
pcie_hcmd_nlb_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (w_hcmd_nlb_wr0_en),
.wr0_addr (w_hcmd_nlb_wr0_addr),
.wr0_data (w_hcmd_nlb_wr0_data),
.wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.wr1_en (hcmd_nlb_wr1_en),
.wr1_addr (hcmd_nlb_wr1_addr),
.wr1_data (hcmd_nlb_wr1_data),
.wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.rd_addr (hcmd_nlb_rd_addr),
.rd_data (hcmd_nlb_rd_data)
);
pcie_hcmd_slot_mgt
pcie_hcmd_slot_mgt_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag)
);
pcie_hcmd_sq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.cpld_sq_fifo_tag (cpld_sq_fifo_tag),
.cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack),
.hcmd_table_wr_en (w_hcmd_table_wr_en),
.hcmd_table_wr_addr (w_hcmd_table_wr_addr),
.hcmd_table_wr_data (w_hcmd_table_wr_data),
.hcmd_cid_wr_en (w_hcmd_cid_wr_en),
.hcmd_cid_wr_addr (w_hcmd_cid_wr_addr),
.hcmd_cid_wr_data (w_hcmd_cid_wr_data),
.hcmd_prp_wr_en (w_hcmd_prp_wr_en),
.hcmd_prp_wr_addr (w_hcmd_prp_wr_addr),
.hcmd_prp_wr_data (w_hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n)
);
pcie_hcmd_cq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cid_rd_addr (w_hcmd_cid_rd_addr),
.hcmd_cid_rd_data (w_hcmd_cid_rd_data),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_cq_size (admin_cq_size),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
endmodule |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// soc_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// soc_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
module data_packet_fifo
( input reset,
input clock,
input [31:0]ram_data_in,
input write_enable,
output reg have_space,
output reg [31:0]ram_data_out,
output reg pkt_waiting,
output reg isfull,
output reg [1:0]usb_ram_packet_out,
output reg [1:0]usb_ram_packet_in,
input read_enable,
input pkt_complete,
input skip_packet) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 32 ;
parameter PKT_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [6:0] usb_ram_offset_out ;
//reg [1:0] usb_ram_packet_out ;
reg [6:0] usb_ram_offset_in ;
//reg [1:0] usb_ram_packet_in ;
wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
//reg isfull;
assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull ;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
else
pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0;
else
have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
/* RAM Writing/Reading process */
always @(posedge clock)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
ram_data_out <= usb_ram[usb_ram_aout] ;
end
/* RAM Write/Read Address process */
always @(posedge clock)
begin
if( reset )
begin
usb_ram_packet_out <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_offset_in <= 0 ;
usb_ram_packet_in <= 0 ;
isfull <= 0;
end
else
begin
if( skip_packet )
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
isfull <= 0;
end
else if(read_enable)
begin
if( usb_ram_offset_out == 7'b1111111 )
begin
isfull <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
end
if( pkt_complete )
begin
usb_ram_packet_in <= usb_ram_packet_in + 1 ;
usb_ram_offset_in <= 0 ;
if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
isfull <= 1 ;
end
else if( write_enable )
begin
if (usb_ram_offset_in == 7'b1111111)
usb_ram_offset_in <= 7'b1111111 ;
else
usb_ram_offset_in <= usb_ram_offset_in + 1 ;
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_irq_gen # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input pcie_legacy_irq_set,
input pcie_msi_irq_set,
input [2:0] pcie_irq_vector,
input pcie_legacy_irq_clear,
output pcie_irq_done
);
localparam S_IDLE = 7'b0000001;
localparam S_SEND_MSI = 7'b0000010;
localparam S_LEGACY_ASSERT = 7'b0000100;
localparam S_LEGACY_ASSERT_HOLD = 7'b0001000;
localparam S_LEGACY_DEASSERT = 7'b0010000;
localparam S_WAIT_RDY_N = 7'b0100000;
localparam S_IRQ_DONE = 7'b1000000;
reg [6:0] cur_state;
reg [6:0] next_state;
reg r_cfg_interrupt;
reg r_cfg_interrupt_assert;
reg [7:0] r_cfg_interrupt_di;
reg [2:0] r_pcie_irq_vector;
reg r_pcie_irq_done;
assign cfg_interrupt = r_cfg_interrupt;
assign cfg_interrupt_assert = r_cfg_interrupt_assert;
assign cfg_interrupt_di = r_cfg_interrupt_di;
assign cfg_interrupt_stat = 1'b0;
assign cfg_pciecap_interrupt_msgnum = 5'b0;
assign pcie_irq_done = r_pcie_irq_done;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_msi_irq_set == 1)
next_state <= S_SEND_MSI;
else if(pcie_legacy_irq_set == 1)
next_state <= S_LEGACY_ASSERT;
else
next_state <= S_IDLE;
end
S_SEND_MSI: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_WAIT_RDY_N;
else
next_state <= S_SEND_MSI;
end
S_LEGACY_ASSERT: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_LEGACY_ASSERT_HOLD;
else
next_state <= S_LEGACY_ASSERT;
end
S_LEGACY_ASSERT_HOLD: begin
if(pcie_legacy_irq_clear == 1)
next_state <= S_LEGACY_DEASSERT;
else
next_state <= S_LEGACY_ASSERT_HOLD;
end
S_LEGACY_DEASSERT: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_WAIT_RDY_N;
else
next_state <= S_LEGACY_DEASSERT;
end
S_WAIT_RDY_N: begin
if(cfg_interrupt_rdy == 0)
next_state <= S_IRQ_DONE;
else
next_state <= S_WAIT_RDY_N;
end
S_IRQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_pcie_irq_vector <= pcie_irq_vector;
end
S_SEND_MSI: begin
end
S_LEGACY_ASSERT: begin
end
S_LEGACY_ASSERT_HOLD: begin
end
S_LEGACY_DEASSERT: begin
end
S_WAIT_RDY_N: begin
end
S_IRQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_SEND_MSI: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= {5'b0, r_pcie_irq_vector};
r_pcie_irq_done <= 0;
end
S_LEGACY_ASSERT: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 1;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_LEGACY_ASSERT_HOLD: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 1;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_LEGACY_DEASSERT: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_WAIT_RDY_N: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_IRQ_DONE: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 1;
end
default: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_cq_rd_en,
input [34:0] hcmd_cq_rd_data,
input hcmd_cq_empty_n,
output [6:0] hcmd_cid_rd_addr,
input [19:0] hcmd_cid_rd_data,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] sq_valid,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] admin_cq_size,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
input [7:0] admin_sq_head_ptr,
input [7:0] io_sq1_head_ptr,
input [7:0] io_sq2_head_ptr,
input [7:0] io_sq3_head_ptr,
input [7:0] io_sq4_head_ptr,
input [7:0] io_sq5_head_ptr,
input [7:0] io_sq6_head_ptr,
input [7:0] io_sq7_head_ptr,
input [7:0] io_sq8_head_ptr,
output hcmd_slot_free_en,
output [6:0] hcmd_slot_invalid_tag,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last
);
localparam LP_CPL_PCIE_TAG_PREFIX = 8'b00000000;
localparam LP_CPL_SIZE = 10'h04;
localparam S_IDLE = 11'b00000000001;
localparam S_CPL_STATUS0 = 11'b00000000010;
localparam S_CPL_STATUS1 = 11'b00000000100;
localparam S_CPL_STATUS2 = 11'b00000001000;
localparam S_CPL_STATUS3 = 11'b00000010000;
localparam S_HEAD_PTR = 11'b00000100000;
localparam S_PCIE_ADDR = 11'b00001000000;
localparam S_PCIE_MWR_REQ = 11'b00010000000;
localparam S_PCIE_MWR_DATA_LAST = 11'b00100000000;
localparam S_PCIE_MWR_DONE = 11'b01000000000;
localparam S_PCIE_SLOT_RELEASE = 11'b10000000000;
reg [10:0] cur_state;
reg [10:0] next_state;
reg r_sq_is_valid;
reg r_cq_is_valid;
reg [7:0] r_admin_cq_tail_ptr;
reg [7:0] r_io_cq1_tail_ptr;
reg [7:0] r_io_cq2_tail_ptr;
reg [7:0] r_io_cq3_tail_ptr;
reg [7:0] r_io_cq4_tail_ptr;
reg [7:0] r_io_cq5_tail_ptr;
reg [7:0] r_io_cq6_tail_ptr;
reg [7:0] r_io_cq7_tail_ptr;
reg [7:0] r_io_cq8_tail_ptr;
reg [8:0] r_cq_phase_tag;
reg [3:0] r_sq_cq_vec;
reg [8:0] r_cq_valid_entry;
reg [8:0] r_cq_update_entry;
reg r_hcmd_cq_rd_en;
wire [6:0] w_hcmd_slot_tag;
reg r_hcmd_slot_free_en;
reg [1:0] r_cql_type;
reg [19:0] r_cql_info;
reg [3:0] r_cpl_sq_qid;
reg [15:0] r_cpl_cid;
reg [14:0] r_cpl_status;
reg [31:0] r_cpl_specific;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_sq_head_ptr;
reg r_phase_tag;
reg r_tx_cq_mwr_req;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_cq_mwr_addr;
wire [31:0] w_cpl_dw0;
wire [31:0] w_cpl_dw1;
wire [31:0] w_cpl_dw2;
wire [31:0] w_cpl_dw3;
wire [8:0] w_cq_rst_n;
assign admin_cq_tail_ptr = r_admin_cq_tail_ptr;
assign io_cq1_tail_ptr = r_io_cq1_tail_ptr;
assign io_cq2_tail_ptr = r_io_cq2_tail_ptr;
assign io_cq3_tail_ptr = r_io_cq3_tail_ptr;
assign io_cq4_tail_ptr = r_io_cq4_tail_ptr;
assign io_cq5_tail_ptr = r_io_cq5_tail_ptr;
assign io_cq6_tail_ptr = r_io_cq6_tail_ptr;
assign io_cq7_tail_ptr = r_io_cq7_tail_ptr;
assign io_cq8_tail_ptr = r_io_cq8_tail_ptr;
assign hcmd_cq_rd_en = r_hcmd_cq_rd_en;
assign hcmd_cid_rd_addr = w_hcmd_slot_tag;
assign hcmd_slot_free_en = r_hcmd_slot_free_en;
assign hcmd_slot_invalid_tag = w_hcmd_slot_tag;
assign w_cpl_dw0 = r_cpl_specific;
assign w_cpl_dw1 = 0;
assign w_cpl_dw2 = {12'b0, r_cpl_sq_qid, 8'b0, r_sq_head_ptr};
assign w_cpl_dw3 = {r_cpl_status, r_phase_tag, r_cpl_cid};
assign tx_cq_mwr_req = r_tx_cq_mwr_req;
assign tx_cq_mwr_tag = LP_CPL_PCIE_TAG_PREFIX;
assign tx_cq_mwr_len = LP_CPL_SIZE;
assign tx_cq_mwr_addr = r_tx_cq_mwr_addr;
assign tx_cq_mwr_rd_data = {w_cpl_dw3, w_cpl_dw2, w_cpl_dw1, w_cpl_dw0};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(hcmd_cq_empty_n == 1)
next_state <= S_CPL_STATUS0;
else
next_state <= S_IDLE;
end
S_CPL_STATUS0: begin
next_state <= S_CPL_STATUS1;
end
S_CPL_STATUS1: begin
if(r_cql_type[0] == 1)
next_state <= S_CPL_STATUS2;
else if(r_cql_type[1] == 1)
next_state <= S_PCIE_SLOT_RELEASE;
else
next_state <= S_CPL_STATUS3;
end
S_CPL_STATUS2: begin
next_state <= S_CPL_STATUS3;
end
S_CPL_STATUS3: begin
next_state <= S_HEAD_PTR;
end
S_HEAD_PTR: begin
if(r_sq_is_valid == 1)
next_state <= S_PCIE_ADDR;
else
next_state <= S_IDLE;
end
S_PCIE_ADDR: begin
if(r_cq_is_valid == 1)
next_state <= S_PCIE_MWR_REQ;
else
next_state <= S_IDLE;
end
S_PCIE_MWR_REQ: begin
next_state <= S_PCIE_MWR_DATA_LAST;
end
S_PCIE_MWR_DATA_LAST: begin
if(tx_cq_mwr_data_last == 1)
next_state <= S_PCIE_MWR_DONE;
else
next_state <= S_PCIE_MWR_DATA_LAST;
end
S_PCIE_MWR_DONE: begin
if(r_cql_type[0] == 1)
next_state <= S_PCIE_SLOT_RELEASE;
else
next_state <= S_IDLE;
end
S_PCIE_SLOT_RELEASE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
assign w_hcmd_slot_tag = r_cql_info[6:0];
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CPL_STATUS0: begin
r_cql_type <= hcmd_cq_rd_data[1:0];
r_cql_info <= hcmd_cq_rd_data[21:2];
r_cpl_status[12:0] <= hcmd_cq_rd_data[34:22];
end
S_CPL_STATUS1: begin
r_cpl_cid <= r_cql_info[15:0];
r_cpl_sq_qid <= r_cql_info[19:16];
r_cpl_status[14:13] <= hcmd_cq_rd_data[1:0];
r_cpl_specific[31:0] <= hcmd_cq_rd_data[33:2];
end
S_CPL_STATUS2: begin
r_cpl_cid <= hcmd_cid_rd_data[15:0];
r_cpl_sq_qid <= hcmd_cid_rd_data[19:16];
end
S_CPL_STATUS3: begin
case(r_cpl_sq_qid) // synthesis parallel_case full_case
4'h0: begin
r_sq_is_valid <= sq_valid[0];
r_sq_cq_vec <= 4'h0;
r_sq_head_ptr <= admin_sq_head_ptr;
end
4'h1: begin
r_sq_is_valid <= sq_valid[1];
r_sq_cq_vec <= io_sq1_cq_vec;
r_sq_head_ptr <= io_sq1_head_ptr;
end
4'h2: begin
r_sq_is_valid <= sq_valid[2];
r_sq_cq_vec <= io_sq2_cq_vec;
r_sq_head_ptr <= io_sq2_head_ptr;
end
4'h3: begin
r_sq_is_valid <= sq_valid[3];
r_sq_cq_vec <= io_sq3_cq_vec;
r_sq_head_ptr <= io_sq3_head_ptr;
end
4'h4: begin
r_sq_is_valid <= sq_valid[4];
r_sq_cq_vec <= io_sq4_cq_vec;
r_sq_head_ptr <= io_sq4_head_ptr;
end
4'h5: begin
r_sq_is_valid <= sq_valid[5];
r_sq_cq_vec <= io_sq5_cq_vec;
r_sq_head_ptr <= io_sq5_head_ptr;
end
4'h6: begin
r_sq_is_valid <= sq_valid[6];
r_sq_cq_vec <= io_sq6_cq_vec;
r_sq_head_ptr <= io_sq6_head_ptr;
end
4'h7: begin
r_sq_is_valid <= sq_valid[7];
r_sq_cq_vec <= io_sq7_cq_vec;
r_sq_head_ptr <= io_sq7_head_ptr;
end
4'h8: begin
r_sq_is_valid <= sq_valid[8];
r_sq_cq_vec <= io_sq8_cq_vec;
r_sq_head_ptr <= io_sq8_head_ptr;
end
endcase
end
S_HEAD_PTR: begin
case(r_sq_cq_vec) // synthesis parallel_case full_case
4'h0: begin
r_cq_is_valid <= cq_valid[0];
r_tx_cq_mwr_addr <= admin_cq_bs_addr;
r_cq_tail_ptr <= r_admin_cq_tail_ptr;
r_phase_tag <= r_cq_phase_tag[0];
r_cq_valid_entry <= 9'b000000001;
end
4'h1: begin
r_cq_is_valid <= cq_valid[1];
r_tx_cq_mwr_addr <= io_cq1_bs_addr;
r_cq_tail_ptr <= r_io_cq1_tail_ptr;
r_phase_tag <= r_cq_phase_tag[1];
r_cq_valid_entry <= 9'b000000010;
end
4'h2: begin
r_cq_is_valid <= cq_valid[2];
r_tx_cq_mwr_addr <= io_cq2_bs_addr;
r_cq_tail_ptr <= r_io_cq2_tail_ptr;
r_phase_tag <= r_cq_phase_tag[2];
r_sq_head_ptr <= io_sq2_head_ptr;
r_cq_valid_entry <= 9'b000000100;
end
4'h3: begin
r_cq_is_valid <= cq_valid[3];
r_tx_cq_mwr_addr <= io_cq3_bs_addr;
r_cq_tail_ptr <= r_io_cq3_tail_ptr;
r_phase_tag <= r_cq_phase_tag[3];
r_sq_head_ptr <= io_sq3_head_ptr;
r_cq_valid_entry <= 9'b000001000;
end
4'h4: begin
r_cq_is_valid <= cq_valid[4];
r_tx_cq_mwr_addr <= io_cq4_bs_addr;
r_cq_tail_ptr <= r_io_cq4_tail_ptr;
r_phase_tag <= r_cq_phase_tag[4];
r_sq_head_ptr <= io_sq4_head_ptr;
r_cq_valid_entry <= 9'b000010000;
end
4'h5: begin
r_cq_is_valid <= cq_valid[5];
r_tx_cq_mwr_addr <= io_cq5_bs_addr;
r_cq_tail_ptr <= r_io_cq5_tail_ptr;
r_phase_tag <= r_cq_phase_tag[5];
r_sq_head_ptr <= io_sq5_head_ptr;
r_cq_valid_entry <= 9'b000100000;
end
4'h6: begin
r_cq_is_valid <= cq_valid[6];
r_tx_cq_mwr_addr <= io_cq6_bs_addr;
r_cq_tail_ptr <= r_io_cq6_tail_ptr;
r_phase_tag <= r_cq_phase_tag[6];
r_sq_head_ptr <= io_sq6_head_ptr;
r_cq_valid_entry <= 9'b001000000;
end
4'h7: begin
r_cq_is_valid <= cq_valid[7];
r_tx_cq_mwr_addr <= io_cq7_bs_addr;
r_cq_tail_ptr <= r_io_cq7_tail_ptr;
r_phase_tag <= r_cq_phase_tag[7];
r_sq_head_ptr <= io_sq7_head_ptr;
r_cq_valid_entry <= 9'b010000000;
end
4'h8: begin
r_cq_is_valid <= cq_valid[8];
r_tx_cq_mwr_addr <= io_cq8_bs_addr;
r_cq_tail_ptr <= r_io_cq8_tail_ptr;
r_phase_tag <= r_cq_phase_tag[8];
r_sq_head_ptr <= io_sq8_head_ptr;
r_cq_valid_entry <= 9'b100000000;
end
endcase
end
S_PCIE_ADDR: begin
r_tx_cq_mwr_addr <= r_tx_cq_mwr_addr + {r_cq_tail_ptr, 2'b0};
r_cq_tail_ptr <= r_cq_tail_ptr + 1;
end
S_PCIE_MWR_REQ: begin
end
S_PCIE_MWR_DATA_LAST: begin
end
S_PCIE_MWR_DONE: begin
end
S_PCIE_SLOT_RELEASE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS0: begin
r_hcmd_cq_rd_en <= 1;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS1: begin
r_hcmd_cq_rd_en <= 1;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS2: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS3: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_HEAD_PTR: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_ADDR: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_REQ: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 1;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_DATA_LAST: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_DONE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= r_cq_valid_entry;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_SLOT_RELEASE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 1;
end
default: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
endcase
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_admin_cq_tail_ptr <= 0;
r_cq_phase_tag[0] <= 1;
end
else begin
if(r_cq_update_entry[0] == 1) begin
if(r_admin_cq_tail_ptr == admin_cq_size) begin
r_admin_cq_tail_ptr <= 0;
r_cq_phase_tag[0] <= ~r_cq_phase_tag[0];
end
else begin
r_admin_cq_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_io_cq1_tail_ptr <= 0;
r_cq_phase_tag[1] <= 1;
end
else begin
if(r_cq_update_entry[1] == 1) begin
if(r_io_cq1_tail_ptr == io_cq1_size) begin
r_io_cq1_tail_ptr <= 0;
r_cq_phase_tag[1] <= ~r_cq_phase_tag[1];
end
else begin
r_io_cq1_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_io_cq2_tail_ptr <= 0;
r_cq_phase_tag[2] <= 1;
end
else begin
if(r_cq_update_entry[2] == 1) begin
if(r_io_cq2_tail_ptr == io_cq2_size) begin
r_io_cq2_tail_ptr <= 0;
r_cq_phase_tag[2] <= ~r_cq_phase_tag[2];
end
else begin
r_io_cq2_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_io_cq3_tail_ptr <= 0;
r_cq_phase_tag[3] <= 1;
end
else begin
if(r_cq_update_entry[3] == 1) begin
if(r_io_cq3_tail_ptr == io_cq3_size) begin
r_io_cq3_tail_ptr <= 0;
r_cq_phase_tag[3] <= ~r_cq_phase_tag[3];
end
else begin
r_io_cq3_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_io_cq4_tail_ptr <= 0;
r_cq_phase_tag[4] <= 1;
end
else begin
if(r_cq_update_entry[4] == 1) begin
if(r_io_cq4_tail_ptr == io_cq4_size) begin
r_io_cq4_tail_ptr <= 0;
r_cq_phase_tag[4] <= ~r_cq_phase_tag[4];
end
else begin
r_io_cq4_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_io_cq5_tail_ptr <= 0;
r_cq_phase_tag[5] <= 1;
end
else begin
if(r_cq_update_entry[5] == 1) begin
if(r_io_cq5_tail_ptr == io_cq5_size) begin
r_io_cq5_tail_ptr <= 0;
r_cq_phase_tag[5] <= ~r_cq_phase_tag[5];
end
else begin
r_io_cq5_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_io_cq6_tail_ptr <= 0;
r_cq_phase_tag[6] <= 1;
end
else begin
if(r_cq_update_entry[6] == 1) begin
if(r_io_cq6_tail_ptr == io_cq6_size) begin
r_io_cq6_tail_ptr <= 0;
r_cq_phase_tag[6] <= ~r_cq_phase_tag[6];
end
else begin
r_io_cq6_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_io_cq7_tail_ptr <= 0;
r_cq_phase_tag[7] <= 1;
end
else begin
if(r_cq_update_entry[7] == 1) begin
if(r_io_cq7_tail_ptr == io_cq7_size) begin
r_io_cq7_tail_ptr <= 0;
r_cq_phase_tag[7] <= ~r_cq_phase_tag[7];
end
else begin
r_io_cq7_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_io_cq8_tail_ptr <= 0;
r_cq_phase_tag[8] <= 1;
end
else begin
if(r_cq_update_entry[8] == 1) begin
if(r_io_cq8_tail_ptr == io_cq8_size) begin
r_io_cq8_tail_ptr <= 0;
r_cq_phase_tag[8] <= ~r_cq_phase_tag[8];
end
else begin
r_io_cq8_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
endmodule
|
module chan_fifo_reader
(reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and tx_q
input wire [31:0] adc_time ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is ready
output reg rdreq ; //actually an ack to the current fifodata
output reg skip ; //finish reading current packet
output reg [15:0] tx_q ; //top 16 bit output of fifodata
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
output reg underrun ;
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
output wire [14:0] debug;
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
`define JITTER 5
//Samples format
// 16 bits interleaved complex samples
`define QI16 4'b0
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter TIMESTAMP = 3'd2;
parameter WAIT = 3'd3;
parameter WAITSTROBE = 3'd4;
parameter SEND = 3'd5;
// Header format
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
/* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
always @(posedge tx_clock)
begin
if (reset)
begin
reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
end
else
begin
case (reader_state)
IDLE:
begin
/*
* reset all the variables and wait for a tx_strobe
* it is assumed that the ram connected to this fifo_reader
* is a short hand fifo meaning that the header to the next packet
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
/* Process header */
HEADER:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
begin
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 1;
reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
end
// Decide if we wait, send or discard samples
WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
// Outdated
if ((timestamp < adc_time) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
reader_state <= IDLE;
skip <= 1;
end
// Let's send it
else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
begin
trash <= 0;
reader_state <= WAITSTROBE;
end
else
reader_state <= WAIT;
end
else
reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
reader_state <= IDLE;
skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
case(samples_format)
`QI16:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
endcase
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
end
endmodule
|
module chan_fifo_reader
(reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and tx_q
input wire [31:0] adc_time ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is ready
output reg rdreq ; //actually an ack to the current fifodata
output reg skip ; //finish reading current packet
output reg [15:0] tx_q ; //top 16 bit output of fifodata
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
output reg underrun ;
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
output wire [14:0] debug;
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
`define JITTER 5
//Samples format
// 16 bits interleaved complex samples
`define QI16 4'b0
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter TIMESTAMP = 3'd2;
parameter WAIT = 3'd3;
parameter WAITSTROBE = 3'd4;
parameter SEND = 3'd5;
// Header format
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
/* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
always @(posedge tx_clock)
begin
if (reset)
begin
reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
end
else
begin
case (reader_state)
IDLE:
begin
/*
* reset all the variables and wait for a tx_strobe
* it is assumed that the ram connected to this fifo_reader
* is a short hand fifo meaning that the header to the next packet
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
/* Process header */
HEADER:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
begin
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 1;
reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
end
// Decide if we wait, send or discard samples
WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
// Outdated
if ((timestamp < adc_time) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
reader_state <= IDLE;
skip <= 1;
end
// Let's send it
else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
begin
trash <= 0;
reader_state <= WAITSTROBE;
end
else
reader_state <= WAIT;
end
else
reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
reader_state <= IDLE;
skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
case(samples_format)
`QI16:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
endcase
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [6:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [6:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [6:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [6:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [33:0] in = crc[33:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] code; // From test of Test.v
wire [4:0] len; // From test of Test.v
wire next; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.next (next),
.code (code[31:0]),
.len (len[4:0]),
// Inputs
.clk (clk),
.in (in[33:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {26'h0, next, len, code};
// What checksum will we end up with
`define EXPECTED_SUM 64'h5537fa30d49bf865
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
next, code, len,
// Inputs
clk, in
);
input clk;
input [33:0] in;
output next;
output [31:0] code;
output [4:0] len;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] code;
reg [4:0] len;
reg next;
// End of automatics
/*
#!/usr/bin/perl -w
srand(5);
my @used;
pat:
for (my $pat=0; 1; ) {
last if $pat > 196;
my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20;
my ($try, $val, $mask);
try:
for ($try=0; ; $try++) {
next pat if $try>50;
$val = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = int(rand()*2);
$val |= (1<<$bit) if $b;
}
$mask = (1<<(23-$len+1))-1;
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
next try if $used[$testval];
}
last;
}
my $bits = "";
my $val2 = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = ($val & (1<<$bit));
$bits .= $b?'1':'0';
}
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
$used[$testval]= 1; #printf "U%08x\n", $testval;
}
if ($try<90) {
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
$pat++;
}
}
*/
always @* begin
next = 1'b0;
code = 32'd0;
len = 5'b11111;
casez (in[31:8])
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
24'b000000??????????????????: begin
casez (in[33:32])
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
default: ;
endcase
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [33:0] in = crc[33:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] code; // From test of Test.v
wire [4:0] len; // From test of Test.v
wire next; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.next (next),
.code (code[31:0]),
.len (len[4:0]),
// Inputs
.clk (clk),
.in (in[33:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {26'h0, next, len, code};
// What checksum will we end up with
`define EXPECTED_SUM 64'h5537fa30d49bf865
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
next, code, len,
// Inputs
clk, in
);
input clk;
input [33:0] in;
output next;
output [31:0] code;
output [4:0] len;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] code;
reg [4:0] len;
reg next;
// End of automatics
/*
#!/usr/bin/perl -w
srand(5);
my @used;
pat:
for (my $pat=0; 1; ) {
last if $pat > 196;
my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20;
my ($try, $val, $mask);
try:
for ($try=0; ; $try++) {
next pat if $try>50;
$val = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = int(rand()*2);
$val |= (1<<$bit) if $b;
}
$mask = (1<<(23-$len+1))-1;
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
next try if $used[$testval];
}
last;
}
my $bits = "";
my $val2 = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = ($val & (1<<$bit));
$bits .= $b?'1':'0';
}
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
$used[$testval]= 1; #printf "U%08x\n", $testval;
}
if ($try<90) {
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
$pat++;
}
}
*/
always @* begin
next = 1'b0;
code = 32'd0;
len = 5'b11111;
casez (in[31:8])
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
24'b000000??????????????????: begin
casez (in[33:32])
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
default: ;
endcase
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [33:0] in = crc[33:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] code; // From test of Test.v
wire [4:0] len; // From test of Test.v
wire next; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.next (next),
.code (code[31:0]),
.len (len[4:0]),
// Inputs
.clk (clk),
.in (in[33:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {26'h0, next, len, code};
// What checksum will we end up with
`define EXPECTED_SUM 64'h5537fa30d49bf865
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
next, code, len,
// Inputs
clk, in
);
input clk;
input [33:0] in;
output next;
output [31:0] code;
output [4:0] len;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] code;
reg [4:0] len;
reg next;
// End of automatics
/*
#!/usr/bin/perl -w
srand(5);
my @used;
pat:
for (my $pat=0; 1; ) {
last if $pat > 196;
my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20;
my ($try, $val, $mask);
try:
for ($try=0; ; $try++) {
next pat if $try>50;
$val = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = int(rand()*2);
$val |= (1<<$bit) if $b;
}
$mask = (1<<(23-$len+1))-1;
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
next try if $used[$testval];
}
last;
}
my $bits = "";
my $val2 = 0;
for (my $bit=23; $bit>(23-$len); $bit--) {
my $b = ($val & (1<<$bit));
$bits .= $b?'1':'0';
}
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
$used[$testval]= 1; #printf "U%08x\n", $testval;
}
if ($try<90) {
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
$pat++;
}
}
*/
always @* begin
next = 1'b0;
code = 32'd0;
len = 5'b11111;
casez (in[31:8])
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
24'b000000??????????????????: begin
casez (in[33:32])
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
default: ;
endcase
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a;
reg [31:0] b;
wire [2:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
// verilator lint_off IMPLICIT
not #(0.108) NT0 (nt0, a[0]);
and #1 AN0 (an0, a[0], b[0]);
nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
or OR0 (or0, a[0], b[0]);
nor NR0 (nr0, a[0], b[0], b[2]);
xor (xo0, a[0], b[0]);
xnor (xn0, a[0], b[0], b[2]);
// verilator lint_on IMPLICIT
parameter BITS=32;
wire [BITS-1:0] ba;
buf BARRAY [BITS-1:0] (ba, a);
`ifdef verilator
specify
specparam CDS_LIBNAME = "foobar";
(nt0 *> nt0) = (0, 0);
endspecify
specify
// delay parameters
specparam
a$A1$Y = 1.0,
b$A0$Z = 1.0;
// path delays
(A1 *> Q) = (a$A1$Y, a$A1$Y);
(A0 *> Q) = (b$A0$Y, a$A0$Z);
endspecify
`endif
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 32'h18f6b034;
b <= 32'h834bf892;
end
if (cyc==2) begin
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf !== 3'b100) $stop;
if (nt0 !== 1'b1) $stop;
if (an0 !== 1'b0) $stop;
if (nd0 !== 1'b1) $stop;
if (or0 !== 1'b0) $stop;
if (nr0 !== 1'b1) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b1) $stop;
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (bf !== 3'b111) $stop;
if (nt0 !== 1'b0) $stop;
if (an0 !== 1'b1) $stop;
if (nd0 !== 1'b0) $stop;
if (or0 !== 1'b1) $stop;
if (nr0 !== 1'b0) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b0) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (int i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Check we can declare the same signal twice
loops = 0;
for (int i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (loops !== 17) $stop;
// Check type is correct
loops = 0;
for (byte unsigned i=5; i>4; i=i+1) begin
loops = loops + 1;
end
if (loops !== 251) $stop;
// Check large loops
loops = 0;
for (int i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (int i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Check we can declare the same signal twice
loops = 0;
for (int i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (loops !== 17) $stop;
// Check type is correct
loops = 0;
for (byte unsigned i=5; i>4; i=i+1) begin
loops = loops + 1;
end
if (loops !== 251) $stop;
// Check large loops
loops = 0;
for (int i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (int i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Check we can declare the same signal twice
loops = 0;
for (int i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (loops !== 17) $stop;
// Check type is correct
loops = 0;
for (byte unsigned i=5; i>4; i=i+1) begin
loops = loops + 1;
end
if (loops !== 251) $stop;
// Check large loops
loops = 0;
for (int i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] a;
reg [255:0] q;
reg [63:0] qq;
integer i;
always @* begin
for (i=0; i<256; i=i+1) begin
q[255-i] = a[i];
end
q[27:16] = 12'hfed;
for (i=0; i<64; i=i+1) begin
qq[63-i] = a[i];
end
qq[27:16] = 12'hfed;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x/%x %x\n", q, qq, a);
`endif
if (cyc==1) begin
a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
if (qq != 64'h64fe7e285fed892e) $stop;
end
if (cyc==3) begin
if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
if (qq != 64'h1da9cf939fed1250) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] a;
reg [255:0] q;
reg [63:0] qq;
integer i;
always @* begin
for (i=0; i<256; i=i+1) begin
q[255-i] = a[i];
end
q[27:16] = 12'hfed;
for (i=0; i<64; i=i+1) begin
qq[63-i] = a[i];
end
qq[27:16] = 12'hfed;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x/%x %x\n", q, qq, a);
`endif
if (cyc==1) begin
a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
if (qq != 64'h64fe7e285fed892e) $stop;
end
if (cyc==3) begin
if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
if (qq != 64'h1da9cf939fed1250) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] a;
reg [255:0] q;
reg [63:0] qq;
integer i;
always @* begin
for (i=0; i<256; i=i+1) begin
q[255-i] = a[i];
end
q[27:16] = 12'hfed;
for (i=0; i<64; i=i+1) begin
qq[63-i] = a[i];
end
qq[27:16] = 12'hfed;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x/%x %x\n", q, qq, a);
`endif
if (cyc==1) begin
a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
if (qq != 64'h64fe7e285fed892e) $stop;
end
if (cyc==3) begin
if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
if (qq != 64'h1da9cf939fed1250) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] narrow;
reg [63:0] quad;
reg [127:0] wide;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [6:0] index;
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
narrow <= 32'h0;
quad <= 64'h0;
wide <= 128'h0;
crc <= 8'hed;
index <= 7'h0;
end
else if (cyc<90) begin
index <= index + 7'h2;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
// verilator lint_off WIDTH
if (index < 9'd20) narrow[index +: 3] <= crc[2:0];
if (index < 9'd60) quad [index +: 3] <= crc[2:0];
if (index < 9'd120) wide [index +: 3] <= crc[2:0];
//
narrow[index[3:0]] <= ~narrow[index[3:0]];
quad [~index[3:0]]<= ~quad [~index[3:0]];
wide [~index[3:0]] <= ~wide [~index[3:0]];
// verilator lint_on WIDTH
end
else if (cyc==90) begin
wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6;
wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6;
wide[82 +: 4] <=4'h6;
end
else if (cyc==91) begin
wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1;
wide[41] <=1'b1; quad[41] <=1'b1;
wide[81] <=1'b1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide);
if (crc != 8'b01111001) $stop;
if (narrow != 32'h001661c7) $stop;
if (quad != 64'h16d49b6f64266039) $stop;
if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] narrow;
reg [63:0] quad;
reg [127:0] wide;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [6:0] index;
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
narrow <= 32'h0;
quad <= 64'h0;
wide <= 128'h0;
crc <= 8'hed;
index <= 7'h0;
end
else if (cyc<90) begin
index <= index + 7'h2;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
// verilator lint_off WIDTH
if (index < 9'd20) narrow[index +: 3] <= crc[2:0];
if (index < 9'd60) quad [index +: 3] <= crc[2:0];
if (index < 9'd120) wide [index +: 3] <= crc[2:0];
//
narrow[index[3:0]] <= ~narrow[index[3:0]];
quad [~index[3:0]]<= ~quad [~index[3:0]];
wide [~index[3:0]] <= ~wide [~index[3:0]];
// verilator lint_on WIDTH
end
else if (cyc==90) begin
wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6;
wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6;
wide[82 +: 4] <=4'h6;
end
else if (cyc==91) begin
wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1;
wide[41] <=1'b1; quad[41] <=1'b1;
wide[81] <=1'b1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide);
if (crc != 8'b01111001) $stop;
if (narrow != 32'h001661c7) $stop;
if (quad != 64'h16d49b6f64266039) $stop;
if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m3_inst.P2 = 2;
//defparam m3_inst.P3 = PAR;
defparam m3_inst.P3 = 3;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (FROMDEFP !== 19) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m3_inst.P2 = 2;
//defparam m3_inst.P3 = PAR;
defparam m3_inst.P3 = 3;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (FROMDEFP !== 19) $stop;
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * MSetRBT : Implementation of MSetInterface via Red-Black trees *)
(** Initial author: Andrew W. Appel, 2011.
Extra modifications by: Pierre Letouzey
The design decisions behind this implementation are described here:
- Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011.
http://www.cs.princeton.edu/~appel/papers/redblack.pdf
Additional suggested reading:
- Red-Black Trees in a Functional Setting by Chris Okasaki.
Journal of Functional Programming, 9(4):471-477, July 1999.
http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf
- Red-black trees with types, by Stefan Kahrs.
Journal of Functional Programming, 11(4), 425-432, 2001.
- Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey.
ESOP'04: European Symposium on Programming, pp. 370-384, 2004.
http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz
*)
Require MSetGenTree.
Require Import Bool List BinPos Pnat Setoid SetoidList PeanoNat.
Local Open Scope list_scope.
(* For nicer extraction, we create induction principles
only when needed *)
Local Unset Elimination Schemes.
(** An extra function not (yet?) in MSetInterface.S *)
Module Type MSetRemoveMin (Import M:MSetInterface.S).
Parameter remove_min : t -> option (elt * t).
Axiom remove_min_spec1 : forall s k s',
remove_min s = Some (k,s') ->
min_elt s = Some k /\ remove k s [=] s'.
Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s.
End MSetRemoveMin.
(** The type of color annotation. *)
Inductive color := Red | Black.
Module Color.
Definition t := color.
End Color.
(** * Ops : the pure functions *)
Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X.
(** ** Generic trees instantiated with color *)
(** We reuse a generic definition of trees where the information
parameter is a color. Functions like mem or fold are also
provided by this generic functor. *)
Include MSetGenTree.Ops X Color.
Definition t := tree.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
(** ** Basic tree *)
Definition singleton (k: elt) : tree := Bk Leaf k Leaf.
(** ** Changing root color *)
Definition makeBlack t :=
match t with
| Leaf => Leaf
| Node _ a x b => Bk a x b
end.
Definition makeRed t :=
match t with
| Leaf => Leaf
| Node _ a x b => Rd a x b
end.
(** ** Balancing *)
(** We adapt when one side is not a true red-black tree.
Both sides have the same black depth. *)
Definition lbal l k r :=
match l with
| Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r)
| Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r)
| _ => Bk l k r
end.
Definition rbal l k r :=
match r with
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** A variant of [rbal], with reverse pattern order.
Is it really useful ? Should we always use it ? *)
Definition rbal' l k r :=
match r with
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** Balancing with different black depth.
One side is almost a red-black tree, while the other is
a true red-black tree, but with black depth + 1.
Used in deletion. *)
Definition lbalS l k r :=
match l with
| Rd a x b => Rd (Bk a x b) k r
| _ =>
match r with
| Bk a y b => rbal' l k (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c))
| _ => Rd l k r (* impossible *)
end
end.
Definition rbalS l k r :=
match r with
| Rd b y c => Rd l k (Bk b y c)
| _ =>
match l with
| Bk a x b => lbal (Rd a x b) k r
| Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r)
| _ => Rd l k r (* impossible *)
end
end.
(** ** Insertion *)
Fixpoint ins x s :=
match s with
| Leaf => Rd Leaf x Leaf
| Node c l y r =>
match X.compare x y with
| Eq => s
| Lt =>
match c with
| Red => Rd (ins x l) y r
| Black => lbal (ins x l) y r
end
| Gt =>
match c with
| Red => Rd l y (ins x r)
| Black => rbal l y (ins x r)
end
end
end.
Definition add x s := makeBlack (ins x s).
(** ** Deletion *)
Fixpoint append (l:tree) : tree -> tree :=
match l with
| Leaf => fun r => r
| Node lc ll lx lr =>
fix append_l (r:tree) : tree :=
match r with
| Leaf => l
| Node rc rl rx rr =>
match lc, rc with
| Red, Red =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr)
| _ => Rd ll lx (Rd lrl rx rr)
end
| Black, Black =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr)
| _ => lbalS ll lx (Bk lrl rx rr)
end
| Black, Red => Rd (append_l rl) rx rr
| Red, Black => Rd ll lx (append lr r)
end
end
end.
Fixpoint del x t :=
match t with
| Leaf => Leaf
| Node _ a y b =>
match X.compare x y with
| Eq => append a b
| Lt =>
match a with
| Bk _ _ _ => lbalS (del x a) y b
| _ => Rd (del x a) y b
end
| Gt =>
match b with
| Bk _ _ _ => rbalS a y (del x b)
| _ => Rd a y (del x b)
end
end
end.
Definition remove x t := makeBlack (del x t).
(** ** Removing minimal element *)
Fixpoint delmin l x r : (elt * tree) :=
match l with
| Leaf => (x,r)
| Node lc ll lx lr =>
let (k,l') := delmin ll lx lr in
match lc with
| Black => (k, lbalS l' x r)
| Red => (k, Rd l' x r)
end
end.
Definition remove_min t : option (elt * tree) :=
match t with
| Leaf => None
| Node _ l x r =>
let (k,t) := delmin l x r in
Some (k, makeBlack t)
end.
(** ** Tree-ification
We rebuild a tree of size [if pred then n-1 else n] as soon
as the list [l] has enough elements *)
Definition bogus : tree * list elt := (Leaf, nil).
Notation treeify_t := (list elt -> tree * list elt).
Definition treeify_zero : treeify_t :=
fun acc => (Leaf,acc).
Definition treeify_one : treeify_t :=
fun acc => match acc with
| x::acc => (Rd Leaf x Leaf, acc)
| _ => bogus
end.
Definition treeify_cont (f g : treeify_t) : treeify_t :=
fun acc =>
match f acc with
| (l, x::acc) =>
match g acc with
| (r, acc) => (Bk l x r, acc)
end
| _ => bogus
end.
Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t :=
match n with
| xH => if pred then treeify_zero else treeify_one
| xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n)
| xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n)
end.
Fixpoint plength_aux (l:list elt)(p:positive) := match l with
| nil => p
| _::l => plength_aux l (Pos.succ p)
end.
Definition plength l := plength_aux l 1.
Definition treeify (l:list elt) :=
fst (treeify_aux true (plength l) l).
(** ** Filtering *)
Fixpoint filter_aux (f: elt -> bool) s acc :=
match s with
| Leaf => acc
| Node _ l k r =>
let acc := filter_aux f r acc in
if f k then filter_aux f l (k::acc)
else filter_aux f l acc
end.
Definition filter (f: elt -> bool) (s: t) : t :=
treeify (filter_aux f s nil).
Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 :=
match s with
| Leaf => (acc1,acc2)
| Node _ sl k sr =>
let (acc1, acc2) := partition_aux f sr acc1 acc2 in
if f k then partition_aux f sl (k::acc1) acc2
else partition_aux f sl acc1 (k::acc2)
end.
Definition partition (f: elt -> bool) (s:t) : t*t :=
let (ok,ko) := partition_aux f s nil nil in
(treeify ok, treeify ko).
(** ** Union, intersection, difference *)
(** union of the elements of [l1] and [l2] into a third [acc] list. *)
Fixpoint union_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => @rev_append _
| x::l1' =>
fix union_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => union_list l1' l2' (x::acc)
| Lt => union_l1 l2' (y::acc)
| Gt => union_list l1' l2 (x::acc)
end
end
end.
Definition linear_union s1 s2 :=
treeify (union_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint inter_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix inter_l1 l2 acc :=
match l2 with
| nil => acc
| y::l2' =>
match X.compare x y with
| Eq => inter_list l1' l2' (x::acc)
| Lt => inter_l1 l2' acc
| Gt => inter_list l1' l2 acc
end
end
end.
Definition linear_inter s1 s2 :=
treeify (inter_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint diff_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix diff_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => diff_list l1' l2' acc
| Lt => diff_l1 l2' acc
| Gt => diff_list l1' l2 (x::acc)
end
end
end.
Definition linear_diff s1 s2 :=
treeify (diff_list (rev_elements s1) (rev_elements s2) nil).
(** [compare_height] returns:
- [Lt] if [height s2] is at least twice [height s1];
- [Gt] if [height s1] is at least twice [height s2];
- [Eq] if heights are approximately equal.
Warning: this is not an equivalence relation! but who cares.... *)
Definition skip_red t :=
match t with
| Rd t' _ _ => t'
| _ => t
end.
Definition skip_black t :=
match skip_red t with
| Bk t' _ _ => t'
| t' => t'
end.
Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison :=
match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height (skip_black s1x') s1' s2' (skip_black s2x')
| _, Leaf, _, Node _ _ _ _ => Lt
| Node _ _ _ _, _, Leaf, _ => Gt
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf =>
compare_height (skip_black s1x') s1' s2' Leaf
| Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height Leaf s1' s2' (skip_black s2x')
| _, _, _, _ => Eq
end.
(** When one tree is quite smaller than the other, we simply
adds repeatively all its elements in the big one.
For trees of comparable height, we rather use [linear_union]. *)
Definition union (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => fold add t1 t2
| Gt => fold add t2 t1
| Eq => linear_union t1 t2
end.
Definition diff (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => negb (mem k t2)) t1
| Gt => fold remove t2 t1
| Eq => linear_diff t1 t2
end.
Definition inter (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => mem k t2) t1
| Gt => filter (fun k => mem k t1) t2
| Eq => linear_inter t1 t2
end.
End Ops.
(** * MakeRaw : the pure functions and their specifications *)
Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X.
Include Ops X.
(** Generic definition of binary-search-trees and proofs of
specifications for generic functions such as mem or fold. *)
Include MSetGenTree.Props X Color.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Local Hint Immediate MX.eq_sym.
Local Hint Unfold In lt_tree gt_tree Ok.
Local Hint Constructors InT bst.
Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok.
Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node.
Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans.
Local Hint Resolve elements_spec2.
(** ** Singleton set *)
Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x.
Proof.
unfold singleton; intuition_in.
Qed.
Instance singleton_ok x : Ok (singleton x).
Proof.
unfold singleton; auto.
Qed.
(** ** makeBlack, MakeRed *)
Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s).
Proof.
destruct s; simpl; ok.
Qed.
Instance makeRed_ok s `{Ok s} : Ok (makeRed s).
Proof.
destruct s; simpl; ok.
Qed.
(** ** Generic handling for red-matching and red-red-matching *)
Definition isblack t :=
match t with Bk _ _ _ => True | _ => False end.
Definition notblack t :=
match t with Bk _ _ _ => False | _ => True end.
Definition notred t :=
match t with Rd _ _ _ => False | _ => True end.
Definition rcase {A} f g t : A :=
match t with
| Rd a x b => f a x b
| _ => g t
end.
Inductive rspec {A} f g : tree -> A -> Prop :=
| rred a x b : rspec f g (Rd a x b) (f a x b)
| relse t : notred t -> rspec f g t (g t).
Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; now constructor.
Qed.
Definition rrcase {A} f g t : A :=
match t with
| Rd (Rd a x b) y c => f a x b y c
| Rd a x (Rd b y c) => f a x b y c
| _ => g t
end.
Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)).
Inductive rrspec {A} f g : tree -> A -> Prop :=
| rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c)
| rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c)
| rrelse t : notredred t -> rrspec f g t (g t).
Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
Definition rrcase' {A} f g t : A :=
match t with
| Rd a x (Rd b y c) => f a x b y c
| Rd (Rd a x b) y c => f a x b y c
| _ => g t
end.
Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
(** Balancing operations are instances of generic match *)
Fact lbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk a x b) y (Bk c k r))
(fun l => Bk l k r)
l
(lbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal'_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal' l k r).
Proof.
exact (rrmatch' _ _ _).
Qed.
Fact lbalS_match l x r :
rspec
(fun a y b => Rd (Bk a y b) x r)
(fun l =>
match r with
| Bk a y b => rbal' l x (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c))
| _ => Rd l x r
end)
l
(lbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
Fact rbalS_match l x r :
rspec
(fun a y b => Rd l x (Bk a y b))
(fun r =>
match l with
| Bk a y b => lbal (Rd a y b) x r
| Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r)
| _ => Rd l x r
end)
r
(rbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
(** ** Balancing for insertion *)
Lemma lbal_spec l x r y :
InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbal_match; intuition_in.
Qed.
Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (lbal l x r).
Proof.
destruct (lbal_match l x r); ok.
Qed.
Lemma rbal_spec l x r y :
InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal_match; intuition_in.
Qed.
Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal l x r).
Proof.
destruct (rbal_match l x r); ok.
Qed.
Lemma rbal'_spec l x r y :
InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal'_match; intuition_in.
Qed.
Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal' l x r).
Proof.
destruct (rbal'_match l x r); ok.
Qed.
Hint Rewrite In_node_iff In_leaf_iff
makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb.
Ltac descolor := destruct_all Color.t.
Ltac destree t := destruct t as [|[|] ? ? ?].
Ltac autorew := autorewrite with rb.
Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H.
(** ** Insertion *)
Lemma ins_spec : forall s x y,
InT y (ins x s) <-> X.eq y x \/ InT y s.
Proof.
induct s x.
- intuition_in.
- intuition_in. setoid_replace y with x; eauto.
- descolor; autorew; rewrite IHl; intuition_in.
- descolor; autorew; rewrite IHr; intuition_in.
Qed.
Hint Rewrite ins_spec : rb.
Instance ins_ok s x `{Ok s} : Ok (ins x s).
Proof.
induct s x; auto; descolor;
(apply lbal_ok || apply rbal_ok || ok); auto;
intros y; autorew; intuition; order.
Qed.
Lemma add_spec' s x y :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
unfold add. now autorew.
Qed.
Hint Rewrite add_spec' : rb.
Lemma add_spec s x y `{Ok s} :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
apply add_spec'.
Qed.
Instance add_ok s x `{Ok s} : Ok (add x s).
Proof.
unfold add; auto_tc.
Qed.
(** ** Balancing for deletion *)
Lemma lbalS_spec l x r y :
InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbalS_match.
- intros; autorew; intuition_in.
- clear l. intros l _.
destruct r as [|[|] rl rx rr].
* autorew. intuition_in.
* destree rl; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance lbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r).
Proof.
case lbalS_match; intros.
- ok.
- destruct r as [|[|] rl rx rr].
* ok.
* destruct rl as [|[|] rll rlx rlr]; intros; ok.
+ apply rbal'_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. autorew. apply rbal'_ok; ok.
Qed.
Lemma rbalS_spec l x r y :
InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbalS_match.
- intros; autorew; intuition_in.
- intros t _.
destruct l as [|[|] ll lx lr].
* autorew. intuition_in.
* destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance rbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r).
Proof.
case rbalS_match; intros.
- ok.
- destruct l as [|[|] ll lx lr].
* ok.
* destruct lr as [|[|] lrl lrx lrr]; intros; ok.
+ apply lbal_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. apply lbal_ok; ok.
Qed.
Hint Rewrite lbalS_spec rbalS_spec : rb.
(** ** Append for deletion *)
Ltac append_tac l r :=
induction l as [| lc ll _ lx lr IHlr];
[intro r; simpl
|induction r as [| rc rl IHrl rx rr _];
[simpl
|destruct lc, rc;
[specialize (IHlr rl); clear IHrl
|simpl;
assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial);
set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr;
specialize (IHlr r)
|change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr);
assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial);
set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr
|specialize (IHlr rl); clear IHrl]]].
Fact append_rr_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Rd ll lx a) x (Rd b rx rr))
(fun t => Rd ll lx (Rd t rx rr))
(append lr rl)
(append (Rd ll lx lr) (Rd rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Fact append_bb_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Bk ll lx a) x (Bk b rx rr))
(fun t => lbalS ll lx (Bk t rx rr))
(append lr rl)
(append (Bk ll lx lr) (Bk rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Lemma append_spec l r x :
InT x (append l r) <-> InT x l \/ InT x r.
Proof.
revert r.
append_tac l r; autorew; try tauto.
- (* Red / Red *)
revert IHlr; case append_rr_match;
[intros a y b | intros t Ht]; autorew; tauto.
- (* Black / Black *)
revert IHlr; case append_bb_match;
[intros a y b | intros t Ht]; autorew; tauto.
Qed.
Hint Rewrite append_spec : rb.
Lemma append_ok : forall x l r `{Ok l, Ok r},
lt_tree x l -> gt_tree x r -> Ok (append l r).
Proof.
append_tac l r.
- (* Leaf / _ *)
trivial.
- (* _ / Leaf *)
trivial.
- (* Red / Red *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_rr_match; intros; ok.
- (* Red / Black *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Red *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Black *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_bb_match; intros; ok.
apply lbalS_ok; ok.
Qed.
(** ** Deletion *)
Lemma del_spec : forall s x y `{Ok s},
InT y (del x s) <-> InT y s /\ ~X.eq y x.
Proof.
induct s x.
- intuition_in.
- autorew; intuition_in.
assert (X.lt y x') by eauto. order.
assert (X.lt x' y) by eauto. order.
order.
- destruct l as [|[|] ll lx lr]; autorew;
rewrite ?IHl by trivial; intuition_in; order.
- destruct r as [|[|] rl rx rr]; autorew;
rewrite ?IHr by trivial; intuition_in; order.
Qed.
Hint Rewrite del_spec : rb.
Instance del_ok s x `{Ok s} : Ok (del x s).
Proof.
induct s x.
- trivial.
- eapply append_ok; eauto.
- assert (lt_tree x' (del x l)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct l as [|[|] ll lx lr]; auto_tc.
- assert (gt_tree x' (del x r)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct r as [|[|] rl rx rr]; auto_tc.
Qed.
Lemma remove_spec s x y `{Ok s} :
InT y (remove x s) <-> InT y s /\ ~X.eq y x.
Proof.
unfold remove. now autorew.
Qed.
Hint Rewrite remove_spec : rb.
Instance remove_ok s x `{Ok s} : Ok (remove x s).
Proof.
unfold remove; auto_tc.
Qed.
(** ** Removing the minimal element *)
Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} :
delmin l y r = (x,s') ->
min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'.
Proof.
revert y r c x s' O.
induction l as [|lc ll IH ly lr _].
- simpl. intros y r _ x s' _. injection 1; intros; subst.
now rewrite MX.compare_refl.
- intros y r c x s' O.
simpl delmin.
specialize (IH ly lr). destruct delmin as (x0,s0).
destruct (IH lc x0 s0); clear IH; [ok|trivial|].
remember (Node lc ll ly lr) as l.
simpl min_elt in *.
intros E.
replace x0 with x in * by (destruct lc; now injection E).
split.
* subst l; intuition.
* assert (X.lt x y).
{ inversion_clear O.
assert (InT x l) by now apply min_elt_spec1. auto. }
simpl. case X.compare_spec; try order.
destruct lc; injection E; clear E; intros; subst l s0; auto.
Qed.
Lemma remove_min_spec1 s x s' `{Ok s}:
remove_min s = Some (x,s') ->
min_elt s = Some x /\ remove x s = s'.
Proof.
unfold remove_min.
destruct s as [|c l y r]; try easy.
generalize (delmin_spec l y r c).
destruct delmin as (x0,s0). intros D.
destruct (D x0 s0) as (->,<-); auto.
fold (remove x0 (Node c l y r)).
inversion_clear 1; auto.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
unfold remove_min.
destruct s as [|c l y r].
- easy.
- now destruct delmin.
Qed.
Lemma remove_min_ok (s:t) `{Ok s}:
match remove_min s with
| Some (_,s') => Ok s'
| None => True
end.
Proof.
generalize (remove_min_spec1 s).
destruct remove_min as [(x0,s0)|]; auto.
intros R. destruct (R x0 s0); auto. subst s0. auto_tc.
Qed.
(** ** Treeify *)
Notation ifpred p n := (if p then pred n else n%nat).
Definition treeify_invariant size (f:treeify_t) :=
forall acc,
size <= length acc ->
let (t,acc') := f acc in
cardinal t = size /\ acc = elements t ++ acc'.
Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero.
Proof.
intro. simpl. auto.
Qed.
Lemma treeify_one_spec : treeify_invariant 1 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_spec f g size1 size2 size :
treeify_invariant size1 f ->
treeify_invariant size2 g ->
size = S (size1 + size2) ->
treeify_invariant size (treeify_cont f g).
Proof.
intros Hf Hg EQ acc LE. unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (t1,acc1).
destruct Hf as (Hf1,Hf2).
{ transitivity size; trivial. subst. auto with arith. }
destruct acc1 as [|x acc1].
{ exfalso. revert LE. apply Nat.lt_nge. subst.
rewrite app_nil_r, <- elements_cardinal; auto with arith. }
specialize (Hg acc1).
destruct (g acc1) as (t2,acc2).
destruct Hg as (Hg1,Hg2).
{ revert LE. subst.
rewrite app_length, <- elements_cardinal. simpl.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
rewrite elements_node, app_ass. now subst.
Qed.
Lemma treeify_aux_spec n (p:bool) :
treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n).
Proof.
revert p.
induction n as [n|n|]; intros p; simpl treeify_aux.
- eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ].
Qed.
Lemma plength_aux_spec l p :
Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p.
Proof.
revert p. induction l; trivial. simpl plength_aux.
intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r.
Qed.
Lemma plength_spec l : Pos.to_nat (plength l) = S (length l).
Proof.
unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r.
Qed.
Lemma treeify_elements l : elements (treeify l) = l.
Proof.
assert (H := treeify_aux_spec (plength l) true l).
unfold treeify. destruct treeify_aux as (t,acc); simpl in *.
destruct H as (H,H'). { now rewrite plength_spec. }
subst l. rewrite plength_spec, app_length, <- elements_cardinal in *.
destruct acc.
* now rewrite app_nil_r.
* exfalso. revert H. simpl.
rewrite Nat.add_succ_r, Nat.add_comm.
apply Nat.succ_add_discr.
Qed.
Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l.
Proof.
intros. now rewrite <- elements_spec1, treeify_elements.
Qed.
Lemma treeify_ok l : sort X.lt l -> Ok (treeify l).
Proof.
intros. apply elements_sort_ok. rewrite treeify_elements; auto.
Qed.
(** ** Filter *)
Lemma filter_app A f (l l':list A) :
List.filter f (l ++ l') = List.filter f l ++ List.filter f l'.
Proof.
induction l as [|x l IH]; simpl; trivial.
destruct (f x); simpl; now rewrite IH.
Qed.
Lemma filter_aux_elements s f acc :
filter_aux f s acc = List.filter f (elements s) ++ acc.
Proof.
revert acc.
induction s as [|c l IHl x r IHr]; trivial.
intros acc.
rewrite elements_node, filter_app. simpl.
destruct (f x); now rewrite IHl, IHr, app_ass.
Qed.
Lemma filter_elements s f :
elements (filter f s) = List.filter f (elements s).
Proof.
unfold filter.
now rewrite treeify_elements, filter_aux_elements, app_nil_r.
Qed.
Lemma filter_spec s x f :
Proper (X.eq==>Logic.eq) f ->
(InT x (filter f s) <-> InT x s /\ f x = true).
Proof.
intros Hf.
rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1;
now auto_tc.
Qed.
Instance filter_ok s f `(Ok s) : Ok (filter f s).
Proof.
apply elements_sort_ok.
rewrite filter_elements.
apply filter_sort with X.eq; auto_tc.
Qed.
(** ** Partition *)
Lemma partition_aux_spec s f acc1 acc2 :
partition_aux f s acc1 acc2 =
(filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2).
Proof.
revert acc1 acc2.
induction s as [ | c l Hl x r Hr ]; simpl.
- trivial.
- intros acc1 acc2.
destruct (f x); simpl; now rewrite Hr, Hl.
Qed.
Lemma partition_spec s f :
partition f s = (filter f s, filter (fun x => negb (f x)) s).
Proof.
unfold partition, filter. now rewrite partition_aux_spec.
Qed.
Lemma partition_spec1 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (fst (partition f s)) (filter f s).
Proof. now rewrite partition_spec. Qed.
Lemma partition_spec2 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. now rewrite partition_spec. Qed.
Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
(** ** An invariant for binary list functions with accumulator. *)
Ltac inA :=
rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc.
Record INV l1 l2 acc : Prop := {
l1_sorted : sort X.lt (rev l1);
l2_sorted : sort X.lt (rev l2);
acc_sorted : sort X.lt acc;
l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y;
l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}.
Local Hint Resolve l1_sorted l2_sorted acc_sorted.
Lemma INV_init s1 s2 `(Ok s1, Ok s2) :
INV (rev_elements s1) (rev_elements s2) nil.
Proof.
rewrite !rev_elements_rev.
split; rewrite ?rev_involutive; auto; intros; now inA.
Qed.
Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc.
Proof.
destruct 1; now split.
Qed.
Lemma INV_drop x1 l1 l2 acc :
INV (x1 :: l1) l2 acc -> INV l1 l2 acc.
Proof.
intros (l1s,l2s,accs,l1a,l2a). simpl in *.
destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto.
split; auto.
Qed.
Lemma INV_eq x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 ->
INV l1 l2 (x1 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy, EQ; apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_lt x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 ->
INV (x1 :: l1) l2 (x2 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy; clear Hy. destruct Hx; [order|].
transitivity x1; auto. apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy. apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_rev l1 l2 acc :
INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc).
Proof.
intros. rewrite rev_append_rev.
apply SortA_app with X.eq; eauto with *.
intros x y. inA. eapply @l1_lt_acc; eauto.
Qed.
(** ** union *)
Lemma union_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eapply INV_rev, INV_sym; eauto.
- eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 (x2::acc)). eapply INV_lt; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_union s1 s2).
Proof.
unfold linear_union. now apply treeify_ok, union_list_ok, INV_init.
Qed.
Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) :
Ok (fold add s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2).
Proof.
unfold union. destruct compare_height; auto_tc.
Qed.
Lemma union_list_spec x l1 l2 acc :
InA X.eq x (union_list l1 l2 acc) <->
InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc.
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc; simpl.
* rewrite rev_append_rev. inA. tauto.
* case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 (x2::acc)), !InA_cons. tauto.
+ rewrite IH1, !InA_cons; tauto.
Qed.
Lemma linear_union_spec s1 s2 x :
InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold linear_union.
rewrite treeify_spec, union_list_spec, !rev_elements_rev.
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc.
tauto.
Qed.
Lemma fold_add_spec s1 s2 x :
InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl.
- rewrite InA_nil. tauto.
- unfold flip. rewrite add_spec', IHl, InA_cons. tauto.
Qed.
Lemma union_spec' s1 s2 x :
InT x (union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold union. destruct compare_height.
- apply linear_union_spec.
- apply fold_add_spec.
- rewrite fold_add_spec. tauto.
Qed.
Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2},
(InT y (union s1 s2) <-> InT y s1 \/ InT y s2).
Proof.
intros; apply union_spec'.
Qed.
(** ** inter *)
Lemma inter_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl.
- eauto.
- eauto.
- intros acc inv.
case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_drop; eauto.
Qed.
Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_inter s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init.
Qed.
Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2).
Proof.
unfold inter. destruct compare_height; auto_tc.
Qed.
Lemma inter_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (inter_list l1 l2 acc) <->
(InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* simpl. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 acc); auto. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2.
Proof.
unfold linear_inter.
rewrite !rev_elements_rev, treeify_spec, inter_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Local Instance mem_proper s `(Ok s) :
Proper (X.eq ==> Logic.eq) (fun k => mem k s).
Proof.
intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto.
now rewrite EQ.
Qed.
Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (inter s1 s2) <-> InT y s1 /\ InT y s2.
Proof.
unfold inter. destruct compare_height.
- now apply linear_inter_spec.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
Qed.
(** ** difference *)
Lemma diff_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eauto.
- unfold diff_list. eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_diff s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init.
Qed.
Instance fold_remove_ok s1 s2 `(Ok s2) :
Ok (fold remove s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2).
Proof.
unfold diff. destruct compare_height; auto_tc.
Qed.
Lemma diff_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (diff_list l1 l2 acc) <->
(InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* intros; simpl. rewrite rev_append_rev. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1; auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
left; split; auto. destruct 1. order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2.
Proof.
unfold linear_diff.
rewrite !rev_elements_rev, treeify_spec, diff_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Lemma fold_remove_spec s1 s2 x `(Ok s2) :
InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl; intros.
- rewrite InA_nil. intuition.
- unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto.
clear IHl. induction l; simpl; auto_tc.
Qed.
Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2.
Proof.
unfold diff. destruct compare_height.
- now apply linear_diff_spec.
- rewrite filter_spec, Bool.negb_true_iff,
<- Bool.not_true_iff_false, mem_spec;
intuition.
intros x1 x2 EQ. f_equal. now apply mem_proper.
- now apply fold_remove_spec.
Qed.
End MakeRaw.
(** * Balancing properties
We now prove that all operations preserve a red-black invariant,
and that trees have hence a logarithmic depth.
*)
Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X).
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Import M.MX.
(** ** Red-Black invariants *)
(** In a red-black tree :
- a red node has no red children
- the black depth at each node is the same along all paths.
The black depth is here an argument of the predicate. *)
Inductive rbt : nat -> tree -> Prop :=
| RB_Leaf : rbt 0 Leaf
| RB_Rd n l k r :
notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r)
| RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r).
(** A red-red tree is almost a red-black tree, except that it has
a _red_ root node which _may_ have red children. Note that a
red-red tree is hence non-empty, and all its strict subtrees
are red-black. *)
Inductive rrt (n:nat) : tree -> Prop :=
| RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r).
(** An almost-red-black tree is almost a red-black tree, except that
it's permitted to have two red nodes in a row at the very root (only).
We implement this notion by saying that a quasi-red-black tree
is either a red-black tree or a red-red tree. *)
Inductive arbt (n:nat)(t:tree) : Prop :=
| ARB_RB : rbt n t -> arbt n t
| ARB_RR : rrt n t -> arbt n t.
(** The main exported invariant : being a red-black tree for some
black depth. *)
Class Rbt (t:tree) := RBT : exists d, rbt d t.
(** ** Basic tactics and results about red-black *)
Scheme rbt_ind := Induction for rbt Sort Prop.
Local Hint Constructors rbt rrt arbt.
Local Hint Extern 0 (notred _) => (exact I).
Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction.
Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end.
Ltac nonzero n := destruct n as [|n]; [try split; invrb|].
Lemma rr_nrr_rb n t :
rrt n t -> notredred t -> rbt n t.
Proof.
destruct 1 as [l x r Hl Hr].
destruct l, r; descolor; invrb; auto.
Qed.
Local Hint Resolve rr_nrr_rb.
Lemma arb_nrr_rb n t :
arbt n t -> notredred t -> rbt n t.
Proof.
destruct 1; auto.
Qed.
Lemma arb_nr_rb n t :
arbt n t -> notred t -> rbt n t.
Proof.
destruct 1; destruct t; descolor; invrb; auto.
Qed.
Local Hint Resolve arb_nrr_rb arb_nr_rb.
(** ** A Red-Black tree has indeed a logarithmic depth *)
Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s.
Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s.
Proof.
induction 1.
- simpl; auto.
- replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
simpl maxdepth. simpl redcarac.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
now apply Nat.max_lub.
- simpl. rewrite <- Nat.succ_le_mono.
apply Nat.max_lub; eapply Nat.le_trans; eauto;
[destree l | destree r]; simpl;
rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith.
Qed.
Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s.
Proof.
induction 1; simpl.
- trivial.
- rewrite Nat.add_succ_r.
apply -> Nat.succ_le_mono.
replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
now apply Nat.min_glb.
- apply -> Nat.succ_le_mono. rewrite Nat.add_0_r.
apply Nat.min_glb; eauto with arith.
Qed.
Lemma maxdepth_upperbound s : Rbt s ->
maxdepth s <= 2 * Nat.log2 (S (cardinal s)).
Proof.
intros (n,H).
eapply Nat.le_trans; [eapply rb_maxdepth; eauto|].
transitivity (2*(n+redcarac s)).
- rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l.
rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r.
auto with arith.
- apply Nat.mul_le_mono_l.
transitivity (mindepth s).
+ now apply rb_mindepth.
+ apply mindepth_log_cardinal.
Qed.
Lemma maxdepth_lowerbound s : s<>Leaf ->
Nat.log2 (cardinal s) < maxdepth s.
Proof.
apply maxdepth_log_cardinal.
Qed.
(** ** Singleton *)
Lemma singleton_rb x : Rbt (singleton x).
Proof.
unfold singleton. exists 1; auto.
Qed.
(** ** [makeBlack] and [makeRed] *)
Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t).
Proof.
destruct t as [|[|] l x r].
- exists 0; auto.
- destruct 1; invrb; exists (S n); simpl; auto.
- exists n; auto.
Qed.
Lemma makeRed_rr t n :
rbt (S n) t -> notred t -> rrt n (makeRed t).
Proof.
destruct t as [|[|] l x r]; invrb; simpl; auto.
Qed.
(** ** Balancing *)
Lemma lbal_rb n l k r :
arbt n l -> rbt n r -> rbt (S n) (lbal l k r).
Proof.
case lbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal l k r).
Proof.
case rbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal'_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal' l k r).
Proof.
case rbal'_match; intros; desarb; invrb; auto.
Qed.
Lemma lbalS_rb n l x r :
arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r).
Proof.
intros Hl Hr Hr'.
destruct r as [|[|] rl rx rr]; invrb. clear Hr'.
revert Hl.
case lbalS_match.
- destruct 1; invrb; auto.
- intros. apply rbal'_rb; auto.
Qed.
Lemma lbalS_arb n l x r :
arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r).
Proof.
case lbalS_match.
- destruct 1; invrb; auto.
- clear l. intros l Hl Hl' Hr.
destruct r as [|[|] rl rx rr]; invrb.
* destruct rl as [|[|] rll rlx rlr]; invrb.
right; auto using rbal'_rb, makeRed_rr.
* left; apply rbal'_rb; auto.
Qed.
Lemma rbalS_rb n l x r :
rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r).
Proof.
intros Hl Hl' Hr.
destruct l as [|[|] ll lx lr]; invrb. clear Hl'.
revert Hr.
case rbalS_match.
- destruct 1; invrb; auto.
- intros. apply lbal_rb; auto.
Qed.
Lemma rbalS_arb n l x r :
rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r).
Proof.
case rbalS_match.
- destruct 2; invrb; auto.
- clear r. intros r Hr Hr' Hl.
destruct l as [|[|] ll lx lr]; invrb.
* destruct lr as [|[|] lrl lrx lrr]; invrb.
right; auto using lbal_rb, makeRed_rr.
* left; apply lbal_rb; auto.
Qed.
(** ** Insertion *)
(** The next lemmas combine simultaneous results about rbt and arbt.
A first solution here: statement with [if ... then ... else] *)
Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s.
Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B).
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ifred_or s A B : ifred s A B -> A\/B.
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ins_rr_rb x s n : rbt n s ->
ifred s (rrt n (ins x s)) (rbt n (ins x s)).
Proof.
induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ].
- simpl; auto.
- simpl. rewrite ifred_notred in * by trivial.
elim_compare x k; auto.
- rewrite ifred_notred by trivial.
unfold ins; fold ins. (* simpl is too much here ... *)
elim_compare x k.
* auto.
* apply lbal_rb; trivial. apply ifred_or in IHl; intuition.
* apply rbal_rb; trivial. apply ifred_or in IHr; intuition.
Qed.
Lemma ins_arb x s n : rbt n s -> arbt n (ins x s).
Proof.
intros H. apply (ins_rr_rb x), ifred_or in H. intuition.
Qed.
Instance add_rb x s : Rbt s -> Rbt (add x s).
Proof.
intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb.
Qed.
(** ** Deletion *)
(** A second approach here: statement with ... /\ ... *)
Lemma append_arb_rb n l r : rbt n l -> rbt n r ->
(arbt n (append l r)) /\
(notred l -> notred r -> rbt n (append l r)).
Proof.
revert r n.
append_tac l r.
- split; auto.
- split; auto.
- (* Red / Red *)
intros n. invrb.
case (IHlr n); auto; clear IHlr.
case append_rr_match.
+ intros a x b _ H; split; invrb.
assert (rbt n (Rd a x b)) by auto. invrb. auto.
+ split; invrb; auto.
- (* Red / Black *)
split; invrb. destruct (IHlr n) as (_,IH); auto.
- (* Black / Red *)
split; invrb. destruct (IHrl n) as (_,IH); auto.
- (* Black / Black *)
nonzero n.
invrb.
destruct (IHlr n) as (IH,_); auto; clear IHlr.
revert IH.
case append_bb_match.
+ intros a x b IH; split; destruct IH; invrb; auto.
+ split; [left | invrb]; auto using lbalS_rb.
Qed.
(** A third approach : Lemma ... with ... *)
Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s)
with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s).
Proof.
{ revert n.
induct s x; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_rb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. apply lbalS_arb; auto.
- assert (IHr' := del_rb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_arb; auto. }
{ revert n.
induct s x; try assumption; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_arb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto.
- assert (IHr' := del_arb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_rb; auto. }
Qed.
Instance remove_rb s x : Rbt s -> Rbt (remove x s).
Proof.
intros (n,H). unfold remove.
destruct s as [|[|] l y r].
- apply (makeBlack_rb n). auto.
- apply (makeBlack_rb n). left. apply del_rb; simpl; auto.
- nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto.
Qed.
(** ** Treeify *)
Definition treeify_rb_invariant size depth (f:treeify_t) :=
forall acc,
size <= length acc ->
rbt depth (fst (f acc)) /\
size + length (snd (f acc)) = length acc.
Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero.
Proof.
intros acc _; simpl; auto.
Qed.
Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_rb f g size1 size2 size d :
treeify_rb_invariant size1 d f ->
treeify_rb_invariant size2 d g ->
size = S (size1 + size2) ->
treeify_rb_invariant size (S d) (treeify_cont f g).
Proof.
intros Hf Hg H acc Hacc.
unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (l, acc1). simpl in *.
destruct Hf as (Hf1, Hf2). { subst. eauto with arith. }
destruct acc1 as [|x acc2]; simpl in *.
- exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2.
auto with arith.
- specialize (Hg acc2).
destruct (g acc2) as (r, acc3). simpl in *.
destruct Hg as (Hg1, Hg2).
{ revert Hacc.
rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
split; auto.
now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc.
Qed.
Lemma treeify_aux_rb n :
exists d, forall (b:bool),
treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n).
Proof.
induction n as [n (d,IHn)|n (d,IHn)| ].
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- exists 0; destruct b;
[ apply treeify_zero_rb | apply treeify_one_rb ].
Qed.
(** The black depth of [treeify l] is actually a log2, but
we don't need to mention that. *)
Instance treeify_rb l : Rbt (treeify l).
Proof.
unfold treeify.
destruct (treeify_aux_rb (plength l)) as (d,H).
exists d.
apply H.
now rewrite plength_spec.
Qed.
(** ** Filtering *)
Instance filter_rb f s : Rbt (filter f s).
Proof.
unfold filter; auto_tc.
Qed.
Instance partition_rb1 f s : Rbt (fst (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
Instance partition_rb2 f s : Rbt (snd (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
(** ** Union, intersection, difference *)
Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2).
Proof.
intros. unfold union, linear_union. destruct compare_height; auto_tc.
Qed.
Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2).
Proof.
intros. unfold inter, linear_inter. destruct compare_height; auto_tc.
Qed.
Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2).
Proof.
intros. unfold diff, linear_diff. destruct compare_height; auto_tc.
Qed.
End BalanceProps.
(** * Final Encapsulation
Now, in order to really provide a functor implementing [S], we
need to encapsulate everything into a type of binary search trees.
They also happen to be well-balanced, but this has no influence
on the correctness of operations, so we won't state this here,
see [BalanceProps] if you need more than just the MSet interface.
*)
Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin.
Module Make (X: Orders.OrderedType) <:
MSetInterface_S_Ext with Module E := X.
Module Raw. Include MakeRaw X. End Raw.
Include MSetInterface.Raw2Sets X Raw.
Definition opt_ok (x:option (elt * Raw.t)) :=
match x with Some (_,s) => Raw.Ok s | None => True end.
Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) :
option (elt * t) :=
match x as o return opt_ok o -> option (elt * t) with
| Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s')
| None => fun _ => None
end P.
Definition remove_min s : option (elt * t) :=
mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s).
Lemma remove_min_spec1 s x s' :
remove_min s = Some (x,s') ->
min_elt s = Some x /\ Equal (remove x s) s'.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl.
generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; try easy.
intros H U. injection U. clear U; intros; subst. simpl.
destruct (H x s0); auto. subst; intuition.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, Empty, In; simpl.
generalize (Raw.remove_min_spec2 s).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition.
Qed.
End Make.
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * MSetRBT : Implementation of MSetInterface via Red-Black trees *)
(** Initial author: Andrew W. Appel, 2011.
Extra modifications by: Pierre Letouzey
The design decisions behind this implementation are described here:
- Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011.
http://www.cs.princeton.edu/~appel/papers/redblack.pdf
Additional suggested reading:
- Red-Black Trees in a Functional Setting by Chris Okasaki.
Journal of Functional Programming, 9(4):471-477, July 1999.
http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf
- Red-black trees with types, by Stefan Kahrs.
Journal of Functional Programming, 11(4), 425-432, 2001.
- Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey.
ESOP'04: European Symposium on Programming, pp. 370-384, 2004.
http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz
*)
Require MSetGenTree.
Require Import Bool List BinPos Pnat Setoid SetoidList PeanoNat.
Local Open Scope list_scope.
(* For nicer extraction, we create induction principles
only when needed *)
Local Unset Elimination Schemes.
(** An extra function not (yet?) in MSetInterface.S *)
Module Type MSetRemoveMin (Import M:MSetInterface.S).
Parameter remove_min : t -> option (elt * t).
Axiom remove_min_spec1 : forall s k s',
remove_min s = Some (k,s') ->
min_elt s = Some k /\ remove k s [=] s'.
Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s.
End MSetRemoveMin.
(** The type of color annotation. *)
Inductive color := Red | Black.
Module Color.
Definition t := color.
End Color.
(** * Ops : the pure functions *)
Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X.
(** ** Generic trees instantiated with color *)
(** We reuse a generic definition of trees where the information
parameter is a color. Functions like mem or fold are also
provided by this generic functor. *)
Include MSetGenTree.Ops X Color.
Definition t := tree.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
(** ** Basic tree *)
Definition singleton (k: elt) : tree := Bk Leaf k Leaf.
(** ** Changing root color *)
Definition makeBlack t :=
match t with
| Leaf => Leaf
| Node _ a x b => Bk a x b
end.
Definition makeRed t :=
match t with
| Leaf => Leaf
| Node _ a x b => Rd a x b
end.
(** ** Balancing *)
(** We adapt when one side is not a true red-black tree.
Both sides have the same black depth. *)
Definition lbal l k r :=
match l with
| Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r)
| Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r)
| _ => Bk l k r
end.
Definition rbal l k r :=
match r with
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** A variant of [rbal], with reverse pattern order.
Is it really useful ? Should we always use it ? *)
Definition rbal' l k r :=
match r with
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** Balancing with different black depth.
One side is almost a red-black tree, while the other is
a true red-black tree, but with black depth + 1.
Used in deletion. *)
Definition lbalS l k r :=
match l with
| Rd a x b => Rd (Bk a x b) k r
| _ =>
match r with
| Bk a y b => rbal' l k (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c))
| _ => Rd l k r (* impossible *)
end
end.
Definition rbalS l k r :=
match r with
| Rd b y c => Rd l k (Bk b y c)
| _ =>
match l with
| Bk a x b => lbal (Rd a x b) k r
| Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r)
| _ => Rd l k r (* impossible *)
end
end.
(** ** Insertion *)
Fixpoint ins x s :=
match s with
| Leaf => Rd Leaf x Leaf
| Node c l y r =>
match X.compare x y with
| Eq => s
| Lt =>
match c with
| Red => Rd (ins x l) y r
| Black => lbal (ins x l) y r
end
| Gt =>
match c with
| Red => Rd l y (ins x r)
| Black => rbal l y (ins x r)
end
end
end.
Definition add x s := makeBlack (ins x s).
(** ** Deletion *)
Fixpoint append (l:tree) : tree -> tree :=
match l with
| Leaf => fun r => r
| Node lc ll lx lr =>
fix append_l (r:tree) : tree :=
match r with
| Leaf => l
| Node rc rl rx rr =>
match lc, rc with
| Red, Red =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr)
| _ => Rd ll lx (Rd lrl rx rr)
end
| Black, Black =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr)
| _ => lbalS ll lx (Bk lrl rx rr)
end
| Black, Red => Rd (append_l rl) rx rr
| Red, Black => Rd ll lx (append lr r)
end
end
end.
Fixpoint del x t :=
match t with
| Leaf => Leaf
| Node _ a y b =>
match X.compare x y with
| Eq => append a b
| Lt =>
match a with
| Bk _ _ _ => lbalS (del x a) y b
| _ => Rd (del x a) y b
end
| Gt =>
match b with
| Bk _ _ _ => rbalS a y (del x b)
| _ => Rd a y (del x b)
end
end
end.
Definition remove x t := makeBlack (del x t).
(** ** Removing minimal element *)
Fixpoint delmin l x r : (elt * tree) :=
match l with
| Leaf => (x,r)
| Node lc ll lx lr =>
let (k,l') := delmin ll lx lr in
match lc with
| Black => (k, lbalS l' x r)
| Red => (k, Rd l' x r)
end
end.
Definition remove_min t : option (elt * tree) :=
match t with
| Leaf => None
| Node _ l x r =>
let (k,t) := delmin l x r in
Some (k, makeBlack t)
end.
(** ** Tree-ification
We rebuild a tree of size [if pred then n-1 else n] as soon
as the list [l] has enough elements *)
Definition bogus : tree * list elt := (Leaf, nil).
Notation treeify_t := (list elt -> tree * list elt).
Definition treeify_zero : treeify_t :=
fun acc => (Leaf,acc).
Definition treeify_one : treeify_t :=
fun acc => match acc with
| x::acc => (Rd Leaf x Leaf, acc)
| _ => bogus
end.
Definition treeify_cont (f g : treeify_t) : treeify_t :=
fun acc =>
match f acc with
| (l, x::acc) =>
match g acc with
| (r, acc) => (Bk l x r, acc)
end
| _ => bogus
end.
Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t :=
match n with
| xH => if pred then treeify_zero else treeify_one
| xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n)
| xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n)
end.
Fixpoint plength_aux (l:list elt)(p:positive) := match l with
| nil => p
| _::l => plength_aux l (Pos.succ p)
end.
Definition plength l := plength_aux l 1.
Definition treeify (l:list elt) :=
fst (treeify_aux true (plength l) l).
(** ** Filtering *)
Fixpoint filter_aux (f: elt -> bool) s acc :=
match s with
| Leaf => acc
| Node _ l k r =>
let acc := filter_aux f r acc in
if f k then filter_aux f l (k::acc)
else filter_aux f l acc
end.
Definition filter (f: elt -> bool) (s: t) : t :=
treeify (filter_aux f s nil).
Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 :=
match s with
| Leaf => (acc1,acc2)
| Node _ sl k sr =>
let (acc1, acc2) := partition_aux f sr acc1 acc2 in
if f k then partition_aux f sl (k::acc1) acc2
else partition_aux f sl acc1 (k::acc2)
end.
Definition partition (f: elt -> bool) (s:t) : t*t :=
let (ok,ko) := partition_aux f s nil nil in
(treeify ok, treeify ko).
(** ** Union, intersection, difference *)
(** union of the elements of [l1] and [l2] into a third [acc] list. *)
Fixpoint union_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => @rev_append _
| x::l1' =>
fix union_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => union_list l1' l2' (x::acc)
| Lt => union_l1 l2' (y::acc)
| Gt => union_list l1' l2 (x::acc)
end
end
end.
Definition linear_union s1 s2 :=
treeify (union_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint inter_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix inter_l1 l2 acc :=
match l2 with
| nil => acc
| y::l2' =>
match X.compare x y with
| Eq => inter_list l1' l2' (x::acc)
| Lt => inter_l1 l2' acc
| Gt => inter_list l1' l2 acc
end
end
end.
Definition linear_inter s1 s2 :=
treeify (inter_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint diff_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix diff_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => diff_list l1' l2' acc
| Lt => diff_l1 l2' acc
| Gt => diff_list l1' l2 (x::acc)
end
end
end.
Definition linear_diff s1 s2 :=
treeify (diff_list (rev_elements s1) (rev_elements s2) nil).
(** [compare_height] returns:
- [Lt] if [height s2] is at least twice [height s1];
- [Gt] if [height s1] is at least twice [height s2];
- [Eq] if heights are approximately equal.
Warning: this is not an equivalence relation! but who cares.... *)
Definition skip_red t :=
match t with
| Rd t' _ _ => t'
| _ => t
end.
Definition skip_black t :=
match skip_red t with
| Bk t' _ _ => t'
| t' => t'
end.
Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison :=
match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height (skip_black s1x') s1' s2' (skip_black s2x')
| _, Leaf, _, Node _ _ _ _ => Lt
| Node _ _ _ _, _, Leaf, _ => Gt
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf =>
compare_height (skip_black s1x') s1' s2' Leaf
| Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height Leaf s1' s2' (skip_black s2x')
| _, _, _, _ => Eq
end.
(** When one tree is quite smaller than the other, we simply
adds repeatively all its elements in the big one.
For trees of comparable height, we rather use [linear_union]. *)
Definition union (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => fold add t1 t2
| Gt => fold add t2 t1
| Eq => linear_union t1 t2
end.
Definition diff (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => negb (mem k t2)) t1
| Gt => fold remove t2 t1
| Eq => linear_diff t1 t2
end.
Definition inter (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => mem k t2) t1
| Gt => filter (fun k => mem k t1) t2
| Eq => linear_inter t1 t2
end.
End Ops.
(** * MakeRaw : the pure functions and their specifications *)
Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X.
Include Ops X.
(** Generic definition of binary-search-trees and proofs of
specifications for generic functions such as mem or fold. *)
Include MSetGenTree.Props X Color.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Local Hint Immediate MX.eq_sym.
Local Hint Unfold In lt_tree gt_tree Ok.
Local Hint Constructors InT bst.
Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok.
Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node.
Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans.
Local Hint Resolve elements_spec2.
(** ** Singleton set *)
Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x.
Proof.
unfold singleton; intuition_in.
Qed.
Instance singleton_ok x : Ok (singleton x).
Proof.
unfold singleton; auto.
Qed.
(** ** makeBlack, MakeRed *)
Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s).
Proof.
destruct s; simpl; ok.
Qed.
Instance makeRed_ok s `{Ok s} : Ok (makeRed s).
Proof.
destruct s; simpl; ok.
Qed.
(** ** Generic handling for red-matching and red-red-matching *)
Definition isblack t :=
match t with Bk _ _ _ => True | _ => False end.
Definition notblack t :=
match t with Bk _ _ _ => False | _ => True end.
Definition notred t :=
match t with Rd _ _ _ => False | _ => True end.
Definition rcase {A} f g t : A :=
match t with
| Rd a x b => f a x b
| _ => g t
end.
Inductive rspec {A} f g : tree -> A -> Prop :=
| rred a x b : rspec f g (Rd a x b) (f a x b)
| relse t : notred t -> rspec f g t (g t).
Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; now constructor.
Qed.
Definition rrcase {A} f g t : A :=
match t with
| Rd (Rd a x b) y c => f a x b y c
| Rd a x (Rd b y c) => f a x b y c
| _ => g t
end.
Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)).
Inductive rrspec {A} f g : tree -> A -> Prop :=
| rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c)
| rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c)
| rrelse t : notredred t -> rrspec f g t (g t).
Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
Definition rrcase' {A} f g t : A :=
match t with
| Rd a x (Rd b y c) => f a x b y c
| Rd (Rd a x b) y c => f a x b y c
| _ => g t
end.
Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
(** Balancing operations are instances of generic match *)
Fact lbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk a x b) y (Bk c k r))
(fun l => Bk l k r)
l
(lbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal'_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal' l k r).
Proof.
exact (rrmatch' _ _ _).
Qed.
Fact lbalS_match l x r :
rspec
(fun a y b => Rd (Bk a y b) x r)
(fun l =>
match r with
| Bk a y b => rbal' l x (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c))
| _ => Rd l x r
end)
l
(lbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
Fact rbalS_match l x r :
rspec
(fun a y b => Rd l x (Bk a y b))
(fun r =>
match l with
| Bk a y b => lbal (Rd a y b) x r
| Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r)
| _ => Rd l x r
end)
r
(rbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
(** ** Balancing for insertion *)
Lemma lbal_spec l x r y :
InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbal_match; intuition_in.
Qed.
Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (lbal l x r).
Proof.
destruct (lbal_match l x r); ok.
Qed.
Lemma rbal_spec l x r y :
InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal_match; intuition_in.
Qed.
Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal l x r).
Proof.
destruct (rbal_match l x r); ok.
Qed.
Lemma rbal'_spec l x r y :
InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal'_match; intuition_in.
Qed.
Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal' l x r).
Proof.
destruct (rbal'_match l x r); ok.
Qed.
Hint Rewrite In_node_iff In_leaf_iff
makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb.
Ltac descolor := destruct_all Color.t.
Ltac destree t := destruct t as [|[|] ? ? ?].
Ltac autorew := autorewrite with rb.
Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H.
(** ** Insertion *)
Lemma ins_spec : forall s x y,
InT y (ins x s) <-> X.eq y x \/ InT y s.
Proof.
induct s x.
- intuition_in.
- intuition_in. setoid_replace y with x; eauto.
- descolor; autorew; rewrite IHl; intuition_in.
- descolor; autorew; rewrite IHr; intuition_in.
Qed.
Hint Rewrite ins_spec : rb.
Instance ins_ok s x `{Ok s} : Ok (ins x s).
Proof.
induct s x; auto; descolor;
(apply lbal_ok || apply rbal_ok || ok); auto;
intros y; autorew; intuition; order.
Qed.
Lemma add_spec' s x y :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
unfold add. now autorew.
Qed.
Hint Rewrite add_spec' : rb.
Lemma add_spec s x y `{Ok s} :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
apply add_spec'.
Qed.
Instance add_ok s x `{Ok s} : Ok (add x s).
Proof.
unfold add; auto_tc.
Qed.
(** ** Balancing for deletion *)
Lemma lbalS_spec l x r y :
InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbalS_match.
- intros; autorew; intuition_in.
- clear l. intros l _.
destruct r as [|[|] rl rx rr].
* autorew. intuition_in.
* destree rl; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance lbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r).
Proof.
case lbalS_match; intros.
- ok.
- destruct r as [|[|] rl rx rr].
* ok.
* destruct rl as [|[|] rll rlx rlr]; intros; ok.
+ apply rbal'_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. autorew. apply rbal'_ok; ok.
Qed.
Lemma rbalS_spec l x r y :
InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbalS_match.
- intros; autorew; intuition_in.
- intros t _.
destruct l as [|[|] ll lx lr].
* autorew. intuition_in.
* destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance rbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r).
Proof.
case rbalS_match; intros.
- ok.
- destruct l as [|[|] ll lx lr].
* ok.
* destruct lr as [|[|] lrl lrx lrr]; intros; ok.
+ apply lbal_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. apply lbal_ok; ok.
Qed.
Hint Rewrite lbalS_spec rbalS_spec : rb.
(** ** Append for deletion *)
Ltac append_tac l r :=
induction l as [| lc ll _ lx lr IHlr];
[intro r; simpl
|induction r as [| rc rl IHrl rx rr _];
[simpl
|destruct lc, rc;
[specialize (IHlr rl); clear IHrl
|simpl;
assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial);
set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr;
specialize (IHlr r)
|change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr);
assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial);
set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr
|specialize (IHlr rl); clear IHrl]]].
Fact append_rr_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Rd ll lx a) x (Rd b rx rr))
(fun t => Rd ll lx (Rd t rx rr))
(append lr rl)
(append (Rd ll lx lr) (Rd rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Fact append_bb_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Bk ll lx a) x (Bk b rx rr))
(fun t => lbalS ll lx (Bk t rx rr))
(append lr rl)
(append (Bk ll lx lr) (Bk rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Lemma append_spec l r x :
InT x (append l r) <-> InT x l \/ InT x r.
Proof.
revert r.
append_tac l r; autorew; try tauto.
- (* Red / Red *)
revert IHlr; case append_rr_match;
[intros a y b | intros t Ht]; autorew; tauto.
- (* Black / Black *)
revert IHlr; case append_bb_match;
[intros a y b | intros t Ht]; autorew; tauto.
Qed.
Hint Rewrite append_spec : rb.
Lemma append_ok : forall x l r `{Ok l, Ok r},
lt_tree x l -> gt_tree x r -> Ok (append l r).
Proof.
append_tac l r.
- (* Leaf / _ *)
trivial.
- (* _ / Leaf *)
trivial.
- (* Red / Red *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_rr_match; intros; ok.
- (* Red / Black *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Red *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Black *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_bb_match; intros; ok.
apply lbalS_ok; ok.
Qed.
(** ** Deletion *)
Lemma del_spec : forall s x y `{Ok s},
InT y (del x s) <-> InT y s /\ ~X.eq y x.
Proof.
induct s x.
- intuition_in.
- autorew; intuition_in.
assert (X.lt y x') by eauto. order.
assert (X.lt x' y) by eauto. order.
order.
- destruct l as [|[|] ll lx lr]; autorew;
rewrite ?IHl by trivial; intuition_in; order.
- destruct r as [|[|] rl rx rr]; autorew;
rewrite ?IHr by trivial; intuition_in; order.
Qed.
Hint Rewrite del_spec : rb.
Instance del_ok s x `{Ok s} : Ok (del x s).
Proof.
induct s x.
- trivial.
- eapply append_ok; eauto.
- assert (lt_tree x' (del x l)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct l as [|[|] ll lx lr]; auto_tc.
- assert (gt_tree x' (del x r)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct r as [|[|] rl rx rr]; auto_tc.
Qed.
Lemma remove_spec s x y `{Ok s} :
InT y (remove x s) <-> InT y s /\ ~X.eq y x.
Proof.
unfold remove. now autorew.
Qed.
Hint Rewrite remove_spec : rb.
Instance remove_ok s x `{Ok s} : Ok (remove x s).
Proof.
unfold remove; auto_tc.
Qed.
(** ** Removing the minimal element *)
Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} :
delmin l y r = (x,s') ->
min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'.
Proof.
revert y r c x s' O.
induction l as [|lc ll IH ly lr _].
- simpl. intros y r _ x s' _. injection 1; intros; subst.
now rewrite MX.compare_refl.
- intros y r c x s' O.
simpl delmin.
specialize (IH ly lr). destruct delmin as (x0,s0).
destruct (IH lc x0 s0); clear IH; [ok|trivial|].
remember (Node lc ll ly lr) as l.
simpl min_elt in *.
intros E.
replace x0 with x in * by (destruct lc; now injection E).
split.
* subst l; intuition.
* assert (X.lt x y).
{ inversion_clear O.
assert (InT x l) by now apply min_elt_spec1. auto. }
simpl. case X.compare_spec; try order.
destruct lc; injection E; clear E; intros; subst l s0; auto.
Qed.
Lemma remove_min_spec1 s x s' `{Ok s}:
remove_min s = Some (x,s') ->
min_elt s = Some x /\ remove x s = s'.
Proof.
unfold remove_min.
destruct s as [|c l y r]; try easy.
generalize (delmin_spec l y r c).
destruct delmin as (x0,s0). intros D.
destruct (D x0 s0) as (->,<-); auto.
fold (remove x0 (Node c l y r)).
inversion_clear 1; auto.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
unfold remove_min.
destruct s as [|c l y r].
- easy.
- now destruct delmin.
Qed.
Lemma remove_min_ok (s:t) `{Ok s}:
match remove_min s with
| Some (_,s') => Ok s'
| None => True
end.
Proof.
generalize (remove_min_spec1 s).
destruct remove_min as [(x0,s0)|]; auto.
intros R. destruct (R x0 s0); auto. subst s0. auto_tc.
Qed.
(** ** Treeify *)
Notation ifpred p n := (if p then pred n else n%nat).
Definition treeify_invariant size (f:treeify_t) :=
forall acc,
size <= length acc ->
let (t,acc') := f acc in
cardinal t = size /\ acc = elements t ++ acc'.
Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero.
Proof.
intro. simpl. auto.
Qed.
Lemma treeify_one_spec : treeify_invariant 1 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_spec f g size1 size2 size :
treeify_invariant size1 f ->
treeify_invariant size2 g ->
size = S (size1 + size2) ->
treeify_invariant size (treeify_cont f g).
Proof.
intros Hf Hg EQ acc LE. unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (t1,acc1).
destruct Hf as (Hf1,Hf2).
{ transitivity size; trivial. subst. auto with arith. }
destruct acc1 as [|x acc1].
{ exfalso. revert LE. apply Nat.lt_nge. subst.
rewrite app_nil_r, <- elements_cardinal; auto with arith. }
specialize (Hg acc1).
destruct (g acc1) as (t2,acc2).
destruct Hg as (Hg1,Hg2).
{ revert LE. subst.
rewrite app_length, <- elements_cardinal. simpl.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
rewrite elements_node, app_ass. now subst.
Qed.
Lemma treeify_aux_spec n (p:bool) :
treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n).
Proof.
revert p.
induction n as [n|n|]; intros p; simpl treeify_aux.
- eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ].
Qed.
Lemma plength_aux_spec l p :
Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p.
Proof.
revert p. induction l; trivial. simpl plength_aux.
intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r.
Qed.
Lemma plength_spec l : Pos.to_nat (plength l) = S (length l).
Proof.
unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r.
Qed.
Lemma treeify_elements l : elements (treeify l) = l.
Proof.
assert (H := treeify_aux_spec (plength l) true l).
unfold treeify. destruct treeify_aux as (t,acc); simpl in *.
destruct H as (H,H'). { now rewrite plength_spec. }
subst l. rewrite plength_spec, app_length, <- elements_cardinal in *.
destruct acc.
* now rewrite app_nil_r.
* exfalso. revert H. simpl.
rewrite Nat.add_succ_r, Nat.add_comm.
apply Nat.succ_add_discr.
Qed.
Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l.
Proof.
intros. now rewrite <- elements_spec1, treeify_elements.
Qed.
Lemma treeify_ok l : sort X.lt l -> Ok (treeify l).
Proof.
intros. apply elements_sort_ok. rewrite treeify_elements; auto.
Qed.
(** ** Filter *)
Lemma filter_app A f (l l':list A) :
List.filter f (l ++ l') = List.filter f l ++ List.filter f l'.
Proof.
induction l as [|x l IH]; simpl; trivial.
destruct (f x); simpl; now rewrite IH.
Qed.
Lemma filter_aux_elements s f acc :
filter_aux f s acc = List.filter f (elements s) ++ acc.
Proof.
revert acc.
induction s as [|c l IHl x r IHr]; trivial.
intros acc.
rewrite elements_node, filter_app. simpl.
destruct (f x); now rewrite IHl, IHr, app_ass.
Qed.
Lemma filter_elements s f :
elements (filter f s) = List.filter f (elements s).
Proof.
unfold filter.
now rewrite treeify_elements, filter_aux_elements, app_nil_r.
Qed.
Lemma filter_spec s x f :
Proper (X.eq==>Logic.eq) f ->
(InT x (filter f s) <-> InT x s /\ f x = true).
Proof.
intros Hf.
rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1;
now auto_tc.
Qed.
Instance filter_ok s f `(Ok s) : Ok (filter f s).
Proof.
apply elements_sort_ok.
rewrite filter_elements.
apply filter_sort with X.eq; auto_tc.
Qed.
(** ** Partition *)
Lemma partition_aux_spec s f acc1 acc2 :
partition_aux f s acc1 acc2 =
(filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2).
Proof.
revert acc1 acc2.
induction s as [ | c l Hl x r Hr ]; simpl.
- trivial.
- intros acc1 acc2.
destruct (f x); simpl; now rewrite Hr, Hl.
Qed.
Lemma partition_spec s f :
partition f s = (filter f s, filter (fun x => negb (f x)) s).
Proof.
unfold partition, filter. now rewrite partition_aux_spec.
Qed.
Lemma partition_spec1 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (fst (partition f s)) (filter f s).
Proof. now rewrite partition_spec. Qed.
Lemma partition_spec2 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. now rewrite partition_spec. Qed.
Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
(** ** An invariant for binary list functions with accumulator. *)
Ltac inA :=
rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc.
Record INV l1 l2 acc : Prop := {
l1_sorted : sort X.lt (rev l1);
l2_sorted : sort X.lt (rev l2);
acc_sorted : sort X.lt acc;
l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y;
l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}.
Local Hint Resolve l1_sorted l2_sorted acc_sorted.
Lemma INV_init s1 s2 `(Ok s1, Ok s2) :
INV (rev_elements s1) (rev_elements s2) nil.
Proof.
rewrite !rev_elements_rev.
split; rewrite ?rev_involutive; auto; intros; now inA.
Qed.
Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc.
Proof.
destruct 1; now split.
Qed.
Lemma INV_drop x1 l1 l2 acc :
INV (x1 :: l1) l2 acc -> INV l1 l2 acc.
Proof.
intros (l1s,l2s,accs,l1a,l2a). simpl in *.
destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto.
split; auto.
Qed.
Lemma INV_eq x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 ->
INV l1 l2 (x1 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy, EQ; apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_lt x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 ->
INV (x1 :: l1) l2 (x2 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy; clear Hy. destruct Hx; [order|].
transitivity x1; auto. apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy. apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_rev l1 l2 acc :
INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc).
Proof.
intros. rewrite rev_append_rev.
apply SortA_app with X.eq; eauto with *.
intros x y. inA. eapply @l1_lt_acc; eauto.
Qed.
(** ** union *)
Lemma union_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eapply INV_rev, INV_sym; eauto.
- eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 (x2::acc)). eapply INV_lt; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_union s1 s2).
Proof.
unfold linear_union. now apply treeify_ok, union_list_ok, INV_init.
Qed.
Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) :
Ok (fold add s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2).
Proof.
unfold union. destruct compare_height; auto_tc.
Qed.
Lemma union_list_spec x l1 l2 acc :
InA X.eq x (union_list l1 l2 acc) <->
InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc.
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc; simpl.
* rewrite rev_append_rev. inA. tauto.
* case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 (x2::acc)), !InA_cons. tauto.
+ rewrite IH1, !InA_cons; tauto.
Qed.
Lemma linear_union_spec s1 s2 x :
InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold linear_union.
rewrite treeify_spec, union_list_spec, !rev_elements_rev.
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc.
tauto.
Qed.
Lemma fold_add_spec s1 s2 x :
InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl.
- rewrite InA_nil. tauto.
- unfold flip. rewrite add_spec', IHl, InA_cons. tauto.
Qed.
Lemma union_spec' s1 s2 x :
InT x (union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold union. destruct compare_height.
- apply linear_union_spec.
- apply fold_add_spec.
- rewrite fold_add_spec. tauto.
Qed.
Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2},
(InT y (union s1 s2) <-> InT y s1 \/ InT y s2).
Proof.
intros; apply union_spec'.
Qed.
(** ** inter *)
Lemma inter_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl.
- eauto.
- eauto.
- intros acc inv.
case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_drop; eauto.
Qed.
Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_inter s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init.
Qed.
Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2).
Proof.
unfold inter. destruct compare_height; auto_tc.
Qed.
Lemma inter_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (inter_list l1 l2 acc) <->
(InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* simpl. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 acc); auto. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2.
Proof.
unfold linear_inter.
rewrite !rev_elements_rev, treeify_spec, inter_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Local Instance mem_proper s `(Ok s) :
Proper (X.eq ==> Logic.eq) (fun k => mem k s).
Proof.
intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto.
now rewrite EQ.
Qed.
Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (inter s1 s2) <-> InT y s1 /\ InT y s2.
Proof.
unfold inter. destruct compare_height.
- now apply linear_inter_spec.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
Qed.
(** ** difference *)
Lemma diff_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eauto.
- unfold diff_list. eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_diff s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init.
Qed.
Instance fold_remove_ok s1 s2 `(Ok s2) :
Ok (fold remove s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2).
Proof.
unfold diff. destruct compare_height; auto_tc.
Qed.
Lemma diff_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (diff_list l1 l2 acc) <->
(InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* intros; simpl. rewrite rev_append_rev. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1; auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
left; split; auto. destruct 1. order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2.
Proof.
unfold linear_diff.
rewrite !rev_elements_rev, treeify_spec, diff_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Lemma fold_remove_spec s1 s2 x `(Ok s2) :
InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl; intros.
- rewrite InA_nil. intuition.
- unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto.
clear IHl. induction l; simpl; auto_tc.
Qed.
Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2.
Proof.
unfold diff. destruct compare_height.
- now apply linear_diff_spec.
- rewrite filter_spec, Bool.negb_true_iff,
<- Bool.not_true_iff_false, mem_spec;
intuition.
intros x1 x2 EQ. f_equal. now apply mem_proper.
- now apply fold_remove_spec.
Qed.
End MakeRaw.
(** * Balancing properties
We now prove that all operations preserve a red-black invariant,
and that trees have hence a logarithmic depth.
*)
Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X).
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Import M.MX.
(** ** Red-Black invariants *)
(** In a red-black tree :
- a red node has no red children
- the black depth at each node is the same along all paths.
The black depth is here an argument of the predicate. *)
Inductive rbt : nat -> tree -> Prop :=
| RB_Leaf : rbt 0 Leaf
| RB_Rd n l k r :
notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r)
| RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r).
(** A red-red tree is almost a red-black tree, except that it has
a _red_ root node which _may_ have red children. Note that a
red-red tree is hence non-empty, and all its strict subtrees
are red-black. *)
Inductive rrt (n:nat) : tree -> Prop :=
| RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r).
(** An almost-red-black tree is almost a red-black tree, except that
it's permitted to have two red nodes in a row at the very root (only).
We implement this notion by saying that a quasi-red-black tree
is either a red-black tree or a red-red tree. *)
Inductive arbt (n:nat)(t:tree) : Prop :=
| ARB_RB : rbt n t -> arbt n t
| ARB_RR : rrt n t -> arbt n t.
(** The main exported invariant : being a red-black tree for some
black depth. *)
Class Rbt (t:tree) := RBT : exists d, rbt d t.
(** ** Basic tactics and results about red-black *)
Scheme rbt_ind := Induction for rbt Sort Prop.
Local Hint Constructors rbt rrt arbt.
Local Hint Extern 0 (notred _) => (exact I).
Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction.
Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end.
Ltac nonzero n := destruct n as [|n]; [try split; invrb|].
Lemma rr_nrr_rb n t :
rrt n t -> notredred t -> rbt n t.
Proof.
destruct 1 as [l x r Hl Hr].
destruct l, r; descolor; invrb; auto.
Qed.
Local Hint Resolve rr_nrr_rb.
Lemma arb_nrr_rb n t :
arbt n t -> notredred t -> rbt n t.
Proof.
destruct 1; auto.
Qed.
Lemma arb_nr_rb n t :
arbt n t -> notred t -> rbt n t.
Proof.
destruct 1; destruct t; descolor; invrb; auto.
Qed.
Local Hint Resolve arb_nrr_rb arb_nr_rb.
(** ** A Red-Black tree has indeed a logarithmic depth *)
Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s.
Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s.
Proof.
induction 1.
- simpl; auto.
- replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
simpl maxdepth. simpl redcarac.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
now apply Nat.max_lub.
- simpl. rewrite <- Nat.succ_le_mono.
apply Nat.max_lub; eapply Nat.le_trans; eauto;
[destree l | destree r]; simpl;
rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith.
Qed.
Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s.
Proof.
induction 1; simpl.
- trivial.
- rewrite Nat.add_succ_r.
apply -> Nat.succ_le_mono.
replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
now apply Nat.min_glb.
- apply -> Nat.succ_le_mono. rewrite Nat.add_0_r.
apply Nat.min_glb; eauto with arith.
Qed.
Lemma maxdepth_upperbound s : Rbt s ->
maxdepth s <= 2 * Nat.log2 (S (cardinal s)).
Proof.
intros (n,H).
eapply Nat.le_trans; [eapply rb_maxdepth; eauto|].
transitivity (2*(n+redcarac s)).
- rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l.
rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r.
auto with arith.
- apply Nat.mul_le_mono_l.
transitivity (mindepth s).
+ now apply rb_mindepth.
+ apply mindepth_log_cardinal.
Qed.
Lemma maxdepth_lowerbound s : s<>Leaf ->
Nat.log2 (cardinal s) < maxdepth s.
Proof.
apply maxdepth_log_cardinal.
Qed.
(** ** Singleton *)
Lemma singleton_rb x : Rbt (singleton x).
Proof.
unfold singleton. exists 1; auto.
Qed.
(** ** [makeBlack] and [makeRed] *)
Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t).
Proof.
destruct t as [|[|] l x r].
- exists 0; auto.
- destruct 1; invrb; exists (S n); simpl; auto.
- exists n; auto.
Qed.
Lemma makeRed_rr t n :
rbt (S n) t -> notred t -> rrt n (makeRed t).
Proof.
destruct t as [|[|] l x r]; invrb; simpl; auto.
Qed.
(** ** Balancing *)
Lemma lbal_rb n l k r :
arbt n l -> rbt n r -> rbt (S n) (lbal l k r).
Proof.
case lbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal l k r).
Proof.
case rbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal'_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal' l k r).
Proof.
case rbal'_match; intros; desarb; invrb; auto.
Qed.
Lemma lbalS_rb n l x r :
arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r).
Proof.
intros Hl Hr Hr'.
destruct r as [|[|] rl rx rr]; invrb. clear Hr'.
revert Hl.
case lbalS_match.
- destruct 1; invrb; auto.
- intros. apply rbal'_rb; auto.
Qed.
Lemma lbalS_arb n l x r :
arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r).
Proof.
case lbalS_match.
- destruct 1; invrb; auto.
- clear l. intros l Hl Hl' Hr.
destruct r as [|[|] rl rx rr]; invrb.
* destruct rl as [|[|] rll rlx rlr]; invrb.
right; auto using rbal'_rb, makeRed_rr.
* left; apply rbal'_rb; auto.
Qed.
Lemma rbalS_rb n l x r :
rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r).
Proof.
intros Hl Hl' Hr.
destruct l as [|[|] ll lx lr]; invrb. clear Hl'.
revert Hr.
case rbalS_match.
- destruct 1; invrb; auto.
- intros. apply lbal_rb; auto.
Qed.
Lemma rbalS_arb n l x r :
rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r).
Proof.
case rbalS_match.
- destruct 2; invrb; auto.
- clear r. intros r Hr Hr' Hl.
destruct l as [|[|] ll lx lr]; invrb.
* destruct lr as [|[|] lrl lrx lrr]; invrb.
right; auto using lbal_rb, makeRed_rr.
* left; apply lbal_rb; auto.
Qed.
(** ** Insertion *)
(** The next lemmas combine simultaneous results about rbt and arbt.
A first solution here: statement with [if ... then ... else] *)
Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s.
Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B).
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ifred_or s A B : ifred s A B -> A\/B.
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ins_rr_rb x s n : rbt n s ->
ifred s (rrt n (ins x s)) (rbt n (ins x s)).
Proof.
induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ].
- simpl; auto.
- simpl. rewrite ifred_notred in * by trivial.
elim_compare x k; auto.
- rewrite ifred_notred by trivial.
unfold ins; fold ins. (* simpl is too much here ... *)
elim_compare x k.
* auto.
* apply lbal_rb; trivial. apply ifred_or in IHl; intuition.
* apply rbal_rb; trivial. apply ifred_or in IHr; intuition.
Qed.
Lemma ins_arb x s n : rbt n s -> arbt n (ins x s).
Proof.
intros H. apply (ins_rr_rb x), ifred_or in H. intuition.
Qed.
Instance add_rb x s : Rbt s -> Rbt (add x s).
Proof.
intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb.
Qed.
(** ** Deletion *)
(** A second approach here: statement with ... /\ ... *)
Lemma append_arb_rb n l r : rbt n l -> rbt n r ->
(arbt n (append l r)) /\
(notred l -> notred r -> rbt n (append l r)).
Proof.
revert r n.
append_tac l r.
- split; auto.
- split; auto.
- (* Red / Red *)
intros n. invrb.
case (IHlr n); auto; clear IHlr.
case append_rr_match.
+ intros a x b _ H; split; invrb.
assert (rbt n (Rd a x b)) by auto. invrb. auto.
+ split; invrb; auto.
- (* Red / Black *)
split; invrb. destruct (IHlr n) as (_,IH); auto.
- (* Black / Red *)
split; invrb. destruct (IHrl n) as (_,IH); auto.
- (* Black / Black *)
nonzero n.
invrb.
destruct (IHlr n) as (IH,_); auto; clear IHlr.
revert IH.
case append_bb_match.
+ intros a x b IH; split; destruct IH; invrb; auto.
+ split; [left | invrb]; auto using lbalS_rb.
Qed.
(** A third approach : Lemma ... with ... *)
Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s)
with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s).
Proof.
{ revert n.
induct s x; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_rb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. apply lbalS_arb; auto.
- assert (IHr' := del_rb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_arb; auto. }
{ revert n.
induct s x; try assumption; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_arb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto.
- assert (IHr' := del_arb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_rb; auto. }
Qed.
Instance remove_rb s x : Rbt s -> Rbt (remove x s).
Proof.
intros (n,H). unfold remove.
destruct s as [|[|] l y r].
- apply (makeBlack_rb n). auto.
- apply (makeBlack_rb n). left. apply del_rb; simpl; auto.
- nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto.
Qed.
(** ** Treeify *)
Definition treeify_rb_invariant size depth (f:treeify_t) :=
forall acc,
size <= length acc ->
rbt depth (fst (f acc)) /\
size + length (snd (f acc)) = length acc.
Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero.
Proof.
intros acc _; simpl; auto.
Qed.
Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_rb f g size1 size2 size d :
treeify_rb_invariant size1 d f ->
treeify_rb_invariant size2 d g ->
size = S (size1 + size2) ->
treeify_rb_invariant size (S d) (treeify_cont f g).
Proof.
intros Hf Hg H acc Hacc.
unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (l, acc1). simpl in *.
destruct Hf as (Hf1, Hf2). { subst. eauto with arith. }
destruct acc1 as [|x acc2]; simpl in *.
- exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2.
auto with arith.
- specialize (Hg acc2).
destruct (g acc2) as (r, acc3). simpl in *.
destruct Hg as (Hg1, Hg2).
{ revert Hacc.
rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
split; auto.
now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc.
Qed.
Lemma treeify_aux_rb n :
exists d, forall (b:bool),
treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n).
Proof.
induction n as [n (d,IHn)|n (d,IHn)| ].
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- exists 0; destruct b;
[ apply treeify_zero_rb | apply treeify_one_rb ].
Qed.
(** The black depth of [treeify l] is actually a log2, but
we don't need to mention that. *)
Instance treeify_rb l : Rbt (treeify l).
Proof.
unfold treeify.
destruct (treeify_aux_rb (plength l)) as (d,H).
exists d.
apply H.
now rewrite plength_spec.
Qed.
(** ** Filtering *)
Instance filter_rb f s : Rbt (filter f s).
Proof.
unfold filter; auto_tc.
Qed.
Instance partition_rb1 f s : Rbt (fst (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
Instance partition_rb2 f s : Rbt (snd (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
(** ** Union, intersection, difference *)
Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2).
Proof.
intros. unfold union, linear_union. destruct compare_height; auto_tc.
Qed.
Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2).
Proof.
intros. unfold inter, linear_inter. destruct compare_height; auto_tc.
Qed.
Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2).
Proof.
intros. unfold diff, linear_diff. destruct compare_height; auto_tc.
Qed.
End BalanceProps.
(** * Final Encapsulation
Now, in order to really provide a functor implementing [S], we
need to encapsulate everything into a type of binary search trees.
They also happen to be well-balanced, but this has no influence
on the correctness of operations, so we won't state this here,
see [BalanceProps] if you need more than just the MSet interface.
*)
Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin.
Module Make (X: Orders.OrderedType) <:
MSetInterface_S_Ext with Module E := X.
Module Raw. Include MakeRaw X. End Raw.
Include MSetInterface.Raw2Sets X Raw.
Definition opt_ok (x:option (elt * Raw.t)) :=
match x with Some (_,s) => Raw.Ok s | None => True end.
Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) :
option (elt * t) :=
match x as o return opt_ok o -> option (elt * t) with
| Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s')
| None => fun _ => None
end P.
Definition remove_min s : option (elt * t) :=
mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s).
Lemma remove_min_spec1 s x s' :
remove_min s = Some (x,s') ->
min_elt s = Some x /\ Equal (remove x s) s'.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl.
generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; try easy.
intros H U. injection U. clear U; intros; subst. simpl.
destruct (H x s0); auto. subst; intuition.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, Empty, In; simpl.
generalize (Raw.remove_min_spec2 s).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition.
Qed.
End Make.
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.