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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done ,
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
output \escaped_normal ;
wire \escaped_normal = cyc[0];
output double__underscore ;
wire double__underscore = cyc[0];
// C doesn't allow leading non-alpha, so must escape
output \9num ;
wire \9num = cyc[0];
output \bra[ket]slash/dash-colon:9backslash\done ;
wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0];
wire \wire = cyc[0];
wire \check_alias = cyc[0];
wire \check:alias = cyc[0];
wire \check;alias = !cyc[0];
// These are *different entities*, bug83
wire [31:0] \a0.cyc = ~a0.cyc;
wire [31:0] \other.cyc = ~a0.cyc;
sub a0 (.cyc(cyc));
sub \mod.with_dot (.cyc(cyc));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (escaped_normal != cyc[0]) $stop;
if (\escaped_normal != cyc[0]) $stop;
if (double__underscore != cyc[0]) $stop;
if (\9num != cyc[0]) $stop;
if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop;
if (\wire != cyc[0]) $stop;
if (\check_alias != cyc[0]) $stop;
if (\check:alias != cyc[0]) $stop;
if (\check;alias != !cyc[0]) $stop;
if (\a0.cyc != ~cyc) $stop;
if (\other.cyc != ~cyc) $stop;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input [31:0] cyc
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done ,
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
output \escaped_normal ;
wire \escaped_normal = cyc[0];
output double__underscore ;
wire double__underscore = cyc[0];
// C doesn't allow leading non-alpha, so must escape
output \9num ;
wire \9num = cyc[0];
output \bra[ket]slash/dash-colon:9backslash\done ;
wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0];
wire \wire = cyc[0];
wire \check_alias = cyc[0];
wire \check:alias = cyc[0];
wire \check;alias = !cyc[0];
// These are *different entities*, bug83
wire [31:0] \a0.cyc = ~a0.cyc;
wire [31:0] \other.cyc = ~a0.cyc;
sub a0 (.cyc(cyc));
sub \mod.with_dot (.cyc(cyc));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (escaped_normal != cyc[0]) $stop;
if (\escaped_normal != cyc[0]) $stop;
if (double__underscore != cyc[0]) $stop;
if (\9num != cyc[0]) $stop;
if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop;
if (\wire != cyc[0]) $stop;
if (\check_alias != cyc[0]) $stop;
if (\check:alias != cyc[0]) $stop;
if (\check;alias != !cyc[0]) $stop;
if (\a0.cyc != ~cyc) $stop;
if (\other.cyc != ~cyc) $stop;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input [31:0] cyc
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
ma ma0 ();
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
function [31:0] getName; input fake; getName = "t "; endfunction
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==2) begin
if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop;
if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop;
end
if (cyc==3) begin
if (ma0. getName(1'b0) !== "ma ") $stop;
if (ma0.mb0. getName(1'b0) !== "mb ") $stop;
if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
if (cyc==4) begin
if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop;
end
if (cyc==5) begin
ma0. checkName(ma0. getName(1'b0));
ma0.mb0. checkName(ma0.mb0. getName(1'b0));
ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0));
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
function [31:0] getName; input fake; getName = "gmod"; endfunction
function [31:0] getGlob; input fake; getGlob = globali; endfunction
endmodule
module ma ();
`INLINE_MODULE
mb #(0) mb0 ();
reg [31:0] gName; initial gName = "ma ";
function [31:0] getName; input fake; getName = "ma "; endfunction
task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask
initial begin
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb0.getName(1'b0) !== "mb ") $stop;
if (mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
endmodule
module mb ();
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 ();
mc #(P2,1) mc1 ();
global_mod #(32'hf33d) global_cell2 ();
reg [31:0] gName; initial gName = "mb ";
function [31:0] getName; input fake; getName = "mb "; endfunction
function [31:0] getP2 ; input fake; getP2 = P2; endfunction
task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma. getName(1'b0) !== "ma ") $stop;
if ( getName(1'b0) !== "mb ") $stop;
if (mc1.getName(1'b0) !== "mc ") $stop;
ma. checkName (ma. gName);
/**/checkName ( gName);
mc1.checkName (mc1.gName);
ma. checkName (ma. getName(1'b0));
/**/checkName ( getName(1'b0));
mc1.checkName (mc1.getName(1'b0));
end
endmodule
module mc ();
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
reg [31:0] gName; initial gName = "mc ";
function [31:0] getName; input fake; getName = "mc "; endfunction
function [31:0] getP3 ; input fake; getP3 = P3; endfunction
task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb.getName(1'b0) !== "mb ") $stop;
if (mc.getName(1'b0) !== "mc ") $stop;
ma.checkName (ma.gName);
mb.checkName (mb.gName);
mc.checkName (mc.gName);
ma.checkName (ma.getName(1'b0));
mb.checkName (mb.getName(1'b0));
mc.checkName (mc.getName(1'b0));
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
ma ma0 ();
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
function [31:0] getName; input fake; getName = "t "; endfunction
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==2) begin
if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop;
if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop;
end
if (cyc==3) begin
if (ma0. getName(1'b0) !== "ma ") $stop;
if (ma0.mb0. getName(1'b0) !== "mb ") $stop;
if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
if (cyc==4) begin
if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop;
end
if (cyc==5) begin
ma0. checkName(ma0. getName(1'b0));
ma0.mb0. checkName(ma0.mb0. getName(1'b0));
ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0));
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
function [31:0] getName; input fake; getName = "gmod"; endfunction
function [31:0] getGlob; input fake; getGlob = globali; endfunction
endmodule
module ma ();
`INLINE_MODULE
mb #(0) mb0 ();
reg [31:0] gName; initial gName = "ma ";
function [31:0] getName; input fake; getName = "ma "; endfunction
task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask
initial begin
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb0.getName(1'b0) !== "mb ") $stop;
if (mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
endmodule
module mb ();
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 ();
mc #(P2,1) mc1 ();
global_mod #(32'hf33d) global_cell2 ();
reg [31:0] gName; initial gName = "mb ";
function [31:0] getName; input fake; getName = "mb "; endfunction
function [31:0] getP2 ; input fake; getP2 = P2; endfunction
task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma. getName(1'b0) !== "ma ") $stop;
if ( getName(1'b0) !== "mb ") $stop;
if (mc1.getName(1'b0) !== "mc ") $stop;
ma. checkName (ma. gName);
/**/checkName ( gName);
mc1.checkName (mc1.gName);
ma. checkName (ma. getName(1'b0));
/**/checkName ( getName(1'b0));
mc1.checkName (mc1.getName(1'b0));
end
endmodule
module mc ();
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
reg [31:0] gName; initial gName = "mc ";
function [31:0] getName; input fake; getName = "mc "; endfunction
function [31:0] getP3 ; input fake; getP3 = P3; endfunction
task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb.getName(1'b0) !== "mb ") $stop;
if (mc.getName(1'b0) !== "mc ") $stop;
ma.checkName (ma.gName);
mb.checkName (mb.gName);
mc.checkName (mc.gName);
ma.checkName (ma.getName(1'b0));
mb.checkName (mb.getName(1'b0));
mc.checkName (mc.getName(1'b0));
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = (N-1)*log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
wire [bw-1:0] signal_in;
output [bw-1:0] signal_out;
wire [bw-1:0] signal_out;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable & strobe_out)
begin
if(strobe_in)
integrator[0] <= #1 integrator[0] + pipeline[N-1];
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
for(i=0;i<N;i=i+1)
begin
differentiator[i] <= #1 0;
pipeline[i] <= #1 0;
end
end
else if (enable && strobe_in)
begin
differentiator[0] <= #1 signal_in_ext;
pipeline[0] <= #1 signal_in_ext - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
cic_int_shifter #(bw)
cic_int_shifter(rate,signal_out_unnorm,signal_out);
endmodule // cic_interp
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:57 09/06/2015
// Design Name:
// Module Name: FSM_Mult_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Mult_Function(
//INPUTS
input wire clk,
input wire rst,
input wire beg_FSM, //Be gin the multiply operation
input wire ack_FSM, //Is used in the last state, is an aknowledge signal
//ZERO PHASE EVALUATION SIGNALS
input wire zero_flag_i,
//Sgf_Operation *EVALUATION SIGNALS
input wire Mult_shift_i,
//round decoder EVALUATION SIGNALS
input wire round_flag_i,
//Adder round EV LUATION Signals
input wire Add_Overflow_i,
///////////////////////Load Signals/////////////////////////////////////7
//Oper Start_in load signal
output reg load_0_o,
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
output reg load_1_o,
//Exp operation result,
output reg load_2_o,
//Exp operation Overflow, Sgf operation second reg
output reg load_3_o,
//Adder round register
output reg load_4_o,
//Final result registers
output reg load_5_o,
//Barrel shifter registers
output reg load_6_o,
/////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
output reg ctrl_select_a_o,
output reg ctrl_select_b_o,
output reg [1:0] selector_b_o,
output reg ctrl_select_c_o,
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
output reg exp_op_o,
//Barrel shifter control signals
output reg shift_value_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
////////States///////////
//Zero Phase
parameter [3:0] start = 4'd0,//A
load_operands = 4'd1, //B) loads both operands to registers
extra64_1 = 4'd2,
add_exp = 4'd3, //C) Add both operands, evaluate underflow
subt_bias = 4'd4, //D) Subtract bias to the result, evaluate overflow, evaluate zero
mult_overf= 4'd5, //E) Evaluate overflow in Sgf multiplication for normalization case
mult_norn = 4'd6, //F) Overflow normalization, right shift significant and increment exponent
mult_no_norn = 4'd7, //G)No_normalization sgf
round_case = 4'd8, //H) Rounding evaluation. Positive= adder rounding, Negative,=Final load
adder_round = 4'd9, //I) add a 1 to the significand in case of rounding
round_norm = 4'd10, //J) Evaluate overflow in adder for normalization, Positive = normalization, same that F
final_load = 4'd11, //K) Load output registers
ready_flag = 4'd12; //L) Ready flag, wait for ack signal
//State registers
reg [3:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= start;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
load_0_o=0;
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
load_1_o=0;
//Exp operation result,
load_2_o=0;
//Exp operation Overflow, Sgf operation second reg
load_3_o=0;
//Adder round register
load_4_o=0;
//Final result registers
load_5_o=0;
load_6_o=0;
//////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
ctrl_select_a_o=0;
ctrl_select_b_o=0;
selector_b_o=2'b0;
ctrl_select_c_o=0;
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
exp_op_o=0;
//Barrel shifter control signals
shift_value_o=0;
//Internal reset signal
rst_int=0;
//Ready Signal
ready=0;
case(state_reg)
start:
begin
rst_int = 1;
if(beg_FSM)
state_next = load_operands; //Jump to the first state of the machine
end
//First Phase
load_operands:
begin
load_0_o = 1;
state_next = extra64_1;
end
extra64_1:
begin
state_next = add_exp;
end
//Zero Check
add_exp:
begin
load_1_o = 1;
load_2_o = 1;
ctrl_select_a_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = subt_bias;
end
subt_bias:
begin
load_2_o = 1;
load_3_o = 1;
exp_op_o = 1;
if(zero_flag_i)
state_next = ready_flag;
else
state_next = mult_overf;
end
mult_overf:
begin
if(Mult_shift_i) begin
ctrl_select_b_o =1;
selector_b_o =2'b10;
state_next = mult_norn;
end
else
state_next = mult_no_norn;
end
//Ninth Phase
mult_norn:
begin
shift_value_o =1;
load_6_o = 1;
load_2_o = 1;
load_3_o = 1;
//exp_op_o = 1;
state_next = round_case;
end
mult_no_norn:
begin
shift_value_o =0;
load_6_o = 1;
state_next = round_case;
end
round_case:
begin
if(round_flag_i) begin
ctrl_select_c_o =1;
state_next = adder_round;
end
else
state_next = final_load;
end
adder_round:
begin
load_4_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = round_norm;
end
round_norm:
begin
load_6_o = 1;
if(Add_Overflow_i)begin
shift_value_o =1;
load_2_o = 1;
load_3_o = 1;
state_next = final_load;
end
else begin
shift_value_o =0;
state_next = final_load;
end
end
final_load:
begin
load_5_o =1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(ack_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:57 09/06/2015
// Design Name:
// Module Name: FSM_Mult_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Mult_Function(
//INPUTS
input wire clk,
input wire rst,
input wire beg_FSM, //Be gin the multiply operation
input wire ack_FSM, //Is used in the last state, is an aknowledge signal
//ZERO PHASE EVALUATION SIGNALS
input wire zero_flag_i,
//Sgf_Operation *EVALUATION SIGNALS
input wire Mult_shift_i,
//round decoder EVALUATION SIGNALS
input wire round_flag_i,
//Adder round EV LUATION Signals
input wire Add_Overflow_i,
///////////////////////Load Signals/////////////////////////////////////7
//Oper Start_in load signal
output reg load_0_o,
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
output reg load_1_o,
//Exp operation result,
output reg load_2_o,
//Exp operation Overflow, Sgf operation second reg
output reg load_3_o,
//Adder round register
output reg load_4_o,
//Final result registers
output reg load_5_o,
//Barrel shifter registers
output reg load_6_o,
/////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
output reg ctrl_select_a_o,
output reg ctrl_select_b_o,
output reg [1:0] selector_b_o,
output reg ctrl_select_c_o,
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
output reg exp_op_o,
//Barrel shifter control signals
output reg shift_value_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
////////States///////////
//Zero Phase
parameter [3:0] start = 4'd0,//A
load_operands = 4'd1, //B) loads both operands to registers
extra64_1 = 4'd2,
add_exp = 4'd3, //C) Add both operands, evaluate underflow
subt_bias = 4'd4, //D) Subtract bias to the result, evaluate overflow, evaluate zero
mult_overf= 4'd5, //E) Evaluate overflow in Sgf multiplication for normalization case
mult_norn = 4'd6, //F) Overflow normalization, right shift significant and increment exponent
mult_no_norn = 4'd7, //G)No_normalization sgf
round_case = 4'd8, //H) Rounding evaluation. Positive= adder rounding, Negative,=Final load
adder_round = 4'd9, //I) add a 1 to the significand in case of rounding
round_norm = 4'd10, //J) Evaluate overflow in adder for normalization, Positive = normalization, same that F
final_load = 4'd11, //K) Load output registers
ready_flag = 4'd12; //L) Ready flag, wait for ack signal
//State registers
reg [3:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= start;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
load_0_o=0;
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
load_1_o=0;
//Exp operation result,
load_2_o=0;
//Exp operation Overflow, Sgf operation second reg
load_3_o=0;
//Adder round register
load_4_o=0;
//Final result registers
load_5_o=0;
load_6_o=0;
//////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
ctrl_select_a_o=0;
ctrl_select_b_o=0;
selector_b_o=2'b0;
ctrl_select_c_o=0;
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
exp_op_o=0;
//Barrel shifter control signals
shift_value_o=0;
//Internal reset signal
rst_int=0;
//Ready Signal
ready=0;
case(state_reg)
start:
begin
rst_int = 1;
if(beg_FSM)
state_next = load_operands; //Jump to the first state of the machine
end
//First Phase
load_operands:
begin
load_0_o = 1;
state_next = extra64_1;
end
extra64_1:
begin
state_next = add_exp;
end
//Zero Check
add_exp:
begin
load_1_o = 1;
load_2_o = 1;
ctrl_select_a_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = subt_bias;
end
subt_bias:
begin
load_2_o = 1;
load_3_o = 1;
exp_op_o = 1;
if(zero_flag_i)
state_next = ready_flag;
else
state_next = mult_overf;
end
mult_overf:
begin
if(Mult_shift_i) begin
ctrl_select_b_o =1;
selector_b_o =2'b10;
state_next = mult_norn;
end
else
state_next = mult_no_norn;
end
//Ninth Phase
mult_norn:
begin
shift_value_o =1;
load_6_o = 1;
load_2_o = 1;
load_3_o = 1;
//exp_op_o = 1;
state_next = round_case;
end
mult_no_norn:
begin
shift_value_o =0;
load_6_o = 1;
state_next = round_case;
end
round_case:
begin
if(round_flag_i) begin
ctrl_select_c_o =1;
state_next = adder_round;
end
else
state_next = final_load;
end
adder_round:
begin
load_4_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = round_norm;
end
round_norm:
begin
load_6_o = 1;
if(Add_Overflow_i)begin
shift_value_o =1;
load_2_o = 1;
load_3_o = 1;
state_next = final_load;
end
else begin
shift_value_o =0;
state_next = final_load;
end
end
final_load:
begin
load_5_o =1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(ack_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg genclk;
// verilator lint_off MULTIDRIVEN
reg [7:0] set_both;
// verilator lint_on MULTIDRIVEN
wire genthiscyc = ( (cyc % 2) == 1 );
always @ (posedge clk) begin
cyc <= cyc + 8'h1;
genclk <= genthiscyc;
set_both <= cyc;
$write ("SB set_both %x <= cyc %x\n", set_both, cyc);
if (genthiscyc) begin
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
end
else begin
if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @ (posedge genclk) begin
set_both <= ~ set_both;
$write ("SB set_both %x <= cyc %x\n", set_both, ~cyc);
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Peter Debacker.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [10:0] in;
reg signed[7:0] min;
reg signed[7:0] max;
wire signed[7:0] filtered_data;
reg signed[7:0] delay_minmax[31:0];
integer k;
initial begin
in = 11'b10000001000;
for(k=0;k<32;k=k+1)
delay_minmax[k] = 0;
end
assign filtered_data = $signed(in[10:3]);
always @(posedge clk) begin
in = in + 8;
`ifdef TEST_VERBOSE
$write("filtered_data: %d\n", filtered_data);
`endif
// delay line shift
for (k=31;k>0;k=k-1) begin
delay_minmax[k] = delay_minmax[k-1];
end
delay_minmax[0] = filtered_data;
`ifdef TEST_VERBOSE
$write("delay_minmax[0] = %d\n", delay_minmax[0]);
$write("delay_minmax[31] = %d\n", delay_minmax[31]);
`endif
// find min and max
min = 127;
max = -128;
`ifdef TEST_VERBOSE
$write("max init: %d\n", max);
$write("min init: %d\n", min);
`endif
for(k=0;k<32;k=k+1) begin
if ((delay_minmax[k]) > $signed(max))
max = delay_minmax[k];
if ((delay_minmax[k]) < $signed(min))
min = delay_minmax[k];
end
`ifdef TEST_VERBOSE
$write("max: %d\n", max);
$write("min: %d\n", min);
`endif
if (min == 127) begin
$stop;
end
else if (filtered_data >= -61) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [11:0] in_a;
reg [31:0] sel;
wire [2:0] out_x;
extractor #(4,3) extractor (
// Outputs
.out (out_x),
// Inputs
.in (in_a),
.sel (sel));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, in_a, sel, out_x);
if (cyc==1) begin
in_a <= 12'b001_101_111_010;
sel <= 32'd0;
end
if (cyc==2) begin
sel <= 32'd1;
if (out_x != 3'b010) $stop;
end
if (cyc==3) begin
sel <= 32'd2;
if (out_x != 3'b111) $stop;
end
if (cyc==4) begin
sel <= 32'd3;
if (out_x != 3'b101) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module extractor (/*AUTOARG*/
// Outputs
out,
// Inputs
in, sel
);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=2;
input [IN_WIDTH*OUT_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
input [31:0] sel;
wire [OUT_WIDTH-1:0] out = selector(in,sel);
function [OUT_WIDTH-1:0] selector;
input [IN_WIDTH*OUT_WIDTH-1:0] inv;
input [31:0] selv;
integer i;
begin
selector = 0;
for (i=0; i<OUT_WIDTH; i=i+1) begin
selector[i] = inv[selv*OUT_WIDTH+i];
end
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [125:0] a;
wire q;
sub sub (
.q (q),
.a (a),
.clk (clk));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 126'b1000;
end
if (cyc==2) begin
a <= 126'h1001;
end
if (cyc==3) begin
a <= 126'h1010;
end
if (cyc==4) begin
a <= 126'h1111;
if (q !== 1'b0) $stop;
end
if (cyc==5) begin
if (q !== 1'b1) $stop;
end
if (cyc==6) begin
if (q !== 1'b0) $stop;
end
if (cyc==7) begin
if (q !== 1'b0) $stop;
end
if (cyc==8) begin
if (q !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (
input clk,
input [125:0] a,
output reg q
);
// verilator public_module
reg [125:0] g_r;
wire [127:0] g_extend = { g_r, 1'b1, 1'b0 };
reg [6:0] sel;
wire g_sel = g_extend[sel];
always @ (posedge clk) begin
g_r <= a;
sel <= a[6:0];
q <= g_sel;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [125:0] a;
wire q;
sub sub (
.q (q),
.a (a),
.clk (clk));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 126'b1000;
end
if (cyc==2) begin
a <= 126'h1001;
end
if (cyc==3) begin
a <= 126'h1010;
end
if (cyc==4) begin
a <= 126'h1111;
if (q !== 1'b0) $stop;
end
if (cyc==5) begin
if (q !== 1'b1) $stop;
end
if (cyc==6) begin
if (q !== 1'b0) $stop;
end
if (cyc==7) begin
if (q !== 1'b0) $stop;
end
if (cyc==8) begin
if (q !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (
input clk,
input [125:0] a,
output reg q
);
// verilator public_module
reg [125:0] g_r;
wire [127:0] g_extend = { g_r, 1'b1, 1'b0 };
reg [6:0] sel;
wire g_sel = g_extend[sel];
always @ (posedge clk) begin
g_r <= a;
sel <= a[6:0];
q <= g_sel;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [7:0] crc;
genvar g;
wire [7:0] out_p1;
wire [15:0] out_p2;
wire [7:0] out_p3;
wire [7:0] out_p4;
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
wire [7:0] out_ef;
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
end
else if (cyc==1) begin
end
else if (cyc==3) begin
if (out_p1 !== 8'h2d) $stop;
if (out_p2 !== 16'h2d2d) $stop;
if (out_p3 !== 8'h78) $stop;
if (out_p4 !== 8'h44) $stop;
if (out_ef !== 8'hda) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module gencase (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter MODE = 0;
input [7:0] in;
output [7:0] out;
generate // : genblk1
begin
case (MODE)
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
endcase
end
endgenerate
endmodule
module paramed (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter WIDTH = 1;
parameter MODE = 0;
input [WIDTH-1:0] in;
output [WIDTH-1:0] out;
generate
if (MODE==0) initial $write("Mode=0\n");
// No else
endgenerate
`ifndef NC // for(genvar) unsupported
`ifndef ATSIM // for(genvar) unsupported
generate
// Empty loop body, local genvar
for (genvar j=0; j<3; j=j+1) begin end
// Ditto to make sure j has new scope
for (genvar j=0; j<5; j=j+1) begin end
endgenerate
`endif
`endif
generate
endgenerate
genvar i;
generate
if (MODE==0) begin
// Flip bitorder, direct assign method
for (i=0; i<WIDTH; i=i+1) begin
assign out[i] = in[WIDTH-i-1];
end
end
else if (MODE==1) begin
// Flip using instantiation
for (i=0; i<WIDTH; i=i+1) begin
integer from = WIDTH-i-1;
if (i==0) begin // Test if's within a for
mbuf m0 (.q(out[i]), .a(in[from]));
end
else begin
mbuf ma (.q(out[i]), .a(in[from]));
end
end
end
else begin
for (i=0; i<WIDTH; i=i+1) begin
mbuf ma (.q(out[i]), .a(in[i^1]));
end
end
endgenerate
endmodule
module mbuf (
input a,
output q
);
assign q = a;
endmodule
module enflop (clk, oe_e1, a,q);
parameter WIDTH=1;
input clk;
input oe_e1;
input [WIDTH-1:0] a;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] oe_r;
reg [WIDTH-1:0] q_r;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
enflop_one enflop_one
(.clk (clk),
.d (a[i]),
.q_r (q_r[i]));
always @(posedge clk) oe_r[i] <= oe_e1;
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
end
endgenerate
endmodule
module enflop_one (
input clk,
input d,
output reg q_r
);
always @(posedge clk) q_r <= d;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [7:0] crc;
genvar g;
wire [7:0] out_p1;
wire [15:0] out_p2;
wire [7:0] out_p3;
wire [7:0] out_p4;
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
wire [7:0] out_ef;
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
end
else if (cyc==1) begin
end
else if (cyc==3) begin
if (out_p1 !== 8'h2d) $stop;
if (out_p2 !== 16'h2d2d) $stop;
if (out_p3 !== 8'h78) $stop;
if (out_p4 !== 8'h44) $stop;
if (out_ef !== 8'hda) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module gencase (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter MODE = 0;
input [7:0] in;
output [7:0] out;
generate // : genblk1
begin
case (MODE)
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
endcase
end
endgenerate
endmodule
module paramed (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter WIDTH = 1;
parameter MODE = 0;
input [WIDTH-1:0] in;
output [WIDTH-1:0] out;
generate
if (MODE==0) initial $write("Mode=0\n");
// No else
endgenerate
`ifndef NC // for(genvar) unsupported
`ifndef ATSIM // for(genvar) unsupported
generate
// Empty loop body, local genvar
for (genvar j=0; j<3; j=j+1) begin end
// Ditto to make sure j has new scope
for (genvar j=0; j<5; j=j+1) begin end
endgenerate
`endif
`endif
generate
endgenerate
genvar i;
generate
if (MODE==0) begin
// Flip bitorder, direct assign method
for (i=0; i<WIDTH; i=i+1) begin
assign out[i] = in[WIDTH-i-1];
end
end
else if (MODE==1) begin
// Flip using instantiation
for (i=0; i<WIDTH; i=i+1) begin
integer from = WIDTH-i-1;
if (i==0) begin // Test if's within a for
mbuf m0 (.q(out[i]), .a(in[from]));
end
else begin
mbuf ma (.q(out[i]), .a(in[from]));
end
end
end
else begin
for (i=0; i<WIDTH; i=i+1) begin
mbuf ma (.q(out[i]), .a(in[i^1]));
end
end
endgenerate
endmodule
module mbuf (
input a,
output q
);
assign q = a;
endmodule
module enflop (clk, oe_e1, a,q);
parameter WIDTH=1;
input clk;
input oe_e1;
input [WIDTH-1:0] a;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] oe_r;
reg [WIDTH-1:0] q_r;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
enflop_one enflop_one
(.clk (clk),
.d (a[i]),
.q_r (q_r[i]));
always @(posedge clk) oe_r[i] <= oe_e1;
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
end
endgenerate
endmodule
module enflop_one (
input clk,
input d,
output reg q_r
);
always @(posedge clk) q_r <= d;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [7:0] crc;
genvar g;
wire [7:0] out_p1;
wire [15:0] out_p2;
wire [7:0] out_p3;
wire [7:0] out_p4;
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
wire [7:0] out_ef;
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
end
else if (cyc==1) begin
end
else if (cyc==3) begin
if (out_p1 !== 8'h2d) $stop;
if (out_p2 !== 16'h2d2d) $stop;
if (out_p3 !== 8'h78) $stop;
if (out_p4 !== 8'h44) $stop;
if (out_ef !== 8'hda) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module gencase (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter MODE = 0;
input [7:0] in;
output [7:0] out;
generate // : genblk1
begin
case (MODE)
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
endcase
end
endgenerate
endmodule
module paramed (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter WIDTH = 1;
parameter MODE = 0;
input [WIDTH-1:0] in;
output [WIDTH-1:0] out;
generate
if (MODE==0) initial $write("Mode=0\n");
// No else
endgenerate
`ifndef NC // for(genvar) unsupported
`ifndef ATSIM // for(genvar) unsupported
generate
// Empty loop body, local genvar
for (genvar j=0; j<3; j=j+1) begin end
// Ditto to make sure j has new scope
for (genvar j=0; j<5; j=j+1) begin end
endgenerate
`endif
`endif
generate
endgenerate
genvar i;
generate
if (MODE==0) begin
// Flip bitorder, direct assign method
for (i=0; i<WIDTH; i=i+1) begin
assign out[i] = in[WIDTH-i-1];
end
end
else if (MODE==1) begin
// Flip using instantiation
for (i=0; i<WIDTH; i=i+1) begin
integer from = WIDTH-i-1;
if (i==0) begin // Test if's within a for
mbuf m0 (.q(out[i]), .a(in[from]));
end
else begin
mbuf ma (.q(out[i]), .a(in[from]));
end
end
end
else begin
for (i=0; i<WIDTH; i=i+1) begin
mbuf ma (.q(out[i]), .a(in[i^1]));
end
end
endgenerate
endmodule
module mbuf (
input a,
output q
);
assign q = a;
endmodule
module enflop (clk, oe_e1, a,q);
parameter WIDTH=1;
input clk;
input oe_e1;
input [WIDTH-1:0] a;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] oe_r;
reg [WIDTH-1:0] q_r;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
enflop_one enflop_one
(.clk (clk),
.d (a[i]),
.q_r (q_r[i]));
always @(posedge clk) oe_r[i] <= oe_e1;
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
end
endgenerate
endmodule
module enflop_one (
input clk,
input d,
output reg q_r
);
always @(posedge clk) q_r <= d;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Check empty blocks
task EmptyFor;
/* verilator public */
integer i;
begin
for (i = 0; i < 2; i = i+1)
begin
end
end
endtask
// Check look unroller
reg signed signed_tests_only = 1'sb1;
integer total;
integer i;
reg [31:0] iu;
reg [31:0] dly_to_insure_was_unrolled [1:0];
reg [2:0] i3;
integer cyc; initial cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
case (cyc)
1: begin
// >= signed
total = 0;
for (i=5; i>=0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -21) $stop;
end
2: begin
// > signed
total = 0;
for (i=5; i>0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
3: begin
// < signed
total = 0;
for (i=1; i<5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -14) $stop;
end
4: begin
// <= signed
total = 0;
for (i=1; i<=5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
// UNSIGNED
5: begin
// >= unsigned
total = 0;
for (iu=5; iu>=1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
6: begin
// > unsigned
total = 0;
for (iu=5; iu>1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -18) $stop;
end
7: begin
// < unsigned
total = 0;
for (iu=1; iu<5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -14) $stop;
end
8: begin
// <= unsigned
total = 0;
for (iu=1; iu<=5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
//===
9: begin
// mostly cover a small index
total = 0;
for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
10: begin
// mostly cover a small index
total = 0;
for (i3=0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
11: begin
// width violation on <, causes extend
total = 0;
for (i3=3'd0; i3<7; i3=i3+1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
// width violation on <, causes extend signed
// Unsupported as yet
//===
19: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Check empty blocks
task EmptyFor;
/* verilator public */
integer i;
begin
for (i = 0; i < 2; i = i+1)
begin
end
end
endtask
// Check look unroller
reg signed signed_tests_only = 1'sb1;
integer total;
integer i;
reg [31:0] iu;
reg [31:0] dly_to_insure_was_unrolled [1:0];
reg [2:0] i3;
integer cyc; initial cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
case (cyc)
1: begin
// >= signed
total = 0;
for (i=5; i>=0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -21) $stop;
end
2: begin
// > signed
total = 0;
for (i=5; i>0; i=i-1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
3: begin
// < signed
total = 0;
for (i=1; i<5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -14) $stop;
end
4: begin
// <= signed
total = 0;
for (i=1; i<=5; i=i+1) begin
total = total - i -1;
dly_to_insure_was_unrolled[i] <= i;
end
if (total != -20) $stop;
end
// UNSIGNED
5: begin
// >= unsigned
total = 0;
for (iu=5; iu>=1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
6: begin
// > unsigned
total = 0;
for (iu=5; iu>1; iu=iu-1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -18) $stop;
end
7: begin
// < unsigned
total = 0;
for (iu=1; iu<5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -14) $stop;
end
8: begin
// <= unsigned
total = 0;
for (iu=1; iu<=5; iu=iu+1) begin
total = total - iu -1;
dly_to_insure_was_unrolled[iu] <= iu;
end
if (total != -20) $stop;
end
//===
9: begin
// mostly cover a small index
total = 0;
for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
10: begin
// mostly cover a small index
total = 0;
for (i3=0; i3<3'd7; i3=i3+3'd1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
11: begin
// width violation on <, causes extend
total = 0;
for (i3=3'd0; i3<7; i3=i3+1) begin
total = total - {29'd0,i3} -1;
dly_to_insure_was_unrolled[i3[0]] <= 0;
end
if (total != -28) $stop;
end
//===
// width violation on <, causes extend signed
// Unsupported as yet
//===
19: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic use_AnB;
logic [1:0] active_command [8:0];
logic [1:0] command_A [8:0];
logic [1:0] command_B [8:0];
logic [1:0] active_command2 [8:0];
logic [1:0] command_A2 [7:0];
logic [1:0] command_B2 [8:0];
logic [1:0] active_command3 [1:0][2:0][3:0];
logic [1:0] command_A3 [1:0][2:0][3:0];
logic [1:0] command_B3 [1:0][2:0][3:0];
logic [1:0] active_command4 [8:0];
logic [1:0] command_A4 [7:0];
logic [1:0] active_command5 [8:0];
logic [1:0] command_A5 [7:0];
// Single dimension assign
assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0];
// Assignment of entire arrays
assign active_command2 = (use_AnB) ? command_A2 : command_B2;
// Multi-dimension assign
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
// Supported: Delayed assigment with RHS Var == LHS Var
logic [7:0] arrd [7:0];
always_ff @(posedge clk) arrd[7:4] <= arrd[3:0];
// Unsupported: Non-delayed assigment with RHS Var == LHS Var
logic [7:0] arr [7:0];
assign arr[7:4] = arr[3:0];
// Delayed assign
always @(posedge clk) begin
active_command4[7:0] <= command_A4[8:0];
end
// Combinational assign
always_comb begin
active_command5[8:0] = command_A5[7:0];
end
endmodule : t
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
// surefire lint_off STMINI
// surefire lint_off CSEBEQ
input clk;
reg [7:0] a_to_clk_levm3;
reg [7:0] b_to_clk_levm1;
reg [7:0] c_com_levs10;
reg [7:0] d_to_clk_levm2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v
wire [7:0] n_from_clk_lev2; // From a of t_order_a.v
wire [7:0] o_from_com_levs11; // From a of t_order_a.v
wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v
wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
// End of automatics
reg [7:0] cyc; initial cyc=0;
t_order_a a (
.one (8'h1),
/*AUTOINST*/
// Outputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]),
.n_from_clk_lev2 (n_from_clk_lev2[7:0]),
.o_from_com_levs11 (o_from_com_levs11[7:0]),
.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
// Inputs
.clk (clk),
.a_to_clk_levm3 (a_to_clk_levm3[7:0]),
.b_to_clk_levm1 (b_to_clk_levm1[7:0]),
.c_com_levs10 (c_com_levs10[7:0]),
.d_to_clk_levm2 (d_to_clk_levm2[7:0]));
t_order_b b (
/*AUTOINST*/
// Outputs
.o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]),
// Inputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]));
reg [7:0] o_from_com_levs12;
reg [7:0] o_from_com_levs13;
always @ (/*AS*/o_from_com_levs11) begin
o_from_com_levs12 = o_from_com_levs11 + 8'h1;
o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize
o_from_com_levs13 = o_from_com_levs12;
end
reg sepassign_in;
// verilator lint_off UNOPTFLAT
wire [3:0] sepassign;
// verilator lint_on UNOPTFLAT
// verilator lint_off UNOPT
assign #0.1 sepassign[0] = 0,
sepassign[1] = sepassign[2],
sepassign[2] = sepassign[3],
sepassign[3] = sepassign_in;
wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
// verilator lint_on UNOPT
always @ (posedge clk) begin
cyc <= cyc+8'd1;
sepassign_in <= 0;
if (cyc == 8'd1) begin
a_to_clk_levm3 <= 0;
d_to_clk_levm2 <= 1;
b_to_clk_levm1 <= 1;
c_com_levs10 <= 2;
sepassign_in <= 1;
end
if (cyc == 8'd2) begin
if (sepassign !== 4'b1110) $stop;
end
if (cyc == 8'd3) begin
$display("%d %d %d %d",m_from_clk_lev1_r,
n_from_clk_lev2,
o_from_com_levs11,
o_from_comandclk_levs12);
if (m_from_clk_lev1_r !== 8'h2) $stop;
if (o_subfrom_clk_lev3 !== 8'h2) $stop;
if (n_from_clk_lev2 !== 8'h2) $stop;
if (o_from_com_levs11 !== 8'h3) $stop;
if (o_from_com_levs13 !== 8'h5) $stop;
if (o_from_comandclk_levs12 !== 8'h5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
// surefire lint_off STMINI
// surefire lint_off CSEBEQ
input clk;
reg [7:0] a_to_clk_levm3;
reg [7:0] b_to_clk_levm1;
reg [7:0] c_com_levs10;
reg [7:0] d_to_clk_levm2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v
wire [7:0] n_from_clk_lev2; // From a of t_order_a.v
wire [7:0] o_from_com_levs11; // From a of t_order_a.v
wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v
wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
// End of automatics
reg [7:0] cyc; initial cyc=0;
t_order_a a (
.one (8'h1),
/*AUTOINST*/
// Outputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]),
.n_from_clk_lev2 (n_from_clk_lev2[7:0]),
.o_from_com_levs11 (o_from_com_levs11[7:0]),
.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
// Inputs
.clk (clk),
.a_to_clk_levm3 (a_to_clk_levm3[7:0]),
.b_to_clk_levm1 (b_to_clk_levm1[7:0]),
.c_com_levs10 (c_com_levs10[7:0]),
.d_to_clk_levm2 (d_to_clk_levm2[7:0]));
t_order_b b (
/*AUTOINST*/
// Outputs
.o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]),
// Inputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]));
reg [7:0] o_from_com_levs12;
reg [7:0] o_from_com_levs13;
always @ (/*AS*/o_from_com_levs11) begin
o_from_com_levs12 = o_from_com_levs11 + 8'h1;
o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize
o_from_com_levs13 = o_from_com_levs12;
end
reg sepassign_in;
// verilator lint_off UNOPTFLAT
wire [3:0] sepassign;
// verilator lint_on UNOPTFLAT
// verilator lint_off UNOPT
assign #0.1 sepassign[0] = 0,
sepassign[1] = sepassign[2],
sepassign[2] = sepassign[3],
sepassign[3] = sepassign_in;
wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
// verilator lint_on UNOPT
always @ (posedge clk) begin
cyc <= cyc+8'd1;
sepassign_in <= 0;
if (cyc == 8'd1) begin
a_to_clk_levm3 <= 0;
d_to_clk_levm2 <= 1;
b_to_clk_levm1 <= 1;
c_com_levs10 <= 2;
sepassign_in <= 1;
end
if (cyc == 8'd2) begin
if (sepassign !== 4'b1110) $stop;
end
if (cyc == 8'd3) begin
$display("%d %d %d %d",m_from_clk_lev1_r,
n_from_clk_lev2,
o_from_com_levs11,
o_from_comandclk_levs12);
if (m_from_clk_lev1_r !== 8'h2) $stop;
if (o_subfrom_clk_lev3 !== 8'h2) $stop;
if (n_from_clk_lev2 !== 8'h2) $stop;
if (o_from_com_levs11 !== 8'h3) $stop;
if (o_from_com_levs13 !== 8'h5) $stop;
if (o_from_comandclk_levs12 !== 8'h5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
module flag_cdc(
clkA, FlagIn_clkA,
clkB, FlagOut_clkB,rst_n);
// clkA domain signals
input clkA, FlagIn_clkA;
input rst_n;
// clkB domain signals
input clkB;
output FlagOut_clkB;
reg FlagToggle_clkA;
reg [2:0] SyncA_clkB;
// this changes level when a flag is seen
always @(posedge clkA)
begin : cdc_clk_a
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end
else if(FlagIn_clkA == 1'b1) begin
FlagToggle_clkA <= ~FlagToggle_clkA;
end
end
// which can then be sync-ed to clkB
always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
// and recreate the flag from the level change
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule
*/
module flag_cdc(
input clkA,
input FlagIn_clkA,
input clkB,
output FlagOut_clkB,
input rst_n
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA = 1'b0;
always @(posedge clkA or negedge rst_n)
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end else begin
FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;
end
// which can then be sync-ed to clkB
reg [2:0] SyncA_clkB = 3'b0;
always @(posedge clkB or negedge rst_n)
if (rst_n == 1'b0) begin
SyncA_clkB <= 3'b0;
end else begin
SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
end
// and recreate the flag in clkB
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule |
/*
module flag_cdc(
clkA, FlagIn_clkA,
clkB, FlagOut_clkB,rst_n);
// clkA domain signals
input clkA, FlagIn_clkA;
input rst_n;
// clkB domain signals
input clkB;
output FlagOut_clkB;
reg FlagToggle_clkA;
reg [2:0] SyncA_clkB;
// this changes level when a flag is seen
always @(posedge clkA)
begin : cdc_clk_a
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end
else if(FlagIn_clkA == 1'b1) begin
FlagToggle_clkA <= ~FlagToggle_clkA;
end
end
// which can then be sync-ed to clkB
always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
// and recreate the flag from the level change
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule
*/
module flag_cdc(
input clkA,
input FlagIn_clkA,
input clkB,
output FlagOut_clkB,
input rst_n
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA = 1'b0;
always @(posedge clkA or negedge rst_n)
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end else begin
FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;
end
// which can then be sync-ed to clkB
reg [2:0] SyncA_clkB = 3'b0;
always @(posedge clkB or negedge rst_n)
if (rst_n == 1'b0) begin
SyncA_clkB <= 3'b0;
end else begin
SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
end
// and recreate the flag in clkB
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [31:0] r32;
wire [3:0] w4;
wire [4:0] w5;
assign w4 = NUMONES_8 ( r32[7:0] );
assign w5 = NUMONES_16( r32[15:0] );
function [3:0] NUMONES_8;
input [7:0] i8;
reg [7:0] i8;
begin
NUMONES_8 = 4'b1;
end
endfunction // NUMONES_8
function [4:0] NUMONES_16;
input [15:0] i16;
reg [15:0] i16;
begin
NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] ));
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
r32 <= 32'h12345678;
end
if (cyc==2) begin
if (w4 !== 1) $stop;
if (w5 !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [31:0] r32;
wire [3:0] w4;
wire [4:0] w5;
assign w4 = NUMONES_8 ( r32[7:0] );
assign w5 = NUMONES_16( r32[15:0] );
function [3:0] NUMONES_8;
input [7:0] i8;
reg [7:0] i8;
begin
NUMONES_8 = 4'b1;
end
endfunction // NUMONES_8
function [4:0] NUMONES_16;
input [15:0] i16;
reg [15:0] i16;
begin
NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] ));
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
r32 <= 32'h12345678;
end
if (cyc==2) begin
if (w4 !== 1) $stop;
if (w5 !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [9:0] in = crc[9:0];
/*AUTOWIRE*/
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[9:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [9:0] in;
reg a [9:0];
integer ai;
always @* begin
for (ai=0;ai<10;ai=ai+1) begin
a[ai]=in[ai];
end
end
reg [1:0] b [9:0];
integer j;
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
for (j=0; j<10; j=j+1) begin
if (a[j])
b[i][j] <= 1'b0;
else
b[i][j] <= 1'b1;
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef reg [2:0] threeansi_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef reg [2:0] three_t;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
threeansi_t outa; // From testa of TestAnsi.v
three_t outna; // From test of TestNonAnsi.v
// End of automatics
TestNonAnsi test (// Outputs
.out (outna),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
TestAnsi testa (// Outputs
.out (outa),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, outna, 1'b0, outa};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module TestNonAnsi (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
typedef reg [2:0] three_t;
input clk;
input three_t in;
output three_t out;
always @(posedge clk) begin
out <= ~in;
end
endmodule
module TestAnsi (
input clk,
input threeansi_t in,
output threeansi_t out
);
always @(posedge clk) begin
out <= ~in;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef reg [2:0] threeansi_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef reg [2:0] three_t;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
threeansi_t outa; // From testa of TestAnsi.v
three_t outna; // From test of TestNonAnsi.v
// End of automatics
TestNonAnsi test (// Outputs
.out (outna),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
TestAnsi testa (// Outputs
.out (outa),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, outna, 1'b0, outa};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module TestNonAnsi (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
typedef reg [2:0] three_t;
input clk;
input three_t in;
output three_t out;
always @(posedge clk) begin
out <= ~in;
end
endmodule
module TestAnsi (
input clk,
input threeansi_t in,
output threeansi_t out
);
always @(posedge clk) begin
out <= ~in;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef reg [2:0] threeansi_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef reg [2:0] three_t;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
threeansi_t outa; // From testa of TestAnsi.v
three_t outna; // From test of TestNonAnsi.v
// End of automatics
TestNonAnsi test (// Outputs
.out (outna),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
TestAnsi testa (// Outputs
.out (outa),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, outna, 1'b0, outa};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module TestNonAnsi (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
typedef reg [2:0] three_t;
input clk;
input three_t in;
output three_t out;
always @(posedge clk) begin
out <= ~in;
end
endmodule
module TestAnsi (
input clk,
input threeansi_t in,
output threeansi_t out
);
always @(posedge clk) begin
out <= ~in;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [1:0] d_bit2;
logic [1:0] d_logic2;
reg [1:0] d_reg2;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
// Declarations using var
var byte v_b;
`ifndef VCS
var [2:0] v_b3;
var signed [2:0] v_bs;
`endif
// verilator lint_off WIDTH
localparam p_implicit = {96{1'b1}};
localparam [89:0] p_explicit = {96{1'b1}};
localparam byte p_byte = {96{1'b1}};
localparam shortint p_shortint = {96{1'b1}};
localparam int p_int = {96{1'b1}};
localparam longint p_longint = {96{1'b1}};
localparam integer p_integer = {96{1'b1}};
localparam reg p_reg = {96{1'b1}};
localparam bit p_bit = {96{1'b1}};
localparam logic p_logic = {96{1'b1}};
localparam reg [0:0] p_reg1 = {96{1'b1}};
localparam bit [0:0] p_bit1 = {96{1'b1}};
localparam logic [0:0] p_logic1= {96{1'b1}};
localparam reg [1:0] p_reg2 = {96{1'b1}};
localparam bit [1:0] p_bit2 = {96{1'b1}};
localparam logic [1:0] p_logic2= {96{1'b1}};
// verilator lint_on WIDTH
byte v_byte[2];
shortint v_shortint[2];
int v_int[2];
longint v_longint[2];
integer v_integer[2];
time v_time[2];
chandle v_chandle[2];
bit v_bit[2];
logic v_logic[2];
reg v_reg[2];
real v_real[2];
realtime v_realtime[2];
// We do this in two steps so we can check that initialization inside functions works properly
// verilator lint_off WIDTH
function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction
function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction
function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction
function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction
function int f_int; int lv_int; f_int = lv_int; endfunction
function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction
function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction
function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction
function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction
function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction
function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction
function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction
function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction
function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction
function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
function time f_time; time lv_time; f_time = lv_time; endfunction
function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction
// verilator lint_on WIDTH
`ifdef verilator
// For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default!
`define XINIT 1'b1
`define ALL_TWOSTATE 1'b1
`else
`define XINIT 1'bx
`define ALL_TWOSTATE 1'b0
`endif
`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \
if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \
begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \
name = {96{1'b1}}; \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \
name = {96{1'bx}}; \
if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \
begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \
initial begin
// verilator lint_off WIDTH
// verilator lint_off UNSIGNED
// name b sign twost 0init
`CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1);
`CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1);
`CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1);
`CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1);
`CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0);
`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0);
// verilator lint_on WIDTH
// verilator lint_on UNSIGNED
// Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
`ifdef VERILATOR // else indeterminate
if ($bits(d_chandle) !== 64) $stop;
`endif
`define CHECK_P(name,nbits) \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
// name b
`CHECK_P(p_implicit ,96);
`CHECK_P(p_implicit[0] ,1 );
`CHECK_P(p_explicit ,90);
`CHECK_P(p_explicit[0] ,1 );
`CHECK_P(p_byte ,8 );
`CHECK_P(p_byte[0] ,1 );
`CHECK_P(p_shortint ,16);
`CHECK_P(p_shortint[0] ,1 );
`CHECK_P(p_int ,32);
`CHECK_P(p_int[0] ,1 );
`CHECK_P(p_longint ,64);
`CHECK_P(p_longint[0] ,1 );
`CHECK_P(p_integer ,32);
`CHECK_P(p_integer[0] ,1 );
`CHECK_P(p_bit ,1 );
`CHECK_P(p_logic ,1 );
`CHECK_P(p_reg ,1 );
`CHECK_P(p_bit1 ,1 );
`CHECK_P(p_logic1 ,1 );
`CHECK_P(p_reg1 ,1 );
`CHECK_P(p_bit1[0] ,1 );
`CHECK_P(p_logic1[0] ,1 );
`CHECK_P(p_reg1[0] ,1 );
`CHECK_P(p_bit2 ,2 );
`CHECK_P(p_logic2 ,2 );
`CHECK_P(p_reg2 ,2 );
`define CHECK_B(varname,nbits) \
if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \
`CHECK_B(v_byte[1] ,8 );
`CHECK_B(v_shortint[1] ,16);
`CHECK_B(v_int[1] ,32);
`CHECK_B(v_longint[1] ,64);
`CHECK_B(v_integer[1] ,32);
`CHECK_B(v_time[1] ,64);
//`CHECK_B(v_chandle[1]
`CHECK_B(v_bit[1] ,1 );
`CHECK_B(v_logic[1] ,1 );
`CHECK_B(v_reg[1] ,1 );
//`CHECK_B(v_real[1] ,64); // $bits not allowed
//`CHECK_B(v_realtime[1] ,64); // $bits not allowed
`define CHECK_F(fname,nbits,zeroinit) \
if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \
// name b 0init
`CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96
`CHECK_F(f_explicit ,90,1'b0);
`CHECK_F(f_byte ,8 ,1'b1);
`CHECK_F(f_shortint ,16,1'b1);
`CHECK_F(f_int ,32,1'b1);
`CHECK_F(f_longint ,64,1'b1);
`CHECK_F(f_integer ,32,1'b0);
`CHECK_F(f_time ,64,1'b0);
`ifdef VERILATOR // else indeterminate
`CHECK_F(f_chandle ,64,1'b0);
`endif
`CHECK_F(f_bit ,1 ,1'b1);
`CHECK_F(f_logic ,1 ,1'b0);
`CHECK_F(f_reg ,1 ,1'b0);
`CHECK_F(f_bit1 ,1 ,1'b1);
`CHECK_F(f_logic1 ,1 ,1'b0);
`CHECK_F(f_reg1 ,1 ,1'b0);
`CHECK_F(f_bit2 ,2 ,1'b1);
`CHECK_F(f_logic2 ,2 ,1'b0);
`CHECK_F(f_reg2 ,2 ,1'b0);
// For unpacked types we don't want width warnings for unsized numbers that fit
d_byte = 2;
d_shortint= 2;
d_int = 2;
d_longint = 2;
d_integer = 2;
// Special check
d_time = $time;
if ($time !== d_time) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [1:0] d_bit2;
logic [1:0] d_logic2;
reg [1:0] d_reg2;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
// Declarations using var
var byte v_b;
`ifndef VCS
var [2:0] v_b3;
var signed [2:0] v_bs;
`endif
// verilator lint_off WIDTH
localparam p_implicit = {96{1'b1}};
localparam [89:0] p_explicit = {96{1'b1}};
localparam byte p_byte = {96{1'b1}};
localparam shortint p_shortint = {96{1'b1}};
localparam int p_int = {96{1'b1}};
localparam longint p_longint = {96{1'b1}};
localparam integer p_integer = {96{1'b1}};
localparam reg p_reg = {96{1'b1}};
localparam bit p_bit = {96{1'b1}};
localparam logic p_logic = {96{1'b1}};
localparam reg [0:0] p_reg1 = {96{1'b1}};
localparam bit [0:0] p_bit1 = {96{1'b1}};
localparam logic [0:0] p_logic1= {96{1'b1}};
localparam reg [1:0] p_reg2 = {96{1'b1}};
localparam bit [1:0] p_bit2 = {96{1'b1}};
localparam logic [1:0] p_logic2= {96{1'b1}};
// verilator lint_on WIDTH
byte v_byte[2];
shortint v_shortint[2];
int v_int[2];
longint v_longint[2];
integer v_integer[2];
time v_time[2];
chandle v_chandle[2];
bit v_bit[2];
logic v_logic[2];
reg v_reg[2];
real v_real[2];
realtime v_realtime[2];
// We do this in two steps so we can check that initialization inside functions works properly
// verilator lint_off WIDTH
function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction
function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction
function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction
function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction
function int f_int; int lv_int; f_int = lv_int; endfunction
function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction
function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction
function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction
function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction
function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction
function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction
function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction
function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction
function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction
function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
function time f_time; time lv_time; f_time = lv_time; endfunction
function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction
// verilator lint_on WIDTH
`ifdef verilator
// For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default!
`define XINIT 1'b1
`define ALL_TWOSTATE 1'b1
`else
`define XINIT 1'bx
`define ALL_TWOSTATE 1'b0
`endif
`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \
if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \
begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \
name = {96{1'b1}}; \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \
name = {96{1'bx}}; \
if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \
begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \
initial begin
// verilator lint_off WIDTH
// verilator lint_off UNSIGNED
// name b sign twost 0init
`CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1);
`CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1);
`CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1);
`CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1);
`CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0);
`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0);
// verilator lint_on WIDTH
// verilator lint_on UNSIGNED
// Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
`ifdef VERILATOR // else indeterminate
if ($bits(d_chandle) !== 64) $stop;
`endif
`define CHECK_P(name,nbits) \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
// name b
`CHECK_P(p_implicit ,96);
`CHECK_P(p_implicit[0] ,1 );
`CHECK_P(p_explicit ,90);
`CHECK_P(p_explicit[0] ,1 );
`CHECK_P(p_byte ,8 );
`CHECK_P(p_byte[0] ,1 );
`CHECK_P(p_shortint ,16);
`CHECK_P(p_shortint[0] ,1 );
`CHECK_P(p_int ,32);
`CHECK_P(p_int[0] ,1 );
`CHECK_P(p_longint ,64);
`CHECK_P(p_longint[0] ,1 );
`CHECK_P(p_integer ,32);
`CHECK_P(p_integer[0] ,1 );
`CHECK_P(p_bit ,1 );
`CHECK_P(p_logic ,1 );
`CHECK_P(p_reg ,1 );
`CHECK_P(p_bit1 ,1 );
`CHECK_P(p_logic1 ,1 );
`CHECK_P(p_reg1 ,1 );
`CHECK_P(p_bit1[0] ,1 );
`CHECK_P(p_logic1[0] ,1 );
`CHECK_P(p_reg1[0] ,1 );
`CHECK_P(p_bit2 ,2 );
`CHECK_P(p_logic2 ,2 );
`CHECK_P(p_reg2 ,2 );
`define CHECK_B(varname,nbits) \
if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \
`CHECK_B(v_byte[1] ,8 );
`CHECK_B(v_shortint[1] ,16);
`CHECK_B(v_int[1] ,32);
`CHECK_B(v_longint[1] ,64);
`CHECK_B(v_integer[1] ,32);
`CHECK_B(v_time[1] ,64);
//`CHECK_B(v_chandle[1]
`CHECK_B(v_bit[1] ,1 );
`CHECK_B(v_logic[1] ,1 );
`CHECK_B(v_reg[1] ,1 );
//`CHECK_B(v_real[1] ,64); // $bits not allowed
//`CHECK_B(v_realtime[1] ,64); // $bits not allowed
`define CHECK_F(fname,nbits,zeroinit) \
if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \
// name b 0init
`CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96
`CHECK_F(f_explicit ,90,1'b0);
`CHECK_F(f_byte ,8 ,1'b1);
`CHECK_F(f_shortint ,16,1'b1);
`CHECK_F(f_int ,32,1'b1);
`CHECK_F(f_longint ,64,1'b1);
`CHECK_F(f_integer ,32,1'b0);
`CHECK_F(f_time ,64,1'b0);
`ifdef VERILATOR // else indeterminate
`CHECK_F(f_chandle ,64,1'b0);
`endif
`CHECK_F(f_bit ,1 ,1'b1);
`CHECK_F(f_logic ,1 ,1'b0);
`CHECK_F(f_reg ,1 ,1'b0);
`CHECK_F(f_bit1 ,1 ,1'b1);
`CHECK_F(f_logic1 ,1 ,1'b0);
`CHECK_F(f_reg1 ,1 ,1'b0);
`CHECK_F(f_bit2 ,2 ,1'b1);
`CHECK_F(f_logic2 ,2 ,1'b0);
`CHECK_F(f_reg2 ,2 ,1'b0);
// For unpacked types we don't want width warnings for unsized numbers that fit
d_byte = 2;
d_shortint= 2;
d_int = 2;
d_longint = 2;
d_integer = 2;
// Special check
d_time = $time;
if ($time !== d_time) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [1:0] d_bit2;
logic [1:0] d_logic2;
reg [1:0] d_reg2;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
// Declarations using var
var byte v_b;
`ifndef VCS
var [2:0] v_b3;
var signed [2:0] v_bs;
`endif
// verilator lint_off WIDTH
localparam p_implicit = {96{1'b1}};
localparam [89:0] p_explicit = {96{1'b1}};
localparam byte p_byte = {96{1'b1}};
localparam shortint p_shortint = {96{1'b1}};
localparam int p_int = {96{1'b1}};
localparam longint p_longint = {96{1'b1}};
localparam integer p_integer = {96{1'b1}};
localparam reg p_reg = {96{1'b1}};
localparam bit p_bit = {96{1'b1}};
localparam logic p_logic = {96{1'b1}};
localparam reg [0:0] p_reg1 = {96{1'b1}};
localparam bit [0:0] p_bit1 = {96{1'b1}};
localparam logic [0:0] p_logic1= {96{1'b1}};
localparam reg [1:0] p_reg2 = {96{1'b1}};
localparam bit [1:0] p_bit2 = {96{1'b1}};
localparam logic [1:0] p_logic2= {96{1'b1}};
// verilator lint_on WIDTH
byte v_byte[2];
shortint v_shortint[2];
int v_int[2];
longint v_longint[2];
integer v_integer[2];
time v_time[2];
chandle v_chandle[2];
bit v_bit[2];
logic v_logic[2];
reg v_reg[2];
real v_real[2];
realtime v_realtime[2];
// We do this in two steps so we can check that initialization inside functions works properly
// verilator lint_off WIDTH
function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction
function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction
function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction
function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction
function int f_int; int lv_int; f_int = lv_int; endfunction
function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction
function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction
function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction
function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction
function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction
function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction
function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction
function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction
function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction
function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
function time f_time; time lv_time; f_time = lv_time; endfunction
function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction
// verilator lint_on WIDTH
`ifdef verilator
// For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default!
`define XINIT 1'b1
`define ALL_TWOSTATE 1'b1
`else
`define XINIT 1'bx
`define ALL_TWOSTATE 1'b0
`endif
`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \
if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \
begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \
name = {96{1'b1}}; \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \
name = {96{1'bx}}; \
if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \
begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \
initial begin
// verilator lint_off WIDTH
// verilator lint_off UNSIGNED
// name b sign twost 0init
`CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1);
`CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1);
`CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1);
`CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1);
`CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0);
`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0);
// verilator lint_on WIDTH
// verilator lint_on UNSIGNED
// Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
`ifdef VERILATOR // else indeterminate
if ($bits(d_chandle) !== 64) $stop;
`endif
`define CHECK_P(name,nbits) \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
// name b
`CHECK_P(p_implicit ,96);
`CHECK_P(p_implicit[0] ,1 );
`CHECK_P(p_explicit ,90);
`CHECK_P(p_explicit[0] ,1 );
`CHECK_P(p_byte ,8 );
`CHECK_P(p_byte[0] ,1 );
`CHECK_P(p_shortint ,16);
`CHECK_P(p_shortint[0] ,1 );
`CHECK_P(p_int ,32);
`CHECK_P(p_int[0] ,1 );
`CHECK_P(p_longint ,64);
`CHECK_P(p_longint[0] ,1 );
`CHECK_P(p_integer ,32);
`CHECK_P(p_integer[0] ,1 );
`CHECK_P(p_bit ,1 );
`CHECK_P(p_logic ,1 );
`CHECK_P(p_reg ,1 );
`CHECK_P(p_bit1 ,1 );
`CHECK_P(p_logic1 ,1 );
`CHECK_P(p_reg1 ,1 );
`CHECK_P(p_bit1[0] ,1 );
`CHECK_P(p_logic1[0] ,1 );
`CHECK_P(p_reg1[0] ,1 );
`CHECK_P(p_bit2 ,2 );
`CHECK_P(p_logic2 ,2 );
`CHECK_P(p_reg2 ,2 );
`define CHECK_B(varname,nbits) \
if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \
`CHECK_B(v_byte[1] ,8 );
`CHECK_B(v_shortint[1] ,16);
`CHECK_B(v_int[1] ,32);
`CHECK_B(v_longint[1] ,64);
`CHECK_B(v_integer[1] ,32);
`CHECK_B(v_time[1] ,64);
//`CHECK_B(v_chandle[1]
`CHECK_B(v_bit[1] ,1 );
`CHECK_B(v_logic[1] ,1 );
`CHECK_B(v_reg[1] ,1 );
//`CHECK_B(v_real[1] ,64); // $bits not allowed
//`CHECK_B(v_realtime[1] ,64); // $bits not allowed
`define CHECK_F(fname,nbits,zeroinit) \
if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \
// name b 0init
`CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96
`CHECK_F(f_explicit ,90,1'b0);
`CHECK_F(f_byte ,8 ,1'b1);
`CHECK_F(f_shortint ,16,1'b1);
`CHECK_F(f_int ,32,1'b1);
`CHECK_F(f_longint ,64,1'b1);
`CHECK_F(f_integer ,32,1'b0);
`CHECK_F(f_time ,64,1'b0);
`ifdef VERILATOR // else indeterminate
`CHECK_F(f_chandle ,64,1'b0);
`endif
`CHECK_F(f_bit ,1 ,1'b1);
`CHECK_F(f_logic ,1 ,1'b0);
`CHECK_F(f_reg ,1 ,1'b0);
`CHECK_F(f_bit1 ,1 ,1'b1);
`CHECK_F(f_logic1 ,1 ,1'b0);
`CHECK_F(f_reg1 ,1 ,1'b0);
`CHECK_F(f_bit2 ,2 ,1'b1);
`CHECK_F(f_logic2 ,2 ,1'b0);
`CHECK_F(f_reg2 ,2 ,1'b0);
// For unpacked types we don't want width warnings for unsized numbers that fit
d_byte = 2;
d_shortint= 2;
d_int = 2;
d_longint = 2;
d_integer = 2;
// Special check
d_time = $time;
if ($time !== d_time) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg reset_l;
// verilator lint_off GENCLK
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
reg clkgate_e2r;
reg clkgate_e1r_l;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
clkgate_e1r_l <= ~1'b1;
end
else begin
clkgate_e1r_l <= ~clkgate_e2r;
end
end
reg clkgate_e1f;
always @(negedge clk) begin
// Yes, it's really a =
clkgate_e1f = ~clkgate_e1r_l | ~reset_l;
end
wire clkgated = clk & clkgate_e1f;
reg [31:0] countgated;
always @(posedge clkgated or negedge reset_l) begin
if (!reset_l) begin
countgated <= 32'h1000;
end
else begin
countgated <= countgated + 32'd1;
end
end
reg [31:0] count;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
count <= 32'h1000;
end
else begin
count <= count + 32'd1;
end
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated);
`endif
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
reset_l <= ~1'b0;
clkgate_e2r <= 1'b1;
end
8'd01: begin
reset_l <= ~1'b0;
end
8'd02: begin
end
8'd03: begin
reset_l <= ~1'b1; // Need a posedge
end
8'd04: begin
end
8'd05: begin
reset_l <= ~1'b0;
end
8'd09: begin
clkgate_e2r <= 1'b0;
end
8'd11: begin
clkgate_e2r <= 1'b1;
end
8'd20: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
8'd00: ;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop;
8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop;
8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop;
8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop;
8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop;
8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop;
8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop;
8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop;
8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop;
8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop;
8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop;
8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop;
8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop;
8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop;
default: $stop;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg rst_n;
// Take CRC data and apply to testblock inputs
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] pos1; // From test of Test.v
wire [2:0] pos2; // From test of Test.v
// End of automatics
Test test (
// Outputs
.pos1 (pos1[2:0]),
.pos2 (pos2[2:0]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst_n (rst_n));
// Aggregate outputs into a single result vector
wire [63:0] result = {61'h0, pos1};
// What checksum will we end up with
`define EXPECTED_SUM 64'h039ea4d039c2e70b
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
rst_n <= ~1'b0;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
rst_n <= ~1'b1;
end
else if (cyc<10) begin
sum <= 64'h0;
rst_n <= ~1'b1;
end
else if (cyc<90) begin
if (pos1 !== pos2) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
#(parameter SAMPLE_WIDTH = 5 )
(
`ifdef verilator // Some simulators don't support clog2
output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1,
`else
output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1,
`endif
output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2,
// System
input clk,
input rst_n
);
function integer log2(input integer arg);
begin
for(log2=0; arg>0; log2=log2+1)
arg = (arg >> 1);
end
endfunction
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
pos1 <= 0;
pos2 <= 0;
end
else begin
pos1 <= pos1 + 1;
pos2 <= pos2 + 1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub4 (/*AUTOARG*/
// Outputs
outq,
// Inputs
index
);
input [7:0] index;
output [9:0] outq;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outq;
// End of automatics
// =============================
always @(/*AS*/index) begin
case (index)
// default below: no change
8'h00: begin outq = 10'h001; end
8'he0: begin outq = 10'h05b; end
8'he1: begin outq = 10'h126; end
8'he2: begin outq = 10'h369; end
8'he3: begin outq = 10'h291; end
8'he4: begin outq = 10'h2ca; end
8'he5: begin outq = 10'h25b; end
8'he6: begin outq = 10'h106; end
8'he7: begin outq = 10'h172; end
8'he8: begin outq = 10'h2f7; end
8'he9: begin outq = 10'h2d3; end
8'hea: begin outq = 10'h182; end
8'heb: begin outq = 10'h327; end
8'hec: begin outq = 10'h1d0; end
8'hed: begin outq = 10'h204; end
8'hee: begin outq = 10'h11f; end
8'hef: begin outq = 10'h365; end
8'hf0: begin outq = 10'h2c2; end
8'hf1: begin outq = 10'h2b5; end
8'hf2: begin outq = 10'h1f8; end
8'hf3: begin outq = 10'h2a7; end
8'hf4: begin outq = 10'h1be; end
8'hf5: begin outq = 10'h25e; end
8'hf6: begin outq = 10'h032; end
8'hf7: begin outq = 10'h2ef; end
8'hf8: begin outq = 10'h02f; end
8'hf9: begin outq = 10'h201; end
8'hfa: begin outq = 10'h054; end
8'hfb: begin outq = 10'h013; end
8'hfc: begin outq = 10'h249; end
8'hfd: begin outq = 10'h09a; end
8'hfe: begin outq = 10'h012; end
8'hff: begin outq = 10'h114; end
default: ; // No change
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub4 (/*AUTOARG*/
// Outputs
outq,
// Inputs
index
);
input [7:0] index;
output [9:0] outq;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outq;
// End of automatics
// =============================
always @(/*AS*/index) begin
case (index)
// default below: no change
8'h00: begin outq = 10'h001; end
8'he0: begin outq = 10'h05b; end
8'he1: begin outq = 10'h126; end
8'he2: begin outq = 10'h369; end
8'he3: begin outq = 10'h291; end
8'he4: begin outq = 10'h2ca; end
8'he5: begin outq = 10'h25b; end
8'he6: begin outq = 10'h106; end
8'he7: begin outq = 10'h172; end
8'he8: begin outq = 10'h2f7; end
8'he9: begin outq = 10'h2d3; end
8'hea: begin outq = 10'h182; end
8'heb: begin outq = 10'h327; end
8'hec: begin outq = 10'h1d0; end
8'hed: begin outq = 10'h204; end
8'hee: begin outq = 10'h11f; end
8'hef: begin outq = 10'h365; end
8'hf0: begin outq = 10'h2c2; end
8'hf1: begin outq = 10'h2b5; end
8'hf2: begin outq = 10'h1f8; end
8'hf3: begin outq = 10'h2a7; end
8'hf4: begin outq = 10'h1be; end
8'hf5: begin outq = 10'h25e; end
8'hf6: begin outq = 10'h032; end
8'hf7: begin outq = 10'h2ef; end
8'hf8: begin outq = 10'h02f; end
8'hf9: begin outq = 10'h201; end
8'hfa: begin outq = 10'h054; end
8'hfb: begin outq = 10'h013; end
8'hfc: begin outq = 10'h249; end
8'hfd: begin outq = 10'h09a; end
8'hfe: begin outq = 10'h012; end
8'hff: begin outq = 10'h114; end
default: ; // No change
endcase
end
endmodule
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (15),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (15),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (15),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire bit_in = crc[0];
wire [30:0] vec_in = crc[31:1];
wire [123:0] wide_in = {crc[59:0],~crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire exp_bit_out; // From reference of t_embed1_child.v
wire exp_did_init_out; // From reference of t_embed1_child.v
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
wire got_bit_out; // From test of t_embed1_wrap.v
wire got_did_init_out; // From test of t_embed1_wrap.v
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
// End of automatics
// A non-embedded master
/* t_embed1_child AUTO_TEMPLATE(
.\(.*_out\) (exp_\1[]),
.is_ref (1'b1));
*/
t_embed1_child reference
(/*AUTOINST*/
// Outputs
.bit_out (exp_bit_out), // Templated
.vec_out (exp_vec_out[30:0]), // Templated
.wide_out (exp_wide_out[123:0]), // Templated
.did_init_out (exp_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b1)); // Templated
// The embeded comparison
/* t_embed1_wrap AUTO_TEMPLATE(
.\(.*_out\) (got_\1[]),
.is_ref (1'b0));
*/
t_embed1_wrap test
(/*AUTOINST*/
// Outputs
.bit_out (got_bit_out), // Templated
.vec_out (got_vec_out[30:0]), // Templated
.wide_out (got_wide_out[123:0]), // Templated
.did_init_out (got_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b0)); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0,
got_wide_out !== exp_wide_out,
got_vec_out !== exp_vec_out,
got_bit_out !== exp_bit_out,
got_did_init_out !== exp_did_init_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
if (result != 64'h0) begin
$display("Bit mismatch, result=%x\n", result);
$stop;
end
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire bit_in = crc[0];
wire [30:0] vec_in = crc[31:1];
wire [123:0] wide_in = {crc[59:0],~crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire exp_bit_out; // From reference of t_embed1_child.v
wire exp_did_init_out; // From reference of t_embed1_child.v
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
wire got_bit_out; // From test of t_embed1_wrap.v
wire got_did_init_out; // From test of t_embed1_wrap.v
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
// End of automatics
// A non-embedded master
/* t_embed1_child AUTO_TEMPLATE(
.\(.*_out\) (exp_\1[]),
.is_ref (1'b1));
*/
t_embed1_child reference
(/*AUTOINST*/
// Outputs
.bit_out (exp_bit_out), // Templated
.vec_out (exp_vec_out[30:0]), // Templated
.wide_out (exp_wide_out[123:0]), // Templated
.did_init_out (exp_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b1)); // Templated
// The embeded comparison
/* t_embed1_wrap AUTO_TEMPLATE(
.\(.*_out\) (got_\1[]),
.is_ref (1'b0));
*/
t_embed1_wrap test
(/*AUTOINST*/
// Outputs
.bit_out (got_bit_out), // Templated
.vec_out (got_vec_out[30:0]), // Templated
.wide_out (got_wide_out[123:0]), // Templated
.did_init_out (got_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b0)); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0,
got_wide_out !== exp_wide_out,
got_vec_out !== exp_vec_out,
got_bit_out !== exp_bit_out,
got_did_init_out !== exp_did_init_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
if (result != 64'h0) begin
$display("Bit mismatch, result=%x\n", result);
$stop;
end
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
//============================================================
reg bad;
initial begin
bad=0;
c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888);
c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0);
c96(96'h0003, 96'h0002, 96'h0001, 96'h0001);
c96(96'h0003, 96'h0003, 96'h0001, 96'h0000);
c96(96'h0003, 96'h0004, 96'h0000, 96'h0003);
c96(96'h0000, 96'hffff, 96'h0000, 96'h0000);
c96(96'hffff, 96'h0001, 96'hffff, 96'h0000);
c96(96'hffff, 96'hffff, 96'h0001, 96'h0000);
c96(96'hffff, 96'h0003, 96'h5555, 96'h0000);
c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000);
c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000);
c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe);
c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70);
c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000);
c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000);
c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005);
c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000);
c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001);
c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000);
c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001);
c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899);
c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000);
c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff);
c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab);
c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff);
c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000);
c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000);
c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000);
c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000);
c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000);
c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000);
c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000);
c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000);
c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000);
c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000);
c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002);
c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff);
c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888);
if (bad) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
task c96;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
c96u( u, v, expq, expr);
c96s( u, v, expq, expr);
c96s(-u, v,-expq,-expr);
c96s( u,-v,-expq, expr);
c96s(-u,-v, expq,-expr);
endtask
task c96u;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
reg [95:0] gotq;
reg [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
task c96s;
input signed [95:0] u;
input signed [95:0] v;
input signed [95:0] expq;
input signed [95:0] expr;
reg signed [95:0] gotq;
reg signed [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h1a0d07009b6a30d2
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [3:0] out;
assign out[0] = in[3:0] ==? 4'b1001;
assign out[1] = in[3:0] !=? 4'b1001;
assign out[2] = in[3:0] ==? 4'bx01x;
assign out[3] = in[3:0] !=? 4'bx01x;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h1a0d07009b6a30d2
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [3:0] out;
assign out[0] = in[3:0] ==? 4'b1001;
assign out[1] = in[3:0] !=? 4'b1001;
assign out[2] = in[3:0] ==? 4'bx01x;
assign out[3] = in[3:0] !=? 4'bx01x;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [63:0] inwide;
reg [39:0] addr;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write ("%x %x\n", cyc, addr);
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
addr <= 40'h12_3456_7890;
end
if (cyc==2) begin
if (addr !== 40'h1234567890) $stop;
addr[31:0] <= 32'habcd_efaa;
end
if (cyc==3) begin
if (addr !== 40'h12abcdefaa) $stop;
addr[39:32] <= 8'h44;
inwide <= 64'hffeeddcc_11334466;
end
if (cyc==4) begin
if (addr !== 40'h44abcdefaa) $stop;
addr[31:0] <= inwide[31:0];
end
if (cyc==5) begin
if (addr !== 40'h4411334466) $stop;
$display ("Flip [%x]\n", inwide[3:0]);
addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
end
if (cyc==6) begin
if (addr !== 40'h4411334426) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [63:0] inwide;
reg [39:0] addr;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write ("%x %x\n", cyc, addr);
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
addr <= 40'h12_3456_7890;
end
if (cyc==2) begin
if (addr !== 40'h1234567890) $stop;
addr[31:0] <= 32'habcd_efaa;
end
if (cyc==3) begin
if (addr !== 40'h12abcdefaa) $stop;
addr[39:32] <= 8'h44;
inwide <= 64'hffeeddcc_11334466;
end
if (cyc==4) begin
if (addr !== 40'h44abcdefaa) $stop;
addr[31:0] <= inwide[31:0];
end
if (cyc==5) begin
if (addr !== 40'h4411334466) $stop;
$display ("Flip [%x]\n", inwide[3:0]);
addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
end
if (cyc==6) begin
if (addr !== 40'h4411334426) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [63:0] inwide;
reg [39:0] addr;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write ("%x %x\n", cyc, addr);
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
addr <= 40'h12_3456_7890;
end
if (cyc==2) begin
if (addr !== 40'h1234567890) $stop;
addr[31:0] <= 32'habcd_efaa;
end
if (cyc==3) begin
if (addr !== 40'h12abcdefaa) $stop;
addr[39:32] <= 8'h44;
inwide <= 64'hffeeddcc_11334466;
end
if (cyc==4) begin
if (addr !== 40'h44abcdefaa) $stop;
addr[31:0] <= inwide[31:0];
end
if (cyc==5) begin
if (addr !== 40'h4411334466) $stop;
$display ("Flip [%x]\n", inwide[3:0]);
addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
end
if (cyc==6) begin
if (addr !== 40'h4411334426) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [63:0] inwide;
reg [39:0] addr;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write ("%x %x\n", cyc, addr);
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
addr <= 40'h12_3456_7890;
end
if (cyc==2) begin
if (addr !== 40'h1234567890) $stop;
addr[31:0] <= 32'habcd_efaa;
end
if (cyc==3) begin
if (addr !== 40'h12abcdefaa) $stop;
addr[39:32] <= 8'h44;
inwide <= 64'hffeeddcc_11334466;
end
if (cyc==4) begin
if (addr !== 40'h44abcdefaa) $stop;
addr[31:0] <= inwide[31:0];
end
if (cyc==5) begin
if (addr !== 40'h4411334466) $stop;
$display ("Flip [%x]\n", inwide[3:0]);
addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
end
if (cyc==6) begin
if (addr !== 40'h4411334426) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [63:0] inwide;
reg [39:0] addr;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write ("%x %x\n", cyc, addr);
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
addr <= 40'h12_3456_7890;
end
if (cyc==2) begin
if (addr !== 40'h1234567890) $stop;
addr[31:0] <= 32'habcd_efaa;
end
if (cyc==3) begin
if (addr !== 40'h12abcdefaa) $stop;
addr[39:32] <= 8'h44;
inwide <= 64'hffeeddcc_11334466;
end
if (cyc==4) begin
if (addr !== 40'h44abcdefaa) $stop;
addr[31:0] <= inwide[31:0];
end
if (cyc==5) begin
if (addr !== 40'h4411334466) $stop;
$display ("Flip [%x]\n", inwide[3:0]);
addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}];
end
if (cyc==6) begin
if (addr !== 40'h4411334426) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports. This "FIFO" stores no data and only counts the number
// of valids.
//
//===----------------------------------------------------------------------===//
module acl_valid_fifo_counter
#(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 0, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
)
(
input logic clock,
input logic resetn,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_out,
output logic empty,
output logic full
);
// No data, so just build a counter to count the number of valids stored in this "FIFO".
//
// The counter is constructed to count up to a MINIMUM value of DEPTH entries.
// * Logical range of the counter C0 is [0, DEPTH].
// * empty = (C0 <= 0)
// * full = (C0 >= DEPTH)
//
// To have efficient detection of the empty condition (C0 == 0), the range is offset
// by -1 so that a negative number indicates empty.
// * Logical range of the counter C1 is [-1, DEPTH-1].
// * empty = (C1 < 0)
// * full = (C1 >= DEPTH-1)
// The size of counter C1 is $clog2((DEPTH-1) + 1) + 1 => $clog2(DEPTH) + 1.
//
// To have efficient detection of the full condition (C1 >= DEPTH-1), change the
// full condition to C1 == 2^$clog2(DEPTH-1), which is DEPTH-1 rounded up
// to the next power of 2. This is only done if STRICT_DEPTH == 0, otherwise
// the full condition is comparison vs. DEPTH-1.
// * Logical range of the counter C2 is [-1, 2^$clog2(DEPTH-1)]
// * empty = (C2 < 0)
// * full = (C2 == 2^$clog2(DEPTH - 1))
// The size of counter C2 is $clog2(DEPTH-1) + 2.
// * empty = MSB
// * full = ~[MSB] & [MSB-1]
localparam COUNTER_WIDTH = (STRICT_DEPTH == 0) ?
((DEPTH > 1 ? $clog2(DEPTH-1) : 0) + 2) :
($clog2(DEPTH) + 1);
logic [COUNTER_WIDTH - 1:0] valid_counter /* synthesis maxfan=1 dont_merge */;
logic incr, decr;
assign empty = valid_counter[$bits(valid_counter) - 1];
assign full = (STRICT_DEPTH == 0) ?
(~valid_counter[$bits(valid_counter) - 1] & valid_counter[$bits(valid_counter) - 2]) :
(valid_counter == DEPTH - 1);
assign incr = valid_in & ~stall_out;
assign decr = valid_out & ~stall_in;
assign valid_out = ~empty;
assign stall_out = ALLOW_FULL_WRITE ? (full & stall_in) : full;
always @( posedge clock or negedge resetn )
if( !resetn )
valid_counter <= {$bits(valid_counter){1'b1}}; // -1
else
valid_counter <= valid_counter + incr - decr;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] mode_d1r;
reg [7:0] mode_d2r;
reg [7:0] mode_d3r;
// surefire lint_off ITENST
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
end
else begin
_mode <= _mode + 1;
if (_mode==0) begin
$write("[%0t] t_blocking: Running\n", $time);
a <= 8'd0;
b <= 8'd0;
c <= 8'd0;
end
else if (_mode==1) begin
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd1;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd2;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==3) begin
if (a !== 8'd1) $stop;
if (b !== 8'd2) $stop;
if (c !== 8'd1) $stop;
end
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
always @ (posedge clk) begin
mode_d3r <= mode_d2r;
mode_d2r <= mode_d1r;
mode_d1r <= _mode[7:0];
end
reg [14:10] bits;
// surefire lint_off SEQASS
always @ (posedge clk) begin
if (_mode==1) begin
bits[14:13] <= 2'b11;
bits[12] <= 1'b1;
end
if (_mode==2) begin
bits[11:10] <= 2'b10;
bits[13] <= 0;
end
if (_mode==3) begin
if (bits !== 5'b10110) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] mode_d1r;
reg [7:0] mode_d2r;
reg [7:0] mode_d3r;
// surefire lint_off ITENST
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
end
else begin
_mode <= _mode + 1;
if (_mode==0) begin
$write("[%0t] t_blocking: Running\n", $time);
a <= 8'd0;
b <= 8'd0;
c <= 8'd0;
end
else if (_mode==1) begin
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd1;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd2;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==3) begin
if (a !== 8'd1) $stop;
if (b !== 8'd2) $stop;
if (c !== 8'd1) $stop;
end
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
always @ (posedge clk) begin
mode_d3r <= mode_d2r;
mode_d2r <= mode_d1r;
mode_d1r <= _mode[7:0];
end
reg [14:10] bits;
// surefire lint_off SEQASS
always @ (posedge clk) begin
if (_mode==1) begin
bits[14:13] <= 2'b11;
bits[12] <= 1'b1;
end
if (_mode==2) begin
bits[11:10] <= 2'b10;
bits[13] <= 0;
end
if (_mode==3) begin
if (bits !== 5'b10110) $stop;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
// verilator lint_off WIDTH
`define INT_RANGE 31:0
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 63:0
reg [`INT_RANGE] stashb, stasha, stashn, stashm;
function [`VECTOR_RANGE] copy_range;
input [`VECTOR_RANGE] y;
input [`INT_RANGE] b;
input [`INT_RANGE] a;
input [`VECTOR_RANGE] x;
input [`INT_RANGE] n;
input [`INT_RANGE] m;
begin
copy_range = y;
stashb = b;
stasha = a;
stashn = n;
stashm = m;
end
endfunction
parameter DATA_SIZE = 16;
parameter NUM_OF_REGS = 32;
reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf;
reg [DATA_SIZE-1:0] memread_rf_reg;
always @(memread_rf) begin : memread_convert
memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf,
DATA_SIZE-'d1, DATA_SIZE-'d1);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
memread_rf = 512'haa;
end
if (cyc==3) begin
if (stashb != 'd15) $stop;
if (stasha != 'd15) $stop;
if (stashn != 'd15) $stop;
if (stashm != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
// verilator lint_off WIDTH
`define INT_RANGE 31:0
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 63:0
reg [`INT_RANGE] stashb, stasha, stashn, stashm;
function [`VECTOR_RANGE] copy_range;
input [`VECTOR_RANGE] y;
input [`INT_RANGE] b;
input [`INT_RANGE] a;
input [`VECTOR_RANGE] x;
input [`INT_RANGE] n;
input [`INT_RANGE] m;
begin
copy_range = y;
stashb = b;
stasha = a;
stashn = n;
stashm = m;
end
endfunction
parameter DATA_SIZE = 16;
parameter NUM_OF_REGS = 32;
reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf;
reg [DATA_SIZE-1:0] memread_rf_reg;
always @(memread_rf) begin : memread_convert
memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf,
DATA_SIZE-'d1, DATA_SIZE-'d1);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
memread_rf = 512'haa;
end
if (cyc==3) begin
if (stashb != 'd15) $stop;
if (stasha != 'd15) $stop;
if (stashn != 'd15) $stop;
if (stashm != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
`define DDIFF_BITS 9
`define AOA_BITS 8
`define HALF_DDIFF `DDIFF_BITS'd256
`define MAX_AOA `AOA_BITS'd255
`define BURP_DIVIDER 9'd16
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0];
wire reset = (cyc<7);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.AOA_B (AOA_B[`AOA_BITS-1:0]),
// Inputs
.DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]),
.reset (reset),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {56'h0, AOA_B};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3a74e9d34771ad93
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
AOA_B,
// Inputs
DDIFF_B, reset, clk
);
input [`DDIFF_BITS-1:0] DDIFF_B;
input reset;
input clk;
output reg [`AOA_BITS-1:0] AOA_B;
reg [`AOA_BITS-1:0] AOA_NEXT_B;
reg [`AOA_BITS-1:0] tmp;
always @(posedge clk) begin
if (reset) begin
AOA_B <= 8'h80;
end
else begin
AOA_B <= AOA_NEXT_B;
end
end
always @* begin
// verilator lint_off WIDTH
tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER);
t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER));
// verilator lint_on WIDTH
end
task t_aoa_update;
output [`AOA_BITS-1:0] aoa_reg_next;
input [`AOA_BITS-1:0] aoa_reg;
input [`AOA_BITS-1:0] aoa_delta_update;
begin
if ((`MAX_AOA-aoa_reg)<aoa_delta_update) //Overflow protection
aoa_reg_next=`MAX_AOA;
else
aoa_reg_next=aoa_reg+aoa_delta_update;
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg rnd;
reg [2:0] a;
reg [2:0] b;
reg [31:0] wide;
// surefire lint_off STMINI
initial _ranit = 0;
wire sigone1 = 1'b1;
wire sigone2 = 1'b1;
reg ok;
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
// Large case statements should be well optimizable.
reg [2:0] anot;
always @ (/*AS*/a) begin
casez (a)
default: anot = 3'b001;
3'd0: anot = 3'b111;
3'd1: anot = 3'b110;
3'd2: anot = 3'b101;
3'd3: anot = 3'b101;
3'd4: anot = 3'b011;
3'd5: anot = 3'b010;
3'd6: anot = 3'b001; // Same so folds with 7
endcase
end
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
rnd <= 1;
$write("[%0t] t_case: Running\n", $time);
//
a = 3'b101;
b = 3'b111;
// verilator lint_off CASEX
casex (a)
default: $stop;
3'bx1x: $stop;
3'b100: $stop;
3'bx01: ;
endcase
casez (a)
default: $stop;
3'b?1?: $stop;
3'b100: $stop;
3'b?01: ;
endcase
casez (a)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
endcase
casez (b)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase
case(a[0])
default: ;
endcase
casex(a)
default: ;
3'b?0?: ;
endcase
// verilator lint_off CASEX
//This is illegal, the default occurs before the statements.
//case(a[0])
// default: $stop;
// 1'b1: ;
//endcase
//
wide = 32'h12345678;
casez (wide)
default: $stop;
32'h12345677,
32'h12345678,
32'h12345679: ;
endcase
//
ok = 0;
casez ({sigone1,sigone2})
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
2'b10, 2'b01: ;
2'b00: ;
default: ok=1'b1;
endcase
if (ok !== 1'b1) $stop;
//
if (rnd) begin
$write("");
end
//
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check parameters in case statements
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
parameter DSP_REGISTER_V = 6'h03;
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
reg [15:10] f_tmp_2s; // Delayed copy of F
reg p00_2s;
initial begin
alu_ctl_2s = 3'h1;
reg_addr_2s = 6'h3;
ir_slave_2s= 0;
f_tmp_2s= 0;
casex ({alu_ctl_2s,reg_addr_2s,
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
f_tmp_2s[11:10]})
default: p00_2s = 1'b0;
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
endcase
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
//
case ({1'b1, 1'b1})
default: $stop;
{1'b1, p00_2s}: ;
endcase
end
// Check wide overlapping cases
// surefire lint_off CSEOVR
parameter ANY_STATE = 7'h??;
reg [19:0] foo;
initial begin
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
casez (foo)
default: $stop;
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
endcase
end
initial begin
foo = 20'b1010;
casex (foo[3:0])
default: $stop;
4'b0xxx,
4'b100x,
4'b11xx: $stop;
4'b1010: ;
endcase
end
initial begin
foo = 20'b1010;
ok = 1'b0;
// Test of RANGE(CONCAT reductions...
casex ({foo[3:2],foo[1:0],foo[3]})
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
5'bxx00x: $stop;
5'bxx01x: $stop;
5'bxx11x: $stop;
endcase
if (!ok) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
enum integer {
EP_State_IDLE ,
EP_State_CMDSHIFT0 ,
EP_State_CMDSHIFT13 ,
EP_State_CMDSHIFT14 ,
EP_State_CMDSHIFT15 ,
EP_State_CMDSHIFT16 ,
EP_State_DWAIT ,
EP_State_DSHIFT0 ,
EP_State_DSHIFT1 ,
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
m_state2_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
if (m_state2_xr != EP_State_IDLE) $stop;
m_state2_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
m_state2_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
m_state2_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
if (m_state2_xr != EP_State_DWAIT) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
(** * PE: Partial Evaluation *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
(** * PE: Partial Evaluation *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
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